2 * Intel D82875P Memory Controller kernel module
3 * (C) 2003 Linux Networx (http://lnxi.com)
4 * This file may be distributed under the terms of the
5 * GNU General Public License.
7 * Written by Thayne Harbaugh
9 * Wang Zhenyu at intel.com
11 * $Id: edac_i82875p.c,v 1.5.2.11 2005/10/05 00:43:44 dsp_llnl Exp $
13 * Note: E7210 appears same as D82875P - zhenyu.z.wang at intel.com
16 #include <linux/module.h>
17 #include <linux/init.h>
18 #include <linux/pci.h>
19 #include <linux/pci_ids.h>
20 #include <linux/slab.h>
21 #include "edac_core.h"
23 #define I82875P_REVISION " Ver: 2.0.2 " __DATE__
24 #define EDAC_MOD_STR "i82875p_edac"
26 #define i82875p_printk(level, fmt, arg...) \
27 edac_printk(level, "i82875p", fmt, ##arg)
29 #define i82875p_mc_printk(mci, level, fmt, arg...) \
30 edac_mc_chipset_printk(mci, level, "i82875p", fmt, ##arg)
32 #ifndef PCI_DEVICE_ID_INTEL_82875_0
33 #define PCI_DEVICE_ID_INTEL_82875_0 0x2578
34 #endif /* PCI_DEVICE_ID_INTEL_82875_0 */
36 #ifndef PCI_DEVICE_ID_INTEL_82875_6
37 #define PCI_DEVICE_ID_INTEL_82875_6 0x257e
38 #endif /* PCI_DEVICE_ID_INTEL_82875_6 */
40 /* four csrows in dual channel, eight in single channel */
41 #define I82875P_NR_CSROWS(nr_chans) (8/(nr_chans))
43 /* Intel 82875p register addresses - device 0 function 0 - DRAM Controller */
44 #define I82875P_EAP 0x58 /* Error Address Pointer (32b)
50 #define I82875P_DERRSYN 0x5c /* DRAM Error Syndrome (8b)
52 * 7:0 DRAM ECC Syndrome
55 #define I82875P_DES 0x5d /* DRAM Error Status (8b)
61 #define I82875P_ERRSTS 0xc8 /* Error Status Register (16b)
64 * 9 non-DRAM lock error (ndlock)
65 * 8 Sftwr Generated SMI
68 * 5 MCH detects unimplemented cycle
69 * 4 AGP access outside GA
70 * 3 Invalid AGP access
71 * 2 Invalid GA translation table
72 * 1 Unsupported AGP command
76 #define I82875P_ERRCMD 0xca /* Error Command (16b)
79 * 9 SERR on non-DRAM lock
82 * 6 target abort on high exception
83 * 5 detect unimplemented cyc
84 * 4 AGP access outside of GA
85 * 3 SERR on invalid AGP access
86 * 2 invalid translation table
87 * 1 SERR on unsupported AGP command
91 /* Intel 82875p register addresses - device 6 function 0 - DRAM Controller */
92 #define I82875P_PCICMD6 0x04 /* PCI Command Register (16b)
95 * 9 fast back-to-back - ro 0
96 * 8 SERR enable - ro 0
97 * 7 addr/data stepping - ro 0
98 * 6 parity err enable - ro 0
99 * 5 VGA palette snoop - ro 0
100 * 4 mem wr & invalidate - ro 0
101 * 3 special cycle - ro 0
102 * 2 bus master - ro 0
103 * 1 mem access dev6 - 0(dis),1(en)
104 * 0 IO access dev3 - 0(dis),1(en)
107 #define I82875P_BAR6 0x10 /* Mem Delays Base ADDR Reg (32b)
109 * 31:12 mem base addr [31:12]
110 * 11:4 address mask - ro 0
111 * 3 prefetchable - ro 0(non),1(pre)
112 * 2:1 mem type - ro 0
116 /* Intel 82875p MMIO register space - device 0 function 0 - MMR space */
118 #define I82875P_DRB_SHIFT 26 /* 64MiB grain */
119 #define I82875P_DRB 0x00 /* DRAM Row Boundary (8b x 8)
122 * 6:0 64MiB row boundary addr
125 #define I82875P_DRA 0x10 /* DRAM Row Attribute (4b x 8)
138 #define I82875P_DRC 0x68 /* DRAM Controller Mode (32b)
143 * 22:21 nr chan 00=1,01=2
145 * 19:18 Data Integ Mode 00=none,01=ecc
151 * 1:0 DRAM type 01=DDR
159 struct pci_dev *ovrfl_pdev;
160 void __iomem *ovrfl_window;
163 struct i82875p_dev_info {
164 const char *ctl_name;
167 struct i82875p_error_info {
175 static const struct i82875p_dev_info i82875p_devs[] = {
177 .ctl_name = "i82875p"},
180 static struct pci_dev *mci_pdev = NULL; /* init dev: in case that AGP code has
181 * already registered driver
184 static int i82875p_registered = 1;
186 static struct edac_pci_ctl_info *i82875p_pci;
188 static void i82875p_get_error_info(struct mem_ctl_info *mci,
189 struct i82875p_error_info *info)
191 struct pci_dev *pdev;
193 pdev = to_pci_dev(mci->dev);
196 * This is a mess because there is no atomic way to read all the
197 * registers at once and the registers can transition from CE being
200 pci_read_config_word(pdev, I82875P_ERRSTS, &info->errsts);
201 pci_read_config_dword(pdev, I82875P_EAP, &info->eap);
202 pci_read_config_byte(pdev, I82875P_DES, &info->des);
203 pci_read_config_byte(pdev, I82875P_DERRSYN, &info->derrsyn);
204 pci_read_config_word(pdev, I82875P_ERRSTS, &info->errsts2);
206 pci_write_bits16(pdev, I82875P_ERRSTS, 0x0081, 0x0081);
209 * If the error is the same then we can for both reads then
210 * the first set of reads is valid. If there is a change then
211 * there is a CE no info and the second set of reads is valid
212 * and should be UE info.
214 if (!(info->errsts2 & 0x0081))
217 if ((info->errsts ^ info->errsts2) & 0x0081) {
218 pci_read_config_dword(pdev, I82875P_EAP, &info->eap);
219 pci_read_config_byte(pdev, I82875P_DES, &info->des);
220 pci_read_config_byte(pdev, I82875P_DERRSYN, &info->derrsyn);
224 static int i82875p_process_error_info(struct mem_ctl_info *mci,
225 struct i82875p_error_info *info,
230 multi_chan = mci->csrows[0].nr_channels - 1;
232 if (!(info->errsts2 & 0x0081))
238 if ((info->errsts ^ info->errsts2) & 0x0081) {
239 edac_mc_handle_ce_no_info(mci, "UE overwrote CE");
240 info->errsts = info->errsts2;
243 info->eap >>= PAGE_SHIFT;
244 row = edac_mc_find_csrow_by_page(mci, info->eap);
246 if (info->errsts & 0x0080)
247 edac_mc_handle_ue(mci, info->eap, 0, row, "i82875p UE");
249 edac_mc_handle_ce(mci, info->eap, 0, info->derrsyn, row,
250 multi_chan ? (info->des & 0x1) : 0,
256 static void i82875p_check(struct mem_ctl_info *mci)
258 struct i82875p_error_info info;
260 debugf1("MC%d: %s()\n", mci->mc_idx, __func__);
261 i82875p_get_error_info(mci, &info);
262 i82875p_process_error_info(mci, &info, 1);
265 /* Return 0 on success or 1 on failure. */
266 static int i82875p_setup_overfl_dev(struct pci_dev *pdev,
267 struct pci_dev **ovrfl_pdev,
268 void __iomem **ovrfl_window)
271 void __iomem *window;
274 *ovrfl_window = NULL;
275 dev = pci_get_device(PCI_VEND_DEV(INTEL, 82875_6), NULL);
278 /* Intel tells BIOS developers to hide device 6 which
279 * configures the overflow device access containing
280 * the DRBs - this is where we expose device 6.
281 * http://www.x86-secret.com/articles/tweak/pat/patsecrets-2.htm
283 pci_write_bits8(pdev, 0xf4, 0x2, 0x2);
284 dev = pci_scan_single_device(pdev->bus, PCI_DEVFN(6, 0));
289 pci_bus_add_device(dev);
294 if (pci_enable_device(dev)) {
295 i82875p_printk(KERN_ERR, "%s(): Failed to enable overflow "
296 "device\n", __func__);
300 if (pci_request_regions(dev, pci_name(dev))) {
306 /* cache is irrelevant for PCI bus reads/writes */
307 window = ioremap_nocache(pci_resource_start(dev, 0),
308 pci_resource_len(dev, 0));
310 if (window == NULL) {
311 i82875p_printk(KERN_ERR, "%s(): Failed to ioremap bar6\n",
316 *ovrfl_window = window;
320 pci_release_regions(dev);
324 pci_disable_device(dev);
326 /* NOTE: the ovrfl proc entry and pci_dev are intentionally left */
330 /* Return 1 if dual channel mode is active. Else return 0. */
331 static inline int dual_channel_active(u32 drc)
333 return (drc >> 21) & 0x1;
336 static void i82875p_init_csrows(struct mem_ctl_info *mci,
337 struct pci_dev *pdev,
338 void __iomem * ovrfl_window, u32 drc)
340 struct csrow_info *csrow;
341 unsigned long last_cumul_size;
343 u32 drc_ddim; /* DRAM Data Integrity Mode 0=none,2=edac */
347 drc_ddim = (drc >> 18) & 0x1;
350 /* The dram row boundary (DRB) reg values are boundary address
351 * for each DRAM row with a granularity of 32 or 64MB (single/dual
352 * channel operation). DRB regs are cumulative; therefore DRB7 will
353 * contain the total memory contained in all eight rows.
356 for (index = 0; index < mci->nr_csrows; index++) {
357 csrow = &mci->csrows[index];
359 value = readb(ovrfl_window + I82875P_DRB + index);
360 cumul_size = value << (I82875P_DRB_SHIFT - PAGE_SHIFT);
361 debugf3("%s(): (%d) cumul_size 0x%x\n", __func__, index,
363 if (cumul_size == last_cumul_size)
364 continue; /* not populated */
366 csrow->first_page = last_cumul_size;
367 csrow->last_page = cumul_size - 1;
368 csrow->nr_pages = cumul_size - last_cumul_size;
369 last_cumul_size = cumul_size;
370 csrow->grain = 1 << 12; /* I82875P_EAP has 4KiB reolution */
371 csrow->mtype = MEM_DDR;
372 csrow->dtype = DEV_UNKNOWN;
373 csrow->edac_mode = drc_ddim ? EDAC_SECDED : EDAC_NONE;
377 static int i82875p_probe1(struct pci_dev *pdev, int dev_idx)
380 struct mem_ctl_info *mci;
381 struct i82875p_pvt *pvt;
382 struct pci_dev *ovrfl_pdev;
383 void __iomem *ovrfl_window;
386 struct i82875p_error_info discard;
388 debugf0("%s()\n", __func__);
389 ovrfl_pdev = pci_get_device(PCI_VEND_DEV(INTEL, 82875_6), NULL);
391 if (i82875p_setup_overfl_dev(pdev, &ovrfl_pdev, &ovrfl_window))
393 drc = readl(ovrfl_window + I82875P_DRC);
394 nr_chans = dual_channel_active(drc) + 1;
395 mci = edac_mc_alloc(sizeof(*pvt), I82875P_NR_CSROWS(nr_chans),
403 debugf3("%s(): init mci\n", __func__);
404 mci->dev = &pdev->dev;
405 mci->mtype_cap = MEM_FLAG_DDR;
406 mci->edac_ctl_cap = EDAC_FLAG_NONE | EDAC_FLAG_SECDED;
407 mci->edac_cap = EDAC_FLAG_UNKNOWN;
408 mci->mod_name = EDAC_MOD_STR;
409 mci->mod_ver = I82875P_REVISION;
410 mci->ctl_name = i82875p_devs[dev_idx].ctl_name;
411 mci->dev_name = pci_name(pdev);
412 mci->edac_check = i82875p_check;
413 mci->ctl_page_to_phys = NULL;
414 debugf3("%s(): init pvt\n", __func__);
415 pvt = (struct i82875p_pvt *)mci->pvt_info;
416 pvt->ovrfl_pdev = ovrfl_pdev;
417 pvt->ovrfl_window = ovrfl_window;
418 i82875p_init_csrows(mci, pdev, ovrfl_window, drc);
419 i82875p_get_error_info(mci, &discard); /* clear counters */
421 /* Here we assume that we will never see multiple instances of this
422 * type of memory controller. The ID is therefore hardcoded to 0.
424 if (edac_mc_add_mc(mci, 0)) {
425 debugf3("%s(): failed edac_mc_add_mc()\n", __func__);
429 /* allocating generic PCI control info */
430 i82875p_pci = edac_pci_create_generic_ctl(&pdev->dev, EDAC_MOD_STR);
433 "%s(): Unable to create PCI control\n",
436 "%s(): PCI error report via EDAC not setup\n",
440 /* get this far and it's successful */
441 debugf3("%s(): success\n", __func__);
448 iounmap(ovrfl_window);
449 pci_release_regions(ovrfl_pdev);
451 pci_disable_device(ovrfl_pdev);
452 /* NOTE: the ovrfl proc entry and pci_dev are intentionally left */
456 /* returns count (>= 0), or negative on error */
457 static int __devinit i82875p_init_one(struct pci_dev *pdev,
458 const struct pci_device_id *ent)
462 debugf0("%s()\n", __func__);
463 i82875p_printk(KERN_INFO, "i82875p init one\n");
465 if (pci_enable_device(pdev) < 0)
468 rc = i82875p_probe1(pdev, ent->driver_data);
470 if (mci_pdev == NULL)
471 mci_pdev = pci_dev_get(pdev);
476 static void __devexit i82875p_remove_one(struct pci_dev *pdev)
478 struct mem_ctl_info *mci;
479 struct i82875p_pvt *pvt = NULL;
481 debugf0("%s()\n", __func__);
484 edac_pci_release_generic_ctl(i82875p_pci);
486 if ((mci = edac_mc_del_mc(&pdev->dev)) == NULL)
489 pvt = (struct i82875p_pvt *)mci->pvt_info;
491 if (pvt->ovrfl_window)
492 iounmap(pvt->ovrfl_window);
494 if (pvt->ovrfl_pdev) {
496 pci_release_regions(pvt->ovrfl_pdev);
497 #endif /*CORRECT_BIOS */
498 pci_disable_device(pvt->ovrfl_pdev);
499 pci_dev_put(pvt->ovrfl_pdev);
505 static const struct pci_device_id i82875p_pci_tbl[] __devinitdata = {
507 PCI_VEND_DEV(INTEL, 82875_0), PCI_ANY_ID, PCI_ANY_ID, 0, 0,
511 } /* 0 terminated list. */
514 MODULE_DEVICE_TABLE(pci, i82875p_pci_tbl);
516 static struct pci_driver i82875p_driver = {
517 .name = EDAC_MOD_STR,
518 .probe = i82875p_init_one,
519 .remove = __devexit_p(i82875p_remove_one),
520 .id_table = i82875p_pci_tbl,
523 static int __init i82875p_init(void)
527 debugf3("%s()\n", __func__);
528 pci_rc = pci_register_driver(&i82875p_driver);
533 if (mci_pdev == NULL) {
534 mci_pdev = pci_get_device(PCI_VENDOR_ID_INTEL,
535 PCI_DEVICE_ID_INTEL_82875_0, NULL);
538 debugf0("875p pci_get_device fail\n");
543 pci_rc = i82875p_init_one(mci_pdev, i82875p_pci_tbl);
546 debugf0("875p init fail\n");
555 pci_unregister_driver(&i82875p_driver);
558 if (mci_pdev != NULL)
559 pci_dev_put(mci_pdev);
564 static void __exit i82875p_exit(void)
566 debugf3("%s()\n", __func__);
568 pci_unregister_driver(&i82875p_driver);
570 if (!i82875p_registered) {
571 i82875p_remove_one(mci_pdev);
572 pci_dev_put(mci_pdev);
576 module_init(i82875p_init);
577 module_exit(i82875p_exit);
579 MODULE_LICENSE("GPL");
580 MODULE_AUTHOR("Linux Networx (http://lnxi.com) Thayne Harbaugh");
581 MODULE_DESCRIPTION("MC support for Intel 82875 memory hub controllers");