3 * (C) 2003 Linux Networx (http://lnxi.com)
4 * This file may be distributed under the terms of the
5 * GNU General Public License.
7 * Written by Thayne Harbaugh
8 * Based on work by Dan Hollis <goemon at anime dot net> and others.
9 * http://www.anime.net/~goemon/linux-ecc/
11 * NMI handling support added by
12 * Dave Peterson <dsp@llnl.gov> <dave_peterson@pobox.com>
14 * $Id: edac_mc.h,v 1.4.2.10 2005/10/05 00:43:44 dsp_llnl Exp $
21 #include <linux/kernel.h>
22 #include <linux/types.h>
23 #include <linux/module.h>
24 #include <linux/spinlock.h>
25 #include <linux/smp.h>
26 #include <linux/pci.h>
27 #include <linux/time.h>
28 #include <linux/nmi.h>
29 #include <linux/rcupdate.h>
30 #include <linux/completion.h>
31 #include <linux/kobject.h>
33 #define EDAC_MC_LABEL_LEN 31
34 #define MC_PROC_NAME_MAX_LEN 7
37 #define PAGES_TO_MiB( pages ) ( ( pages ) >> ( 20 - PAGE_SHIFT ) )
38 #else /* PAGE_SHIFT > 20 */
39 #define PAGES_TO_MiB( pages ) ( ( pages ) << ( PAGE_SHIFT - 20 ) )
42 #define edac_printk(level, prefix, fmt, arg...) \
43 printk(level "EDAC " prefix ": " fmt, ##arg)
45 #define edac_mc_printk(mci, level, fmt, arg...) \
46 printk(level "EDAC MC%d: " fmt, mci->mc_idx, ##arg)
48 #define edac_mc_chipset_printk(mci, level, prefix, fmt, arg...) \
49 printk(level "EDAC " prefix " MC%d: " fmt, mci->mc_idx, ##arg)
51 /* prefixes for edac_printk() and edac_mc_printk() */
53 #define EDAC_PCI "PCI"
54 #define EDAC_DEBUG "DEBUG"
56 #ifdef CONFIG_EDAC_DEBUG
57 extern int edac_debug_level;
59 #define edac_debug_printk(level, fmt, arg...) \
61 if (level <= edac_debug_level) \
62 edac_printk(KERN_DEBUG, EDAC_DEBUG, fmt, ##arg); \
65 #define debugf0( ... ) edac_debug_printk(0, __VA_ARGS__ )
66 #define debugf1( ... ) edac_debug_printk(1, __VA_ARGS__ )
67 #define debugf2( ... ) edac_debug_printk(2, __VA_ARGS__ )
68 #define debugf3( ... ) edac_debug_printk(3, __VA_ARGS__ )
69 #define debugf4( ... ) edac_debug_printk(4, __VA_ARGS__ )
71 #else /* !CONFIG_EDAC_DEBUG */
73 #define debugf0( ... )
74 #define debugf1( ... )
75 #define debugf2( ... )
76 #define debugf3( ... )
77 #define debugf4( ... )
79 #endif /* !CONFIG_EDAC_DEBUG */
81 #define edac_xstr(s) edac_str(s)
82 #define edac_str(s) #s
83 #define EDAC_MOD_STR edac_xstr(KBUILD_BASENAME)
85 #define BIT(x) (1 << (x))
87 #define PCI_VEND_DEV(vend, dev) PCI_VENDOR_ID_ ## vend, \
88 PCI_DEVICE_ID_ ## vend ## _ ## dev
98 DEV_X32, /* Do these parts exist? */
99 DEV_X64 /* Do these parts exist? */
102 #define DEV_FLAG_UNKNOWN BIT(DEV_UNKNOWN)
103 #define DEV_FLAG_X1 BIT(DEV_X1)
104 #define DEV_FLAG_X2 BIT(DEV_X2)
105 #define DEV_FLAG_X4 BIT(DEV_X4)
106 #define DEV_FLAG_X8 BIT(DEV_X8)
107 #define DEV_FLAG_X16 BIT(DEV_X16)
108 #define DEV_FLAG_X32 BIT(DEV_X32)
109 #define DEV_FLAG_X64 BIT(DEV_X64)
113 MEM_EMPTY = 0, /* Empty csrow */
114 MEM_RESERVED, /* Reserved csrow type */
115 MEM_UNKNOWN, /* Unknown csrow type */
116 MEM_FPM, /* Fast page mode */
117 MEM_EDO, /* Extended data out */
118 MEM_BEDO, /* Burst Extended data out */
119 MEM_SDR, /* Single data rate SDRAM */
120 MEM_RDR, /* Registered single data rate SDRAM */
121 MEM_DDR, /* Double data rate SDRAM */
122 MEM_RDDR, /* Registered Double data rate SDRAM */
123 MEM_RMBS /* Rambus DRAM */
126 #define MEM_FLAG_EMPTY BIT(MEM_EMPTY)
127 #define MEM_FLAG_RESERVED BIT(MEM_RESERVED)
128 #define MEM_FLAG_UNKNOWN BIT(MEM_UNKNOWN)
129 #define MEM_FLAG_FPM BIT(MEM_FPM)
130 #define MEM_FLAG_EDO BIT(MEM_EDO)
131 #define MEM_FLAG_BEDO BIT(MEM_BEDO)
132 #define MEM_FLAG_SDR BIT(MEM_SDR)
133 #define MEM_FLAG_RDR BIT(MEM_RDR)
134 #define MEM_FLAG_DDR BIT(MEM_DDR)
135 #define MEM_FLAG_RDDR BIT(MEM_RDDR)
136 #define MEM_FLAG_RMBS BIT(MEM_RMBS)
138 /* chipset Error Detection and Correction capabilities and mode */
140 EDAC_UNKNOWN = 0, /* Unknown if ECC is available */
141 EDAC_NONE, /* Doesnt support ECC */
142 EDAC_RESERVED, /* Reserved ECC type */
143 EDAC_PARITY, /* Detects parity errors */
144 EDAC_EC, /* Error Checking - no correction */
145 EDAC_SECDED, /* Single bit error correction, Double detection */
146 EDAC_S2ECD2ED, /* Chipkill x2 devices - do these exist? */
147 EDAC_S4ECD4ED, /* Chipkill x4 devices */
148 EDAC_S8ECD8ED, /* Chipkill x8 devices */
149 EDAC_S16ECD16ED, /* Chipkill x16 devices */
152 #define EDAC_FLAG_UNKNOWN BIT(EDAC_UNKNOWN)
153 #define EDAC_FLAG_NONE BIT(EDAC_NONE)
154 #define EDAC_FLAG_PARITY BIT(EDAC_PARITY)
155 #define EDAC_FLAG_EC BIT(EDAC_EC)
156 #define EDAC_FLAG_SECDED BIT(EDAC_SECDED)
157 #define EDAC_FLAG_S2ECD2ED BIT(EDAC_S2ECD2ED)
158 #define EDAC_FLAG_S4ECD4ED BIT(EDAC_S4ECD4ED)
159 #define EDAC_FLAG_S8ECD8ED BIT(EDAC_S8ECD8ED)
160 #define EDAC_FLAG_S16ECD16ED BIT(EDAC_S16ECD16ED)
162 /* scrubbing capabilities */
164 SCRUB_UNKNOWN = 0, /* Unknown if scrubber is available */
165 SCRUB_NONE, /* No scrubber */
166 SCRUB_SW_PROG, /* SW progressive (sequential) scrubbing */
167 SCRUB_SW_SRC, /* Software scrub only errors */
168 SCRUB_SW_PROG_SRC, /* Progressive software scrub from an error */
169 SCRUB_SW_TUNABLE, /* Software scrub frequency is tunable */
170 SCRUB_HW_PROG, /* HW progressive (sequential) scrubbing */
171 SCRUB_HW_SRC, /* Hardware scrub only errors */
172 SCRUB_HW_PROG_SRC, /* Progressive hardware scrub from an error */
173 SCRUB_HW_TUNABLE /* Hardware scrub frequency is tunable */
176 #define SCRUB_FLAG_SW_PROG BIT(SCRUB_SW_PROG)
177 #define SCRUB_FLAG_SW_SRC BIT(SCRUB_SW_SRC_CORR)
178 #define SCRUB_FLAG_SW_PROG_SRC BIT(SCRUB_SW_PROG_SRC_CORR)
179 #define SCRUB_FLAG_SW_TUN BIT(SCRUB_SW_SCRUB_TUNABLE)
180 #define SCRUB_FLAG_HW_PROG BIT(SCRUB_HW_PROG)
181 #define SCRUB_FLAG_HW_SRC BIT(SCRUB_HW_SRC_CORR)
182 #define SCRUB_FLAG_HW_PROG_SRC BIT(SCRUB_HW_PROG_SRC_CORR)
183 #define SCRUB_FLAG_HW_TUN BIT(SCRUB_HW_TUNABLE)
185 /* FIXME - should have notify capabilities: NMI, LOG, PROC, etc */
188 * There are several things to be aware of that aren't at all obvious:
191 * SOCKETS, SOCKET SETS, BANKS, ROWS, CHIP-SELECT ROWS, CHANNELS, etc..
193 * These are some of the many terms that are thrown about that don't always
194 * mean what people think they mean (Inconceivable!). In the interest of
195 * creating a common ground for discussion, terms and their definitions
196 * will be established.
198 * Memory devices: The individual chip on a memory stick. These devices
199 * commonly output 4 and 8 bits each. Grouping several
200 * of these in parallel provides 64 bits which is common
201 * for a memory stick.
203 * Memory Stick: A printed circuit board that agregates multiple
204 * memory devices in parallel. This is the atomic
205 * memory component that is purchaseable by Joe consumer
206 * and loaded into a memory socket.
208 * Socket: A physical connector on the motherboard that accepts
209 * a single memory stick.
211 * Channel: Set of memory devices on a memory stick that must be
212 * grouped in parallel with one or more additional
213 * channels from other memory sticks. This parallel
214 * grouping of the output from multiple channels are
215 * necessary for the smallest granularity of memory access.
216 * Some memory controllers are capable of single channel -
217 * which means that memory sticks can be loaded
218 * individually. Other memory controllers are only
219 * capable of dual channel - which means that memory
220 * sticks must be loaded as pairs (see "socket set").
222 * Chip-select row: All of the memory devices that are selected together.
223 * for a single, minimum grain of memory access.
224 * This selects all of the parallel memory devices across
225 * all of the parallel channels. Common chip-select rows
226 * for single channel are 64 bits, for dual channel 128
229 * Single-Ranked stick: A Single-ranked stick has 1 chip-select row of memmory.
230 * Motherboards commonly drive two chip-select pins to
231 * a memory stick. A single-ranked stick, will occupy
232 * only one of those rows. The other will be unused.
234 * Double-Ranked stick: A double-ranked stick has two chip-select rows which
235 * access different sets of memory devices. The two
236 * rows cannot be accessed concurrently.
238 * Double-sided stick: DEPRECATED TERM, see Double-Ranked stick.
239 * A double-sided stick has two chip-select rows which
240 * access different sets of memory devices. The two
241 * rows cannot be accessed concurrently. "Double-sided"
242 * is irrespective of the memory devices being mounted
243 * on both sides of the memory stick.
245 * Socket set: All of the memory sticks that are required for for
246 * a single memory access or all of the memory sticks
247 * spanned by a chip-select row. A single socket set
248 * has two chip-select rows and if double-sided sticks
249 * are used these will occupy those chip-select rows.
251 * Bank: This term is avoided because it is unclear when
252 * needing to distinguish between chip-select rows and
262 * STRUCTURE ORGANIZATION AND CHOICES
266 * PS - I enjoyed writing all that about as much as you enjoyed reading it.
269 struct channel_info {
270 int chan_idx; /* channel index */
271 u32 ce_count; /* Correctable Errors for this CHANNEL */
272 char label[EDAC_MC_LABEL_LEN + 1]; /* DIMM label on motherboard */
273 struct csrow_info *csrow; /* the parent */
277 unsigned long first_page; /* first page number in dimm */
278 unsigned long last_page; /* last page number in dimm */
279 unsigned long page_mask; /* used for interleaving -
282 u32 nr_pages; /* number of pages in csrow */
283 u32 grain; /* granularity of reported error in bytes */
284 int csrow_idx; /* the chip-select row */
285 enum dev_type dtype; /* memory device type */
286 u32 ue_count; /* Uncorrectable Errors for this csrow */
287 u32 ce_count; /* Correctable Errors for this csrow */
288 enum mem_type mtype; /* memory csrow type */
289 enum edac_type edac_mode; /* EDAC mode for this csrow */
290 struct mem_ctl_info *mci; /* the parent */
292 struct kobject kobj; /* sysfs kobject for this csrow */
293 struct completion kobj_complete;
295 /* FIXME the number of CHANNELs might need to become dynamic */
297 struct channel_info *channels;
300 struct mem_ctl_info {
301 struct list_head link; /* for global list of mem_ctl_info structs */
302 unsigned long mtype_cap; /* memory types supported by mc */
303 unsigned long edac_ctl_cap; /* Mem controller EDAC capabilities */
304 unsigned long edac_cap; /* configuration capabilities - this is
305 * closely related to edac_ctl_cap. The
306 * difference is that the controller may be
307 * capable of s4ecd4ed which would be listed
308 * in edac_ctl_cap, but if channels aren't
309 * capable of s4ecd4ed then the edac_cap would
310 * not have that capability.
312 unsigned long scrub_cap; /* chipset scrub capabilities */
313 enum scrub_type scrub_mode; /* current scrub mode */
315 /* pointer to edac checking routine */
316 void (*edac_check) (struct mem_ctl_info * mci);
318 * Remaps memory pages: controller pages to physical pages.
319 * For most MC's, this will be NULL.
321 /* FIXME - why not send the phys page to begin with? */
322 unsigned long (*ctl_page_to_phys) (struct mem_ctl_info * mci,
326 struct csrow_info *csrows;
328 * FIXME - what about controllers on other busses? - IDs must be
329 * unique. pdev pointer should be sufficiently unique, but
330 * BUS:SLOT.FUNC numbers may not be unique.
332 struct pci_dev *pdev;
333 const char *mod_name;
335 const char *ctl_name;
336 char proc_name[MC_PROC_NAME_MAX_LEN + 1];
338 u32 ue_noinfo_count; /* Uncorrectable Errors w/o info */
339 u32 ce_noinfo_count; /* Correctable Errors w/o info */
340 u32 ue_count; /* Total Uncorrectable Errors for this MC */
341 u32 ce_count; /* Total Correctable Errors for this MC */
342 unsigned long start_time; /* mci load start time (in jiffies) */
344 /* this stuff is for safe removal of mc devices from global list while
345 * NMI handlers may be traversing list
348 struct completion complete;
350 /* edac sysfs device control */
351 struct kobject edac_mci_kobj;
352 struct completion kobj_complete;
355 /* write all or some bits in a byte-register*/
356 static inline void pci_write_bits8(struct pci_dev *pdev, int offset, u8 value,
362 pci_read_config_byte(pdev, offset, &buf);
368 pci_write_config_byte(pdev, offset, value);
371 /* write all or some bits in a word-register*/
372 static inline void pci_write_bits16(struct pci_dev *pdev, int offset,
375 if (mask != 0xffff) {
378 pci_read_config_word(pdev, offset, &buf);
384 pci_write_config_word(pdev, offset, value);
387 /* write all or some bits in a dword-register*/
388 static inline void pci_write_bits32(struct pci_dev *pdev, int offset,
391 if (mask != 0xffff) {
394 pci_read_config_dword(pdev, offset, &buf);
400 pci_write_config_dword(pdev, offset, value);
403 #ifdef CONFIG_EDAC_DEBUG
404 void edac_mc_dump_channel(struct channel_info *chan);
405 void edac_mc_dump_mci(struct mem_ctl_info *mci);
406 void edac_mc_dump_csrow(struct csrow_info *csrow);
407 #endif /* CONFIG_EDAC_DEBUG */
409 extern int edac_mc_add_mc(struct mem_ctl_info *mci);
410 extern struct mem_ctl_info * edac_mc_del_mc(struct pci_dev *pdev);
411 extern int edac_mc_find_csrow_by_page(struct mem_ctl_info *mci,
413 extern void edac_mc_scrub_block(unsigned long page, unsigned long offset,
417 * The no info errors are used when error overflows are reported.
418 * There are a limited number of error logging registers that can
419 * be exausted. When all registers are exhausted and an additional
420 * error occurs then an error overflow register records that an
421 * error occured and the type of error, but doesn't have any
422 * further information. The ce/ue versions make for cleaner
423 * reporting logic and function interface - reduces conditional
424 * statement clutter and extra function arguments.
426 extern void edac_mc_handle_ce(struct mem_ctl_info *mci,
427 unsigned long page_frame_number, unsigned long offset_in_page,
428 unsigned long syndrome, int row, int channel,
430 extern void edac_mc_handle_ce_no_info(struct mem_ctl_info *mci,
432 extern void edac_mc_handle_ue(struct mem_ctl_info *mci,
433 unsigned long page_frame_number, unsigned long offset_in_page,
434 int row, const char *msg);
435 extern void edac_mc_handle_ue_no_info(struct mem_ctl_info *mci,
439 * This kmalloc's and initializes all the structures.
440 * Can't be used if all structures don't have the same lifetime.
442 extern struct mem_ctl_info *edac_mc_alloc(unsigned sz_pvt, unsigned nr_csrows,
445 /* Free an mc previously allocated by edac_mc_alloc() */
446 extern void edac_mc_free(struct mem_ctl_info *mci);
448 #endif /* _EDAC_MC_H_ */