err.no Git - linux-2.6/blob - drivers/edac/e7xxx_edac.c

   1 /*
   2  * Intel e7xxx Memory Controller kernel module
   3  * (C) 2003 Linux Networx (http://lnxi.com)
   4  * This file may be distributed under the terms of the
   5  * GNU General Public License.
   6  *
   7  * See "enum e7xxx_chips" below for supported chipsets
   8  *
   9  * Written by Thayne Harbaugh
  10  * Based on work by Dan Hollis <goemon at anime dot net> and others.
  11  *      http://www.anime.net/~goemon/linux-ecc/
  12  *
  13  * Contributors:
  14  *      Eric Biederman (Linux Networx)
  15  *      Tom Zimmerman (Linux Networx)
  16  *      Jim Garlick (Lawrence Livermore National Labs)
  17  *      Dave Peterson (Lawrence Livermore National Labs)
  18  *      That One Guy (Some other place)
  19  *      Wang Zhenyu (intel.com)
  20  *
  21  * $Id: edac_e7xxx.c,v 1.5.2.9 2005/10/05 00:43:44 dsp_llnl Exp $
  22  *
  23  */
  24
  25 #include <linux/module.h>
  26 #include <linux/init.h>
  27 #include <linux/pci.h>
  28 #include <linux/pci_ids.h>
  29 #include <linux/slab.h>
  30 #include <linux/edac.h>
  31 #include "edac_mc.h"
  32
  33 #define E7XXX_REVISION " Ver: 2.0.1 " __DATE__
  34 #define EDAC_MOD_STR    "e7xxx_edac"
  35
  36 #define e7xxx_printk(level, fmt, arg...) \
  37         edac_printk(level, "e7xxx", fmt, ##arg)
  38
  39 #define e7xxx_mc_printk(mci, level, fmt, arg...) \
  40         edac_mc_chipset_printk(mci, level, "e7xxx", fmt, ##arg)
  41
  42 #ifndef PCI_DEVICE_ID_INTEL_7205_0
  43 #define PCI_DEVICE_ID_INTEL_7205_0      0x255d
  44 #endif                          /* PCI_DEVICE_ID_INTEL_7205_0 */
  45
  46 #ifndef PCI_DEVICE_ID_INTEL_7205_1_ERR
  47 #define PCI_DEVICE_ID_INTEL_7205_1_ERR  0x2551
  48 #endif                          /* PCI_DEVICE_ID_INTEL_7205_1_ERR */
  49
  50 #ifndef PCI_DEVICE_ID_INTEL_7500_0
  51 #define PCI_DEVICE_ID_INTEL_7500_0      0x2540
  52 #endif                          /* PCI_DEVICE_ID_INTEL_7500_0 */
  53
  54 #ifndef PCI_DEVICE_ID_INTEL_7500_1_ERR
  55 #define PCI_DEVICE_ID_INTEL_7500_1_ERR  0x2541
  56 #endif                          /* PCI_DEVICE_ID_INTEL_7500_1_ERR */
  57
  58 #ifndef PCI_DEVICE_ID_INTEL_7501_0
  59 #define PCI_DEVICE_ID_INTEL_7501_0      0x254c
  60 #endif                          /* PCI_DEVICE_ID_INTEL_7501_0 */
  61
  62 #ifndef PCI_DEVICE_ID_INTEL_7501_1_ERR
  63 #define PCI_DEVICE_ID_INTEL_7501_1_ERR  0x2541
  64 #endif                          /* PCI_DEVICE_ID_INTEL_7501_1_ERR */
  65
  66 #ifndef PCI_DEVICE_ID_INTEL_7505_0
  67 #define PCI_DEVICE_ID_INTEL_7505_0      0x2550
  68 #endif                          /* PCI_DEVICE_ID_INTEL_7505_0 */
  69
  70 #ifndef PCI_DEVICE_ID_INTEL_7505_1_ERR
  71 #define PCI_DEVICE_ID_INTEL_7505_1_ERR  0x2551
  72 #endif                          /* PCI_DEVICE_ID_INTEL_7505_1_ERR */
  73
  74 #define E7XXX_NR_CSROWS         8       /* number of csrows */
  75 #define E7XXX_NR_DIMMS          8       /* FIXME - is this correct? */
  76
  77 /* E7XXX register addresses - device 0 function 0 */
  78 #define E7XXX_DRB               0x60    /* DRAM row boundary register (8b) */
  79 #define E7XXX_DRA               0x70    /* DRAM row attribute register (8b) */
  80                                         /*
  81                                          * 31   Device width row 7 0=x8 1=x4
  82                                          * 27   Device width row 6
  83                                          * 23   Device width row 5
  84                                          * 19   Device width row 4
  85                                          * 15   Device width row 3
  86                                          * 11   Device width row 2
  87                                          *  7   Device width row 1
  88                                          *  3   Device width row 0
  89                                          */
  90 #define E7XXX_DRC               0x7C    /* DRAM controller mode reg (32b) */
  91                                         /*
  92                                          * 22    Number channels 0=1,1=2
  93                                          * 19:18 DRB Granularity 32/64MB
  94                                          */
  95 #define E7XXX_TOLM              0xC4    /* DRAM top of low memory reg (16b) */
  96 #define E7XXX_REMAPBASE         0xC6    /* DRAM remap base address reg (16b) */
  97 #define E7XXX_REMAPLIMIT        0xC8    /* DRAM remap limit address reg (16b) */
  98
  99 /* E7XXX register addresses - device 0 function 1 */
 100 #define E7XXX_DRAM_FERR         0x80    /* DRAM first error register (8b) */
 101 #define E7XXX_DRAM_NERR         0x82    /* DRAM next error register (8b) */
 102 #define E7XXX_DRAM_CELOG_ADD    0xA0    /* DRAM first correctable memory */
 103                                         /*     error address register (32b) */
 104                                         /*
 105                                          * 31:28 Reserved
 106                                          * 27:6  CE address (4k block 33:12)
 107                                          *  5:0  Reserved
 108                                          */
 109 #define E7XXX_DRAM_UELOG_ADD    0xB0    /* DRAM first uncorrectable memory */
 110                                         /*     error address register (32b) */
 111                                         /*
 112                                          * 31:28 Reserved
 113                                          * 27:6  CE address (4k block 33:12)
 114                                          *  5:0  Reserved
 115                                          */
 116 #define E7XXX_DRAM_CELOG_SYNDROME 0xD0  /* DRAM first correctable memory */
 117                                         /*     error syndrome register (16b) */
 118
 119 enum e7xxx_chips {
 120         E7500 = 0,
 121         E7501,
 122         E7505,
 123         E7205,
 124 };
 125
 126 struct e7xxx_pvt {
 127         struct pci_dev *bridge_ck;
 128         u32 tolm;
 129         u32 remapbase;
 130         u32 remaplimit;
 131         const struct e7xxx_dev_info *dev_info;
 132 };
 133
 134 struct e7xxx_dev_info {
 135         u16 err_dev;
 136         const char *ctl_name;
 137 };
 138
 139 struct e7xxx_error_info {
 140         u8 dram_ferr;
 141         u8 dram_nerr;
 142         u32 dram_celog_add;
 143         u16 dram_celog_syndrome;
 144         u32 dram_uelog_add;
 145 };
 146
 147 static const struct e7xxx_dev_info e7xxx_devs[] = {
 148         [E7500] = {
 149                 .err_dev = PCI_DEVICE_ID_INTEL_7500_1_ERR,
 150                 .ctl_name = "E7500"
 151         },
 152         [E7501] = {
 153                 .err_dev = PCI_DEVICE_ID_INTEL_7501_1_ERR,
 154                 .ctl_name = "E7501"
 155         },
 156         [E7505] = {
 157                 .err_dev = PCI_DEVICE_ID_INTEL_7505_1_ERR,
 158                 .ctl_name = "E7505"
 159         },
 160         [E7205] = {
 161                 .err_dev = PCI_DEVICE_ID_INTEL_7205_1_ERR,
 162                 .ctl_name = "E7205"
 163         },
 164 };
 165
 166 /* FIXME - is this valid for both SECDED and S4ECD4ED? */
 167 static inline int e7xxx_find_channel(u16 syndrome)
 168 {
 169         debugf3("%s()\n", __func__);
 170
 171         if ((syndrome & 0xff00) == 0)
 172                 return 0;
 173
 174         if ((syndrome & 0x00ff) == 0)
 175                 return 1;
 176
 177         if ((syndrome & 0xf000) == 0 || (syndrome & 0x0f00) == 0)
 178                 return 0;
 179
 180         return 1;
 181 }
 182
 183 static unsigned long ctl_page_to_phys(struct mem_ctl_info *mci,
 184                 unsigned long page)
 185 {
 186         u32 remap;
 187         struct e7xxx_pvt *pvt = (struct e7xxx_pvt *) mci->pvt_info;
 188
 189         debugf3("%s()\n", __func__);
 190
 191         if ((page < pvt->tolm) ||
 192                         ((page >= 0x100000) && (page < pvt->remapbase)))
 193                 return page;
 194
 195         remap = (page - pvt->tolm) + pvt->remapbase;
 196
 197         if (remap < pvt->remaplimit)
 198                 return remap;
 199
 200         e7xxx_printk(KERN_ERR, "Invalid page %lx - out of range\n", page);
 201         return pvt->tolm - 1;
 202 }
 203
 204 static void process_ce(struct mem_ctl_info *mci,
 205                 struct e7xxx_error_info *info)
 206 {
 207         u32 error_1b, page;
 208         u16 syndrome;
 209         int row;
 210         int channel;
 211
 212         debugf3("%s()\n", __func__);
 213         /* read the error address */
 214         error_1b = info->dram_celog_add;
 215         /* FIXME - should use PAGE_SHIFT */
 216         page = error_1b >> 6;  /* convert the address to 4k page */
 217         /* read the syndrome */
 218         syndrome = info->dram_celog_syndrome;
 219         /* FIXME - check for -1 */
 220         row = edac_mc_find_csrow_by_page(mci, page);
 221         /* convert syndrome to channel */
 222         channel = e7xxx_find_channel(syndrome);
 223         edac_mc_handle_ce(mci, page, 0, syndrome, row, channel, "e7xxx CE");
 224 }
 225
 226 static void process_ce_no_info(struct mem_ctl_info *mci)
 227 {
 228         debugf3("%s()\n", __func__);
 229         edac_mc_handle_ce_no_info(mci, "e7xxx CE log register overflow");
 230 }
 231
 232 static void process_ue(struct mem_ctl_info *mci,
 233                 struct e7xxx_error_info *info)
 234 {
 235         u32 error_2b, block_page;
 236         int row;
 237
 238         debugf3("%s()\n", __func__);
 239         /* read the error address */
 240         error_2b = info->dram_uelog_add;
 241         /* FIXME - should use PAGE_SHIFT */
 242         block_page = error_2b >> 6;  /* convert to 4k address */
 243         row = edac_mc_find_csrow_by_page(mci, block_page);
 244         edac_mc_handle_ue(mci, block_page, 0, row, "e7xxx UE");
 245 }
 246
 247 static void process_ue_no_info(struct mem_ctl_info *mci)
 248 {
 249         debugf3("%s()\n", __func__);
 250         edac_mc_handle_ue_no_info(mci, "e7xxx UE log register overflow");
 251 }
 252
 253 static void e7xxx_get_error_info (struct mem_ctl_info *mci,
 254                 struct e7xxx_error_info *info)
 255 {
 256         struct e7xxx_pvt *pvt;
 257
 258         pvt = (struct e7xxx_pvt *) mci->pvt_info;
 259         pci_read_config_byte(pvt->bridge_ck, E7XXX_DRAM_FERR,
 260                         &info->dram_ferr);
 261         pci_read_config_byte(pvt->bridge_ck, E7XXX_DRAM_NERR,
 262                         &info->dram_nerr);
 263
 264         if ((info->dram_ferr & 1) || (info->dram_nerr & 1)) {
 265                 pci_read_config_dword(pvt->bridge_ck, E7XXX_DRAM_CELOG_ADD,
 266                                 &info->dram_celog_add);
 267                 pci_read_config_word(pvt->bridge_ck,
 268                                 E7XXX_DRAM_CELOG_SYNDROME,
 269                                 &info->dram_celog_syndrome);
 270         }
 271
 272         if ((info->dram_ferr & 2) || (info->dram_nerr & 2))
 273                 pci_read_config_dword(pvt->bridge_ck, E7XXX_DRAM_UELOG_ADD,
 274                                 &info->dram_uelog_add);
 275
 276         if (info->dram_ferr & 3)
 277                 pci_write_bits8(pvt->bridge_ck, E7XXX_DRAM_FERR, 0x03, 0x03);
 278
 279         if (info->dram_nerr & 3)
 280                 pci_write_bits8(pvt->bridge_ck, E7XXX_DRAM_NERR, 0x03, 0x03);
 281 }
 282
 283 static int e7xxx_process_error_info (struct mem_ctl_info *mci,
 284                 struct e7xxx_error_info *info, int handle_errors)
 285 {
 286         int error_found;
 287
 288         error_found = 0;
 289
 290         /* decode and report errors */
 291         if (info->dram_ferr & 1) {      /* check first error correctable */
 292                 error_found = 1;
 293
 294                 if (handle_errors)
 295                         process_ce(mci, info);
 296         }
 297
 298         if (info->dram_ferr & 2) {      /* check first error uncorrectable */
 299                 error_found = 1;
 300
 301                 if (handle_errors)
 302                         process_ue(mci, info);
 303         }
 304
 305         if (info->dram_nerr & 1) {      /* check next error correctable */
 306                 error_found = 1;
 307
 308                 if (handle_errors) {
 309                         if (info->dram_ferr & 1)
 310                                 process_ce_no_info(mci);
 311                         else
 312                                 process_ce(mci, info);
 313                 }
 314         }
 315
 316         if (info->dram_nerr & 2) {      /* check next error uncorrectable */
 317                 error_found = 1;
 318
 319                 if (handle_errors) {
 320                         if (info->dram_ferr & 2)
 321                                 process_ue_no_info(mci);
 322                         else
 323                                 process_ue(mci, info);
 324                 }
 325         }
 326
 327         return error_found;
 328 }
 329
 330 static void e7xxx_check(struct mem_ctl_info *mci)
 331 {
 332         struct e7xxx_error_info info;
 333
 334         debugf3("%s()\n", __func__);
 335         e7xxx_get_error_info(mci, &info);
 336         e7xxx_process_error_info(mci, &info, 1);
 337 }
 338
 339 /* Return 1 if dual channel mode is active.  Else return 0. */
 340 static inline int dual_channel_active(u32 drc, int dev_idx)
 341 {
 342         return (dev_idx == E7501) ? ((drc >> 22) & 0x1) : 1;
 343 }
 344
 345
 346 /* Return DRB granularity (0=32mb, 1=64mb). */
 347 static inline int drb_granularity(u32 drc, int dev_idx)
 348 {
 349         /* only e7501 can be single channel */
 350         return (dev_idx == E7501) ? ((drc >> 18) & 0x3) : 1;
 351 }
 352
 353
 354 static void e7xxx_init_csrows(struct mem_ctl_info *mci, struct pci_dev *pdev,
 355                 int dev_idx, u32 drc)
 356 {
 357         unsigned long last_cumul_size;
 358         int index;
 359         u8 value;
 360         u32 dra, cumul_size;
 361         int drc_chan, drc_drbg, drc_ddim, mem_dev;
 362         struct csrow_info *csrow;
 363
 364         pci_read_config_dword(pdev, E7XXX_DRA, &dra);
 365         drc_chan = dual_channel_active(drc, dev_idx);
 366         drc_drbg = drb_granularity(drc, dev_idx);
 367         drc_ddim = (drc >> 20) & 0x3;
 368         last_cumul_size = 0;
 369
 370         /* The dram row boundary (DRB) reg values are boundary address
 371          * for each DRAM row with a granularity of 32 or 64MB (single/dual
 372          * channel operation).  DRB regs are cumulative; therefore DRB7 will
 373          * contain the total memory contained in all eight rows.
 374          */
 375         for (index = 0; index < mci->nr_csrows; index++) {
 376                 /* mem_dev 0=x8, 1=x4 */
 377                 mem_dev = (dra >> (index * 4 + 3)) & 0x1;
 378                 csrow = &mci->csrows[index];
 379
 380                 pci_read_config_byte(pdev, E7XXX_DRB + index, &value);
 381                 /* convert a 64 or 32 MiB DRB to a page size. */
 382                 cumul_size = value << (25 + drc_drbg - PAGE_SHIFT);
 383                 debugf3("%s(): (%d) cumul_size 0x%x\n", __func__, index,
 384                         cumul_size);
 385                 if (cumul_size == last_cumul_size)
 386                         continue;       /* not populated */
 387
 388                 csrow->first_page = last_cumul_size;
 389                 csrow->last_page = cumul_size - 1;
 390                 csrow->nr_pages = cumul_size - last_cumul_size;
 391                 last_cumul_size = cumul_size;
 392                 csrow->grain = 1 << 12; /* 4KiB - resolution of CELOG */
 393                 csrow->mtype = MEM_RDDR;        /* only one type supported */
 394                 csrow->dtype = mem_dev ? DEV_X4 : DEV_X8;
 395
 396                 /*
 397                  * if single channel or x8 devices then SECDED
 398                  * if dual channel and x4 then S4ECD4ED
 399                  */
 400                 if (drc_ddim) {
 401                         if (drc_chan && mem_dev) {
 402                                 csrow->edac_mode = EDAC_S4ECD4ED;
 403                                 mci->edac_cap |= EDAC_FLAG_S4ECD4ED;
 404                         } else {
 405                                 csrow->edac_mode = EDAC_SECDED;
 406                                 mci->edac_cap |= EDAC_FLAG_SECDED;
 407                         }
 408                 } else
 409                         csrow->edac_mode = EDAC_NONE;
 410         }
 411 }
 412
 413 static int e7xxx_probe1(struct pci_dev *pdev, int dev_idx)
 414 {
 415         u16 pci_data;
 416         struct mem_ctl_info *mci = NULL;
 417         struct e7xxx_pvt *pvt = NULL;
 418         u32 drc;
 419         int drc_chan;
 420         struct e7xxx_error_info discard;
 421
 422         debugf0("%s(): mci\n", __func__);
 423
 424         /* make sure error reporting method is sane */
 425         switch(edac_op_state) {
 426                 case EDAC_OPSTATE_POLL:
 427                 case EDAC_OPSTATE_NMI:
 428                         break;
 429                 default:
 430                         edac_op_state = EDAC_OPSTATE_POLL;
 431                         break;
 432         }
 433
 434         pci_read_config_dword(pdev, E7XXX_DRC, &drc);
 435
 436         drc_chan = dual_channel_active(drc, dev_idx);
 437         mci = edac_mc_alloc(sizeof(*pvt), E7XXX_NR_CSROWS, drc_chan + 1);
 438
 439         if (mci == NULL)
 440                 return -ENOMEM;
 441
 442         debugf3("%s(): init mci\n", __func__);
 443         mci->mtype_cap = MEM_FLAG_RDDR;
 444         mci->edac_ctl_cap = EDAC_FLAG_NONE | EDAC_FLAG_SECDED |
 445                         EDAC_FLAG_S4ECD4ED;
 446         /* FIXME - what if different memory types are in different csrows? */
 447         mci->mod_name = EDAC_MOD_STR;
 448         mci->mod_ver = E7XXX_REVISION;
 449         mci->dev = &pdev->dev;
 450         debugf3("%s(): init pvt\n", __func__);
 451         pvt = (struct e7xxx_pvt *) mci->pvt_info;
 452         pvt->dev_info = &e7xxx_devs[dev_idx];
 453         pvt->bridge_ck = pci_get_device(PCI_VENDOR_ID_INTEL,
 454                                         pvt->dev_info->err_dev,
 455                                         pvt->bridge_ck);
 456
 457         if (!pvt->bridge_ck) {
 458                 e7xxx_printk(KERN_ERR, "error reporting device not found:"
 459                         "vendor %x device 0x%x (broken BIOS?)\n",
 460                         PCI_VENDOR_ID_INTEL, e7xxx_devs[dev_idx].err_dev);
 461                 goto fail0;
 462         }
 463
 464         debugf3("%s(): more mci init\n", __func__);
 465         mci->ctl_name = pvt->dev_info->ctl_name;
 466         mci->edac_check = e7xxx_check;
 467         mci->ctl_page_to_phys = ctl_page_to_phys;
 468         e7xxx_init_csrows(mci, pdev, dev_idx, drc);
 469         mci->edac_cap |= EDAC_FLAG_NONE;
 470         debugf3("%s(): tolm, remapbase, remaplimit\n", __func__);
 471         /* load the top of low memory, remap base, and remap limit vars */
 472         pci_read_config_word(pdev, E7XXX_TOLM, &pci_data);
 473         pvt->tolm = ((u32) pci_data) << 4;
 474         pci_read_config_word(pdev, E7XXX_REMAPBASE, &pci_data);
 475         pvt->remapbase = ((u32) pci_data) << 14;
 476         pci_read_config_word(pdev, E7XXX_REMAPLIMIT, &pci_data);
 477         pvt->remaplimit = ((u32) pci_data) << 14;
 478         e7xxx_printk(KERN_INFO,
 479                 "tolm = %x, remapbase = %x, remaplimit = %x\n", pvt->tolm,
 480                 pvt->remapbase, pvt->remaplimit);
 481
 482         /* clear any pending errors, or initial state bits */
 483         e7xxx_get_error_info(mci, &discard);
 484
 485         /* Here we assume that we will never see multiple instances of this
 486          * type of memory controller.  The ID is therefore hardcoded to 0.
 487          */
 488         if (edac_mc_add_mc(mci,0)) {
 489                 debugf3("%s(): failed edac_mc_add_mc()\n", __func__);
 490                 goto fail1;
 491         }
 492
 493         /* get this far and it's successful */
 494         debugf3("%s(): success\n", __func__);
 495         return 0;
 496
 497 fail1:
 498         pci_dev_put(pvt->bridge_ck);
 499
 500 fail0:
 501         edac_mc_free(mci);
 502
 503         return -ENODEV;
 504 }
 505
 506 /* returns count (>= 0), or negative on error */
 507 static int __devinit e7xxx_init_one(struct pci_dev *pdev,
 508                 const struct pci_device_id *ent)
 509 {
 510         debugf0("%s()\n", __func__);
 511
 512         /* wake up and enable device */
 513         return pci_enable_device(pdev) ?
 514                 -EIO : e7xxx_probe1(pdev, ent->driver_data);
 515 }
 516
 517 static void __devexit e7xxx_remove_one(struct pci_dev *pdev)
 518 {
 519         struct mem_ctl_info *mci;
 520         struct e7xxx_pvt *pvt;
 521
 522         debugf0("%s()\n", __func__);
 523
 524         if ((mci = edac_mc_del_mc(&pdev->dev)) == NULL)
 525                 return;
 526
 527         pvt = (struct e7xxx_pvt *) mci->pvt_info;
 528         pci_dev_put(pvt->bridge_ck);
 529         edac_mc_free(mci);
 530 }
 531
 532 static const struct pci_device_id e7xxx_pci_tbl[] __devinitdata = {
 533         {
 534                 PCI_VEND_DEV(INTEL, 7205_0), PCI_ANY_ID, PCI_ANY_ID, 0, 0,
 535                 E7205
 536         },
 537         {
 538                 PCI_VEND_DEV(INTEL, 7500_0), PCI_ANY_ID, PCI_ANY_ID, 0, 0,
 539                 E7500
 540         },
 541         {
 542                 PCI_VEND_DEV(INTEL, 7501_0), PCI_ANY_ID, PCI_ANY_ID, 0, 0,
 543                 E7501
 544         },
 545         {
 546                 PCI_VEND_DEV(INTEL, 7505_0), PCI_ANY_ID, PCI_ANY_ID, 0, 0,
 547                 E7505
 548         },
 549         {
 550                 0,
 551         }       /* 0 terminated list. */
 552 };
 553
 554 MODULE_DEVICE_TABLE(pci, e7xxx_pci_tbl);
 555
 556 static struct pci_driver e7xxx_driver = {
 557         .name = EDAC_MOD_STR,
 558         .probe = e7xxx_init_one,
 559         .remove = __devexit_p(e7xxx_remove_one),
 560         .id_table = e7xxx_pci_tbl,
 561 };
 562
 563 static int __init e7xxx_init(void)
 564 {
 565         return pci_register_driver(&e7xxx_driver);
 566 }
 567
 568 static void __exit e7xxx_exit(void)
 569 {
 570         pci_unregister_driver(&e7xxx_driver);
 571 }
 572
 573 module_init(e7xxx_init);
 574 module_exit(e7xxx_exit);
 575
 576 MODULE_LICENSE("GPL");
 577 MODULE_AUTHOR("Linux Networx (http://lnxi.com) Thayne Harbaugh et al\n"
 578         "Based on.work by Dan Hollis et al");
 579 MODULE_DESCRIPTION("MC support for Intel e7xxx memory controllers");
 580 module_param(edac_op_state, int, 0444);
 581 MODULE_PARM_DESC(edac_op_state, "EDAC Error Reporting state: 0=Poll,1=NMI");