2 * Copyright(c) 2004 - 2007 Intel Corporation. All rights reserved.
4 * This program is free software; you can redistribute it and/or modify it
5 * under the terms of the GNU General Public License as published by the Free
6 * Software Foundation; either version 2 of the License, or (at your option)
9 * This program is distributed in the hope that it will be useful, but WITHOUT
10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
14 * You should have received a copy of the GNU General Public License along with
15 * this program; if not, write to the Free Software Foundation, Inc., 59
16 * Temple Place - Suite 330, Boston, MA 02111-1307, USA.
18 * The full GNU General Public License is included in this distribution in the
19 * file called COPYING.
24 #include <linux/dmaengine.h>
25 #include "ioatdma_hw.h"
26 #include <linux/init.h>
27 #include <linux/dmapool.h>
28 #include <linux/cache.h>
29 #include <linux/pci_ids.h>
31 #define IOAT_DMA_VERSION "2.18"
35 msix_multi_vector = 1,
36 msix_single_vector = 2,
41 #define IOAT_LOW_COMPLETION_MASK 0xffffffc0
42 #define IOAT_DMA_DCA_ANY_CPU ~0
43 #define IOAT_WATCHDOG_PERIOD (2 * HZ)
47 * struct ioatdma_device - internal representation of a IOAT device
48 * @pdev: PCI-Express device
49 * @reg_base: MMIO register space base address
50 * @dma_pool: for allocating DMA descriptors
51 * @common: embedded struct dma_device
52 * @version: version of ioatdma device
53 * @irq_mode: which style irq to use
54 * @msix_entries: irq handlers
55 * @idx: per channel data
58 struct ioatdma_device {
60 void __iomem *reg_base;
61 struct pci_pool *dma_pool;
62 struct pci_pool *completion_pool;
63 struct dma_device common;
65 enum ioat_interrupt irq_mode;
66 struct delayed_work work;
67 struct msix_entry msix_entries[4];
68 struct ioat_dma_chan *idx[4];
72 * struct ioat_dma_chan - internal representation of a DMA channel
74 struct ioat_dma_chan {
76 void __iomem *reg_base;
78 dma_cookie_t completed_cookie;
79 unsigned long last_completion;
80 unsigned long last_completion_time;
82 size_t xfercap; /* XFERCAP register value expanded out */
84 spinlock_t cleanup_lock;
86 struct list_head free_desc;
87 struct list_head used_desc;
88 unsigned long watchdog_completion;
89 int watchdog_tcp_cookie;
90 u32 watchdog_last_tcp_cookie;
91 struct delayed_work work;
97 struct ioatdma_device *device;
98 struct dma_chan common;
100 dma_addr_t completion_addr;
102 u64 full; /* HW completion writeback */
108 unsigned long last_compl_desc_addr_hw;
109 struct tasklet_struct cleanup_task;
112 /* wrapper around hardware descriptor format + additional software fields */
115 * struct ioat_desc_sw - wrapper around hardware descriptor
116 * @hw: hardware DMA descriptor
117 * @node: this descriptor will either be on the free list,
118 * or attached to a transaction list (async_tx.tx_list)
119 * @tx_cnt: number of descriptors required to complete the transaction
120 * @async_tx: the generic software descriptor for all engines
122 struct ioat_desc_sw {
123 struct ioat_dma_descriptor *hw;
124 struct list_head node;
129 struct dma_async_tx_descriptor async_tx;
132 #if defined(CONFIG_INTEL_IOATDMA) || defined(CONFIG_INTEL_IOATDMA_MODULE)
133 struct ioatdma_device *ioat_dma_probe(struct pci_dev *pdev,
134 void __iomem *iobase);
135 void ioat_dma_remove(struct ioatdma_device *device);
136 struct dca_provider *ioat_dca_init(struct pci_dev *pdev, void __iomem *iobase);
137 struct dca_provider *ioat2_dca_init(struct pci_dev *pdev, void __iomem *iobase);
139 #define ioat_dma_probe(pdev, iobase) NULL
140 #define ioat_dma_remove(device) do { } while (0)
141 #define ioat_dca_init(pdev, iobase) NULL
142 #define ioat2_dca_init(pdev, iobase) NULL
145 #endif /* IOATDMA_H */