err.no Git - linux-2.6/blob - drivers/char/synclink_gt.c

   1 /*
   2  * $Id: synclink_gt.c,v 4.50 2007/07/25 19:29:25 paulkf Exp $
   3  *
   4  * Device driver for Microgate SyncLink GT serial adapters.
   5  *
   6  * written by Paul Fulghum for Microgate Corporation
   7  * paulkf@microgate.com
   8  *
   9  * Microgate and SyncLink are trademarks of Microgate Corporation
  10  *
  11  * This code is released under the GNU General Public License (GPL)
  12  *
  13  * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED
  14  * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
  15  * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
  16  * DISCLAIMED.  IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT,
  17  * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
  18  * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
  19  * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
  20  * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
  21  * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
  22  * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED
  23  * OF THE POSSIBILITY OF SUCH DAMAGE.
  24  */
  25
  26 /*
  27  * DEBUG OUTPUT DEFINITIONS
  28  *
  29  * uncomment lines below to enable specific types of debug output
  30  *
  31  * DBGINFO   information - most verbose output
  32  * DBGERR    serious errors
  33  * DBGBH     bottom half service routine debugging
  34  * DBGISR    interrupt service routine debugging
  35  * DBGDATA   output receive and transmit data
  36  * DBGTBUF   output transmit DMA buffers and registers
  37  * DBGRBUF   output receive DMA buffers and registers
  38  */
  39
  40 #define DBGINFO(fmt) if (debug_level >= DEBUG_LEVEL_INFO) printk fmt
  41 #define DBGERR(fmt) if (debug_level >= DEBUG_LEVEL_ERROR) printk fmt
  42 #define DBGBH(fmt) if (debug_level >= DEBUG_LEVEL_BH) printk fmt
  43 #define DBGISR(fmt) if (debug_level >= DEBUG_LEVEL_ISR) printk fmt
  44 #define DBGDATA(info, buf, size, label) if (debug_level >= DEBUG_LEVEL_DATA) trace_block((info), (buf), (size), (label))
  45 //#define DBGTBUF(info) dump_tbufs(info)
  46 //#define DBGRBUF(info) dump_rbufs(info)
  47
  48
  49 #include <linux/module.h>
  50 #include <linux/version.h>
  51 #include <linux/errno.h>
  52 #include <linux/signal.h>
  53 #include <linux/sched.h>
  54 #include <linux/timer.h>
  55 #include <linux/interrupt.h>
  56 #include <linux/pci.h>
  57 #include <linux/tty.h>
  58 #include <linux/tty_flip.h>
  59 #include <linux/serial.h>
  60 #include <linux/major.h>
  61 #include <linux/string.h>
  62 #include <linux/fcntl.h>
  63 #include <linux/ptrace.h>
  64 #include <linux/ioport.h>
  65 #include <linux/mm.h>
  66 #include <linux/slab.h>
  67 #include <linux/netdevice.h>
  68 #include <linux/vmalloc.h>
  69 #include <linux/init.h>
  70 #include <linux/delay.h>
  71 #include <linux/ioctl.h>
  72 #include <linux/termios.h>
  73 #include <linux/bitops.h>
  74 #include <linux/workqueue.h>
  75 #include <linux/hdlc.h>
  76 #include <linux/synclink.h>
  77
  78 #include <asm/system.h>
  79 #include <asm/io.h>
  80 #include <asm/irq.h>
  81 #include <asm/dma.h>
  82 #include <asm/types.h>
  83 #include <asm/uaccess.h>
  84
  85 #if defined(CONFIG_HDLC) || (defined(CONFIG_HDLC_MODULE) && defined(CONFIG_SYNCLINK_GT_MODULE))
  86 #define SYNCLINK_GENERIC_HDLC 1
  87 #else
  88 #define SYNCLINK_GENERIC_HDLC 0
  89 #endif
  90
  91 /*
  92  * module identification
  93  */
  94 static char *driver_name     = "SyncLink GT";
  95 static char *driver_version  = "$Revision: 4.50 $";
  96 static char *tty_driver_name = "synclink_gt";
  97 static char *tty_dev_prefix  = "ttySLG";
  98 MODULE_LICENSE("GPL");
  99 #define MGSL_MAGIC 0x5401
 100 #define MAX_DEVICES 32
 101
 102 static struct pci_device_id pci_table[] = {
 103         {PCI_VENDOR_ID_MICROGATE, SYNCLINK_GT_DEVICE_ID, PCI_ANY_ID, PCI_ANY_ID,},
 104         {PCI_VENDOR_ID_MICROGATE, SYNCLINK_GT2_DEVICE_ID, PCI_ANY_ID, PCI_ANY_ID,},
 105         {PCI_VENDOR_ID_MICROGATE, SYNCLINK_GT4_DEVICE_ID, PCI_ANY_ID, PCI_ANY_ID,},
 106         {PCI_VENDOR_ID_MICROGATE, SYNCLINK_AC_DEVICE_ID, PCI_ANY_ID, PCI_ANY_ID,},
 107         {0,}, /* terminate list */
 108 };
 109 MODULE_DEVICE_TABLE(pci, pci_table);
 110
 111 static int  init_one(struct pci_dev *dev,const struct pci_device_id *ent);
 112 static void remove_one(struct pci_dev *dev);
 113 static struct pci_driver pci_driver = {
 114         .name           = "synclink_gt",
 115         .id_table       = pci_table,
 116         .probe          = init_one,
 117         .remove         = __devexit_p(remove_one),
 118 };
 119
 120 static bool pci_registered;
 121
 122 /*
 123  * module configuration and status
 124  */
 125 static struct slgt_info *slgt_device_list;
 126 static int slgt_device_count;
 127
 128 static int ttymajor;
 129 static int debug_level;
 130 static int maxframe[MAX_DEVICES];
 131 static int dosyncppp[MAX_DEVICES];
 132
 133 module_param(ttymajor, int, 0);
 134 module_param(debug_level, int, 0);
 135 module_param_array(maxframe, int, NULL, 0);
 136 module_param_array(dosyncppp, int, NULL, 0);
 137
 138 MODULE_PARM_DESC(ttymajor, "TTY major device number override: 0=auto assigned");
 139 MODULE_PARM_DESC(debug_level, "Debug syslog output: 0=disabled, 1 to 5=increasing detail");
 140 MODULE_PARM_DESC(maxframe, "Maximum frame size used by device (4096 to 65535)");
 141 MODULE_PARM_DESC(dosyncppp, "Enable synchronous net device, 0=disable 1=enable");
 142
 143 /*
 144  * tty support and callbacks
 145  */
 146 static struct tty_driver *serial_driver;
 147
 148 static int  open(struct tty_struct *tty, struct file * filp);
 149 static void close(struct tty_struct *tty, struct file * filp);
 150 static void hangup(struct tty_struct *tty);
 151 static void set_termios(struct tty_struct *tty, struct ktermios *old_termios);
 152
 153 static int  write(struct tty_struct *tty, const unsigned char *buf, int count);
 154 static int put_char(struct tty_struct *tty, unsigned char ch);
 155 static void send_xchar(struct tty_struct *tty, char ch);
 156 static void wait_until_sent(struct tty_struct *tty, int timeout);
 157 static int  write_room(struct tty_struct *tty);
 158 static void flush_chars(struct tty_struct *tty);
 159 static void flush_buffer(struct tty_struct *tty);
 160 static void tx_hold(struct tty_struct *tty);
 161 static void tx_release(struct tty_struct *tty);
 162
 163 static int  ioctl(struct tty_struct *tty, struct file *file, unsigned int cmd, unsigned long arg);
 164 static int  read_proc(char *page, char **start, off_t off, int count,int *eof, void *data);
 165 static int  chars_in_buffer(struct tty_struct *tty);
 166 static void throttle(struct tty_struct * tty);
 167 static void unthrottle(struct tty_struct * tty);
 168 static int set_break(struct tty_struct *tty, int break_state);
 169
 170 /*
 171  * generic HDLC support and callbacks
 172  */
 173 #if SYNCLINK_GENERIC_HDLC
 174 #define dev_to_port(D) (dev_to_hdlc(D)->priv)
 175 static void hdlcdev_tx_done(struct slgt_info *info);
 176 static void hdlcdev_rx(struct slgt_info *info, char *buf, int size);
 177 static int  hdlcdev_init(struct slgt_info *info);
 178 static void hdlcdev_exit(struct slgt_info *info);
 179 #endif
 180
 181
 182 /*
 183  * device specific structures, macros and functions
 184  */
 185
 186 #define SLGT_MAX_PORTS 4
 187 #define SLGT_REG_SIZE  256
 188
 189 /*
 190  * conditional wait facility
 191  */
 192 struct cond_wait {
 193         struct cond_wait *next;
 194         wait_queue_head_t q;
 195         wait_queue_t wait;
 196         unsigned int data;
 197 };
 198 static void init_cond_wait(struct cond_wait *w, unsigned int data);
 199 static void add_cond_wait(struct cond_wait **head, struct cond_wait *w);
 200 static void remove_cond_wait(struct cond_wait **head, struct cond_wait *w);
 201 static void flush_cond_wait(struct cond_wait **head);
 202
 203 /*
 204  * DMA buffer descriptor and access macros
 205  */
 206 struct slgt_desc
 207 {
 208         __le16 count;
 209         __le16 status;
 210         __le32 pbuf;  /* physical address of data buffer */
 211         __le32 next;  /* physical address of next descriptor */
 212
 213         /* driver book keeping */
 214         char *buf;          /* virtual  address of data buffer */
 215         unsigned int pdesc; /* physical address of this descriptor */
 216         dma_addr_t buf_dma_addr;
 217 };
 218
 219 #define set_desc_buffer(a,b) (a).pbuf = cpu_to_le32((unsigned int)(b))
 220 #define set_desc_next(a,b) (a).next   = cpu_to_le32((unsigned int)(b))
 221 #define set_desc_count(a,b)(a).count  = cpu_to_le16((unsigned short)(b))
 222 #define set_desc_eof(a,b)  (a).status = cpu_to_le16((b) ? (le16_to_cpu((a).status) | BIT0) : (le16_to_cpu((a).status) & ~BIT0))
 223 #define desc_count(a)      (le16_to_cpu((a).count))
 224 #define desc_status(a)     (le16_to_cpu((a).status))
 225 #define desc_complete(a)   (le16_to_cpu((a).status) & BIT15)
 226 #define desc_eof(a)        (le16_to_cpu((a).status) & BIT2)
 227 #define desc_crc_error(a)  (le16_to_cpu((a).status) & BIT1)
 228 #define desc_abort(a)      (le16_to_cpu((a).status) & BIT0)
 229 #define desc_residue(a)    ((le16_to_cpu((a).status) & 0x38) >> 3)
 230
 231 struct _input_signal_events {
 232         int ri_up;
 233         int ri_down;
 234         int dsr_up;
 235         int dsr_down;
 236         int dcd_up;
 237         int dcd_down;
 238         int cts_up;
 239         int cts_down;
 240 };
 241
 242 /*
 243  * device instance data structure
 244  */
 245 struct slgt_info {
 246         void *if_ptr;           /* General purpose pointer (used by SPPP) */
 247         struct tty_port port;
 248
 249         struct slgt_info *next_device;  /* device list link */
 250
 251         int magic;
 252
 253         char device_name[25];
 254         struct pci_dev *pdev;
 255
 256         int port_count;  /* count of ports on adapter */
 257         int adapter_num; /* adapter instance number */
 258         int port_num;    /* port instance number */
 259
 260         /* array of pointers to port contexts on this adapter */
 261         struct slgt_info *port_array[SLGT_MAX_PORTS];
 262
 263         int                     line;           /* tty line instance number */
 264
 265         struct mgsl_icount      icount;
 266
 267         int                     timeout;
 268         int                     x_char;         /* xon/xoff character */
 269         unsigned int            read_status_mask;
 270         unsigned int            ignore_status_mask;
 271
 272         wait_queue_head_t       status_event_wait_q;
 273         wait_queue_head_t       event_wait_q;
 274         struct timer_list       tx_timer;
 275         struct timer_list       rx_timer;
 276
 277         unsigned int            gpio_present;
 278         struct cond_wait        *gpio_wait_q;
 279
 280         spinlock_t lock;        /* spinlock for synchronizing with ISR */
 281
 282         struct work_struct task;
 283         u32 pending_bh;
 284         bool bh_requested;
 285         bool bh_running;
 286
 287         int isr_overflow;
 288         bool irq_requested;     /* true if IRQ requested */
 289         bool irq_occurred;      /* for diagnostics use */
 290
 291         /* device configuration */
 292
 293         unsigned int bus_type;
 294         unsigned int irq_level;
 295         unsigned long irq_flags;
 296
 297         unsigned char __iomem * reg_addr;  /* memory mapped registers address */
 298         u32 phys_reg_addr;
 299         bool reg_addr_requested;
 300
 301         MGSL_PARAMS params;       /* communications parameters */
 302         u32 idle_mode;
 303         u32 max_frame_size;       /* as set by device config */
 304
 305         unsigned int raw_rx_size;
 306         unsigned int if_mode;
 307
 308         /* device status */
 309
 310         bool rx_enabled;
 311         bool rx_restart;
 312
 313         bool tx_enabled;
 314         bool tx_active;
 315
 316         unsigned char signals;    /* serial signal states */
 317         int init_error;  /* initialization error */
 318
 319         unsigned char *tx_buf;
 320         int tx_count;
 321
 322         char flag_buf[MAX_ASYNC_BUFFER_SIZE];
 323         char char_buf[MAX_ASYNC_BUFFER_SIZE];
 324         bool drop_rts_on_tx_done;
 325         struct  _input_signal_events    input_signal_events;
 326
 327         int dcd_chkcount;       /* check counts to prevent */
 328         int cts_chkcount;       /* too many IRQs if a signal */
 329         int dsr_chkcount;       /* is floating */
 330         int ri_chkcount;
 331
 332         char *bufs;             /* virtual address of DMA buffer lists */
 333         dma_addr_t bufs_dma_addr; /* physical address of buffer descriptors */
 334
 335         unsigned int rbuf_count;
 336         struct slgt_desc *rbufs;
 337         unsigned int rbuf_current;
 338         unsigned int rbuf_index;
 339
 340         unsigned int tbuf_count;
 341         struct slgt_desc *tbufs;
 342         unsigned int tbuf_current;
 343         unsigned int tbuf_start;
 344
 345         unsigned char *tmp_rbuf;
 346         unsigned int tmp_rbuf_count;
 347
 348         /* SPPP/Cisco HDLC device parts */
 349
 350         int netcount;
 351         int dosyncppp;
 352         spinlock_t netlock;
 353 #if SYNCLINK_GENERIC_HDLC
 354         struct net_device *netdev;
 355 #endif
 356
 357 };
 358
 359 static MGSL_PARAMS default_params = {
 360         .mode            = MGSL_MODE_HDLC,
 361         .loopback        = 0,
 362         .flags           = HDLC_FLAG_UNDERRUN_ABORT15,
 363         .encoding        = HDLC_ENCODING_NRZI_SPACE,
 364         .clock_speed     = 0,
 365         .addr_filter     = 0xff,
 366         .crc_type        = HDLC_CRC_16_CCITT,
 367         .preamble_length = HDLC_PREAMBLE_LENGTH_8BITS,
 368         .preamble        = HDLC_PREAMBLE_PATTERN_NONE,
 369         .data_rate       = 9600,
 370         .data_bits       = 8,
 371         .stop_bits       = 1,
 372         .parity          = ASYNC_PARITY_NONE
 373 };
 374
 375
 376 #define BH_RECEIVE  1
 377 #define BH_TRANSMIT 2
 378 #define BH_STATUS   4
 379 #define IO_PIN_SHUTDOWN_LIMIT 100
 380
 381 #define DMABUFSIZE 256
 382 #define DESC_LIST_SIZE 4096
 383
 384 #define MASK_PARITY  BIT1
 385 #define MASK_FRAMING BIT0
 386 #define MASK_BREAK   BIT14
 387 #define MASK_OVERRUN BIT4
 388
 389 #define GSR   0x00 /* global status */
 390 #define JCR   0x04 /* JTAG control */
 391 #define IODR  0x08 /* GPIO direction */
 392 #define IOER  0x0c /* GPIO interrupt enable */
 393 #define IOVR  0x10 /* GPIO value */
 394 #define IOSR  0x14 /* GPIO interrupt status */
 395 #define TDR   0x80 /* tx data */
 396 #define RDR   0x80 /* rx data */
 397 #define TCR   0x82 /* tx control */
 398 #define TIR   0x84 /* tx idle */
 399 #define TPR   0x85 /* tx preamble */
 400 #define RCR   0x86 /* rx control */
 401 #define VCR   0x88 /* V.24 control */
 402 #define CCR   0x89 /* clock control */
 403 #define BDR   0x8a /* baud divisor */
 404 #define SCR   0x8c /* serial control */
 405 #define SSR   0x8e /* serial status */
 406 #define RDCSR 0x90 /* rx DMA control/status */
 407 #define TDCSR 0x94 /* tx DMA control/status */
 408 #define RDDAR 0x98 /* rx DMA descriptor address */
 409 #define TDDAR 0x9c /* tx DMA descriptor address */
 410
 411 #define RXIDLE      BIT14
 412 #define RXBREAK     BIT14
 413 #define IRQ_TXDATA  BIT13
 414 #define IRQ_TXIDLE  BIT12
 415 #define IRQ_TXUNDER BIT11 /* HDLC */
 416 #define IRQ_RXDATA  BIT10
 417 #define IRQ_RXIDLE  BIT9  /* HDLC */
 418 #define IRQ_RXBREAK BIT9  /* async */
 419 #define IRQ_RXOVER  BIT8
 420 #define IRQ_DSR     BIT7
 421 #define IRQ_CTS     BIT6
 422 #define IRQ_DCD     BIT5
 423 #define IRQ_RI      BIT4
 424 #define IRQ_ALL     0x3ff0
 425 #define IRQ_MASTER  BIT0
 426
 427 #define slgt_irq_on(info, mask) \
 428         wr_reg16((info), SCR, (unsigned short)(rd_reg16((info), SCR) | (mask)))
 429 #define slgt_irq_off(info, mask) \
 430         wr_reg16((info), SCR, (unsigned short)(rd_reg16((info), SCR) & ~(mask)))
 431
 432 static __u8  rd_reg8(struct slgt_info *info, unsigned int addr);
 433 static void  wr_reg8(struct slgt_info *info, unsigned int addr, __u8 value);
 434 static __u16 rd_reg16(struct slgt_info *info, unsigned int addr);
 435 static void  wr_reg16(struct slgt_info *info, unsigned int addr, __u16 value);
 436 static __u32 rd_reg32(struct slgt_info *info, unsigned int addr);
 437 static void  wr_reg32(struct slgt_info *info, unsigned int addr, __u32 value);
 438
 439 static void  msc_set_vcr(struct slgt_info *info);
 440
 441 static int  startup(struct slgt_info *info);
 442 static int  block_til_ready(struct tty_struct *tty, struct file * filp,struct slgt_info *info);
 443 static void shutdown(struct slgt_info *info);
 444 static void program_hw(struct slgt_info *info);
 445 static void change_params(struct slgt_info *info);
 446
 447 static int  register_test(struct slgt_info *info);
 448 static int  irq_test(struct slgt_info *info);
 449 static int  loopback_test(struct slgt_info *info);
 450 static int  adapter_test(struct slgt_info *info);
 451
 452 static void reset_adapter(struct slgt_info *info);
 453 static void reset_port(struct slgt_info *info);
 454 static void async_mode(struct slgt_info *info);
 455 static void sync_mode(struct slgt_info *info);
 456
 457 static void rx_stop(struct slgt_info *info);
 458 static void rx_start(struct slgt_info *info);
 459 static void reset_rbufs(struct slgt_info *info);
 460 static void free_rbufs(struct slgt_info *info, unsigned int first, unsigned int last);
 461 static void rdma_reset(struct slgt_info *info);
 462 static bool rx_get_frame(struct slgt_info *info);
 463 static bool rx_get_buf(struct slgt_info *info);
 464
 465 static void tx_start(struct slgt_info *info);
 466 static void tx_stop(struct slgt_info *info);
 467 static void tx_set_idle(struct slgt_info *info);
 468 static unsigned int free_tbuf_count(struct slgt_info *info);
 469 static void reset_tbufs(struct slgt_info *info);
 470 static void tdma_reset(struct slgt_info *info);
 471 static void tdma_start(struct slgt_info *info);
 472 static void tx_load(struct slgt_info *info, const char *buf, unsigned int count);
 473
 474 static void get_signals(struct slgt_info *info);
 475 static void set_signals(struct slgt_info *info);
 476 static void enable_loopback(struct slgt_info *info);
 477 static void set_rate(struct slgt_info *info, u32 data_rate);
 478
 479 static int  bh_action(struct slgt_info *info);
 480 static void bh_handler(struct work_struct *work);
 481 static void bh_transmit(struct slgt_info *info);
 482 static void isr_serial(struct slgt_info *info);
 483 static void isr_rdma(struct slgt_info *info);
 484 static void isr_txeom(struct slgt_info *info, unsigned short status);
 485 static void isr_tdma(struct slgt_info *info);
 486
 487 static int  alloc_dma_bufs(struct slgt_info *info);
 488 static void free_dma_bufs(struct slgt_info *info);
 489 static int  alloc_desc(struct slgt_info *info);
 490 static void free_desc(struct slgt_info *info);
 491 static int  alloc_bufs(struct slgt_info *info, struct slgt_desc *bufs, int count);
 492 static void free_bufs(struct slgt_info *info, struct slgt_desc *bufs, int count);
 493
 494 static int  alloc_tmp_rbuf(struct slgt_info *info);
 495 static void free_tmp_rbuf(struct slgt_info *info);
 496
 497 static void tx_timeout(unsigned long context);
 498 static void rx_timeout(unsigned long context);
 499
 500 /*
 501  * ioctl handlers
 502  */
 503 static int  get_stats(struct slgt_info *info, struct mgsl_icount __user *user_icount);
 504 static int  get_params(struct slgt_info *info, MGSL_PARAMS __user *params);
 505 static int  set_params(struct slgt_info *info, MGSL_PARAMS __user *params);
 506 static int  get_txidle(struct slgt_info *info, int __user *idle_mode);
 507 static int  set_txidle(struct slgt_info *info, int idle_mode);
 508 static int  tx_enable(struct slgt_info *info, int enable);
 509 static int  tx_abort(struct slgt_info *info);
 510 static int  rx_enable(struct slgt_info *info, int enable);
 511 static int  modem_input_wait(struct slgt_info *info,int arg);
 512 static int  wait_mgsl_event(struct slgt_info *info, int __user *mask_ptr);
 513 static int  tiocmget(struct tty_struct *tty, struct file *file);
 514 static int  tiocmset(struct tty_struct *tty, struct file *file,
 515                      unsigned int set, unsigned int clear);
 516 static int set_break(struct tty_struct *tty, int break_state);
 517 static int  get_interface(struct slgt_info *info, int __user *if_mode);
 518 static int  set_interface(struct slgt_info *info, int if_mode);
 519 static int  set_gpio(struct slgt_info *info, struct gpio_desc __user *gpio);
 520 static int  get_gpio(struct slgt_info *info, struct gpio_desc __user *gpio);
 521 static int  wait_gpio(struct slgt_info *info, struct gpio_desc __user *gpio);
 522
 523 /*
 524  * driver functions
 525  */
 526 static void add_device(struct slgt_info *info);
 527 static void device_init(int adapter_num, struct pci_dev *pdev);
 528 static int  claim_resources(struct slgt_info *info);
 529 static void release_resources(struct slgt_info *info);
 530
 531 /*
 532  * DEBUG OUTPUT CODE
 533  */
 534 #ifndef DBGINFO
 535 #define DBGINFO(fmt)
 536 #endif
 537 #ifndef DBGERR
 538 #define DBGERR(fmt)
 539 #endif
 540 #ifndef DBGBH
 541 #define DBGBH(fmt)
 542 #endif
 543 #ifndef DBGISR
 544 #define DBGISR(fmt)
 545 #endif
 546
 547 #ifdef DBGDATA
 548 static void trace_block(struct slgt_info *info, const char *data, int count, const char *label)
 549 {
 550         int i;
 551         int linecount;
 552         printk("%s %s data:\n",info->device_name, label);
 553         while(count) {
 554                 linecount = (count > 16) ? 16 : count;
 555                 for(i=0; i < linecount; i++)
 556                         printk("%02X ",(unsigned char)data[i]);
 557                 for(;i<17;i++)
 558                         printk("   ");
 559                 for(i=0;i<linecount;i++) {
 560                         if (data[i]>=040 && data[i]<=0176)
 561                                 printk("%c",data[i]);
 562                         else
 563                                 printk(".");
 564                 }
 565                 printk("\n");
 566                 data  += linecount;
 567                 count -= linecount;
 568         }
 569 }
 570 #else
 571 #define DBGDATA(info, buf, size, label)
 572 #endif
 573
 574 #ifdef DBGTBUF
 575 static void dump_tbufs(struct slgt_info *info)
 576 {
 577         int i;
 578         printk("tbuf_current=%d\n", info->tbuf_current);
 579         for (i=0 ; i < info->tbuf_count ; i++) {
 580                 printk("%d: count=%04X status=%04X\n",
 581                         i, le16_to_cpu(info->tbufs[i].count), le16_to_cpu(info->tbufs[i].status));
 582         }
 583 }
 584 #else
 585 #define DBGTBUF(info)
 586 #endif
 587
 588 #ifdef DBGRBUF
 589 static void dump_rbufs(struct slgt_info *info)
 590 {
 591         int i;
 592         printk("rbuf_current=%d\n", info->rbuf_current);
 593         for (i=0 ; i < info->rbuf_count ; i++) {
 594                 printk("%d: count=%04X status=%04X\n",
 595                         i, le16_to_cpu(info->rbufs[i].count), le16_to_cpu(info->rbufs[i].status));
 596         }
 597 }
 598 #else
 599 #define DBGRBUF(info)
 600 #endif
 601
 602 static inline int sanity_check(struct slgt_info *info, char *devname, const char *name)
 603 {
 604 #ifdef SANITY_CHECK
 605         if (!info) {
 606                 printk("null struct slgt_info for (%s) in %s\n", devname, name);
 607                 return 1;
 608         }
 609         if (info->magic != MGSL_MAGIC) {
 610                 printk("bad magic number struct slgt_info (%s) in %s\n", devname, name);
 611                 return 1;
 612         }
 613 #else
 614         if (!info)
 615                 return 1;
 616 #endif
 617         return 0;
 618 }
 619
 620 /**
 621  * line discipline callback wrappers
 622  *
 623  * The wrappers maintain line discipline references
 624  * while calling into the line discipline.
 625  *
 626  * ldisc_receive_buf  - pass receive data to line discipline
 627  */
 628 static void ldisc_receive_buf(struct tty_struct *tty,
 629                               const __u8 *data, char *flags, int count)
 630 {
 631         struct tty_ldisc *ld;
 632         if (!tty)
 633                 return;
 634         ld = tty_ldisc_ref(tty);
 635         if (ld) {
 636                 if (ld->ops->receive_buf)
 637                         ld->ops->receive_buf(tty, data, flags, count);
 638                 tty_ldisc_deref(ld);
 639         }
 640 }
 641
 642 /* tty callbacks */
 643
 644 static int open(struct tty_struct *tty, struct file *filp)
 645 {
 646         struct slgt_info *info;
 647         int retval, line;
 648         unsigned long flags;
 649
 650         line = tty->index;
 651         if ((line < 0) || (line >= slgt_device_count)) {
 652                 DBGERR(("%s: open with invalid line #%d.\n", driver_name, line));
 653                 return -ENODEV;
 654         }
 655
 656         info = slgt_device_list;
 657         while(info && info->line != line)
 658                 info = info->next_device;
 659         if (sanity_check(info, tty->name, "open"))
 660                 return -ENODEV;
 661         if (info->init_error) {
 662                 DBGERR(("%s init error=%d\n", info->device_name, info->init_error));
 663                 return -ENODEV;
 664         }
 665
 666         tty->driver_data = info;
 667         info->port.tty = tty;
 668
 669         DBGINFO(("%s open, old ref count = %d\n", info->device_name, info->port.count));
 670
 671         /* If port is closing, signal caller to try again */
 672         if (tty_hung_up_p(filp) || info->port.flags & ASYNC_CLOSING){
 673                 if (info->port.flags & ASYNC_CLOSING)
 674                         interruptible_sleep_on(&info->port.close_wait);
 675                 retval = ((info->port.flags & ASYNC_HUP_NOTIFY) ?
 676                         -EAGAIN : -ERESTARTSYS);
 677                 goto cleanup;
 678         }
 679
 680         info->port.tty->low_latency = (info->port.flags & ASYNC_LOW_LATENCY) ? 1 : 0;
 681
 682         spin_lock_irqsave(&info->netlock, flags);
 683         if (info->netcount) {
 684                 retval = -EBUSY;
 685                 spin_unlock_irqrestore(&info->netlock, flags);
 686                 goto cleanup;
 687         }
 688         info->port.count++;
 689         spin_unlock_irqrestore(&info->netlock, flags);
 690
 691         if (info->port.count == 1) {
 692                 /* 1st open on this device, init hardware */
 693                 retval = startup(info);
 694                 if (retval < 0)
 695                         goto cleanup;
 696         }
 697
 698         retval = block_til_ready(tty, filp, info);
 699         if (retval) {
 700                 DBGINFO(("%s block_til_ready rc=%d\n", info->device_name, retval));
 701                 goto cleanup;
 702         }
 703
 704         retval = 0;
 705
 706 cleanup:
 707         if (retval) {
 708                 if (tty->count == 1)
 709                         info->port.tty = NULL; /* tty layer will release tty struct */
 710                 if(info->port.count)
 711                         info->port.count--;
 712         }
 713
 714         DBGINFO(("%s open rc=%d\n", info->device_name, retval));
 715         return retval;
 716 }
 717
 718 static void close(struct tty_struct *tty, struct file *filp)
 719 {
 720         struct slgt_info *info = tty->driver_data;
 721
 722         if (sanity_check(info, tty->name, "close"))
 723                 return;
 724         DBGINFO(("%s close entry, count=%d\n", info->device_name, info->port.count));
 725
 726         if (!info->port.count)
 727                 return;
 728
 729         if (tty_hung_up_p(filp))
 730                 goto cleanup;
 731
 732         if ((tty->count == 1) && (info->port.count != 1)) {
 733                 /*
 734                  * tty->count is 1 and the tty structure will be freed.
 735                  * info->port.count should be one in this case.
 736                  * if it's not, correct it so that the port is shutdown.
 737                  */
 738                 DBGERR(("%s close: bad refcount; tty->count=1, "
 739                        "info->port.count=%d\n", info->device_name, info->port.count));
 740                 info->port.count = 1;
 741         }
 742
 743         info->port.count--;
 744
 745         /* if at least one open remaining, leave hardware active */
 746         if (info->port.count)
 747                 goto cleanup;
 748
 749         info->port.flags |= ASYNC_CLOSING;
 750
 751         /* set tty->closing to notify line discipline to
 752          * only process XON/XOFF characters. Only the N_TTY
 753          * discipline appears to use this (ppp does not).
 754          */
 755         tty->closing = 1;
 756
 757         /* wait for transmit data to clear all layers */
 758
 759         if (info->port.closing_wait != ASYNC_CLOSING_WAIT_NONE) {
 760                 DBGINFO(("%s call tty_wait_until_sent\n", info->device_name));
 761                 tty_wait_until_sent(tty, info->port.closing_wait);
 762         }
 763
 764         if (info->port.flags & ASYNC_INITIALIZED)
 765                 wait_until_sent(tty, info->timeout);
 766         flush_buffer(tty);
 767         tty_ldisc_flush(tty);
 768
 769         shutdown(info);
 770
 771         tty->closing = 0;
 772         info->port.tty = NULL;
 773
 774         if (info->port.blocked_open) {
 775                 if (info->port.close_delay) {
 776                         msleep_interruptible(jiffies_to_msecs(info->port.close_delay));
 777                 }
 778                 wake_up_interruptible(&info->port.open_wait);
 779         }
 780
 781         info->port.flags &= ~(ASYNC_NORMAL_ACTIVE|ASYNC_CLOSING);
 782
 783         wake_up_interruptible(&info->port.close_wait);
 784
 785 cleanup:
 786         DBGINFO(("%s close exit, count=%d\n", tty->driver->name, info->port.count));
 787 }
 788
 789 static void hangup(struct tty_struct *tty)
 790 {
 791         struct slgt_info *info = tty->driver_data;
 792
 793         if (sanity_check(info, tty->name, "hangup"))
 794                 return;
 795         DBGINFO(("%s hangup\n", info->device_name));
 796
 797         flush_buffer(tty);
 798         shutdown(info);
 799
 800         info->port.count = 0;
 801         info->port.flags &= ~ASYNC_NORMAL_ACTIVE;
 802         info->port.tty = NULL;
 803
 804         wake_up_interruptible(&info->port.open_wait);
 805 }
 806
 807 static void set_termios(struct tty_struct *tty, struct ktermios *old_termios)
 808 {
 809         struct slgt_info *info = tty->driver_data;
 810         unsigned long flags;
 811
 812         DBGINFO(("%s set_termios\n", tty->driver->name));
 813
 814         change_params(info);
 815
 816         /* Handle transition to B0 status */
 817         if (old_termios->c_cflag & CBAUD &&
 818             !(tty->termios->c_cflag & CBAUD)) {
 819                 info->signals &= ~(SerialSignal_RTS + SerialSignal_DTR);
 820                 spin_lock_irqsave(&info->lock,flags);
 821                 set_signals(info);
 822                 spin_unlock_irqrestore(&info->lock,flags);
 823         }
 824
 825         /* Handle transition away from B0 status */
 826         if (!(old_termios->c_cflag & CBAUD) &&
 827             tty->termios->c_cflag & CBAUD) {
 828                 info->signals |= SerialSignal_DTR;
 829                 if (!(tty->termios->c_cflag & CRTSCTS) ||
 830                     !test_bit(TTY_THROTTLED, &tty->flags)) {
 831                         info->signals |= SerialSignal_RTS;
 832                 }
 833                 spin_lock_irqsave(&info->lock,flags);
 834                 set_signals(info);
 835                 spin_unlock_irqrestore(&info->lock,flags);
 836         }
 837
 838         /* Handle turning off CRTSCTS */
 839         if (old_termios->c_cflag & CRTSCTS &&
 840             !(tty->termios->c_cflag & CRTSCTS)) {
 841                 tty->hw_stopped = 0;
 842                 tx_release(tty);
 843         }
 844 }
 845
 846 static int write(struct tty_struct *tty,
 847                  const unsigned char *buf, int count)
 848 {
 849         int ret = 0;
 850         struct slgt_info *info = tty->driver_data;
 851         unsigned long flags;
 852
 853         if (sanity_check(info, tty->name, "write"))
 854                 goto cleanup;
 855         DBGINFO(("%s write count=%d\n", info->device_name, count));
 856
 857         if (!info->tx_buf)
 858                 goto cleanup;
 859
 860         if (count > info->max_frame_size) {
 861                 ret = -EIO;
 862                 goto cleanup;
 863         }
 864
 865         if (!count)
 866                 goto cleanup;
 867
 868         if (info->params.mode == MGSL_MODE_RAW ||
 869             info->params.mode == MGSL_MODE_MONOSYNC ||
 870             info->params.mode == MGSL_MODE_BISYNC) {
 871                 unsigned int bufs_needed = (count/DMABUFSIZE);
 872                 unsigned int bufs_free = free_tbuf_count(info);
 873                 if (count % DMABUFSIZE)
 874                         ++bufs_needed;
 875                 if (bufs_needed > bufs_free)
 876                         goto cleanup;
 877         } else {
 878                 if (info->tx_active)
 879                         goto cleanup;
 880                 if (info->tx_count) {
 881                         /* send accumulated data from send_char() calls */
 882                         /* as frame and wait before accepting more data. */
 883                         tx_load(info, info->tx_buf, info->tx_count);
 884                         goto start;
 885                 }
 886         }
 887
 888         ret = info->tx_count = count;
 889         tx_load(info, buf, count);
 890         goto start;
 891
 892 start:
 893         if (info->tx_count && !tty->stopped && !tty->hw_stopped) {
 894                 spin_lock_irqsave(&info->lock,flags);
 895                 if (!info->tx_active)
 896                         tx_start(info);
 897                 else
 898                         tdma_start(info);
 899                 spin_unlock_irqrestore(&info->lock,flags);
 900         }
 901
 902 cleanup:
 903         DBGINFO(("%s write rc=%d\n", info->device_name, ret));
 904         return ret;
 905 }
 906
 907 static int put_char(struct tty_struct *tty, unsigned char ch)
 908 {
 909         struct slgt_info *info = tty->driver_data;
 910         unsigned long flags;
 911         int ret = 0;
 912
 913         if (sanity_check(info, tty->name, "put_char"))
 914                 return 0;
 915         DBGINFO(("%s put_char(%d)\n", info->device_name, ch));
 916         if (!info->tx_buf)
 917                 return 0;
 918         spin_lock_irqsave(&info->lock,flags);
 919         if (!info->tx_active && (info->tx_count < info->max_frame_size)) {
 920                 info->tx_buf[info->tx_count++] = ch;
 921                 ret = 1;
 922         }
 923         spin_unlock_irqrestore(&info->lock,flags);
 924         return ret;
 925 }
 926
 927 static void send_xchar(struct tty_struct *tty, char ch)
 928 {
 929         struct slgt_info *info = tty->driver_data;
 930         unsigned long flags;
 931
 932         if (sanity_check(info, tty->name, "send_xchar"))
 933                 return;
 934         DBGINFO(("%s send_xchar(%d)\n", info->device_name, ch));
 935         info->x_char = ch;
 936         if (ch) {
 937                 spin_lock_irqsave(&info->lock,flags);
 938                 if (!info->tx_enabled)
 939                         tx_start(info);
 940                 spin_unlock_irqrestore(&info->lock,flags);
 941         }
 942 }
 943
 944 static void wait_until_sent(struct tty_struct *tty, int timeout)
 945 {
 946         struct slgt_info *info = tty->driver_data;
 947         unsigned long orig_jiffies, char_time;
 948
 949         if (!info )
 950                 return;
 951         if (sanity_check(info, tty->name, "wait_until_sent"))
 952                 return;
 953         DBGINFO(("%s wait_until_sent entry\n", info->device_name));
 954         if (!(info->port.flags & ASYNC_INITIALIZED))
 955                 goto exit;
 956
 957         orig_jiffies = jiffies;
 958
 959         /* Set check interval to 1/5 of estimated time to
 960          * send a character, and make it at least 1. The check
 961          * interval should also be less than the timeout.
 962          * Note: use tight timings here to satisfy the NIST-PCTS.
 963          */
 964
 965         lock_kernel();
 966
 967         if (info->params.data_rate) {
 968                 char_time = info->timeout/(32 * 5);
 969                 if (!char_time)
 970                         char_time++;
 971         } else
 972                 char_time = 1;
 973
 974         if (timeout)
 975                 char_time = min_t(unsigned long, char_time, timeout);
 976
 977         while (info->tx_active) {
 978                 msleep_interruptible(jiffies_to_msecs(char_time));
 979                 if (signal_pending(current))
 980                         break;
 981                 if (timeout && time_after(jiffies, orig_jiffies + timeout))
 982                         break;
 983         }
 984         unlock_kernel();
 985
 986 exit:
 987         DBGINFO(("%s wait_until_sent exit\n", info->device_name));
 988 }
 989
 990 static int write_room(struct tty_struct *tty)
 991 {
 992         struct slgt_info *info = tty->driver_data;
 993         int ret;
 994
 995         if (sanity_check(info, tty->name, "write_room"))
 996                 return 0;
 997         ret = (info->tx_active) ? 0 : HDLC_MAX_FRAME_SIZE;
 998         DBGINFO(("%s write_room=%d\n", info->device_name, ret));
 999         return ret;
1000 }
1001
1002 static void flush_chars(struct tty_struct *tty)
1003 {
1004         struct slgt_info *info = tty->driver_data;
1005         unsigned long flags;
1006
1007         if (sanity_check(info, tty->name, "flush_chars"))
1008                 return;
1009         DBGINFO(("%s flush_chars entry tx_count=%d\n", info->device_name, info->tx_count));
1010
1011         if (info->tx_count <= 0 || tty->stopped ||
1012             tty->hw_stopped || !info->tx_buf)
1013                 return;
1014
1015         DBGINFO(("%s flush_chars start transmit\n", info->device_name));
1016
1017         spin_lock_irqsave(&info->lock,flags);
1018         if (!info->tx_active && info->tx_count) {
1019                 tx_load(info, info->tx_buf,info->tx_count);
1020                 tx_start(info);
1021         }
1022         spin_unlock_irqrestore(&info->lock,flags);
1023 }
1024
1025 static void flush_buffer(struct tty_struct *tty)
1026 {
1027         struct slgt_info *info = tty->driver_data;
1028         unsigned long flags;
1029
1030         if (sanity_check(info, tty->name, "flush_buffer"))
1031                 return;
1032         DBGINFO(("%s flush_buffer\n", info->device_name));
1033
1034         spin_lock_irqsave(&info->lock,flags);
1035         if (!info->tx_active)
1036                 info->tx_count = 0;
1037         spin_unlock_irqrestore(&info->lock,flags);
1038
1039         tty_wakeup(tty);
1040 }
1041
1042 /*
1043  * throttle (stop) transmitter
1044  */
1045 static void tx_hold(struct tty_struct *tty)
1046 {
1047         struct slgt_info *info = tty->driver_data;
1048         unsigned long flags;
1049
1050         if (sanity_check(info, tty->name, "tx_hold"))
1051                 return;
1052         DBGINFO(("%s tx_hold\n", info->device_name));
1053         spin_lock_irqsave(&info->lock,flags);
1054         if (info->tx_enabled && info->params.mode == MGSL_MODE_ASYNC)
1055                 tx_stop(info);
1056         spin_unlock_irqrestore(&info->lock,flags);
1057 }
1058
1059 /*
1060  * release (start) transmitter
1061  */
1062 static void tx_release(struct tty_struct *tty)
1063 {
1064         struct slgt_info *info = tty->driver_data;
1065         unsigned long flags;
1066
1067         if (sanity_check(info, tty->name, "tx_release"))
1068                 return;
1069         DBGINFO(("%s tx_release\n", info->device_name));
1070         spin_lock_irqsave(&info->lock,flags);
1071         if (!info->tx_active && info->tx_count) {
1072                 tx_load(info, info->tx_buf, info->tx_count);
1073                 tx_start(info);
1074         }
1075         spin_unlock_irqrestore(&info->lock,flags);
1076 }
1077
1078 /*
1079  * Service an IOCTL request
1080  *
1081  * Arguments
1082  *
1083  *      tty     pointer to tty instance data
1084  *      file    pointer to associated file object for device
1085  *      cmd     IOCTL command code
1086  *      arg     command argument/context
1087  *
1088  * Return 0 if success, otherwise error code
1089  */
1090 static int ioctl(struct tty_struct *tty, struct file *file,
1091                  unsigned int cmd, unsigned long arg)
1092 {
1093         struct slgt_info *info = tty->driver_data;
1094         struct mgsl_icount cnow;        /* kernel counter temps */
1095         struct serial_icounter_struct __user *p_cuser;  /* user space */
1096         unsigned long flags;
1097         void __user *argp = (void __user *)arg;
1098         int ret;
1099
1100         if (sanity_check(info, tty->name, "ioctl"))
1101                 return -ENODEV;
1102         DBGINFO(("%s ioctl() cmd=%08X\n", info->device_name, cmd));
1103
1104         if ((cmd != TIOCGSERIAL) && (cmd != TIOCSSERIAL) &&
1105             (cmd != TIOCMIWAIT) && (cmd != TIOCGICOUNT)) {
1106                 if (tty->flags & (1 << TTY_IO_ERROR))
1107                     return -EIO;
1108         }
1109
1110         lock_kernel();
1111
1112         switch (cmd) {
1113         case MGSL_IOCGPARAMS:
1114                 ret = get_params(info, argp);
1115                 break;
1116         case MGSL_IOCSPARAMS:
1117                 ret = set_params(info, argp);
1118                 break;
1119         case MGSL_IOCGTXIDLE:
1120                 ret = get_txidle(info, argp);
1121                 break;
1122         case MGSL_IOCSTXIDLE:
1123                 ret = set_txidle(info, (int)arg);
1124                 break;
1125         case MGSL_IOCTXENABLE:
1126                 ret = tx_enable(info, (int)arg);
1127                 break;
1128         case MGSL_IOCRXENABLE:
1129                 ret = rx_enable(info, (int)arg);
1130                 break;
1131         case MGSL_IOCTXABORT:
1132                 ret = tx_abort(info);
1133                 break;
1134         case MGSL_IOCGSTATS:
1135                 ret = get_stats(info, argp);
1136                 break;
1137         case MGSL_IOCWAITEVENT:
1138                 ret = wait_mgsl_event(info, argp);
1139                 break;
1140         case TIOCMIWAIT:
1141                 ret = modem_input_wait(info,(int)arg);
1142                 break;
1143         case MGSL_IOCGIF:
1144                 ret = get_interface(info, argp);
1145                 break;
1146         case MGSL_IOCSIF:
1147                 ret = set_interface(info,(int)arg);
1148                 break;
1149         case MGSL_IOCSGPIO:
1150                 ret = set_gpio(info, argp);
1151                 break;
1152         case MGSL_IOCGGPIO:
1153                 ret = get_gpio(info, argp);
1154                 break;
1155         case MGSL_IOCWAITGPIO:
1156                 ret = wait_gpio(info, argp);
1157                 break;
1158         case TIOCGICOUNT:
1159                 spin_lock_irqsave(&info->lock,flags);
1160                 cnow = info->icount;
1161                 spin_unlock_irqrestore(&info->lock,flags);
1162                 p_cuser = argp;
1163                 if (put_user(cnow.cts, &p_cuser->cts) ||
1164                     put_user(cnow.dsr, &p_cuser->dsr) ||
1165                     put_user(cnow.rng, &p_cuser->rng) ||
1166                     put_user(cnow.dcd, &p_cuser->dcd) ||
1167                     put_user(cnow.rx, &p_cuser->rx) ||
1168                     put_user(cnow.tx, &p_cuser->tx) ||
1169                     put_user(cnow.frame, &p_cuser->frame) ||
1170                     put_user(cnow.overrun, &p_cuser->overrun) ||
1171                     put_user(cnow.parity, &p_cuser->parity) ||
1172                     put_user(cnow.brk, &p_cuser->brk) ||
1173                     put_user(cnow.buf_overrun, &p_cuser->buf_overrun))
1174                         ret = -EFAULT;
1175                 ret = 0;
1176                 break;
1177         default:
1178                 ret = -ENOIOCTLCMD;
1179         }
1180         unlock_kernel();
1181         return ret;
1182 }
1183
1184 /*
1185  * support for 32 bit ioctl calls on 64 bit systems
1186  */
1187 #ifdef CONFIG_COMPAT
1188 static long get_params32(struct slgt_info *info, struct MGSL_PARAMS32 __user *user_params)
1189 {
1190         struct MGSL_PARAMS32 tmp_params;
1191
1192         DBGINFO(("%s get_params32\n", info->device_name));
1193         tmp_params.mode            = (compat_ulong_t)info->params.mode;
1194         tmp_params.loopback        = info->params.loopback;
1195         tmp_params.flags           = info->params.flags;
1196         tmp_params.encoding        = info->params.encoding;
1197         tmp_params.clock_speed     = (compat_ulong_t)info->params.clock_speed;
1198         tmp_params.addr_filter     = info->params.addr_filter;
1199         tmp_params.crc_type        = info->params.crc_type;
1200         tmp_params.preamble_length = info->params.preamble_length;
1201         tmp_params.preamble        = info->params.preamble;
1202         tmp_params.data_rate       = (compat_ulong_t)info->params.data_rate;
1203         tmp_params.data_bits       = info->params.data_bits;
1204         tmp_params.stop_bits       = info->params.stop_bits;
1205         tmp_params.parity          = info->params.parity;
1206         if (copy_to_user(user_params, &tmp_params, sizeof(struct MGSL_PARAMS32)))
1207                 return -EFAULT;
1208         return 0;
1209 }
1210
1211 static long set_params32(struct slgt_info *info, struct MGSL_PARAMS32 __user *new_params)
1212 {
1213         struct MGSL_PARAMS32 tmp_params;
1214
1215         DBGINFO(("%s set_params32\n", info->device_name));
1216         if (copy_from_user(&tmp_params, new_params, sizeof(struct MGSL_PARAMS32)))
1217                 return -EFAULT;
1218
1219         spin_lock(&info->lock);
1220         info->params.mode            = tmp_params.mode;
1221         info->params.loopback        = tmp_params.loopback;
1222         info->params.flags           = tmp_params.flags;
1223         info->params.encoding        = tmp_params.encoding;
1224         info->params.clock_speed     = tmp_params.clock_speed;
1225         info->params.addr_filter     = tmp_params.addr_filter;
1226         info->params.crc_type        = tmp_params.crc_type;
1227         info->params.preamble_length = tmp_params.preamble_length;
1228         info->params.preamble        = tmp_params.preamble;
1229         info->params.data_rate       = tmp_params.data_rate;
1230         info->params.data_bits       = tmp_params.data_bits;
1231         info->params.stop_bits       = tmp_params.stop_bits;
1232         info->params.parity          = tmp_params.parity;
1233         spin_unlock(&info->lock);
1234
1235         change_params(info);
1236
1237         return 0;
1238 }
1239
1240 static long slgt_compat_ioctl(struct tty_struct *tty, struct file *file,
1241                          unsigned int cmd, unsigned long arg)
1242 {
1243         struct slgt_info *info = tty->driver_data;
1244         int rc = -ENOIOCTLCMD;
1245
1246         if (sanity_check(info, tty->name, "compat_ioctl"))
1247                 return -ENODEV;
1248         DBGINFO(("%s compat_ioctl() cmd=%08X\n", info->device_name, cmd));
1249
1250         switch (cmd) {
1251
1252         case MGSL_IOCSPARAMS32:
1253                 rc = set_params32(info, compat_ptr(arg));
1254                 break;
1255
1256         case MGSL_IOCGPARAMS32:
1257                 rc = get_params32(info, compat_ptr(arg));
1258                 break;
1259
1260         case MGSL_IOCGPARAMS:
1261         case MGSL_IOCSPARAMS:
1262         case MGSL_IOCGTXIDLE:
1263         case MGSL_IOCGSTATS:
1264         case MGSL_IOCWAITEVENT:
1265         case MGSL_IOCGIF:
1266         case MGSL_IOCSGPIO:
1267         case MGSL_IOCGGPIO:
1268         case MGSL_IOCWAITGPIO:
1269         case TIOCGICOUNT:
1270                 rc = ioctl(tty, file, cmd, (unsigned long)(compat_ptr(arg)));
1271                 break;
1272
1273         case MGSL_IOCSTXIDLE:
1274         case MGSL_IOCTXENABLE:
1275         case MGSL_IOCRXENABLE:
1276         case MGSL_IOCTXABORT:
1277         case TIOCMIWAIT:
1278         case MGSL_IOCSIF:
1279                 rc = ioctl(tty, file, cmd, arg);
1280                 break;
1281         }
1282
1283         DBGINFO(("%s compat_ioctl() cmd=%08X rc=%d\n", info->device_name, cmd, rc));
1284         return rc;
1285 }
1286 #else
1287 #define slgt_compat_ioctl NULL
1288 #endif /* ifdef CONFIG_COMPAT */
1289
1290 /*
1291  * proc fs support
1292  */
1293 static inline int line_info(char *buf, struct slgt_info *info)
1294 {
1295         char stat_buf[30];
1296         int ret;
1297         unsigned long flags;
1298
1299         ret = sprintf(buf, "%s: IO=%08X IRQ=%d MaxFrameSize=%u\n",
1300                       info->device_name, info->phys_reg_addr,
1301                       info->irq_level, info->max_frame_size);
1302
1303         /* output current serial signal states */
1304         spin_lock_irqsave(&info->lock,flags);
1305         get_signals(info);
1306         spin_unlock_irqrestore(&info->lock,flags);
1307
1308         stat_buf[0] = 0;
1309         stat_buf[1] = 0;
1310         if (info->signals & SerialSignal_RTS)
1311                 strcat(stat_buf, "|RTS");
1312         if (info->signals & SerialSignal_CTS)
1313                 strcat(stat_buf, "|CTS");
1314         if (info->signals & SerialSignal_DTR)
1315                 strcat(stat_buf, "|DTR");
1316         if (info->signals & SerialSignal_DSR)
1317                 strcat(stat_buf, "|DSR");
1318         if (info->signals & SerialSignal_DCD)
1319                 strcat(stat_buf, "|CD");
1320         if (info->signals & SerialSignal_RI)
1321                 strcat(stat_buf, "|RI");
1322
1323         if (info->params.mode != MGSL_MODE_ASYNC) {
1324                 ret += sprintf(buf+ret, "\tHDLC txok:%d rxok:%d",
1325                                info->icount.txok, info->icount.rxok);
1326                 if (info->icount.txunder)
1327                         ret += sprintf(buf+ret, " txunder:%d", info->icount.txunder);
1328                 if (info->icount.txabort)
1329                         ret += sprintf(buf+ret, " txabort:%d", info->icount.txabort);
1330                 if (info->icount.rxshort)
1331                         ret += sprintf(buf+ret, " rxshort:%d", info->icount.rxshort);
1332                 if (info->icount.rxlong)
1333                         ret += sprintf(buf+ret, " rxlong:%d", info->icount.rxlong);
1334                 if (info->icount.rxover)
1335                         ret += sprintf(buf+ret, " rxover:%d", info->icount.rxover);
1336                 if (info->icount.rxcrc)
1337                         ret += sprintf(buf+ret, " rxcrc:%d", info->icount.rxcrc);
1338         } else {
1339                 ret += sprintf(buf+ret, "\tASYNC tx:%d rx:%d",
1340                                info->icount.tx, info->icount.rx);
1341                 if (info->icount.frame)
1342                         ret += sprintf(buf+ret, " fe:%d", info->icount.frame);
1343                 if (info->icount.parity)
1344                         ret += sprintf(buf+ret, " pe:%d", info->icount.parity);
1345                 if (info->icount.brk)
1346                         ret += sprintf(buf+ret, " brk:%d", info->icount.brk);
1347                 if (info->icount.overrun)
1348                         ret += sprintf(buf+ret, " oe:%d", info->icount.overrun);
1349         }
1350
1351         /* Append serial signal status to end */
1352         ret += sprintf(buf+ret, " %s\n", stat_buf+1);
1353
1354         ret += sprintf(buf+ret, "\ttxactive=%d bh_req=%d bh_run=%d pending_bh=%x\n",
1355                        info->tx_active,info->bh_requested,info->bh_running,
1356                        info->pending_bh);
1357
1358         return ret;
1359 }
1360
1361 /* Called to print information about devices
1362  */
1363 static int read_proc(char *page, char **start, off_t off, int count,
1364                      int *eof, void *data)
1365 {
1366         int len = 0, l;
1367         off_t   begin = 0;
1368         struct slgt_info *info;
1369
1370         len += sprintf(page, "synclink_gt driver:%s\n", driver_version);
1371
1372         info = slgt_device_list;
1373         while( info ) {
1374                 l = line_info(page + len, info);
1375                 len += l;
1376                 if (len+begin > off+count)
1377                         goto done;
1378                 if (len+begin < off) {
1379                         begin += len;
1380                         len = 0;
1381                 }
1382                 info = info->next_device;
1383         }
1384
1385         *eof = 1;
1386 done:
1387         if (off >= len+begin)
1388                 return 0;
1389         *start = page + (off-begin);
1390         return ((count < begin+len-off) ? count : begin+len-off);
1391 }
1392
1393 /*
1394  * return count of bytes in transmit buffer
1395  */
1396 static int chars_in_buffer(struct tty_struct *tty)
1397 {
1398         struct slgt_info *info = tty->driver_data;
1399         if (sanity_check(info, tty->name, "chars_in_buffer"))
1400                 return 0;
1401         DBGINFO(("%s chars_in_buffer()=%d\n", info->device_name, info->tx_count));
1402         return info->tx_count;
1403 }
1404
1405 /*
1406  * signal remote device to throttle send data (our receive data)
1407  */
1408 static void throttle(struct tty_struct * tty)
1409 {
1410         struct slgt_info *info = tty->driver_data;
1411         unsigned long flags;
1412
1413         if (sanity_check(info, tty->name, "throttle"))
1414                 return;
1415         DBGINFO(("%s throttle\n", info->device_name));
1416         if (I_IXOFF(tty))
1417                 send_xchar(tty, STOP_CHAR(tty));
1418         if (tty->termios->c_cflag & CRTSCTS) {
1419                 spin_lock_irqsave(&info->lock,flags);
1420                 info->signals &= ~SerialSignal_RTS;
1421                 set_signals(info);
1422                 spin_unlock_irqrestore(&info->lock,flags);
1423         }
1424 }
1425
1426 /*
1427  * signal remote device to stop throttling send data (our receive data)
1428  */
1429 static void unthrottle(struct tty_struct * tty)
1430 {
1431         struct slgt_info *info = tty->driver_data;
1432         unsigned long flags;
1433
1434         if (sanity_check(info, tty->name, "unthrottle"))
1435                 return;
1436         DBGINFO(("%s unthrottle\n", info->device_name));
1437         if (I_IXOFF(tty)) {
1438                 if (info->x_char)
1439                         info->x_char = 0;
1440                 else
1441                         send_xchar(tty, START_CHAR(tty));
1442         }
1443         if (tty->termios->c_cflag & CRTSCTS) {
1444                 spin_lock_irqsave(&info->lock,flags);
1445                 info->signals |= SerialSignal_RTS;
1446                 set_signals(info);
1447                 spin_unlock_irqrestore(&info->lock,flags);
1448         }
1449 }
1450
1451 /*
1452  * set or clear transmit break condition
1453  * break_state  -1=set break condition, 0=clear
1454  */
1455 static int set_break(struct tty_struct *tty, int break_state)
1456 {
1457         struct slgt_info *info = tty->driver_data;
1458         unsigned short value;
1459         unsigned long flags;
1460
1461         if (sanity_check(info, tty->name, "set_break"))
1462                 return -EINVAL;
1463         DBGINFO(("%s set_break(%d)\n", info->device_name, break_state));
1464
1465         spin_lock_irqsave(&info->lock,flags);
1466         value = rd_reg16(info, TCR);
1467         if (break_state == -1)
1468                 value |= BIT6;
1469         else
1470                 value &= ~BIT6;
1471         wr_reg16(info, TCR, value);
1472         spin_unlock_irqrestore(&info->lock,flags);
1473         return 0;
1474 }
1475
1476 #if SYNCLINK_GENERIC_HDLC
1477
1478 /**
1479  * called by generic HDLC layer when protocol selected (PPP, frame relay, etc.)
1480  * set encoding and frame check sequence (FCS) options
1481  *
1482  * dev       pointer to network device structure
1483  * encoding  serial encoding setting
1484  * parity    FCS setting
1485  *
1486  * returns 0 if success, otherwise error code
1487  */
1488 static int hdlcdev_attach(struct net_device *dev, unsigned short encoding,
1489                           unsigned short parity)
1490 {
1491         struct slgt_info *info = dev_to_port(dev);
1492         unsigned char  new_encoding;
1493         unsigned short new_crctype;
1494
1495         /* return error if TTY interface open */
1496         if (info->port.count)
1497                 return -EBUSY;
1498
1499         DBGINFO(("%s hdlcdev_attach\n", info->device_name));
1500
1501         switch (encoding)
1502         {
1503         case ENCODING_NRZ:        new_encoding = HDLC_ENCODING_NRZ; break;
1504         case ENCODING_NRZI:       new_encoding = HDLC_ENCODING_NRZI_SPACE; break;
1505         case ENCODING_FM_MARK:    new_encoding = HDLC_ENCODING_BIPHASE_MARK; break;
1506         case ENCODING_FM_SPACE:   new_encoding = HDLC_ENCODING_BIPHASE_SPACE; break;
1507         case ENCODING_MANCHESTER: new_encoding = HDLC_ENCODING_BIPHASE_LEVEL; break;
1508         default: return -EINVAL;
1509         }
1510
1511         switch (parity)
1512         {
1513         case PARITY_NONE:            new_crctype = HDLC_CRC_NONE; break;
1514         case PARITY_CRC16_PR1_CCITT: new_crctype = HDLC_CRC_16_CCITT; break;
1515         case PARITY_CRC32_PR1_CCITT: new_crctype = HDLC_CRC_32_CCITT; break;
1516         default: return -EINVAL;
1517         }
1518
1519         info->params.encoding = new_encoding;
1520         info->params.crc_type = new_crctype;
1521
1522         /* if network interface up, reprogram hardware */
1523         if (info->netcount)
1524                 program_hw(info);
1525
1526         return 0;
1527 }
1528
1529 /**
1530  * called by generic HDLC layer to send frame
1531  *
1532  * skb  socket buffer containing HDLC frame
1533  * dev  pointer to network device structure
1534  *
1535  * returns 0 if success, otherwise error code
1536  */
1537 static int hdlcdev_xmit(struct sk_buff *skb, struct net_device *dev)
1538 {
1539         struct slgt_info *info = dev_to_port(dev);
1540         unsigned long flags;
1541
1542         DBGINFO(("%s hdlc_xmit\n", dev->name));
1543
1544         /* stop sending until this frame completes */
1545         netif_stop_queue(dev);
1546
1547         /* copy data to device buffers */
1548         info->tx_count = skb->len;
1549         tx_load(info, skb->data, skb->len);
1550
1551         /* update network statistics */
1552         dev->stats.tx_packets++;
1553         dev->stats.tx_bytes += skb->len;
1554
1555         /* done with socket buffer, so free it */
1556         dev_kfree_skb(skb);
1557
1558         /* save start time for transmit timeout detection */
1559         dev->trans_start = jiffies;
1560
1561         /* start hardware transmitter if necessary */
1562         spin_lock_irqsave(&info->lock,flags);
1563         if (!info->tx_active)
1564                 tx_start(info);
1565         spin_unlock_irqrestore(&info->lock,flags);
1566
1567         return 0;
1568 }
1569
1570 /**
1571  * called by network layer when interface enabled
1572  * claim resources and initialize hardware
1573  *
1574  * dev  pointer to network device structure
1575  *
1576  * returns 0 if success, otherwise error code
1577  */
1578 static int hdlcdev_open(struct net_device *dev)
1579 {
1580         struct slgt_info *info = dev_to_port(dev);
1581         int rc;
1582         unsigned long flags;
1583
1584         if (!try_module_get(THIS_MODULE))
1585                 return -EBUSY;
1586
1587         DBGINFO(("%s hdlcdev_open\n", dev->name));
1588
1589         /* generic HDLC layer open processing */
1590         if ((rc = hdlc_open(dev)))
1591                 return rc;
1592
1593         /* arbitrate between network and tty opens */
1594         spin_lock_irqsave(&info->netlock, flags);
1595         if (info->port.count != 0 || info->netcount != 0) {
1596                 DBGINFO(("%s hdlc_open busy\n", dev->name));
1597                 spin_unlock_irqrestore(&info->netlock, flags);
1598                 return -EBUSY;
1599         }
1600         info->netcount=1;
1601         spin_unlock_irqrestore(&info->netlock, flags);
1602
1603         /* claim resources and init adapter */
1604         if ((rc = startup(info)) != 0) {
1605                 spin_lock_irqsave(&info->netlock, flags);
1606                 info->netcount=0;
1607                 spin_unlock_irqrestore(&info->netlock, flags);
1608                 return rc;
1609         }
1610
1611         /* assert DTR and RTS, apply hardware settings */
1612         info->signals |= SerialSignal_RTS + SerialSignal_DTR;
1613         program_hw(info);
1614
1615         /* enable network layer transmit */
1616         dev->trans_start = jiffies;
1617         netif_start_queue(dev);
1618
1619         /* inform generic HDLC layer of current DCD status */
1620         spin_lock_irqsave(&info->lock, flags);
1621         get_signals(info);
1622         spin_unlock_irqrestore(&info->lock, flags);
1623         if (info->signals & SerialSignal_DCD)
1624                 netif_carrier_on(dev);
1625         else
1626                 netif_carrier_off(dev);
1627         return 0;
1628 }
1629
1630 /**
1631  * called by network layer when interface is disabled
1632  * shutdown hardware and release resources
1633  *
1634  * dev  pointer to network device structure
1635  *
1636  * returns 0 if success, otherwise error code
1637  */
1638 static int hdlcdev_close(struct net_device *dev)
1639 {
1640         struct slgt_info *info = dev_to_port(dev);
1641         unsigned long flags;
1642
1643         DBGINFO(("%s hdlcdev_close\n", dev->name));
1644
1645         netif_stop_queue(dev);
1646
1647         /* shutdown adapter and release resources */
1648         shutdown(info);
1649
1650         hdlc_close(dev);
1651
1652         spin_lock_irqsave(&info->netlock, flags);
1653         info->netcount=0;
1654         spin_unlock_irqrestore(&info->netlock, flags);
1655
1656         module_put(THIS_MODULE);
1657         return 0;
1658 }
1659
1660 /**
1661  * called by network layer to process IOCTL call to network device
1662  *
1663  * dev  pointer to network device structure
1664  * ifr  pointer to network interface request structure
1665  * cmd  IOCTL command code
1666  *
1667  * returns 0 if success, otherwise error code
1668  */
1669 static int hdlcdev_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd)
1670 {
1671         const size_t size = sizeof(sync_serial_settings);
1672         sync_serial_settings new_line;
1673         sync_serial_settings __user *line = ifr->ifr_settings.ifs_ifsu.sync;
1674         struct slgt_info *info = dev_to_port(dev);
1675         unsigned int flags;
1676
1677         DBGINFO(("%s hdlcdev_ioctl\n", dev->name));
1678
1679         /* return error if TTY interface open */
1680         if (info->port.count)
1681                 return -EBUSY;
1682
1683         if (cmd != SIOCWANDEV)
1684                 return hdlc_ioctl(dev, ifr, cmd);
1685
1686         switch(ifr->ifr_settings.type) {
1687         case IF_GET_IFACE: /* return current sync_serial_settings */
1688
1689                 ifr->ifr_settings.type = IF_IFACE_SYNC_SERIAL;
1690                 if (ifr->ifr_settings.size < size) {
1691                         ifr->ifr_settings.size = size; /* data size wanted */
1692                         return -ENOBUFS;
1693                 }
1694
1695                 flags = info->params.flags & (HDLC_FLAG_RXC_RXCPIN | HDLC_FLAG_RXC_DPLL |
1696                                               HDLC_FLAG_RXC_BRG    | HDLC_FLAG_RXC_TXCPIN |
1697                                               HDLC_FLAG_TXC_TXCPIN | HDLC_FLAG_TXC_DPLL |
1698                                               HDLC_FLAG_TXC_BRG    | HDLC_FLAG_TXC_RXCPIN);
1699
1700                 switch (flags){
1701                 case (HDLC_FLAG_RXC_RXCPIN | HDLC_FLAG_TXC_TXCPIN): new_line.clock_type = CLOCK_EXT; break;
1702                 case (HDLC_FLAG_RXC_BRG    | HDLC_FLAG_TXC_BRG):    new_line.clock_type = CLOCK_INT; break;
1703                 case (HDLC_FLAG_RXC_RXCPIN | HDLC_FLAG_TXC_BRG):    new_line.clock_type = CLOCK_TXINT; break;
1704                 case (HDLC_FLAG_RXC_RXCPIN | HDLC_FLAG_TXC_RXCPIN): new_line.clock_type = CLOCK_TXFROMRX; break;
1705                 default: new_line.clock_type = CLOCK_DEFAULT;
1706                 }
1707
1708                 new_line.clock_rate = info->params.clock_speed;
1709                 new_line.loopback   = info->params.loopback ? 1:0;
1710
1711                 if (copy_to_user(line, &new_line, size))
1712                         return -EFAULT;
1713                 return 0;
1714
1715         case IF_IFACE_SYNC_SERIAL: /* set sync_serial_settings */
1716
1717                 if(!capable(CAP_NET_ADMIN))
1718                         return -EPERM;
1719                 if (copy_from_user(&new_line, line, size))
1720                         return -EFAULT;
1721
1722                 switch (new_line.clock_type)
1723                 {
1724                 case CLOCK_EXT:      flags = HDLC_FLAG_RXC_RXCPIN | HDLC_FLAG_TXC_TXCPIN; break;
1725                 case CLOCK_TXFROMRX: flags = HDLC_FLAG_RXC_RXCPIN | HDLC_FLAG_TXC_RXCPIN; break;
1726                 case CLOCK_INT:      flags = HDLC_FLAG_RXC_BRG    | HDLC_FLAG_TXC_BRG;    break;
1727                 case CLOCK_TXINT:    flags = HDLC_FLAG_RXC_RXCPIN | HDLC_FLAG_TXC_BRG;    break;
1728                 case CLOCK_DEFAULT:  flags = info->params.flags &
1729                                              (HDLC_FLAG_RXC_RXCPIN | HDLC_FLAG_RXC_DPLL |
1730                                               HDLC_FLAG_RXC_BRG    | HDLC_FLAG_RXC_TXCPIN |
1731                                               HDLC_FLAG_TXC_TXCPIN | HDLC_FLAG_TXC_DPLL |
1732                                               HDLC_FLAG_TXC_BRG    | HDLC_FLAG_TXC_RXCPIN); break;
1733                 default: return -EINVAL;
1734                 }
1735
1736                 if (new_line.loopback != 0 && new_line.loopback != 1)
1737                         return -EINVAL;
1738
1739                 info->params.flags &= ~(HDLC_FLAG_RXC_RXCPIN | HDLC_FLAG_RXC_DPLL |
1740                                         HDLC_FLAG_RXC_BRG    | HDLC_FLAG_RXC_TXCPIN |
1741                                         HDLC_FLAG_TXC_TXCPIN | HDLC_FLAG_TXC_DPLL |
1742                                         HDLC_FLAG_TXC_BRG    | HDLC_FLAG_TXC_RXCPIN);
1743                 info->params.flags |= flags;
1744
1745                 info->params.loopback = new_line.loopback;
1746
1747                 if (flags & (HDLC_FLAG_RXC_BRG | HDLC_FLAG_TXC_BRG))
1748                         info->params.clock_speed = new_line.clock_rate;
1749                 else
1750                         info->params.clock_speed = 0;
1751
1752                 /* if network interface up, reprogram hardware */
1753                 if (info->netcount)
1754                         program_hw(info);
1755                 return 0;
1756
1757         default:
1758                 return hdlc_ioctl(dev, ifr, cmd);
1759         }
1760 }
1761
1762 /**
1763  * called by network layer when transmit timeout is detected
1764  *
1765  * dev  pointer to network device structure
1766  */
1767 static void hdlcdev_tx_timeout(struct net_device *dev)
1768 {
1769         struct slgt_info *info = dev_to_port(dev);
1770         unsigned long flags;
1771
1772         DBGINFO(("%s hdlcdev_tx_timeout\n", dev->name));
1773
1774         dev->stats.tx_errors++;
1775         dev->stats.tx_aborted_errors++;
1776
1777         spin_lock_irqsave(&info->lock,flags);
1778         tx_stop(info);
1779         spin_unlock_irqrestore(&info->lock,flags);
1780
1781         netif_wake_queue(dev);
1782 }
1783
1784 /**
1785  * called by device driver when transmit completes
1786  * reenable network layer transmit if stopped
1787  *
1788  * info  pointer to device instance information
1789  */
1790 static void hdlcdev_tx_done(struct slgt_info *info)
1791 {
1792         if (netif_queue_stopped(info->netdev))
1793                 netif_wake_queue(info->netdev);
1794 }
1795
1796 /**
1797  * called by device driver when frame received
1798  * pass frame to network layer
1799  *
1800  * info  pointer to device instance information
1801  * buf   pointer to buffer contianing frame data
1802  * size  count of data bytes in buf
1803  */
1804 static void hdlcdev_rx(struct slgt_info *info, char *buf, int size)
1805 {
1806         struct sk_buff *skb = dev_alloc_skb(size);
1807         struct net_device *dev = info->netdev;
1808
1809         DBGINFO(("%s hdlcdev_rx\n", dev->name));
1810
1811         if (skb == NULL) {
1812                 DBGERR(("%s: can't alloc skb, drop packet\n", dev->name));
1813                 dev->stats.rx_dropped++;
1814                 return;
1815         }
1816
1817         memcpy(skb_put(skb, size), buf, size);
1818
1819         skb->protocol = hdlc_type_trans(skb, dev);
1820
1821         dev->stats.rx_packets++;
1822         dev->stats.rx_bytes += size;
1823
1824         netif_rx(skb);
1825
1826         dev->last_rx = jiffies;
1827 }
1828
1829 /**
1830  * called by device driver when adding device instance
1831  * do generic HDLC initialization
1832  *
1833  * info  pointer to device instance information
1834  *
1835  * returns 0 if success, otherwise error code
1836  */
1837 static int hdlcdev_init(struct slgt_info *info)
1838 {
1839         int rc;
1840         struct net_device *dev;
1841         hdlc_device *hdlc;
1842
1843         /* allocate and initialize network and HDLC layer objects */
1844
1845         if (!(dev = alloc_hdlcdev(info))) {
1846                 printk(KERN_ERR "%s hdlc device alloc failure\n", info->device_name);
1847                 return -ENOMEM;
1848         }
1849
1850         /* for network layer reporting purposes only */
1851         dev->mem_start = info->phys_reg_addr;
1852         dev->mem_end   = info->phys_reg_addr + SLGT_REG_SIZE - 1;
1853         dev->irq       = info->irq_level;
1854
1855         /* network layer callbacks and settings */
1856         dev->do_ioctl       = hdlcdev_ioctl;
1857         dev->open           = hdlcdev_open;
1858         dev->stop           = hdlcdev_close;
1859         dev->tx_timeout     = hdlcdev_tx_timeout;
1860         dev->watchdog_timeo = 10*HZ;
1861         dev->tx_queue_len   = 50;
1862
1863         /* generic HDLC layer callbacks and settings */
1864         hdlc         = dev_to_hdlc(dev);
1865         hdlc->attach = hdlcdev_attach;
1866         hdlc->xmit   = hdlcdev_xmit;
1867
1868         /* register objects with HDLC layer */
1869         if ((rc = register_hdlc_device(dev))) {
1870                 printk(KERN_WARNING "%s:unable to register hdlc device\n",__FILE__);
1871                 free_netdev(dev);
1872                 return rc;
1873         }
1874
1875         info->netdev = dev;
1876         return 0;
1877 }
1878
1879 /**
1880  * called by device driver when removing device instance
1881  * do generic HDLC cleanup
1882  *
1883  * info  pointer to device instance information
1884  */
1885 static void hdlcdev_exit(struct slgt_info *info)
1886 {
1887         unregister_hdlc_device(info->netdev);
1888         free_netdev(info->netdev);
1889         info->netdev = NULL;
1890 }
1891
1892 #endif /* ifdef CONFIG_HDLC */
1893
1894 /*
1895  * get async data from rx DMA buffers
1896  */
1897 static void rx_async(struct slgt_info *info)
1898 {
1899         struct tty_struct *tty = info->port.tty;
1900         struct mgsl_icount *icount = &info->icount;
1901         unsigned int start, end;
1902         unsigned char *p;
1903         unsigned char status;
1904         struct slgt_desc *bufs = info->rbufs;
1905         int i, count;
1906         int chars = 0;
1907         int stat;
1908         unsigned char ch;
1909
1910         start = end = info->rbuf_current;
1911
1912         while(desc_complete(bufs[end])) {
1913                 count = desc_count(bufs[end]) - info->rbuf_index;
1914                 p     = bufs[end].buf + info->rbuf_index;
1915
1916                 DBGISR(("%s rx_async count=%d\n", info->device_name, count));
1917                 DBGDATA(info, p, count, "rx");
1918
1919                 for(i=0 ; i < count; i+=2, p+=2) {
1920                         ch = *p;
1921                         icount->rx++;
1922
1923                         stat = 0;
1924
1925                         if ((status = *(p+1) & (BIT1 + BIT0))) {
1926                                 if (status & BIT1)
1927                                         icount->parity++;
1928                                 else if (status & BIT0)
1929                                         icount->frame++;
1930                                 /* discard char if tty control flags say so */
1931                                 if (status & info->ignore_status_mask)
1932                                         continue;
1933                                 if (status & BIT1)
1934                                         stat = TTY_PARITY;
1935                                 else if (status & BIT0)
1936                                         stat = TTY_FRAME;
1937                         }
1938                         if (tty) {
1939                                 tty_insert_flip_char(tty, ch, stat);
1940                                 chars++;
1941                         }
1942                 }
1943
1944                 if (i < count) {
1945                         /* receive buffer not completed */
1946                         info->rbuf_index += i;
1947                         mod_timer(&info->rx_timer, jiffies + 1);
1948                         break;
1949                 }
1950
1951                 info->rbuf_index = 0;
1952                 free_rbufs(info, end, end);
1953
1954                 if (++end == info->rbuf_count)
1955                         end = 0;
1956
1957                 /* if entire list searched then no frame available */
1958                 if (end == start)
1959                         break;
1960         }
1961
1962         if (tty && chars)
1963                 tty_flip_buffer_push(tty);
1964 }
1965
1966 /*
1967  * return next bottom half action to perform
1968  */
1969 static int bh_action(struct slgt_info *info)
1970 {
1971         unsigned long flags;
1972         int rc;
1973
1974         spin_lock_irqsave(&info->lock,flags);
1975
1976         if (info->pending_bh & BH_RECEIVE) {
1977                 info->pending_bh &= ~BH_RECEIVE;
1978                 rc = BH_RECEIVE;
1979         } else if (info->pending_bh & BH_TRANSMIT) {
1980                 info->pending_bh &= ~BH_TRANSMIT;
1981                 rc = BH_TRANSMIT;
1982         } else if (info->pending_bh & BH_STATUS) {
1983                 info->pending_bh &= ~BH_STATUS;
1984                 rc = BH_STATUS;
1985         } else {
1986                 /* Mark BH routine as complete */
1987                 info->bh_running = false;
1988                 info->bh_requested = false;
1989                 rc = 0;
1990         }
1991
1992         spin_unlock_irqrestore(&info->lock,flags);
1993
1994         return rc;
1995 }
1996
1997 /*
1998  * perform bottom half processing
1999  */
2000 static void bh_handler(struct work_struct *work)
2001 {
2002         struct slgt_info *info = container_of(work, struct slgt_info, task);
2003         int action;
2004
2005         if (!info)
2006                 return;
2007         info->bh_running = true;
2008
2009         while((action = bh_action(info))) {
2010                 switch (action) {
2011                 case BH_RECEIVE:
2012                         DBGBH(("%s bh receive\n", info->device_name));
2013                         switch(info->params.mode) {
2014                         case MGSL_MODE_ASYNC:
2015                                 rx_async(info);
2016                                 break;
2017                         case MGSL_MODE_HDLC:
2018                                 while(rx_get_frame(info));
2019                                 break;
2020                         case MGSL_MODE_RAW:
2021                         case MGSL_MODE_MONOSYNC:
2022                         case MGSL_MODE_BISYNC:
2023                                 while(rx_get_buf(info));
2024                                 break;
2025                         }
2026                         /* restart receiver if rx DMA buffers exhausted */
2027                         if (info->rx_restart)
2028                                 rx_start(info);
2029                         break;
2030                 case BH_TRANSMIT:
2031                         bh_transmit(info);
2032                         break;
2033                 case BH_STATUS:
2034                         DBGBH(("%s bh status\n", info->device_name));
2035                         info->ri_chkcount = 0;
2036                         info->dsr_chkcount = 0;
2037                         info->dcd_chkcount = 0;
2038                         info->cts_chkcount = 0;
2039                         break;
2040                 default:
2041                         DBGBH(("%s unknown action\n", info->device_name));
2042                         break;
2043                 }
2044         }
2045         DBGBH(("%s bh_handler exit\n", info->device_name));
2046 }
2047
2048 static void bh_transmit(struct slgt_info *info)
2049 {
2050         struct tty_struct *tty = info->port.tty;
2051
2052         DBGBH(("%s bh_transmit\n", info->device_name));
2053         if (tty)
2054                 tty_wakeup(tty);
2055 }
2056
2057 static void dsr_change(struct slgt_info *info, unsigned short status)
2058 {
2059         if (status & BIT3) {
2060                 info->signals |= SerialSignal_DSR;
2061                 info->input_signal_events.dsr_up++;
2062         } else {
2063                 info->signals &= ~SerialSignal_DSR;
2064                 info->input_signal_events.dsr_down++;
2065         }
2066         DBGISR(("dsr_change %s signals=%04X\n", info->device_name, info->signals));
2067         if ((info->dsr_chkcount)++ == IO_PIN_SHUTDOWN_LIMIT) {
2068                 slgt_irq_off(info, IRQ_DSR);
2069                 return;
2070         }
2071         info->icount.dsr++;
2072         wake_up_interruptible(&info->status_event_wait_q);
2073         wake_up_interruptible(&info->event_wait_q);
2074         info->pending_bh |= BH_STATUS;
2075 }
2076
2077 static void cts_change(struct slgt_info *info, unsigned short status)
2078 {
2079         if (status & BIT2) {
2080                 info->signals |= SerialSignal_CTS;
2081                 info->input_signal_events.cts_up++;
2082         } else {
2083                 info->signals &= ~SerialSignal_CTS;
2084                 info->input_signal_events.cts_down++;
2085         }
2086         DBGISR(("cts_change %s signals=%04X\n", info->device_name, info->signals));
2087         if ((info->cts_chkcount)++ == IO_PIN_SHUTDOWN_LIMIT) {
2088                 slgt_irq_off(info, IRQ_CTS);
2089                 return;
2090         }
2091         info->icount.cts++;
2092         wake_up_interruptible(&info->status_event_wait_q);
2093         wake_up_interruptible(&info->event_wait_q);
2094         info->pending_bh |= BH_STATUS;
2095
2096         if (info->port.flags & ASYNC_CTS_FLOW) {
2097                 if (info->port.tty) {
2098                         if (info->port.tty->hw_stopped) {
2099                                 if (info->signals & SerialSignal_CTS) {
2100                                         info->port.tty->hw_stopped = 0;
2101                                         info->pending_bh |= BH_TRANSMIT;
2102                                         return;
2103                                 }
2104                         } else {
2105                                 if (!(info->signals & SerialSignal_CTS))
2106                                         info->port.tty->hw_stopped = 1;
2107                         }
2108                 }
2109         }
2110 }
2111
2112 static void dcd_change(struct slgt_info *info, unsigned short status)
2113 {
2114         if (status & BIT1) {
2115                 info->signals |= SerialSignal_DCD;
2116                 info->input_signal_events.dcd_up++;
2117         } else {
2118                 info->signals &= ~SerialSignal_DCD;
2119                 info->input_signal_events.dcd_down++;
2120         }
2121         DBGISR(("dcd_change %s signals=%04X\n", info->device_name, info->signals));
2122         if ((info->dcd_chkcount)++ == IO_PIN_SHUTDOWN_LIMIT) {
2123                 slgt_irq_off(info, IRQ_DCD);
2124                 return;
2125         }
2126         info->icount.dcd++;
2127 #if SYNCLINK_GENERIC_HDLC
2128         if (info->netcount) {
2129                 if (info->signals & SerialSignal_DCD)
2130                         netif_carrier_on(info->netdev);
2131                 else
2132                         netif_carrier_off(info->netdev);
2133         }
2134 #endif
2135         wake_up_interruptible(&info->status_event_wait_q);
2136         wake_up_interruptible(&info->event_wait_q);
2137         info->pending_bh |= BH_STATUS;
2138
2139         if (info->port.flags & ASYNC_CHECK_CD) {
2140                 if (info->signals & SerialSignal_DCD)
2141                         wake_up_interruptible(&info->port.open_wait);
2142                 else {
2143                         if (info->port.tty)
2144                                 tty_hangup(info->port.tty);
2145                 }
2146         }
2147 }
2148
2149 static void ri_change(struct slgt_info *info, unsigned short status)
2150 {
2151         if (status & BIT0) {
2152                 info->signals |= SerialSignal_RI;
2153                 info->input_signal_events.ri_up++;
2154         } else {
2155                 info->signals &= ~SerialSignal_RI;
2156                 info->input_signal_events.ri_down++;
2157         }
2158         DBGISR(("ri_change %s signals=%04X\n", info->device_name, info->signals));
2159         if ((info->ri_chkcount)++ == IO_PIN_SHUTDOWN_LIMIT) {
2160                 slgt_irq_off(info, IRQ_RI);
2161                 return;
2162         }
2163         info->icount.rng++;
2164         wake_up_interruptible(&info->status_event_wait_q);
2165         wake_up_interruptible(&info->event_wait_q);
2166         info->pending_bh |= BH_STATUS;
2167 }
2168
2169 static void isr_serial(struct slgt_info *info)
2170 {
2171         unsigned short status = rd_reg16(info, SSR);
2172
2173         DBGISR(("%s isr_serial status=%04X\n", info->device_name, status));
2174
2175         wr_reg16(info, SSR, status); /* clear pending */
2176
2177         info->irq_occurred = true;
2178
2179         if (info->params.mode == MGSL_MODE_ASYNC) {
2180                 if (status & IRQ_TXIDLE) {
2181                         if (info->tx_count)
2182                                 isr_txeom(info, status);
2183                 }
2184                 if ((status & IRQ_RXBREAK) && (status & RXBREAK)) {
2185                         info->icount.brk++;
2186                         /* process break detection if tty control allows */
2187                         if (info->port.tty) {
2188                                 if (!(status & info->ignore_status_mask)) {
2189                                         if (info->read_status_mask & MASK_BREAK) {
2190                                                 tty_insert_flip_char(info->port.tty, 0, TTY_BREAK);
2191                                                 if (info->port.flags & ASYNC_SAK)
2192                                                         do_SAK(info->port.tty);
2193                                         }
2194                                 }
2195                         }
2196                 }
2197         } else {
2198                 if (status & (IRQ_TXIDLE + IRQ_TXUNDER))
2199                         isr_txeom(info, status);
2200
2201                 if (status & IRQ_RXIDLE) {
2202                         if (status & RXIDLE)
2203                                 info->icount.rxidle++;
2204                         else
2205                                 info->icount.exithunt++;
2206                         wake_up_interruptible(&info->event_wait_q);
2207                 }
2208
2209                 if (status & IRQ_RXOVER)
2210                         rx_start(info);
2211         }
2212
2213         if (status & IRQ_DSR)
2214                 dsr_change(info, status);
2215         if (status & IRQ_CTS)
2216                 cts_change(info, status);
2217         if (status & IRQ_DCD)
2218                 dcd_change(info, status);
2219         if (status & IRQ_RI)
2220                 ri_change(info, status);
2221 }
2222
2223 static void isr_rdma(struct slgt_info *info)
2224 {
2225         unsigned int status = rd_reg32(info, RDCSR);
2226
2227         DBGISR(("%s isr_rdma status=%08x\n", info->device_name, status));
2228
2229         /* RDCSR (rx DMA control/status)
2230          *
2231          * 31..07  reserved
2232          * 06      save status byte to DMA buffer
2233          * 05      error
2234          * 04      eol (end of list)
2235          * 03      eob (end of buffer)
2236          * 02      IRQ enable
2237          * 01      reset
2238          * 00      enable
2239          */
2240         wr_reg32(info, RDCSR, status);  /* clear pending */
2241
2242         if (status & (BIT5 + BIT4)) {
2243                 DBGISR(("%s isr_rdma rx_restart=1\n", info->device_name));
2244                 info->rx_restart = true;
2245         }
2246         info->pending_bh |= BH_RECEIVE;
2247 }
2248
2249 static void isr_tdma(struct slgt_info *info)
2250 {
2251         unsigned int status = rd_reg32(info, TDCSR);
2252
2253         DBGISR(("%s isr_tdma status=%08x\n", info->device_name, status));
2254
2255         /* TDCSR (tx DMA control/status)
2256          *
2257          * 31..06  reserved
2258          * 05      error
2259          * 04      eol (end of list)
2260          * 03      eob (end of buffer)
2261          * 02      IRQ enable
2262          * 01      reset
2263          * 00      enable
2264          */
2265         wr_reg32(info, TDCSR, status);  /* clear pending */
2266
2267         if (status & (BIT5 + BIT4 + BIT3)) {
2268                 // another transmit buffer has completed
2269                 // run bottom half to get more send data from user
2270                 info->pending_bh |= BH_TRANSMIT;
2271         }
2272 }
2273
2274 static void isr_txeom(struct slgt_info *info, unsigned short status)
2275 {
2276         DBGISR(("%s txeom status=%04x\n", info->device_name, status));
2277
2278         slgt_irq_off(info, IRQ_TXDATA + IRQ_TXIDLE + IRQ_TXUNDER);
2279         tdma_reset(info);
2280         reset_tbufs(info);
2281         if (status & IRQ_TXUNDER) {
2282                 unsigned short val = rd_reg16(info, TCR);
2283                 wr_reg16(info, TCR, (unsigned short)(val | BIT2)); /* set reset bit */
2284                 wr_reg16(info, TCR, val); /* clear reset bit */
2285         }
2286
2287         if (info->tx_active) {
2288                 if (info->params.mode != MGSL_MODE_ASYNC) {
2289                         if (status & IRQ_TXUNDER)
2290                                 info->icount.txunder++;
2291                         else if (status & IRQ_TXIDLE)
2292                                 info->icount.txok++;
2293                 }
2294
2295                 info->tx_active = false;
2296                 info->tx_count = 0;
2297
2298                 del_timer(&info->tx_timer);
2299
2300                 if (info->params.mode != MGSL_MODE_ASYNC && info->drop_rts_on_tx_done) {
2301                         info->signals &= ~SerialSignal_RTS;
2302                         info->drop_rts_on_tx_done = false;
2303                         set_signals(info);
2304                 }
2305
2306 #if SYNCLINK_GENERIC_HDLC
2307                 if (info->netcount)
2308                         hdlcdev_tx_done(info);
2309                 else
2310 #endif
2311                 {
2312                         if (info->port.tty && (info->port.tty->stopped || info->port.tty->hw_stopped)) {
2313                                 tx_stop(info);
2314                                 return;
2315                         }
2316                         info->pending_bh |= BH_TRANSMIT;
2317                 }
2318         }
2319 }
2320
2321 static void isr_gpio(struct slgt_info *info, unsigned int changed, unsigned int state)
2322 {
2323         struct cond_wait *w, *prev;
2324
2325         /* wake processes waiting for specific transitions */
2326         for (w = info->gpio_wait_q, prev = NULL ; w != NULL ; w = w->next) {
2327                 if (w->data & changed) {
2328                         w->data = state;
2329                         wake_up_interruptible(&w->q);
2330                         if (prev != NULL)
2331                                 prev->next = w->next;
2332                         else
2333                                 info->gpio_wait_q = w->next;
2334                 } else
2335                         prev = w;
2336         }
2337 }
2338
2339 /* interrupt service routine
2340  *
2341  *      irq     interrupt number
2342  *      dev_id  device ID supplied during interrupt registration
2343  */
2344 static irqreturn_t slgt_interrupt(int dummy, void *dev_id)
2345 {
2346         struct slgt_info *info = dev_id;
2347         unsigned int gsr;
2348         unsigned int i;
2349
2350         DBGISR(("slgt_interrupt irq=%d entry\n", info->irq_level));
2351
2352         spin_lock(&info->lock);
2353
2354         while((gsr = rd_reg32(info, GSR) & 0xffffff00)) {
2355                 DBGISR(("%s gsr=%08x\n", info->device_name, gsr));
2356                 info->irq_occurred = true;
2357                 for(i=0; i < info->port_count ; i++) {
2358                         if (info->port_array[i] == NULL)
2359                                 continue;
2360                         if (gsr & (BIT8 << i))
2361                                 isr_serial(info->port_array[i]);
2362                         if (gsr & (BIT16 << (i*2)))
2363                                 isr_rdma(info->port_array[i]);
2364                         if (gsr & (BIT17 << (i*2)))
2365                                 isr_tdma(info->port_array[i]);
2366                 }
2367         }
2368
2369         if (info->gpio_present) {
2370                 unsigned int state;
2371                 unsigned int changed;
2372                 while ((changed = rd_reg32(info, IOSR)) != 0) {
2373                         DBGISR(("%s iosr=%08x\n", info->device_name, changed));
2374                         /* read latched state of GPIO signals */
2375                         state = rd_reg32(info, IOVR);
2376                         /* clear pending GPIO interrupt bits */
2377                         wr_reg32(info, IOSR, changed);
2378                         for (i=0 ; i < info->port_count ; i++) {
2379                                 if (info->port_array[i] != NULL)
2380                                         isr_gpio(info->port_array[i], changed, state);
2381                         }
2382                 }
2383         }
2384
2385         for(i=0; i < info->port_count ; i++) {
2386                 struct slgt_info *port = info->port_array[i];
2387
2388                 if (port && (port->port.count || port->netcount) &&
2389                     port->pending_bh && !port->bh_running &&
2390                     !port->bh_requested) {
2391                         DBGISR(("%s bh queued\n", port->device_name));
2392                         schedule_work(&port->task);
2393                         port->bh_requested = true;
2394                 }
2395         }
2396
2397         spin_unlock(&info->lock);
2398
2399         DBGISR(("slgt_interrupt irq=%d exit\n", info->irq_level));
2400         return IRQ_HANDLED;
2401 }
2402
2403 static int startup(struct slgt_info *info)
2404 {
2405         DBGINFO(("%s startup\n", info->device_name));
2406
2407         if (info->port.flags & ASYNC_INITIALIZED)
2408                 return 0;
2409
2410         if (!info->tx_buf) {
2411                 info->tx_buf = kmalloc(info->max_frame_size, GFP_KERNEL);
2412                 if (!info->tx_buf) {
2413                         DBGERR(("%s can't allocate tx buffer\n", info->device_name));
2414                         return -ENOMEM;
2415                 }
2416         }
2417
2418         info->pending_bh = 0;
2419
2420         memset(&info->icount, 0, sizeof(info->icount));
2421
2422         /* program hardware for current parameters */
2423         change_params(info);
2424
2425         if (info->port.tty)
2426                 clear_bit(TTY_IO_ERROR, &info->port.tty->flags);
2427
2428         info->port.flags |= ASYNC_INITIALIZED;
2429
2430         return 0;
2431 }
2432
2433 /*
2434  *  called by close() and hangup() to shutdown hardware
2435  */
2436 static void shutdown(struct slgt_info *info)
2437 {
2438         unsigned long flags;
2439
2440         if (!(info->port.flags & ASYNC_INITIALIZED))
2441                 return;
2442
2443         DBGINFO(("%s shutdown\n", info->device_name));
2444
2445         /* clear status wait queue because status changes */
2446         /* can't happen after shutting down the hardware */
2447         wake_up_interruptible(&info->status_event_wait_q);
2448         wake_up_interruptible(&info->event_wait_q);
2449
2450         del_timer_sync(&info->tx_timer);
2451         del_timer_sync(&info->rx_timer);
2452
2453         kfree(info->tx_buf);
2454         info->tx_buf = NULL;
2455
2456         spin_lock_irqsave(&info->lock,flags);
2457
2458         tx_stop(info);
2459         rx_stop(info);
2460
2461         slgt_irq_off(info, IRQ_ALL | IRQ_MASTER);
2462
2463         if (!info->port.tty || info->port.tty->termios->c_cflag & HUPCL) {
2464                 info->signals &= ~(SerialSignal_DTR + SerialSignal_RTS);
2465                 set_signals(info);
2466         }
2467
2468         flush_cond_wait(&info->gpio_wait_q);
2469
2470         spin_unlock_irqrestore(&info->lock,flags);
2471
2472         if (info->port.tty)
2473                 set_bit(TTY_IO_ERROR, &info->port.tty->flags);
2474
2475         info->port.flags &= ~ASYNC_INITIALIZED;
2476 }
2477
2478 static void program_hw(struct slgt_info *info)
2479 {
2480         unsigned long flags;
2481
2482         spin_lock_irqsave(&info->lock,flags);
2483
2484         rx_stop(info);
2485         tx_stop(info);
2486
2487         if (info->params.mode != MGSL_MODE_ASYNC ||
2488             info->netcount)
2489                 sync_mode(info);
2490         else
2491                 async_mode(info);
2492
2493         set_signals(info);
2494
2495         info->dcd_chkcount = 0;
2496         info->cts_chkcount = 0;
2497         info->ri_chkcount = 0;
2498         info->dsr_chkcount = 0;
2499
2500         slgt_irq_on(info, IRQ_DCD | IRQ_CTS | IRQ_DSR);
2501         get_signals(info);
2502
2503         if (info->netcount ||
2504             (info->port.tty && info->port.tty->termios->c_cflag & CREAD))
2505                 rx_start(info);
2506
2507         spin_unlock_irqrestore(&info->lock,flags);
2508 }
2509
2510 /*
2511  * reconfigure adapter based on new parameters
2512  */
2513 static void change_params(struct slgt_info *info)
2514 {
2515         unsigned cflag;
2516         int bits_per_char;
2517
2518         if (!info->port.tty || !info->port.tty->termios)
2519                 return;
2520         DBGINFO(("%s change_params\n", info->device_name));
2521
2522         cflag = info->port.tty->termios->c_cflag;
2523
2524         /* if B0 rate (hangup) specified then negate DTR and RTS */
2525         /* otherwise assert DTR and RTS */
2526         if (cflag & CBAUD)
2527                 info->signals |= SerialSignal_RTS + SerialSignal_DTR;
2528         else
2529                 info->signals &= ~(SerialSignal_RTS + SerialSignal_DTR);
2530
2531         /* byte size and parity */
2532
2533         switch (cflag & CSIZE) {
2534         case CS5: info->params.data_bits = 5; break;
2535         case CS6: info->params.data_bits = 6; break;
2536         case CS7: info->params.data_bits = 7; break;
2537         case CS8: info->params.data_bits = 8; break;
2538         default:  info->params.data_bits = 7; break;
2539         }
2540
2541         info->params.stop_bits = (cflag & CSTOPB) ? 2 : 1;
2542
2543         if (cflag & PARENB)
2544                 info->params.parity = (cflag & PARODD) ? ASYNC_PARITY_ODD : ASYNC_PARITY_EVEN;
2545         else
2546                 info->params.parity = ASYNC_PARITY_NONE;
2547
2548         /* calculate number of jiffies to transmit a full
2549          * FIFO (32 bytes) at specified data rate
2550          */
2551         bits_per_char = info->params.data_bits +
2552                         info->params.stop_bits + 1;
2553
2554         info->params.data_rate = tty_get_baud_rate(info->port.tty);
2555
2556         if (info->params.data_rate) {
2557                 info->timeout = (32*HZ*bits_per_char) /
2558                                 info->params.data_rate;
2559         }
2560         info->timeout += HZ/50;         /* Add .02 seconds of slop */
2561
2562         if (cflag & CRTSCTS)
2563                 info->port.flags |= ASYNC_CTS_FLOW;
2564         else
2565                 info->port.flags &= ~ASYNC_CTS_FLOW;
2566
2567         if (cflag & CLOCAL)
2568                 info->port.flags &= ~ASYNC_CHECK_CD;
2569         else
2570                 info->port.flags |= ASYNC_CHECK_CD;
2571
2572         /* process tty input control flags */
2573
2574         info->read_status_mask = IRQ_RXOVER;
2575         if (I_INPCK(info->port.tty))
2576                 info->read_status_mask |= MASK_PARITY | MASK_FRAMING;
2577         if (I_BRKINT(info->port.tty) || I_PARMRK(info->port.tty))
2578                 info->read_status_mask |= MASK_BREAK;
2579         if (I_IGNPAR(info->port.tty))
2580                 info->ignore_status_mask |= MASK_PARITY | MASK_FRAMING;
2581         if (I_IGNBRK(info->port.tty)) {
2582                 info->ignore_status_mask |= MASK_BREAK;
2583                 /* If ignoring parity and break indicators, ignore
2584                  * overruns too.  (For real raw support).
2585                  */
2586                 if (I_IGNPAR(info->port.tty))
2587                         info->ignore_status_mask |= MASK_OVERRUN;
2588         }
2589
2590         program_hw(info);
2591 }
2592
2593 static int get_stats(struct slgt_info *info, struct mgsl_icount __user *user_icount)
2594 {
2595         DBGINFO(("%s get_stats\n",  info->device_name));
2596         if (!user_icount) {
2597                 memset(&info->icount, 0, sizeof(info->icount));
2598         } else {
2599                 if (copy_to_user(user_icount, &info->icount, sizeof(struct mgsl_icount)))
2600                         return -EFAULT;
2601         }
2602         return 0;
2603 }
2604
2605 static int get_params(struct slgt_info *info, MGSL_PARAMS __user *user_params)
2606 {
2607         DBGINFO(("%s get_params\n", info->device_name));
2608         if (copy_to_user(user_params, &info->params, sizeof(MGSL_PARAMS)))
2609                 return -EFAULT;
2610         return 0;
2611 }
2612
2613 static int set_params(struct slgt_info *info, MGSL_PARAMS __user *new_params)
2614 {
2615         unsigned long flags;
2616         MGSL_PARAMS tmp_params;
2617
2618         DBGINFO(("%s set_params\n", info->device_name));
2619         if (copy_from_user(&tmp_params, new_params, sizeof(MGSL_PARAMS)))
2620                 return -EFAULT;
2621
2622         spin_lock_irqsave(&info->lock, flags);
2623         memcpy(&info->params, &tmp_params, sizeof(MGSL_PARAMS));
2624         spin_unlock_irqrestore(&info->lock, flags);
2625
2626         change_params(info);
2627
2628         return 0;
2629 }
2630
2631 static int get_txidle(struct slgt_info *info, int __user *idle_mode)
2632 {
2633         DBGINFO(("%s get_txidle=%d\n", info->device_name, info->idle_mode));
2634         if (put_user(info->idle_mode, idle_mode))
2635                 return -EFAULT;
2636         return 0;
2637 }
2638
2639 static int set_txidle(struct slgt_info *info, int idle_mode)
2640 {
2641         unsigned long flags;
2642         DBGINFO(("%s set_txidle(%d)\n", info->device_name, idle_mode));
2643         spin_lock_irqsave(&info->lock,flags);
2644         info->idle_mode = idle_mode;
2645         if (info->params.mode != MGSL_MODE_ASYNC)
2646                 tx_set_idle(info);
2647         spin_unlock_irqrestore(&info->lock,flags);
2648         return 0;
2649 }
2650
2651 static int tx_enable(struct slgt_info *info, int enable)
2652 {
2653         unsigned long flags;
2654         DBGINFO(("%s tx_enable(%d)\n", info->device_name, enable));
2655         spin_lock_irqsave(&info->lock,flags);
2656         if (enable) {
2657                 if (!info->tx_enabled)
2658                         tx_start(info);
2659         } else {
2660                 if (info->tx_enabled)
2661                         tx_stop(info);
2662         }
2663         spin_unlock_irqrestore(&info->lock,flags);
2664         return 0;
2665 }
2666
2667 /*
2668  * abort transmit HDLC frame
2669  */
2670 static int tx_abort(struct slgt_info *info)
2671 {
2672         unsigned long flags;
2673         DBGINFO(("%s tx_abort\n", info->device_name));
2674         spin_lock_irqsave(&info->lock,flags);
2675         tdma_reset(info);
2676         spin_unlock_irqrestore(&info->lock,flags);
2677         return 0;
2678 }
2679
2680 static int rx_enable(struct slgt_info *info, int enable)
2681 {
2682         unsigned long flags;
2683         DBGINFO(("%s rx_enable(%d)\n", info->device_name, enable));
2684         spin_lock_irqsave(&info->lock,flags);
2685         if (enable) {
2686                 if (!info->rx_enabled)
2687                         rx_start(info);
2688                 else if (enable == 2) {
2689                         /* force hunt mode (write 1 to RCR[3]) */
2690                         wr_reg16(info, RCR, rd_reg16(info, RCR) | BIT3);
2691                 }
2692         } else {
2693                 if (info->rx_enabled)
2694                         rx_stop(info);
2695         }
2696         spin_unlock_irqrestore(&info->lock,flags);
2697         return 0;
2698 }
2699
2700 /*
2701  *  wait for specified event to occur
2702  */
2703 static int wait_mgsl_event(struct slgt_info *info, int __user *mask_ptr)
2704 {
2705         unsigned long flags;
2706         int s;
2707         int rc=0;
2708         struct mgsl_icount cprev, cnow;
2709         int events;
2710         int mask;
2711         struct  _input_signal_events oldsigs, newsigs;
2712         DECLARE_WAITQUEUE(wait, current);
2713
2714         if (get_user(mask, mask_ptr))
2715                 return -EFAULT;
2716
2717         DBGINFO(("%s wait_mgsl_event(%d)\n", info->device_name, mask));
2718
2719         spin_lock_irqsave(&info->lock,flags);
2720
2721         /* return immediately if state matches requested events */
2722         get_signals(info);
2723         s = info->signals;
2724
2725         events = mask &
2726                 ( ((s & SerialSignal_DSR) ? MgslEvent_DsrActive:MgslEvent_DsrInactive) +
2727                   ((s & SerialSignal_DCD) ? MgslEvent_DcdActive:MgslEvent_DcdInactive) +
2728                   ((s & SerialSignal_CTS) ? MgslEvent_CtsActive:MgslEvent_CtsInactive) +
2729                   ((s & SerialSignal_RI)  ? MgslEvent_RiActive :MgslEvent_RiInactive) );
2730         if (events) {
2731                 spin_unlock_irqrestore(&info->lock,flags);
2732                 goto exit;
2733         }
2734
2735         /* save current irq counts */
2736         cprev = info->icount;
2737         oldsigs = info->input_signal_events;
2738
2739         /* enable hunt and idle irqs if needed */
2740         if (mask & (MgslEvent_ExitHuntMode+MgslEvent_IdleReceived)) {
2741                 unsigned short val = rd_reg16(info, SCR);
2742                 if (!(val & IRQ_RXIDLE))
2743                         wr_reg16(info, SCR, (unsigned short)(val | IRQ_RXIDLE));
2744         }
2745
2746         set_current_state(TASK_INTERRUPTIBLE);
2747         add_wait_queue(&info->event_wait_q, &wait);
2748
2749         spin_unlock_irqrestore(&info->lock,flags);
2750
2751         for(;;) {
2752                 schedule();
2753                 if (signal_pending(current)) {
2754                         rc = -ERESTARTSYS;
2755                         break;
2756                 }
2757
2758                 /* get current irq counts */
2759                 spin_lock_irqsave(&info->lock,flags);
2760                 cnow = info->icount;
2761                 newsigs = info->input_signal_events;
2762                 set_current_state(TASK_INTERRUPTIBLE);
2763                 spin_unlock_irqrestore(&info->lock,flags);
2764
2765                 /* if no change, wait aborted for some reason */
2766                 if (newsigs.dsr_up   == oldsigs.dsr_up   &&
2767                     newsigs.dsr_down == oldsigs.dsr_down &&
2768                     newsigs.dcd_up   == oldsigs.dcd_up   &&
2769                     newsigs.dcd_down == oldsigs.dcd_down &&
2770                     newsigs.cts_up   == oldsigs.cts_up   &&
2771                     newsigs.cts_down == oldsigs.cts_down &&
2772                     newsigs.ri_up    == oldsigs.ri_up    &&
2773                     newsigs.ri_down  == oldsigs.ri_down  &&
2774                     cnow.exithunt    == cprev.exithunt   &&
2775                     cnow.rxidle      == cprev.rxidle) {
2776                         rc = -EIO;
2777                         break;
2778                 }
2779
2780                 events = mask &
2781                         ( (newsigs.dsr_up   != oldsigs.dsr_up   ? MgslEvent_DsrActive:0)   +
2782                           (newsigs.dsr_down != oldsigs.dsr_down ? MgslEvent_DsrInactive:0) +
2783                           (newsigs.dcd_up   != oldsigs.dcd_up   ? MgslEvent_DcdActive:0)   +
2784                           (newsigs.dcd_down != oldsigs.dcd_down ? MgslEvent_DcdInactive:0) +
2785                           (newsigs.cts_up   != oldsigs.cts_up   ? MgslEvent_CtsActive:0)   +
2786                           (newsigs.cts_down != oldsigs.cts_down ? MgslEvent_CtsInactive:0) +
2787                           (newsigs.ri_up    != oldsigs.ri_up    ? MgslEvent_RiActive:0)    +
2788                           (newsigs.ri_down  != oldsigs.ri_down  ? MgslEvent_RiInactive:0)  +
2789                           (cnow.exithunt    != cprev.exithunt   ? MgslEvent_ExitHuntMode:0) +
2790                           (cnow.rxidle      != cprev.rxidle     ? MgslEvent_IdleReceived:0) );
2791                 if (events)
2792                         break;
2793
2794                 cprev = cnow;
2795                 oldsigs = newsigs;
2796         }
2797
2798         remove_wait_queue(&info->event_wait_q, &wait);
2799         set_current_state(TASK_RUNNING);
2800
2801
2802         if (mask & (MgslEvent_ExitHuntMode + MgslEvent_IdleReceived)) {
2803                 spin_lock_irqsave(&info->lock,flags);
2804                 if (!waitqueue_active(&info->event_wait_q)) {
2805                         /* disable enable exit hunt mode/idle rcvd IRQs */
2806                         wr_reg16(info, SCR,
2807                                 (unsigned short)(rd_reg16(info, SCR) & ~IRQ_RXIDLE));
2808                 }
2809                 spin_unlock_irqrestore(&info->lock,flags);
2810         }
2811 exit:
2812         if (rc == 0)
2813                 rc = put_user(events, mask_ptr);
2814         return rc;
2815 }
2816
2817 static int get_interface(struct slgt_info *info, int __user *if_mode)
2818 {
2819         DBGINFO(("%s get_interface=%x\n", info->device_name, info->if_mode));
2820         if (put_user(info->if_mode, if_mode))
2821                 return -EFAULT;
2822         return 0;
2823 }
2824
2825 static int set_interface(struct slgt_info *info, int if_mode)
2826 {
2827         unsigned long flags;
2828         unsigned short val;
2829
2830         DBGINFO(("%s set_interface=%x)\n", info->device_name, if_mode));
2831         spin_lock_irqsave(&info->lock,flags);
2832         info->if_mode = if_mode;
2833
2834         msc_set_vcr(info);
2835
2836         /* TCR (tx control) 07  1=RTS driver control */
2837         val = rd_reg16(info, TCR);
2838         if (info->if_mode & MGSL_INTERFACE_RTS_EN)
2839                 val |= BIT7;
2840         else
2841                 val &= ~BIT7;
2842         wr_reg16(info, TCR, val);
2843
2844         spin_unlock_irqrestore(&info->lock,flags);
2845         return 0;
2846 }
2847
2848 /*
2849  * set general purpose IO pin state and direction
2850  *
2851  * user_gpio fields:
2852  * state   each bit indicates a pin state
2853  * smask   set bit indicates pin state to set
2854  * dir     each bit indicates a pin direction (0=input, 1=output)
2855  * dmask   set bit indicates pin direction to set
2856  */
2857 static int set_gpio(struct slgt_info *info, struct gpio_desc __user *user_gpio)
2858 {
2859         unsigned long flags;
2860         struct gpio_desc gpio;
2861         __u32 data;
2862
2863         if (!info->gpio_present)
2864                 return -EINVAL;
2865         if (copy_from_user(&gpio, user_gpio, sizeof(gpio)))
2866                 return -EFAULT;
2867         DBGINFO(("%s set_gpio state=%08x smask=%08x dir=%08x dmask=%08x\n",
2868                  info->device_name, gpio.state, gpio.smask,
2869                  gpio.dir, gpio.dmask));
2870
2871         spin_lock_irqsave(&info->lock,flags);
2872         if (gpio.dmask) {
2873                 data = rd_reg32(info, IODR);
2874                 data |= gpio.dmask & gpio.dir;
2875                 data &= ~(gpio.dmask & ~gpio.dir);
2876                 wr_reg32(info, IODR, data);
2877         }
2878         if (gpio.smask) {
2879                 data = rd_reg32(info, IOVR);
2880                 data |= gpio.smask & gpio.state;
2881                 data &= ~(gpio.smask & ~gpio.state);
2882                 wr_reg32(info, IOVR, data);
2883         }
2884         spin_unlock_irqrestore(&info->lock,flags);
2885
2886         return 0;
2887 }
2888
2889 /*
2890  * get general purpose IO pin state and direction
2891  */
2892 static int get_gpio(struct slgt_info *info, struct gpio_desc __user *user_gpio)
2893 {
2894         struct gpio_desc gpio;
2895         if (!info->gpio_present)
2896                 return -EINVAL;
2897         gpio.state = rd_reg32(info, IOVR);
2898         gpio.smask = 0xffffffff;
2899         gpio.dir   = rd_reg32(info, IODR);
2900         gpio.dmask = 0xffffffff;
2901         if (copy_to_user(user_gpio, &gpio, sizeof(gpio)))
2902                 return -EFAULT;
2903         DBGINFO(("%s get_gpio state=%08x dir=%08x\n",
2904                  info->device_name, gpio.state, gpio.dir));
2905         return 0;
2906 }
2907
2908 /*
2909  * conditional wait facility
2910  */
2911 static void init_cond_wait(struct cond_wait *w, unsigned int data)
2912 {
2913         init_waitqueue_head(&w->q);
2914         init_waitqueue_entry(&w->wait, current);
2915         w->data = data;
2916 }
2917
2918 static void add_cond_wait(struct cond_wait **head, struct cond_wait *w)
2919 {
2920         set_current_state(TASK_INTERRUPTIBLE);
2921         add_wait_queue(&w->q, &w->wait);
2922         w->next = *head;
2923         *head = w;
2924 }
2925
2926 static void remove_cond_wait(struct cond_wait **head, struct cond_wait *cw)
2927 {
2928         struct cond_wait *w, *prev;
2929         remove_wait_queue(&cw->q, &cw->wait);
2930         set_current_state(TASK_RUNNING);
2931         for (w = *head, prev = NULL ; w != NULL ; prev = w, w = w->next) {
2932                 if (w == cw) {
2933                         if (prev != NULL)
2934                                 prev->next = w->next;
2935                         else
2936                                 *head = w->next;
2937                         break;
2938                 }
2939         }
2940 }
2941
2942 static void flush_cond_wait(struct cond_wait **head)
2943 {
2944         while (*head != NULL) {
2945                 wake_up_interruptible(&(*head)->q);
2946                 *head = (*head)->next;
2947         }
2948 }
2949
2950 /*
2951  * wait for general purpose I/O pin(s) to enter specified state
2952  *
2953  * user_gpio fields:
2954  * state - bit indicates target pin state
2955  * smask - set bit indicates watched pin
2956  *
2957  * The wait ends when at least one watched pin enters the specified
2958  * state. When 0 (no error) is returned, user_gpio->state is set to the
2959  * state of all GPIO pins when the wait ends.
2960  *
2961  * Note: Each pin may be a dedicated input, dedicated output, or
2962  * configurable input/output. The number and configuration of pins
2963  * varies with the specific adapter model. Only input pins (dedicated
2964  * or configured) can be monitored with this function.
2965  */
2966 static int wait_gpio(struct slgt_info *info, struct gpio_desc __user *user_gpio)
2967 {
2968         unsigned long flags;
2969         int rc = 0;
2970         struct gpio_desc gpio;
2971         struct cond_wait wait;
2972         u32 state;
2973
2974         if (!info->gpio_present)
2975                 return -EINVAL;
2976         if (copy_from_user(&gpio, user_gpio, sizeof(gpio)))
2977                 return -EFAULT;
2978         DBGINFO(("%s wait_gpio() state=%08x smask=%08x\n",
2979                  info->device_name, gpio.state, gpio.smask));
2980         /* ignore output pins identified by set IODR bit */
2981         if ((gpio.smask &= ~rd_reg32(info, IODR)) == 0)
2982                 return -EINVAL;
2983         init_cond_wait(&wait, gpio.smask);
2984
2985         spin_lock_irqsave(&info->lock, flags);
2986         /* enable interrupts for watched pins */
2987         wr_reg32(info, IOER, rd_reg32(info, IOER) | gpio.smask);
2988         /* get current pin states */
2989         state = rd_reg32(info, IOVR);
2990
2991         if (gpio.smask & ~(state ^ gpio.state)) {
2992                 /* already in target state */
2993                 gpio.state = state;
2994         } else {
2995                 /* wait for target state */
2996                 add_cond_wait(&info->gpio_wait_q, &wait);
2997                 spin_unlock_irqrestore(&info->lock, flags);
2998                 schedule();
2999                 if (signal_pending(current))
3000                         rc = -ERESTARTSYS;
3001                 else
3002                         gpio.state = wait.data;
3003                 spin_lock_irqsave(&info->lock, flags);
3004                 remove_cond_wait(&info->gpio_wait_q, &wait);
3005         }
3006
3007         /* disable all GPIO interrupts if no waiting processes */
3008         if (info->gpio_wait_q == NULL)
3009                 wr_reg32(info, IOER, 0);
3010         spin_unlock_irqrestore(&info->lock,flags);
3011
3012         if ((rc == 0) && copy_to_user(user_gpio, &gpio, sizeof(gpio)))
3013                 rc = -EFAULT;
3014         return rc;
3015 }
3016
3017 static int modem_input_wait(struct slgt_info *info,int arg)
3018 {
3019         unsigned long flags;
3020         int rc;
3021         struct mgsl_icount cprev, cnow;
3022         DECLARE_WAITQUEUE(wait, current);
3023
3024         /* save current irq counts */
3025         spin_lock_irqsave(&info->lock,flags);
3026         cprev = info->icount;
3027         add_wait_queue(&info->status_event_wait_q, &wait);
3028         set_current_state(TASK_INTERRUPTIBLE);
3029         spin_unlock_irqrestore(&info->lock,flags);
3030
3031         for(;;) {
3032                 schedule();
3033                 if (signal_pending(current)) {
3034                         rc = -ERESTARTSYS;
3035                         break;
3036                 }
3037
3038                 /* get new irq counts */
3039                 spin_lock_irqsave(&info->lock,flags);
3040                 cnow = info->icount;
3041                 set_current_state(TASK_INTERRUPTIBLE);
3042                 spin_unlock_irqrestore(&info->lock,flags);
3043
3044                 /* if no change, wait aborted for some reason */
3045                 if (cnow.rng == cprev.rng && cnow.dsr == cprev.dsr &&
3046                     cnow.dcd == cprev.dcd && cnow.cts == cprev.cts) {
3047                         rc = -EIO;
3048                         break;
3049                 }
3050
3051                 /* check for change in caller specified modem input */
3052                 if ((arg & TIOCM_RNG && cnow.rng != cprev.rng) ||
3053                     (arg & TIOCM_DSR && cnow.dsr != cprev.dsr) ||
3054                     (arg & TIOCM_CD  && cnow.dcd != cprev.dcd) ||
3055                     (arg & TIOCM_CTS && cnow.cts != cprev.cts)) {
3056                         rc = 0;
3057                         break;
3058                 }
3059
3060                 cprev = cnow;
3061         }
3062         remove_wait_queue(&info->status_event_wait_q, &wait);
3063         set_current_state(TASK_RUNNING);
3064         return rc;
3065 }
3066
3067 /*
3068  *  return state of serial control and status signals
3069  */
3070 static int tiocmget(struct tty_struct *tty, struct file *file)
3071 {
3072         struct slgt_info *info = tty->driver_data;
3073         unsigned int result;
3074         unsigned long flags;
3075
3076         spin_lock_irqsave(&info->lock,flags);
3077         get_signals(info);
3078         spin_unlock_irqrestore(&info->lock,flags);
3079
3080         result = ((info->signals & SerialSignal_RTS) ? TIOCM_RTS:0) +
3081                 ((info->signals & SerialSignal_DTR) ? TIOCM_DTR:0) +
3082                 ((info->signals & SerialSignal_DCD) ? TIOCM_CAR:0) +
3083                 ((info->signals & SerialSignal_RI)  ? TIOCM_RNG:0) +
3084                 ((info->signals & SerialSignal_DSR) ? TIOCM_DSR:0) +
3085                 ((info->signals & SerialSignal_CTS) ? TIOCM_CTS:0);
3086
3087         DBGINFO(("%s tiocmget value=%08X\n", info->device_name, result));
3088         return result;
3089 }
3090
3091 /*
3092  * set modem control signals (DTR/RTS)
3093  *
3094  *      cmd     signal command: TIOCMBIS = set bit TIOCMBIC = clear bit
3095  *              TIOCMSET = set/clear signal values
3096  *      value   bit mask for command
3097  */
3098 static int tiocmset(struct tty_struct *tty, struct file *file,
3099                     unsigned int set, unsigned int clear)
3100 {
3101         struct slgt_info *info = tty->driver_data;
3102         unsigned long flags;
3103
3104         DBGINFO(("%s tiocmset(%x,%x)\n", info->device_name, set, clear));
3105
3106         if (set & TIOCM_RTS)
3107                 info->signals |= SerialSignal_RTS;
3108         if (set & TIOCM_DTR)
3109                 info->signals |= SerialSignal_DTR;
3110         if (clear & TIOCM_RTS)
3111                 info->signals &= ~SerialSignal_RTS;
3112         if (clear & TIOCM_DTR)
3113                 info->signals &= ~SerialSignal_DTR;
3114
3115         spin_lock_irqsave(&info->lock,flags);
3116         set_signals(info);
3117         spin_unlock_irqrestore(&info->lock,flags);
3118         return 0;
3119 }
3120
3121 /*
3122  *  block current process until the device is ready to open
3123  */
3124 static int block_til_ready(struct tty_struct *tty, struct file *filp,
3125                            struct slgt_info *info)
3126 {
3127         DECLARE_WAITQUEUE(wait, current);
3128         int             retval;
3129         bool            do_clocal = false;
3130         bool            extra_count = false;
3131         unsigned long   flags;
3132
3133         DBGINFO(("%s block_til_ready\n", tty->driver->name));
3134
3135         if (filp->f_flags & O_NONBLOCK || tty->flags & (1 << TTY_IO_ERROR)){
3136                 /* nonblock mode is set or port is not enabled */
3137                 info->port.flags |= ASYNC_NORMAL_ACTIVE;
3138                 return 0;
3139         }
3140
3141         if (tty->termios->c_cflag & CLOCAL)
3142                 do_clocal = true;
3143
3144         /* Wait for carrier detect and the line to become
3145          * free (i.e., not in use by the callout).  While we are in
3146          * this loop, info->port.count is dropped by one, so that
3147          * close() knows when to free things.  We restore it upon
3148          * exit, either normal or abnormal.
3149          */
3150
3151         retval = 0;
3152         add_wait_queue(&info->port.open_wait, &wait);
3153
3154         spin_lock_irqsave(&info->lock, flags);
3155         if (!tty_hung_up_p(filp)) {
3156                 extra_count = true;
3157                 info->port.count--;
3158         }
3159         spin_unlock_irqrestore(&info->lock, flags);
3160         info->port.blocked_open++;
3161
3162         while (1) {
3163                 if ((tty->termios->c_cflag & CBAUD)) {
3164                         spin_lock_irqsave(&info->lock,flags);
3165                         info->signals |= SerialSignal_RTS + SerialSignal_DTR;
3166                         set_signals(info);
3167                         spin_unlock_irqrestore(&info->lock,flags);
3168                 }
3169
3170                 set_current_state(TASK_INTERRUPTIBLE);
3171
3172                 if (tty_hung_up_p(filp) || !(info->port.flags & ASYNC_INITIALIZED)){
3173                         retval = (info->port.flags & ASYNC_HUP_NOTIFY) ?
3174                                         -EAGAIN : -ERESTARTSYS;
3175                         break;
3176                 }
3177
3178                 spin_lock_irqsave(&info->lock,flags);
3179                 get_signals(info);
3180                 spin_unlock_irqrestore(&info->lock,flags);
3181
3182                 if (!(info->port.flags & ASYNC_CLOSING) &&
3183                     (do_clocal || (info->signals & SerialSignal_DCD)) ) {
3184                         break;
3185                 }
3186
3187                 if (signal_pending(current)) {
3188                         retval = -ERESTARTSYS;
3189                         break;
3190                 }
3191
3192                 DBGINFO(("%s block_til_ready wait\n", tty->driver->name));
3193                 schedule();
3194         }
3195
3196         set_current_state(TASK_RUNNING);
3197         remove_wait_queue(&info->port.open_wait, &wait);
3198
3199         if (extra_count)
3200                 info->port.count++;
3201         info->port.blocked_open--;
3202
3203         if (!retval)
3204                 info->port.flags |= ASYNC_NORMAL_ACTIVE;
3205
3206         DBGINFO(("%s block_til_ready ready, rc=%d\n", tty->driver->name, retval));
3207         return retval;
3208 }
3209
3210 static int alloc_tmp_rbuf(struct slgt_info *info)
3211 {
3212         info->tmp_rbuf = kmalloc(info->max_frame_size + 5, GFP_KERNEL);
3213         if (info->tmp_rbuf == NULL)
3214                 return -ENOMEM;
3215         return 0;
3216 }
3217
3218 static void free_tmp_rbuf(struct slgt_info *info)
3219 {
3220         kfree(info->tmp_rbuf);
3221         info->tmp_rbuf = NULL;
3222 }
3223
3224 /*
3225  * allocate DMA descriptor lists.
3226  */
3227 static int alloc_desc(struct slgt_info *info)
3228 {
3229         unsigned int i;
3230         unsigned int pbufs;
3231
3232         /* allocate memory to hold descriptor lists */
3233         info->bufs = pci_alloc_consistent(info->pdev, DESC_LIST_SIZE, &info->bufs_dma_addr);
3234         if (info->bufs == NULL)
3235                 return -ENOMEM;
3236
3237         memset(info->bufs, 0, DESC_LIST_SIZE);
3238
3239         info->rbufs = (struct slgt_desc*)info->bufs;
3240         info->tbufs = ((struct slgt_desc*)info->bufs) + info->rbuf_count;
3241
3242         pbufs = (unsigned int)info->bufs_dma_addr;
3243
3244         /*
3245          * Build circular lists of descriptors
3246          */
3247
3248         for (i=0; i < info->rbuf_count; i++) {
3249                 /* physical address of this descriptor */
3250                 info->rbufs[i].pdesc = pbufs + (i * sizeof(struct slgt_desc));
3251
3252                 /* physical address of next descriptor */
3253                 if (i == info->rbuf_count - 1)
3254                         info->rbufs[i].next = cpu_to_le32(pbufs);
3255                 else
3256                         info->rbufs[i].next = cpu_to_le32(pbufs + ((i+1) * sizeof(struct slgt_desc)));
3257                 set_desc_count(info->rbufs[i], DMABUFSIZE);
3258         }
3259
3260         for (i=0; i < info->tbuf_count; i++) {
3261                 /* physical address of this descriptor */
3262                 info->tbufs[i].pdesc = pbufs + ((info->rbuf_count + i) * sizeof(struct slgt_desc));
3263
3264                 /* physical address of next descriptor */
3265                 if (i == info->tbuf_count - 1)
3266                         info->tbufs[i].next = cpu_to_le32(pbufs + info->rbuf_count * sizeof(struct slgt_desc));
3267                 else
3268                         info->tbufs[i].next = cpu_to_le32(pbufs + ((info->rbuf_count + i + 1) * sizeof(struct slgt_desc)));
3269         }
3270
3271         return 0;
3272 }
3273
3274 static void free_desc(struct slgt_info *info)
3275 {
3276         if (info->bufs != NULL) {
3277                 pci_free_consistent(info->pdev, DESC_LIST_SIZE, info->bufs, info->bufs_dma_addr);
3278                 info->bufs  = NULL;
3279                 info->rbufs = NULL;
3280                 info->tbufs = NULL;
3281         }
3282 }
3283
3284 static int alloc_bufs(struct slgt_info *info, struct slgt_desc *bufs, int count)
3285 {
3286         int i;
3287         for (i=0; i < count; i++) {
3288                 if ((bufs[i].buf = pci_alloc_consistent(info->pdev, DMABUFSIZE, &bufs[i].buf_dma_addr)) == NULL)
3289                         return -ENOMEM;
3290                 bufs[i].pbuf  = cpu_to_le32((unsigned int)bufs[i].buf_dma_addr);
3291         }
3292         return 0;
3293 }
3294
3295 static void free_bufs(struct slgt_info *info, struct slgt_desc *bufs, int count)
3296 {
3297         int i;
3298         for (i=0; i < count; i++) {
3299                 if (bufs[i].buf == NULL)
3300                         continue;
3301                 pci_free_consistent(info->pdev, DMABUFSIZE, bufs[i].buf, bufs[i].buf_dma_addr);
3302                 bufs[i].buf = NULL;
3303         }
3304 }
3305
3306 static int alloc_dma_bufs(struct slgt_info *info)
3307 {
3308         info->rbuf_count = 32;
3309         info->tbuf_count = 32;
3310
3311         if (alloc_desc(info) < 0 ||
3312             alloc_bufs(info, info->rbufs, info->rbuf_count) < 0 ||
3313             alloc_bufs(info, info->tbufs, info->tbuf_count) < 0 ||
3314             alloc_tmp_rbuf(info) < 0) {
3315                 DBGERR(("%s DMA buffer alloc fail\n", info->device_name));
3316                 return -ENOMEM;
3317         }
3318         reset_rbufs(info);
3319         return 0;
3320 }
3321
3322 static void free_dma_bufs(struct slgt_info *info)
3323 {
3324         if (info->bufs) {
3325                 free_bufs(info, info->rbufs, info->rbuf_count);
3326                 free_bufs(info, info->tbufs, info->tbuf_count);
3327                 free_desc(info);
3328         }
3329         free_tmp_rbuf(info);
3330 }
3331
3332 static int claim_resources(struct slgt_info *info)
3333 {
3334         if (request_mem_region(info->phys_reg_addr, SLGT_REG_SIZE, "synclink_gt") == NULL) {
3335                 DBGERR(("%s reg addr conflict, addr=%08X\n",
3336                         info->device_name, info->phys_reg_addr));
3337                 info->init_error = DiagStatus_AddressConflict;
3338                 goto errout;
3339         }
3340         else
3341                 info->reg_addr_requested = true;
3342
3343         info->reg_addr = ioremap_nocache(info->phys_reg_addr, SLGT_REG_SIZE);
3344         if (!info->reg_addr) {
3345                 DBGERR(("%s cant map device registers, addr=%08X\n",
3346                         info->device_name, info->phys_reg_addr));
3347                 info->init_error = DiagStatus_CantAssignPciResources;
3348                 goto errout;
3349         }
3350         return 0;
3351
3352 errout:
3353         release_resources(info);
3354         return -ENODEV;
3355 }
3356
3357 static void release_resources(struct slgt_info *info)
3358 {
3359         if (info->irq_requested) {
3360                 free_irq(info->irq_level, info);
3361                 info->irq_requested = false;
3362         }
3363
3364         if (info->reg_addr_requested) {
3365                 release_mem_region(info->phys_reg_addr, SLGT_REG_SIZE);
3366                 info->reg_addr_requested = false;
3367         }
3368
3369         if (info->reg_addr) {
3370                 iounmap(info->reg_addr);
3371                 info->reg_addr = NULL;
3372         }
3373 }
3374
3375 /* Add the specified device instance data structure to the
3376  * global linked list of devices and increment the device count.
3377  */
3378 static void add_device(struct slgt_info *info)
3379 {
3380         char *devstr;
3381
3382         info->next_device = NULL;
3383         info->line = slgt_device_count;
3384         sprintf(info->device_name, "%s%d", tty_dev_prefix, info->line);
3385
3386         if (info->line < MAX_DEVICES) {
3387                 if (maxframe[info->line])
3388                         info->max_frame_size = maxframe[info->line];
3389                 info->dosyncppp = dosyncppp[info->line];
3390         }
3391
3392         slgt_device_count++;
3393
3394         if (!slgt_device_list)
3395                 slgt_device_list = info;
3396         else {
3397                 struct slgt_info *current_dev = slgt_device_list;
3398                 while(current_dev->next_device)
3399                         current_dev = current_dev->next_device;
3400                 current_dev->next_device = info;
3401         }
3402
3403         if (info->max_frame_size < 4096)
3404                 info->max_frame_size = 4096;
3405         else if (info->max_frame_size > 65535)
3406                 info->max_frame_size = 65535;
3407
3408         switch(info->pdev->device) {
3409         case SYNCLINK_GT_DEVICE_ID:
3410                 devstr = "GT";
3411                 break;
3412         case SYNCLINK_GT2_DEVICE_ID:
3413                 devstr = "GT2";
3414                 break;
3415         case SYNCLINK_GT4_DEVICE_ID:
3416                 devstr = "GT4";
3417                 break;
3418         case SYNCLINK_AC_DEVICE_ID:
3419                 devstr = "AC";
3420                 info->params.mode = MGSL_MODE_ASYNC;
3421                 break;
3422         default:
3423                 devstr = "(unknown model)";
3424         }
3425         printk("SyncLink %s %s IO=%08x IRQ=%d MaxFrameSize=%u\n",
3426                 devstr, info->device_name, info->phys_reg_addr,
3427                 info->irq_level, info->max_frame_size);
3428
3429 #if SYNCLINK_GENERIC_HDLC
3430         hdlcdev_init(info);
3431 #endif
3432 }
3433
3434 /*
3435  *  allocate device instance structure, return NULL on failure
3436  */
3437 static struct slgt_info *alloc_dev(int adapter_num, int port_num, struct pci_dev *pdev)
3438 {
3439         struct slgt_info *info;
3440
3441         info = kzalloc(sizeof(struct slgt_info), GFP_KERNEL);
3442
3443         if (!info) {
3444                 DBGERR(("%s device alloc failed adapter=%d port=%d\n",
3445                         driver_name, adapter_num, port_num));
3446         } else {
3447                 tty_port_init(&info->port);
3448                 info->magic = MGSL_MAGIC;
3449                 INIT_WORK(&info->task, bh_handler);
3450                 info->max_frame_size = 4096;
3451                 info->raw_rx_size = DMABUFSIZE;
3452                 info->port.close_delay = 5*HZ/10;
3453                 info->port.closing_wait = 30*HZ;
3454                 init_waitqueue_head(&info->status_event_wait_q);
3455                 init_waitqueue_head(&info->event_wait_q);
3456                 spin_lock_init(&info->netlock);
3457                 memcpy(&info->params,&default_params,sizeof(MGSL_PARAMS));
3458                 info->idle_mode = HDLC_TXIDLE_FLAGS;
3459                 info->adapter_num = adapter_num;
3460                 info->port_num = port_num;
3461
3462                 setup_timer(&info->tx_timer, tx_timeout, (unsigned long)info);
3463                 setup_timer(&info->rx_timer, rx_timeout, (unsigned long)info);
3464
3465                 /* Copy configuration info to device instance data */
3466                 info->pdev = pdev;
3467                 info->irq_level = pdev->irq;
3468                 info->phys_reg_addr = pci_resource_start(pdev,0);
3469
3470                 info->bus_type = MGSL_BUS_TYPE_PCI;
3471                 info->irq_flags = IRQF_SHARED;
3472
3473                 info->init_error = -1; /* assume error, set to 0 on successful init */
3474         }
3475
3476         return info;
3477 }
3478
3479 static void device_init(int adapter_num, struct pci_dev *pdev)
3480 {
3481         struct slgt_info *port_array[SLGT_MAX_PORTS];
3482         int i;
3483         int port_count = 1;
3484
3485         if (pdev->device == SYNCLINK_GT2_DEVICE_ID)
3486                 port_count = 2;
3487         else if (pdev->device == SYNCLINK_GT4_DEVICE_ID)
3488                 port_count = 4;
3489
3490         /* allocate device instances for all ports */
3491         for (i=0; i < port_count; ++i) {
3492                 port_array[i] = alloc_dev(adapter_num, i, pdev);
3493                 if (port_array[i] == NULL) {
3494                         for (--i; i >= 0; --i)
3495                                 kfree(port_array[i]);
3496                         return;
3497                 }
3498         }
3499
3500         /* give copy of port_array to all ports and add to device list  */
3501         for (i=0; i < port_count; ++i) {
3502                 memcpy(port_array[i]->port_array, port_array, sizeof(port_array));
3503                 add_device(port_array[i]);
3504                 port_array[i]->port_count = port_count;
3505                 spin_lock_init(&port_array[i]->lock);
3506         }
3507
3508         /* Allocate and claim adapter resources */
3509         if (!claim_resources(port_array[0])) {
3510
3511                 alloc_dma_bufs(port_array[0]);
3512
3513                 /* copy resource information from first port to others */
3514                 for (i = 1; i < port_count; ++i) {
3515                         port_array[i]->lock      = port_array[0]->lock;
3516                         port_array[i]->irq_level = port_array[0]->irq_level;
3517                         port_array[i]->reg_addr  = port_array[0]->reg_addr;
3518                         alloc_dma_bufs(port_array[i]);
3519                 }
3520
3521                 if (request_irq(port_array[0]->irq_level,
3522                                         slgt_interrupt,
3523                                         port_array[0]->irq_flags,
3524                                         port_array[0]->device_name,
3525                                         port_array[0]) < 0) {
3526                         DBGERR(("%s request_irq failed IRQ=%d\n",
3527                                 port_array[0]->device_name,
3528                                 port_array[0]->irq_level));
3529                 } else {
3530                         port_array[0]->irq_requested = true;
3531                         adapter_test(port_array[0]);
3532                         for (i=1 ; i < port_count ; i++) {
3533                                 port_array[i]->init_error = port_array[0]->init_error;
3534                                 port_array[i]->gpio_present = port_array[0]->gpio_present;
3535                         }
3536                 }
3537         }
3538
3539         for (i=0; i < port_count; ++i)
3540                 tty_register_device(serial_driver, port_array[i]->line, &(port_array[i]->pdev->dev));
3541 }
3542
3543 static int __devinit init_one(struct pci_dev *dev,
3544                               const struct pci_device_id *ent)
3545 {
3546         if (pci_enable_device(dev)) {
3547                 printk("error enabling pci device %p\n", dev);
3548                 return -EIO;
3549         }
3550         pci_set_master(dev);
3551         device_init(slgt_device_count, dev);
3552         return 0;
3553 }
3554
3555 static void __devexit remove_one(struct pci_dev *dev)
3556 {
3557 }
3558
3559 static const struct tty_operations ops = {
3560         .open = open,
3561         .close = close,
3562         .write = write,
3563         .put_char = put_char,
3564         .flush_chars = flush_chars,
3565         .write_room = write_room,
3566         .chars_in_buffer = chars_in_buffer,
3567         .flush_buffer = flush_buffer,
3568         .ioctl = ioctl,
3569         .compat_ioctl = slgt_compat_ioctl,
3570         .throttle = throttle,
3571         .unthrottle = unthrottle,
3572         .send_xchar = send_xchar,
3573         .break_ctl = set_break,
3574         .wait_until_sent = wait_until_sent,
3575         .read_proc = read_proc,
3576         .set_termios = set_termios,
3577         .stop = tx_hold,
3578         .start = tx_release,
3579         .hangup = hangup,
3580         .tiocmget = tiocmget,
3581         .tiocmset = tiocmset,
3582 };
3583
3584 static void slgt_cleanup(void)
3585 {
3586         int rc;
3587         struct slgt_info *info;
3588         struct slgt_info *tmp;
3589
3590         printk("unload %s %s\n", driver_name, driver_version);
3591
3592         if (serial_driver) {
3593                 for (info=slgt_device_list ; info != NULL ; info=info->next_device)
3594                         tty_unregister_device(serial_driver, info->line);
3595                 if ((rc = tty_unregister_driver(serial_driver)))
3596                         DBGERR(("tty_unregister_driver error=%d\n", rc));
3597                 put_tty_driver(serial_driver);
3598         }
3599
3600         /* reset devices */
3601         info = slgt_device_list;
3602         while(info) {
3603                 reset_port(info);
3604                 info = info->next_device;
3605         }
3606
3607         /* release devices */
3608         info = slgt_device_list;
3609         while(info) {
3610 #if SYNCLINK_GENERIC_HDLC
3611                 hdlcdev_exit(info);
3612 #endif
3613                 free_dma_bufs(info);
3614                 free_tmp_rbuf(info);
3615                 if (info->port_num == 0)
3616                         release_resources(info);
3617                 tmp = info;
3618                 info = info->next_device;
3619                 kfree(tmp);
3620         }
3621
3622         if (pci_registered)
3623                 pci_unregister_driver(&pci_driver);
3624 }
3625
3626 /*
3627  *  Driver initialization entry point.
3628  */
3629 static int __init slgt_init(void)
3630 {
3631         int rc;
3632
3633         printk("%s %s\n", driver_name, driver_version);
3634
3635         serial_driver = alloc_tty_driver(MAX_DEVICES);
3636         if (!serial_driver) {
3637                 printk("%s can't allocate tty driver\n", driver_name);
3638                 return -ENOMEM;
3639         }
3640
3641         /* Initialize the tty_driver structure */
3642
3643         serial_driver->owner = THIS_MODULE;
3644         serial_driver->driver_name = tty_driver_name;
3645         serial_driver->name = tty_dev_prefix;
3646         serial_driver->major = ttymajor;
3647         serial_driver->minor_start = 64;
3648         serial_driver->type = TTY_DRIVER_TYPE_SERIAL;
3649         serial_driver->subtype = SERIAL_TYPE_NORMAL;
3650         serial_driver->init_termios = tty_std_termios;
3651         serial_driver->init_termios.c_cflag =
3652                 B9600 | CS8 | CREAD | HUPCL | CLOCAL;
3653         serial_driver->init_termios.c_ispeed = 9600;
3654         serial_driver->init_termios.c_ospeed = 9600;
3655         serial_driver->flags = TTY_DRIVER_REAL_RAW | TTY_DRIVER_DYNAMIC_DEV;
3656         tty_set_operations(serial_driver, &ops);
3657         if ((rc = tty_register_driver(serial_driver)) < 0) {
3658                 DBGERR(("%s can't register serial driver\n", driver_name));
3659                 put_tty_driver(serial_driver);
3660                 serial_driver = NULL;
3661                 goto error;
3662         }
3663
3664         printk("%s %s, tty major#%d\n",
3665                 driver_name, driver_version,
3666                 serial_driver->major);
3667
3668         slgt_device_count = 0;
3669         if ((rc = pci_register_driver(&pci_driver)) < 0) {
3670                 printk("%s pci_register_driver error=%d\n", driver_name, rc);
3671                 goto error;
3672         }
3673         pci_registered = true;
3674
3675         if (!slgt_device_list)
3676                 printk("%s no devices found\n",driver_name);
3677
3678         return 0;
3679
3680 error:
3681         slgt_cleanup();
3682         return rc;
3683 }
3684
3685 static void __exit slgt_exit(void)
3686 {
3687         slgt_cleanup();
3688 }
3689
3690 module_init(slgt_init);
3691 module_exit(slgt_exit);
3692
3693 /*
3694  * register access routines
3695  */
3696
3697 #define CALC_REGADDR() \
3698         unsigned long reg_addr = ((unsigned long)info->reg_addr) + addr; \
3699         if (addr >= 0x80) \
3700                 reg_addr += (info->port_num) * 32;
3701
3702 static __u8 rd_reg8(struct slgt_info *info, unsigned int addr)
3703 {
3704         CALC_REGADDR();
3705         return readb((void __iomem *)reg_addr);
3706 }
3707
3708 static void wr_reg8(struct slgt_info *info, unsigned int addr, __u8 value)
3709 {
3710         CALC_REGADDR();
3711         writeb(value, (void __iomem *)reg_addr);
3712 }
3713
3714 static __u16 rd_reg16(struct slgt_info *info, unsigned int addr)
3715 {
3716         CALC_REGADDR();
3717         return readw((void __iomem *)reg_addr);
3718 }
3719
3720 static void wr_reg16(struct slgt_info *info, unsigned int addr, __u16 value)
3721 {
3722         CALC_REGADDR();
3723         writew(value, (void __iomem *)reg_addr);
3724 }
3725
3726 static __u32 rd_reg32(struct slgt_info *info, unsigned int addr)
3727 {
3728         CALC_REGADDR();
3729         return readl((void __iomem *)reg_addr);
3730 }
3731
3732 static void wr_reg32(struct slgt_info *info, unsigned int addr, __u32 value)
3733 {
3734         CALC_REGADDR();
3735         writel(value, (void __iomem *)reg_addr);
3736 }
3737
3738 static void rdma_reset(struct slgt_info *info)
3739 {
3740         unsigned int i;
3741
3742         /* set reset bit */
3743         wr_reg32(info, RDCSR, BIT1);
3744
3745         /* wait for enable bit cleared */
3746         for(i=0 ; i < 1000 ; i++)
3747                 if (!(rd_reg32(info, RDCSR) & BIT0))
3748                         break;
3749 }
3750
3751 static void tdma_reset(struct slgt_info *info)
3752 {
3753         unsigned int i;
3754
3755         /* set reset bit */
3756         wr_reg32(info, TDCSR, BIT1);
3757
3758         /* wait for enable bit cleared */
3759         for(i=0 ; i < 1000 ; i++)
3760                 if (!(rd_reg32(info, TDCSR) & BIT0))
3761                         break;
3762 }
3763
3764 /*
3765  * enable internal loopback
3766  * TxCLK and RxCLK are generated from BRG
3767  * and TxD is looped back to RxD internally.
3768  */
3769 static void enable_loopback(struct slgt_info *info)
3770 {
3771         /* SCR (serial control) BIT2=looopback enable */
3772         wr_reg16(info, SCR, (unsigned short)(rd_reg16(info, SCR) | BIT2));
3773
3774         if (info->params.mode != MGSL_MODE_ASYNC) {
3775                 /* CCR (clock control)
3776                  * 07..05  tx clock source (010 = BRG)
3777                  * 04..02  rx clock source (010 = BRG)
3778                  * 01      auxclk enable   (0 = disable)
3779                  * 00      BRG enable      (1 = enable)
3780                  *
3781                  * 0100 1001
3782                  */
3783                 wr_reg8(info, CCR, 0x49);
3784
3785                 /* set speed if available, otherwise use default */
3786                 if (info->params.clock_speed)
3787                         set_rate(info, info->params.clock_speed);
3788                 else
3789                         set_rate(info, 3686400);
3790         }
3791 }
3792
3793 /*
3794  *  set baud rate generator to specified rate
3795  */
3796 static void set_rate(struct slgt_info *info, u32 rate)
3797 {
3798         unsigned int div;
3799         static unsigned int osc = 14745600;
3800
3801         /* div = osc/rate - 1
3802          *
3803          * Round div up if osc/rate is not integer to
3804          * force to next slowest rate.
3805          */
3806
3807         if (rate) {
3808                 div = osc/rate;
3809                 if (!(osc % rate) && div)
3810                         div--;
3811                 wr_reg16(info, BDR, (unsigned short)div);
3812         }
3813 }
3814
3815 static void rx_stop(struct slgt_info *info)
3816 {
3817         unsigned short val;
3818
3819         /* disable and reset receiver */
3820         val = rd_reg16(info, RCR) & ~BIT1;          /* clear enable bit */
3821         wr_reg16(info, RCR, (unsigned short)(val | BIT2)); /* set reset bit */
3822         wr_reg16(info, RCR, val);                  /* clear reset bit */
3823
3824         slgt_irq_off(info, IRQ_RXOVER + IRQ_RXDATA + IRQ_RXIDLE);
3825
3826         /* clear pending rx interrupts */
3827         wr_reg16(info, SSR, IRQ_RXIDLE + IRQ_RXOVER);
3828
3829         rdma_reset(info);
3830
3831         info->rx_enabled = false;
3832         info->rx_restart = false;
3833 }
3834
3835 static void rx_start(struct slgt_info *info)
3836 {
3837         unsigned short val;
3838
3839         slgt_irq_off(info, IRQ_RXOVER + IRQ_RXDATA);
3840
3841         /* clear pending rx overrun IRQ */
3842         wr_reg16(info, SSR, IRQ_RXOVER);
3843
3844         /* reset and disable receiver */
3845         val = rd_reg16(info, RCR) & ~BIT1; /* clear enable bit */
3846         wr_reg16(info, RCR, (unsigned short)(val | BIT2)); /* set reset bit */
3847         wr_reg16(info, RCR, val);                  /* clear reset bit */
3848
3849         rdma_reset(info);
3850         reset_rbufs(info);
3851
3852         /* set 1st descriptor address */
3853         wr_reg32(info, RDDAR, info->rbufs[0].pdesc);
3854
3855         if (info->params.mode != MGSL_MODE_ASYNC) {
3856                 /* enable rx DMA and DMA interrupt */
3857                 wr_reg32(info, RDCSR, (BIT2 + BIT0));
3858         } else {
3859                 /* enable saving of rx status, rx DMA and DMA interrupt */
3860                 wr_reg32(info, RDCSR, (BIT6 + BIT2 + BIT0));
3861         }
3862
3863         slgt_irq_on(info, IRQ_RXOVER);
3864
3865         /* enable receiver */
3866         wr_reg16(info, RCR, (unsigned short)(rd_reg16(info, RCR) | BIT1));
3867
3868         info->rx_restart = false;
3869         info->rx_enabled = true;
3870 }
3871
3872 static void tx_start(struct slgt_info *info)
3873 {
3874         if (!info->tx_enabled) {
3875                 wr_reg16(info, TCR,
3876                          (unsigned short)((rd_reg16(info, TCR) | BIT1) & ~BIT2));
3877                 info->tx_enabled = true;
3878         }
3879
3880         if (info->tx_count) {
3881                 info->drop_rts_on_tx_done = false;
3882
3883                 if (info->params.mode != MGSL_MODE_ASYNC) {
3884                         if (info->params.flags & HDLC_FLAG_AUTO_RTS) {
3885                                 get_signals(info);
3886                                 if (!(info->signals & SerialSignal_RTS)) {
3887                                         info->signals |= SerialSignal_RTS;
3888                                         set_signals(info);
3889                                         info->drop_rts_on_tx_done = true;
3890                                 }
3891                         }
3892
3893                         slgt_irq_off(info, IRQ_TXDATA);
3894                         slgt_irq_on(info, IRQ_TXUNDER + IRQ_TXIDLE);
3895                         /* clear tx idle and underrun status bits */
3896                         wr_reg16(info, SSR, (unsigned short)(IRQ_TXIDLE + IRQ_TXUNDER));
3897                         if (info->params.mode == MGSL_MODE_HDLC)
3898                                 mod_timer(&info->tx_timer, jiffies +
3899                                                 msecs_to_jiffies(5000));
3900                 } else {
3901                         slgt_irq_off(info, IRQ_TXDATA);
3902                         slgt_irq_on(info, IRQ_TXIDLE);
3903                         /* clear tx idle status bit */
3904                         wr_reg16(info, SSR, IRQ_TXIDLE);
3905                 }
3906                 tdma_start(info);
3907                 info->tx_active = true;
3908         }
3909 }
3910
3911 /*
3912  * start transmit DMA if inactive and there are unsent buffers
3913  */
3914 static void tdma_start(struct slgt_info *info)
3915 {
3916         unsigned int i;
3917
3918         if (rd_reg32(info, TDCSR) & BIT0)
3919                 return;
3920
3921         /* transmit DMA inactive, check for unsent buffers */
3922         i = info->tbuf_start;
3923         while (!desc_count(info->tbufs[i])) {
3924                 if (++i == info->tbuf_count)
3925                         i = 0;
3926                 if (i == info->tbuf_current)
3927                         return;
3928         }
3929         info->tbuf_start = i;
3930
3931         /* there are unsent buffers, start transmit DMA */
3932
3933         /* reset needed if previous error condition */
3934         tdma_reset(info);
3935
3936         /* set 1st descriptor address */
3937         wr_reg32(info, TDDAR, info->tbufs[info->tbuf_start].pdesc);
3938         switch(info->params.mode) {
3939         case MGSL_MODE_RAW:
3940         case MGSL_MODE_MONOSYNC:
3941         case MGSL_MODE_BISYNC:
3942                 wr_reg32(info, TDCSR, BIT2 + BIT0); /* IRQ + DMA enable */
3943                 break;
3944         default:
3945                 wr_reg32(info, TDCSR, BIT0); /* DMA enable */
3946         }
3947 }
3948
3949 static void tx_stop(struct slgt_info *info)
3950 {
3951         unsigned short val;
3952
3953         del_timer(&info->tx_timer);
3954
3955         tdma_reset(info);
3956
3957         /* reset and disable transmitter */
3958         val = rd_reg16(info, TCR) & ~BIT1;          /* clear enable bit */
3959         wr_reg16(info, TCR, (unsigned short)(val | BIT2)); /* set reset bit */
3960
3961         slgt_irq_off(info, IRQ_TXDATA + IRQ_TXIDLE + IRQ_TXUNDER);
3962
3963         /* clear tx idle and underrun status bit */
3964         wr_reg16(info, SSR, (unsigned short)(IRQ_TXIDLE + IRQ_TXUNDER));
3965
3966         reset_tbufs(info);
3967
3968         info->tx_enabled = false;
3969         info->tx_active = false;
3970 }
3971
3972 static void reset_port(struct slgt_info *info)
3973 {
3974         if (!info->reg_addr)
3975                 return;
3976
3977         tx_stop(info);
3978         rx_stop(info);
3979
3980         info->signals &= ~(SerialSignal_DTR + SerialSignal_RTS);
3981         set_signals(info);
3982
3983         slgt_irq_off(info, IRQ_ALL | IRQ_MASTER);
3984 }
3985
3986 static void reset_adapter(struct slgt_info *info)
3987 {
3988         int i;
3989         for (i=0; i < info->port_count; ++i) {
3990                 if (info->port_array[i])
3991                         reset_port(info->port_array[i]);
3992         }
3993 }
3994
3995 static void async_mode(struct slgt_info *info)
3996 {
3997         unsigned short val;
3998
3999         slgt_irq_off(info, IRQ_ALL | IRQ_MASTER);
4000         tx_stop(info);
4001         rx_stop(info);
4002
4003         /* TCR (tx control)
4004          *
4005          * 15..13  mode, 010=async
4006          * 12..10  encoding, 000=NRZ
4007          * 09      parity enable
4008          * 08      1=odd parity, 0=even parity
4009          * 07      1=RTS driver control
4010          * 06      1=break enable
4011          * 05..04  character length
4012          *         00=5 bits
4013          *         01=6 bits
4014          *         10=7 bits
4015          *         11=8 bits
4016          * 03      0=1 stop bit, 1=2 stop bits
4017          * 02      reset
4018          * 01      enable
4019          * 00      auto-CTS enable
4020          */
4021         val = 0x4000;
4022
4023         if (info->if_mode & MGSL_INTERFACE_RTS_EN)
4024                 val |= BIT7;
4025
4026         if (info->params.parity != ASYNC_PARITY_NONE) {
4027                 val |= BIT9;
4028                 if (info->params.parity == ASYNC_PARITY_ODD)
4029                         val |= BIT8;
4030         }
4031
4032         switch (info->params.data_bits)
4033         {
4034         case 6: val |= BIT4; break;
4035         case 7: val |= BIT5; break;
4036         case 8: val |= BIT5 + BIT4; break;
4037         }
4038
4039         if (info->params.stop_bits != 1)
4040                 val |= BIT3;
4041
4042         if (info->params.flags & HDLC_FLAG_AUTO_CTS)
4043                 val |= BIT0;
4044
4045         wr_reg16(info, TCR, val);
4046
4047         /* RCR (rx control)
4048          *
4049          * 15..13  mode, 010=async
4050          * 12..10  encoding, 000=NRZ
4051          * 09      parity enable
4052          * 08      1=odd parity, 0=even parity
4053          * 07..06  reserved, must be 0
4054          * 05..04  character length
4055          *         00=5 bits
4056          *         01=6 bits
4057          *         10=7 bits
4058          *         11=8 bits
4059          * 03      reserved, must be zero
4060          * 02      reset
4061          * 01      enable
4062          * 00      auto-DCD enable
4063          */
4064         val = 0x4000;
4065
4066         if (info->params.parity != ASYNC_PARITY_NONE) {
4067                 val |= BIT9;
4068                 if (info->params.parity == ASYNC_PARITY_ODD)
4069                         val |= BIT8;
4070         }
4071
4072         switch (info->params.data_bits)
4073         {
4074         case 6: val |= BIT4; break;
4075         case 7: val |= BIT5; break;
4076         case 8: val |= BIT5 + BIT4; break;
4077         }
4078
4079         if (info->params.flags & HDLC_FLAG_AUTO_DCD)
4080                 val |= BIT0;
4081
4082         wr_reg16(info, RCR, val);
4083
4084         /* CCR (clock control)
4085          *
4086          * 07..05  011 = tx clock source is BRG/16
4087          * 04..02  010 = rx clock source is BRG
4088          * 01      0 = auxclk disabled
4089          * 00      1 = BRG enabled
4090          *
4091          * 0110 1001
4092          */
4093         wr_reg8(info, CCR, 0x69);
4094
4095         msc_set_vcr(info);
4096
4097         /* SCR (serial control)
4098          *
4099          * 15  1=tx req on FIFO half empty
4100          * 14  1=rx req on FIFO half full
4101          * 13  tx data  IRQ enable
4102          * 12  tx idle  IRQ enable
4103          * 11  rx break on IRQ enable
4104          * 10  rx data  IRQ enable
4105          * 09  rx break off IRQ enable
4106          * 08  overrun  IRQ enable
4107          * 07  DSR      IRQ enable
4108          * 06  CTS      IRQ enable
4109          * 05  DCD      IRQ enable
4110          * 04  RI       IRQ enable
4111          * 03  reserved, must be zero
4112          * 02  1=txd->rxd internal loopback enable
4113          * 01  reserved, must be zero
4114          * 00  1=master IRQ enable
4115          */
4116         val = BIT15 + BIT14 + BIT0;
4117         wr_reg16(info, SCR, val);
4118
4119         slgt_irq_on(info, IRQ_RXBREAK | IRQ_RXOVER);
4120
4121         set_rate(info, info->params.data_rate * 16);
4122
4123         if (info->params.loopback)
4124                 enable_loopback(info);
4125 }
4126
4127 static void sync_mode(struct slgt_info *info)
4128 {
4129         unsigned short val;
4130
4131         slgt_irq_off(info, IRQ_ALL | IRQ_MASTER);
4132         tx_stop(info);
4133         rx_stop(info);
4134
4135         /* TCR (tx control)
4136          *
4137          * 15..13  mode, 000=HDLC 001=raw 010=async 011=monosync 100=bisync
4138          * 12..10  encoding
4139          * 09      CRC enable
4140          * 08      CRC32
4141          * 07      1=RTS driver control
4142          * 06      preamble enable
4143          * 05..04  preamble length
4144          * 03      share open/close flag
4145          * 02      reset
4146          * 01      enable
4147          * 00      auto-CTS enable
4148          */
4149         val = 0;
4150
4151         switch(info->params.mode) {
4152         case MGSL_MODE_MONOSYNC: val |= BIT14 + BIT13; break;
4153         case MGSL_MODE_BISYNC:   val |= BIT15; break;
4154         case MGSL_MODE_RAW:      val |= BIT13; break;
4155         }
4156         if (info->if_mode & MGSL_INTERFACE_RTS_EN)
4157                 val |= BIT7;
4158
4159         switch(info->params.encoding)
4160         {
4161         case HDLC_ENCODING_NRZB:          val |= BIT10; break;
4162         case HDLC_ENCODING_NRZI_MARK:     val |= BIT11; break;
4163         case HDLC_ENCODING_NRZI:          val |= BIT11 + BIT10; break;
4164         case HDLC_ENCODING_BIPHASE_MARK:  val |= BIT12; break;
4165         case HDLC_ENCODING_BIPHASE_SPACE: val |= BIT12 + BIT10; break;
4166         case HDLC_ENCODING_BIPHASE_LEVEL: val |= BIT12 + BIT11; break;
4167         case HDLC_ENCODING_DIFF_BIPHASE_LEVEL: val |= BIT12 + BIT11 + BIT10; break;
4168         }
4169
4170         switch (info->params.crc_type & HDLC_CRC_MASK)
4171         {
4172         case HDLC_CRC_16_CCITT: val |= BIT9; break;
4173         case HDLC_CRC_32_CCITT: val |= BIT9 + BIT8; break;
4174         }
4175
4176         if (info->params.preamble != HDLC_PREAMBLE_PATTERN_NONE)
4177                 val |= BIT6;
4178
4179         switch (info->params.preamble_length)
4180         {
4181         case HDLC_PREAMBLE_LENGTH_16BITS: val |= BIT5; break;
4182         case HDLC_PREAMBLE_LENGTH_32BITS: val |= BIT4; break;
4183         case HDLC_PREAMBLE_LENGTH_64BITS: val |= BIT5 + BIT4; break;
4184         }
4185
4186         if (info->params.flags & HDLC_FLAG_AUTO_CTS)
4187                 val |= BIT0;
4188
4189         wr_reg16(info, TCR, val);
4190
4191         /* TPR (transmit preamble) */
4192
4193         switch (info->params.preamble)
4194         {
4195         case HDLC_PREAMBLE_PATTERN_FLAGS: val = 0x7e; break;
4196         case HDLC_PREAMBLE_PATTERN_ONES:  val = 0xff; break;
4197         case HDLC_PREAMBLE_PATTERN_ZEROS: val = 0x00; break;
4198         case HDLC_PREAMBLE_PATTERN_10:    val = 0x55; break;
4199         case HDLC_PREAMBLE_PATTERN_01:    val = 0xaa; break;
4200         default:                          val = 0x7e; break;
4201         }
4202         wr_reg8(info, TPR, (unsigned char)val);
4203
4204         /* RCR (rx control)
4205          *
4206          * 15..13  mode, 000=HDLC 001=raw 010=async 011=monosync 100=bisync
4207          * 12..10  encoding
4208          * 09      CRC enable
4209          * 08      CRC32
4210          * 07..03  reserved, must be 0
4211          * 02      reset
4212          * 01      enable
4213          * 00      auto-DCD enable
4214          */
4215         val = 0;
4216
4217         switch(info->params.mode) {
4218         case MGSL_MODE_MONOSYNC: val |= BIT14 + BIT13; break;
4219         case MGSL_MODE_BISYNC:   val |= BIT15; break;
4220         case MGSL_MODE_RAW:      val |= BIT13; break;
4221         }
4222
4223         switch(info->params.encoding)
4224         {
4225         case HDLC_ENCODING_NRZB:          val |= BIT10; break;
4226         case HDLC_ENCODING_NRZI_MARK:     val |= BIT11; break;
4227         case HDLC_ENCODING_NRZI:          val |= BIT11 + BIT10; break;
4228         case HDLC_ENCODING_BIPHASE_MARK:  val |= BIT12; break;
4229         case HDLC_ENCODING_BIPHASE_SPACE: val |= BIT12 + BIT10; break;
4230         case HDLC_ENCODING_BIPHASE_LEVEL: val |= BIT12 + BIT11; break;
4231         case HDLC_ENCODING_DIFF_BIPHASE_LEVEL: val |= BIT12 + BIT11 + BIT10; break;
4232         }
4233
4234         switch (info->params.crc_type & HDLC_CRC_MASK)
4235         {
4236         case HDLC_CRC_16_CCITT: val |= BIT9; break;
4237         case HDLC_CRC_32_CCITT: val |= BIT9 + BIT8; break;
4238         }
4239
4240         if (info->params.flags & HDLC_FLAG_AUTO_DCD)
4241                 val |= BIT0;
4242
4243         wr_reg16(info, RCR, val);
4244
4245         /* CCR (clock control)
4246          *
4247          * 07..05  tx clock source
4248          * 04..02  rx clock source
4249          * 01      auxclk enable
4250          * 00      BRG enable
4251          */
4252         val = 0;
4253
4254         if (info->params.flags & HDLC_FLAG_TXC_BRG)
4255         {
4256                 // when RxC source is DPLL, BRG generates 16X DPLL
4257                 // reference clock, so take TxC from BRG/16 to get
4258                 // transmit clock at actual data rate
4259                 if (info->params.flags & HDLC_FLAG_RXC_DPLL)
4260                         val |= BIT6 + BIT5;     /* 011, txclk = BRG/16 */
4261                 else
4262                         val |= BIT6;    /* 010, txclk = BRG */
4263         }
4264         else if (info->params.flags & HDLC_FLAG_TXC_DPLL)
4265                 val |= BIT7;    /* 100, txclk = DPLL Input */
4266         else if (info->params.flags & HDLC_FLAG_TXC_RXCPIN)
4267                 val |= BIT5;    /* 001, txclk = RXC Input */
4268
4269         if (info->params.flags & HDLC_FLAG_RXC_BRG)
4270                 val |= BIT3;    /* 010, rxclk = BRG */
4271         else if (info->params.flags & HDLC_FLAG_RXC_DPLL)
4272                 val |= BIT4;    /* 100, rxclk = DPLL */
4273         else if (info->params.flags & HDLC_FLAG_RXC_TXCPIN)
4274                 val |= BIT2;    /* 001, rxclk = TXC Input */
4275
4276         if (info->params.clock_speed)
4277                 val |= BIT1 + BIT0;
4278
4279         wr_reg8(info, CCR, (unsigned char)val);
4280
4281         if (info->params.flags & (HDLC_FLAG_TXC_DPLL + HDLC_FLAG_RXC_DPLL))
4282         {
4283                 // program DPLL mode
4284                 switch(info->params.encoding)
4285                 {
4286                 case HDLC_ENCODING_BIPHASE_MARK:
4287                 case HDLC_ENCODING_BIPHASE_SPACE:
4288                         val = BIT7; break;
4289                 case HDLC_ENCODING_BIPHASE_LEVEL:
4290                 case HDLC_ENCODING_DIFF_BIPHASE_LEVEL:
4291                         val = BIT7 + BIT6; break;
4292                 default: val = BIT6;    // NRZ encodings
4293                 }
4294                 wr_reg16(info, RCR, (unsigned short)(rd_reg16(info, RCR) | val));
4295
4296                 // DPLL requires a 16X reference clock from BRG
4297                 set_rate(info, info->params.clock_speed * 16);
4298         }
4299         else
4300                 set_rate(info, info->params.clock_speed);
4301
4302         tx_set_idle(info);
4303
4304         msc_set_vcr(info);
4305
4306         /* SCR (serial control)
4307          *
4308          * 15  1=tx req on FIFO half empty
4309          * 14  1=rx req on FIFO half full
4310          * 13  tx data  IRQ enable
4311          * 12  tx idle  IRQ enable
4312          * 11  underrun IRQ enable
4313          * 10  rx data  IRQ enable
4314          * 09  rx idle  IRQ enable
4315          * 08  overrun  IRQ enable
4316          * 07  DSR      IRQ enable
4317          * 06  CTS      IRQ enable
4318          * 05  DCD      IRQ enable
4319          * 04  RI       IRQ enable
4320          * 03  reserved, must be zero
4321          * 02  1=txd->rxd internal loopback enable
4322          * 01  reserved, must be zero
4323          * 00  1=master IRQ enable
4324          */
4325         wr_reg16(info, SCR, BIT15 + BIT14 + BIT0);
4326
4327         if (info->params.loopback)
4328                 enable_loopback(info);
4329 }
4330
4331 /*
4332  *  set transmit idle mode
4333  */
4334 static void tx_set_idle(struct slgt_info *info)
4335 {
4336         unsigned char val;
4337         unsigned short tcr;
4338
4339         /* if preamble enabled (tcr[6] == 1) then tx idle size = 8 bits
4340          * else tcr[5:4] = tx idle size: 00 = 8 bits, 01 = 16 bits
4341          */
4342         tcr = rd_reg16(info, TCR);
4343         if (info->idle_mode & HDLC_TXIDLE_CUSTOM_16) {
4344                 /* disable preamble, set idle size to 16 bits */
4345                 tcr = (tcr & ~(BIT6 + BIT5)) | BIT4;
4346                 /* MSB of 16 bit idle specified in tx preamble register (TPR) */
4347                 wr_reg8(info, TPR, (unsigned char)((info->idle_mode >> 8) & 0xff));
4348         } else if (!(tcr & BIT6)) {
4349                 /* preamble is disabled, set idle size to 8 bits */
4350                 tcr &= ~(BIT5 + BIT4);
4351         }
4352         wr_reg16(info, TCR, tcr);
4353
4354         if (info->idle_mode & (HDLC_TXIDLE_CUSTOM_8 | HDLC_TXIDLE_CUSTOM_16)) {
4355                 /* LSB of custom tx idle specified in tx idle register */
4356                 val = (unsigned char)(info->idle_mode & 0xff);
4357         } else {
4358                 /* standard 8 bit idle patterns */
4359                 switch(info->idle_mode)
4360                 {
4361                 case HDLC_TXIDLE_FLAGS:          val = 0x7e; break;
4362                 case HDLC_TXIDLE_ALT_ZEROS_ONES:
4363                 case HDLC_TXIDLE_ALT_MARK_SPACE: val = 0xaa; break;
4364                 case HDLC_TXIDLE_ZEROS:
4365                 case HDLC_TXIDLE_SPACE:          val = 0x00; break;
4366                 default:                         val = 0xff;
4367                 }
4368         }
4369
4370         wr_reg8(info, TIR, val);
4371 }
4372
4373 /*
4374  * get state of V24 status (input) signals
4375  */
4376 static void get_signals(struct slgt_info *info)
4377 {
4378         unsigned short status = rd_reg16(info, SSR);
4379
4380         /* clear all serial signals except DTR and RTS */
4381         info->signals &= SerialSignal_DTR + SerialSignal_RTS;
4382
4383         if (status & BIT3)
4384                 info->signals |= SerialSignal_DSR;
4385         if (status & BIT2)
4386                 info->signals |= SerialSignal_CTS;
4387         if (status & BIT1)
4388                 info->signals |= SerialSignal_DCD;
4389         if (status & BIT0)
4390                 info->signals |= SerialSignal_RI;
4391 }
4392
4393 /*
4394  * set V.24 Control Register based on current configuration
4395  */
4396 static void msc_set_vcr(struct slgt_info *info)
4397 {
4398         unsigned char val = 0;
4399
4400         /* VCR (V.24 control)
4401          *
4402          * 07..04  serial IF select
4403          * 03      DTR
4404          * 02      RTS
4405          * 01      LL
4406          * 00      RL
4407          */
4408
4409         switch(info->if_mode & MGSL_INTERFACE_MASK)
4410         {
4411         case MGSL_INTERFACE_RS232:
4412                 val |= BIT5; /* 0010 */
4413                 break;
4414         case MGSL_INTERFACE_V35:
4415                 val |= BIT7 + BIT6 + BIT5; /* 1110 */
4416                 break;
4417         case MGSL_INTERFACE_RS422:
4418                 val |= BIT6; /* 0100 */
4419                 break;
4420         }
4421
4422         if (info->signals & SerialSignal_DTR)
4423                 val |= BIT3;
4424         if (info->signals & SerialSignal_RTS)
4425                 val |= BIT2;
4426         if (info->if_mode & MGSL_INTERFACE_LL)
4427                 val |= BIT1;
4428         if (info->if_mode & MGSL_INTERFACE_RL)
4429                 val |= BIT0;
4430         wr_reg8(info, VCR, val);
4431 }
4432
4433 /*
4434  * set state of V24 control (output) signals
4435  */
4436 static void set_signals(struct slgt_info *info)
4437 {
4438         unsigned char val = rd_reg8(info, VCR);
4439         if (info->signals & SerialSignal_DTR)
4440                 val |= BIT3;
4441         else
4442                 val &= ~BIT3;
4443         if (info->signals & SerialSignal_RTS)
4444                 val |= BIT2;
4445         else
4446                 val &= ~BIT2;
4447         wr_reg8(info, VCR, val);
4448 }
4449
4450 /*
4451  * free range of receive DMA buffers (i to last)
4452  */
4453 static void free_rbufs(struct slgt_info *info, unsigned int i, unsigned int last)
4454 {
4455         int done = 0;
4456
4457         while(!done) {
4458                 /* reset current buffer for reuse */
4459                 info->rbufs[i].status = 0;
4460                 switch(info->params.mode) {
4461                 case MGSL_MODE_RAW:
4462                 case MGSL_MODE_MONOSYNC:
4463                 case MGSL_MODE_BISYNC:
4464                         set_desc_count(info->rbufs[i], info->raw_rx_size);
4465                         break;
4466                 default:
4467                         set_desc_count(info->rbufs[i], DMABUFSIZE);
4468                 }
4469
4470                 if (i == last)
4471                         done = 1;
4472                 if (++i == info->rbuf_count)
4473                         i = 0;
4474         }
4475         info->rbuf_current = i;
4476 }
4477
4478 /*
4479  * mark all receive DMA buffers as free
4480  */
4481 static void reset_rbufs(struct slgt_info *info)
4482 {
4483         free_rbufs(info, 0, info->rbuf_count - 1);
4484 }
4485
4486 /*
4487  * pass receive HDLC frame to upper layer
4488  *
4489  * return true if frame available, otherwise false
4490  */
4491 static bool rx_get_frame(struct slgt_info *info)
4492 {
4493         unsigned int start, end;
4494         unsigned short status;
4495         unsigned int framesize = 0;
4496         unsigned long flags;
4497         struct tty_struct *tty = info->port.tty;
4498         unsigned char addr_field = 0xff;
4499         unsigned int crc_size = 0;
4500
4501         switch (info->params.crc_type & HDLC_CRC_MASK) {
4502         case HDLC_CRC_16_CCITT: crc_size = 2; break;
4503         case HDLC_CRC_32_CCITT: crc_size = 4; break;
4504         }
4505
4506 check_again:
4507
4508         framesize = 0;
4509         addr_field = 0xff;
4510         start = end = info->rbuf_current;
4511
4512         for (;;) {
4513                 if (!desc_complete(info->rbufs[end]))
4514                         goto cleanup;
4515
4516                 if (framesize == 0 && info->params.addr_filter != 0xff)
4517                         addr_field = info->rbufs[end].buf[0];
4518
4519                 framesize += desc_count(info->rbufs[end]);
4520
4521                 if (desc_eof(info->rbufs[end]))
4522                         break;
4523
4524                 if (++end == info->rbuf_count)
4525                         end = 0;
4526
4527                 if (end == info->rbuf_current) {
4528                         if (info->rx_enabled){
4529                                 spin_lock_irqsave(&info->lock,flags);
4530                                 rx_start(info);
4531                                 spin_unlock_irqrestore(&info->lock,flags);
4532                         }
4533                         goto cleanup;
4534                 }
4535         }
4536
4537         /* status
4538          *
4539          * 15      buffer complete
4540          * 14..06  reserved
4541          * 05..04  residue
4542          * 02      eof (end of frame)
4543          * 01      CRC error
4544          * 00      abort
4545          */
4546         status = desc_status(info->rbufs[end]);
4547
4548         /* ignore CRC bit if not using CRC (bit is undefined) */
4549         if ((info->params.crc_type & HDLC_CRC_MASK) == HDLC_CRC_NONE)
4550                 status &= ~BIT1;
4551
4552         if (framesize == 0 ||
4553                  (addr_field != 0xff && addr_field != info->params.addr_filter)) {
4554                 free_rbufs(info, start, end);
4555                 goto check_again;
4556         }
4557
4558         if (framesize < (2 + crc_size) || status & BIT0) {
4559                 info->icount.rxshort++;
4560                 framesize = 0;
4561         } else if (status & BIT1) {
4562                 info->icount.rxcrc++;
4563                 if (!(info->params.crc_type & HDLC_CRC_RETURN_EX))
4564                         framesize = 0;
4565         }
4566
4567 #if SYNCLINK_GENERIC_HDLC
4568         if (framesize == 0) {
4569                 info->netdev->stats.rx_errors++;
4570                 info->netdev->stats.rx_frame_errors++;
4571         }
4572 #endif
4573
4574         DBGBH(("%s rx frame status=%04X size=%d\n",
4575                 info->device_name, status, framesize));
4576         DBGDATA(info, info->rbufs[start].buf, min_t(int, framesize, DMABUFSIZE), "rx");
4577
4578         if (framesize) {
4579                 if (!(info->params.crc_type & HDLC_CRC_RETURN_EX)) {
4580                         framesize -= crc_size;
4581                         crc_size = 0;
4582                 }
4583
4584                 if (framesize > info->max_frame_size + crc_size)
4585                         info->icount.rxlong++;
4586                 else {
4587                         /* copy dma buffer(s) to contiguous temp buffer */
4588                         int copy_count = framesize;
4589                         int i = start;
4590                         unsigned char *p = info->tmp_rbuf;
4591                         info->tmp_rbuf_count = framesize;
4592
4593                         info->icount.rxok++;
4594
4595                         while(copy_count) {
4596                                 int partial_count = min(copy_count, DMABUFSIZE);
4597                                 memcpy(p, info->rbufs[i].buf, partial_count);
4598                                 p += partial_count;
4599                                 copy_count -= partial_count;
4600                                 if (++i == info->rbuf_count)
4601                                         i = 0;
4602                         }
4603
4604                         if (info->params.crc_type & HDLC_CRC_RETURN_EX) {
4605                                 *p = (status & BIT1) ? RX_CRC_ERROR : RX_OK;
4606                                 framesize++;
4607                         }
4608
4609 #if SYNCLINK_GENERIC_HDLC
4610                         if (info->netcount)
4611                                 hdlcdev_rx(info,info->tmp_rbuf, framesize);
4612                         else
4613 #endif
4614                                 ldisc_receive_buf(tty, info->tmp_rbuf, info->flag_buf, framesize);
4615                 }
4616         }
4617         free_rbufs(info, start, end);
4618         return true;
4619
4620 cleanup:
4621         return false;
4622 }
4623
4624 /*
4625  * pass receive buffer (RAW synchronous mode) to tty layer
4626  * return true if buffer available, otherwise false
4627  */
4628 static bool rx_get_buf(struct slgt_info *info)
4629 {
4630         unsigned int i = info->rbuf_current;
4631         unsigned int count;
4632
4633         if (!desc_complete(info->rbufs[i]))
4634                 return false;
4635         count = desc_count(info->rbufs[i]);
4636         switch(info->params.mode) {
4637         case MGSL_MODE_MONOSYNC:
4638         case MGSL_MODE_BISYNC:
4639                 /* ignore residue in byte synchronous modes */
4640                 if (desc_residue(info->rbufs[i]))
4641                         count--;
4642                 break;
4643         }
4644         DBGDATA(info, info->rbufs[i].buf, count, "rx");
4645         DBGINFO(("rx_get_buf size=%d\n", count));
4646         if (count)
4647                 ldisc_receive_buf(info->port.tty, info->rbufs[i].buf,
4648                                   info->flag_buf, count);
4649         free_rbufs(info, i, i);
4650         return true;
4651 }
4652
4653 static void reset_tbufs(struct slgt_info *info)
4654 {
4655         unsigned int i;
4656         info->tbuf_current = 0;
4657         for (i=0 ; i < info->tbuf_count ; i++) {
4658                 info->tbufs[i].status = 0;
4659                 info->tbufs[i].count  = 0;
4660         }
4661 }
4662
4663 /*
4664  * return number of free transmit DMA buffers
4665  */
4666 static unsigned int free_tbuf_count(struct slgt_info *info)
4667 {
4668         unsigned int count = 0;
4669         unsigned int i = info->tbuf_current;
4670
4671         do
4672         {
4673                 if (desc_count(info->tbufs[i]))
4674                         break; /* buffer in use */
4675                 ++count;
4676                 if (++i == info->tbuf_count)
4677                         i=0;
4678         } while (i != info->tbuf_current);
4679
4680         /* if tx DMA active, last zero count buffer is in use */
4681         if (count && (rd_reg32(info, TDCSR) & BIT0))
4682                 --count;
4683
4684         return count;
4685 }
4686
4687 /*
4688  * load transmit DMA buffer(s) with data
4689  */
4690 static void tx_load(struct slgt_info *info, const char *buf, unsigned int size)
4691 {
4692         unsigned short count;
4693         unsigned int i;
4694         struct slgt_desc *d;
4695
4696         if (size == 0)
4697                 return;
4698
4699         DBGDATA(info, buf, size, "tx");
4700
4701         info->tbuf_start = i = info->tbuf_current;
4702
4703         while (size) {
4704                 d = &info->tbufs[i];
4705                 if (++i == info->tbuf_count)
4706                         i = 0;
4707
4708                 count = (unsigned short)((size > DMABUFSIZE) ? DMABUFSIZE : size);
4709                 memcpy(d->buf, buf, count);
4710
4711                 size -= count;
4712                 buf  += count;
4713
4714                 /*
4715                  * set EOF bit for last buffer of HDLC frame or
4716                  * for every buffer in raw mode
4717                  */
4718                 if ((!size && info->params.mode == MGSL_MODE_HDLC) ||
4719                     info->params.mode == MGSL_MODE_RAW)
4720                         set_desc_eof(*d, 1);
4721                 else
4722                         set_desc_eof(*d, 0);
4723
4724                 set_desc_count(*d, count);
4725         }
4726
4727         info->tbuf_current = i;
4728 }
4729
4730 static int register_test(struct slgt_info *info)
4731 {
4732         static unsigned short patterns[] =
4733                 {0x0000, 0xffff, 0xaaaa, 0x5555, 0x6969, 0x9696};
4734         static unsigned int count = sizeof(patterns)/sizeof(patterns[0]);
4735         unsigned int i;
4736         int rc = 0;
4737
4738         for (i=0 ; i < count ; i++) {
4739                 wr_reg16(info, TIR, patterns[i]);
4740                 wr_reg16(info, BDR, patterns[(i+1)%count]);
4741                 if ((rd_reg16(info, TIR) != patterns[i]) ||
4742                     (rd_reg16(info, BDR) != patterns[(i+1)%count])) {
4743                         rc = -ENODEV;
4744                         break;
4745                 }
4746         }
4747         info->gpio_present = (rd_reg32(info, JCR) & BIT5) ? 1 : 0;
4748         info->init_error = rc ? 0 : DiagStatus_AddressFailure;
4749         return rc;
4750 }
4751
4752 static int irq_test(struct slgt_info *info)
4753 {
4754         unsigned long timeout;
4755         unsigned long flags;
4756         struct tty_struct *oldtty = info->port.tty;
4757         u32 speed = info->params.data_rate;
4758
4759         info->params.data_rate = 921600;
4760         info->port.tty = NULL;
4761
4762         spin_lock_irqsave(&info->lock, flags);
4763         async_mode(info);
4764         slgt_irq_on(info, IRQ_TXIDLE);
4765
4766         /* enable transmitter */
4767         wr_reg16(info, TCR,
4768                 (unsigned short)(rd_reg16(info, TCR) | BIT1));
4769
4770         /* write one byte and wait for tx idle */
4771         wr_reg16(info, TDR, 0);
4772
4773         /* assume failure */
4774         info->init_error = DiagStatus_IrqFailure;
4775         info->irq_occurred = false;
4776
4777         spin_unlock_irqrestore(&info->lock, flags);
4778
4779         timeout=100;
4780         while(timeout-- && !info->irq_occurred)
4781                 msleep_interruptible(10);
4782
4783         spin_lock_irqsave(&info->lock,flags);
4784         reset_port(info);
4785         spin_unlock_irqrestore(&info->lock,flags);
4786
4787         info->params.data_rate = speed;
4788         info->port.tty = oldtty;
4789
4790         info->init_error = info->irq_occurred ? 0 : DiagStatus_IrqFailure;
4791         return info->irq_occurred ? 0 : -ENODEV;
4792 }
4793
4794 static int loopback_test_rx(struct slgt_info *info)
4795 {
4796         unsigned char *src, *dest;
4797         int count;
4798
4799         if (desc_complete(info->rbufs[0])) {
4800                 count = desc_count(info->rbufs[0]);
4801                 src   = info->rbufs[0].buf;
4802                 dest  = info->tmp_rbuf;
4803
4804                 for( ; count ; count-=2, src+=2) {
4805                         /* src=data byte (src+1)=status byte */
4806                         if (!(*(src+1) & (BIT9 + BIT8))) {
4807                                 *dest = *src;
4808                                 dest++;
4809                                 info->tmp_rbuf_count++;
4810                         }
4811                 }
4812                 DBGDATA(info, info->tmp_rbuf, info->tmp_rbuf_count, "rx");
4813                 return 1;
4814         }
4815         return 0;
4816 }
4817
4818 static int loopback_test(struct slgt_info *info)
4819 {
4820 #define TESTFRAMESIZE 20
4821
4822         unsigned long timeout;
4823         u16 count = TESTFRAMESIZE;
4824         unsigned char buf[TESTFRAMESIZE];
4825         int rc = -ENODEV;
4826         unsigned long flags;
4827
4828         struct tty_struct *oldtty = info->port.tty;
4829         MGSL_PARAMS params;
4830
4831         memcpy(&params, &info->params, sizeof(params));
4832
4833         info->params.mode = MGSL_MODE_ASYNC;
4834         info->params.data_rate = 921600;
4835         info->params.loopback = 1;
4836         info->port.tty = NULL;
4837
4838         /* build and send transmit frame */
4839         for (count = 0; count < TESTFRAMESIZE; ++count)
4840                 buf[count] = (unsigned char)count;
4841
4842         info->tmp_rbuf_count = 0;
4843         memset(info->tmp_rbuf, 0, TESTFRAMESIZE);
4844
4845         /* program hardware for HDLC and enabled receiver */
4846         spin_lock_irqsave(&info->lock,flags);
4847         async_mode(info);
4848         rx_start(info);
4849         info->tx_count = count;
4850         tx_load(info, buf, count);
4851         tx_start(info);
4852         spin_unlock_irqrestore(&info->lock, flags);
4853
4854         /* wait for receive complete */
4855         for (timeout = 100; timeout; --timeout) {
4856                 msleep_interruptible(10);
4857                 if (loopback_test_rx(info)) {
4858                         rc = 0;
4859                         break;
4860                 }
4861         }
4862
4863         /* verify received frame length and contents */
4864         if (!rc && (info->tmp_rbuf_count != count ||
4865                   memcmp(buf, info->tmp_rbuf, count))) {
4866                 rc = -ENODEV;
4867         }
4868
4869         spin_lock_irqsave(&info->lock,flags);
4870         reset_adapter(info);
4871         spin_unlock_irqrestore(&info->lock,flags);
4872
4873         memcpy(&info->params, &params, sizeof(info->params));
4874         info->port.tty = oldtty;
4875
4876         info->init_error = rc ? DiagStatus_DmaFailure : 0;
4877         return rc;
4878 }
4879
4880 static int adapter_test(struct slgt_info *info)
4881 {
4882         DBGINFO(("testing %s\n", info->device_name));
4883         if (register_test(info) < 0) {
4884                 printk("register test failure %s addr=%08X\n",
4885                         info->device_name, info->phys_reg_addr);
4886         } else if (irq_test(info) < 0) {
4887                 printk("IRQ test failure %s IRQ=%d\n",
4888                         info->device_name, info->irq_level);
4889         } else if (loopback_test(info) < 0) {
4890                 printk("loopback test failure %s\n", info->device_name);
4891         }
4892         return info->init_error;
4893 }
4894
4895 /*
4896  * transmit timeout handler
4897  */
4898 static void tx_timeout(unsigned long context)
4899 {
4900         struct slgt_info *info = (struct slgt_info*)context;
4901         unsigned long flags;
4902
4903         DBGINFO(("%s tx_timeout\n", info->device_name));
4904         if(info->tx_active && info->params.mode == MGSL_MODE_HDLC) {
4905                 info->icount.txtimeout++;
4906         }
4907         spin_lock_irqsave(&info->lock,flags);
4908         info->tx_active = false;
4909         info->tx_count = 0;
4910         spin_unlock_irqrestore(&info->lock,flags);
4911
4912 #if SYNCLINK_GENERIC_HDLC
4913         if (info->netcount)
4914                 hdlcdev_tx_done(info);
4915         else
4916 #endif
4917                 bh_transmit(info);
4918 }
4919
4920 /*
4921  * receive buffer polling timer
4922  */
4923 static void rx_timeout(unsigned long context)
4924 {
4925         struct slgt_info *info = (struct slgt_info*)context;
4926         unsigned long flags;
4927
4928         DBGINFO(("%s rx_timeout\n", info->device_name));
4929         spin_lock_irqsave(&info->lock, flags);
4930         info->pending_bh |= BH_RECEIVE;
4931         spin_unlock_irqrestore(&info->lock, flags);
4932         bh_handler(&info->task);
4933 }
4934