err.no Git - linux-2.6/blob - drivers/char/synclink_gt.c

   1 /*
   2  * $Id: synclink_gt.c,v 4.50 2007/07/25 19:29:25 paulkf Exp $
   3  *
   4  * Device driver for Microgate SyncLink GT serial adapters.
   5  *
   6  * written by Paul Fulghum for Microgate Corporation
   7  * paulkf@microgate.com
   8  *
   9  * Microgate and SyncLink are trademarks of Microgate Corporation
  10  *
  11  * This code is released under the GNU General Public License (GPL)
  12  *
  13  * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED
  14  * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
  15  * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
  16  * DISCLAIMED.  IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT,
  17  * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
  18  * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
  19  * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
  20  * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
  21  * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
  22  * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED
  23  * OF THE POSSIBILITY OF SUCH DAMAGE.
  24  */
  25
  26 /*
  27  * DEBUG OUTPUT DEFINITIONS
  28  *
  29  * uncomment lines below to enable specific types of debug output
  30  *
  31  * DBGINFO   information - most verbose output
  32  * DBGERR    serious errors
  33  * DBGBH     bottom half service routine debugging
  34  * DBGISR    interrupt service routine debugging
  35  * DBGDATA   output receive and transmit data
  36  * DBGTBUF   output transmit DMA buffers and registers
  37  * DBGRBUF   output receive DMA buffers and registers
  38  */
  39
  40 #define DBGINFO(fmt) if (debug_level >= DEBUG_LEVEL_INFO) printk fmt
  41 #define DBGERR(fmt) if (debug_level >= DEBUG_LEVEL_ERROR) printk fmt
  42 #define DBGBH(fmt) if (debug_level >= DEBUG_LEVEL_BH) printk fmt
  43 #define DBGISR(fmt) if (debug_level >= DEBUG_LEVEL_ISR) printk fmt
  44 #define DBGDATA(info, buf, size, label) if (debug_level >= DEBUG_LEVEL_DATA) trace_block((info), (buf), (size), (label))
  45 //#define DBGTBUF(info) dump_tbufs(info)
  46 //#define DBGRBUF(info) dump_rbufs(info)
  47
  48
  49 #include <linux/module.h>
  50 #include <linux/version.h>
  51 #include <linux/errno.h>
  52 #include <linux/signal.h>
  53 #include <linux/sched.h>
  54 #include <linux/timer.h>
  55 #include <linux/interrupt.h>
  56 #include <linux/pci.h>
  57 #include <linux/tty.h>
  58 #include <linux/tty_flip.h>
  59 #include <linux/serial.h>
  60 #include <linux/major.h>
  61 #include <linux/string.h>
  62 #include <linux/fcntl.h>
  63 #include <linux/ptrace.h>
  64 #include <linux/ioport.h>
  65 #include <linux/mm.h>
  66 #include <linux/slab.h>
  67 #include <linux/netdevice.h>
  68 #include <linux/vmalloc.h>
  69 #include <linux/init.h>
  70 #include <linux/delay.h>
  71 #include <linux/ioctl.h>
  72 #include <linux/termios.h>
  73 #include <linux/bitops.h>
  74 #include <linux/workqueue.h>
  75 #include <linux/hdlc.h>
  76 #include <linux/synclink.h>
  77
  78 #include <asm/system.h>
  79 #include <asm/io.h>
  80 #include <asm/irq.h>
  81 #include <asm/dma.h>
  82 #include <asm/types.h>
  83 #include <asm/uaccess.h>
  84
  85 #if defined(CONFIG_HDLC) || (defined(CONFIG_HDLC_MODULE) && defined(CONFIG_SYNCLINK_GT_MODULE))
  86 #define SYNCLINK_GENERIC_HDLC 1
  87 #else
  88 #define SYNCLINK_GENERIC_HDLC 0
  89 #endif
  90
  91 /*
  92  * module identification
  93  */
  94 static char *driver_name     = "SyncLink GT";
  95 static char *driver_version  = "$Revision: 4.50 $";
  96 static char *tty_driver_name = "synclink_gt";
  97 static char *tty_dev_prefix  = "ttySLG";
  98 MODULE_LICENSE("GPL");
  99 #define MGSL_MAGIC 0x5401
 100 #define MAX_DEVICES 32
 101
 102 static struct pci_device_id pci_table[] = {
 103         {PCI_VENDOR_ID_MICROGATE, SYNCLINK_GT_DEVICE_ID, PCI_ANY_ID, PCI_ANY_ID,},
 104         {PCI_VENDOR_ID_MICROGATE, SYNCLINK_GT2_DEVICE_ID, PCI_ANY_ID, PCI_ANY_ID,},
 105         {PCI_VENDOR_ID_MICROGATE, SYNCLINK_GT4_DEVICE_ID, PCI_ANY_ID, PCI_ANY_ID,},
 106         {PCI_VENDOR_ID_MICROGATE, SYNCLINK_AC_DEVICE_ID, PCI_ANY_ID, PCI_ANY_ID,},
 107         {0,}, /* terminate list */
 108 };
 109 MODULE_DEVICE_TABLE(pci, pci_table);
 110
 111 static int  init_one(struct pci_dev *dev,const struct pci_device_id *ent);
 112 static void remove_one(struct pci_dev *dev);
 113 static struct pci_driver pci_driver = {
 114         .name           = "synclink_gt",
 115         .id_table       = pci_table,
 116         .probe          = init_one,
 117         .remove         = __devexit_p(remove_one),
 118 };
 119
 120 static bool pci_registered;
 121
 122 /*
 123  * module configuration and status
 124  */
 125 static struct slgt_info *slgt_device_list;
 126 static int slgt_device_count;
 127
 128 static int ttymajor;
 129 static int debug_level;
 130 static int maxframe[MAX_DEVICES];
 131 static int dosyncppp[MAX_DEVICES];
 132
 133 module_param(ttymajor, int, 0);
 134 module_param(debug_level, int, 0);
 135 module_param_array(maxframe, int, NULL, 0);
 136 module_param_array(dosyncppp, int, NULL, 0);
 137
 138 MODULE_PARM_DESC(ttymajor, "TTY major device number override: 0=auto assigned");
 139 MODULE_PARM_DESC(debug_level, "Debug syslog output: 0=disabled, 1 to 5=increasing detail");
 140 MODULE_PARM_DESC(maxframe, "Maximum frame size used by device (4096 to 65535)");
 141 MODULE_PARM_DESC(dosyncppp, "Enable synchronous net device, 0=disable 1=enable");
 142
 143 /*
 144  * tty support and callbacks
 145  */
 146 static struct tty_driver *serial_driver;
 147
 148 static int  open(struct tty_struct *tty, struct file * filp);
 149 static void close(struct tty_struct *tty, struct file * filp);
 150 static void hangup(struct tty_struct *tty);
 151 static void set_termios(struct tty_struct *tty, struct ktermios *old_termios);
 152
 153 static int  write(struct tty_struct *tty, const unsigned char *buf, int count);
 154 static int put_char(struct tty_struct *tty, unsigned char ch);
 155 static void send_xchar(struct tty_struct *tty, char ch);
 156 static void wait_until_sent(struct tty_struct *tty, int timeout);
 157 static int  write_room(struct tty_struct *tty);
 158 static void flush_chars(struct tty_struct *tty);
 159 static void flush_buffer(struct tty_struct *tty);
 160 static void tx_hold(struct tty_struct *tty);
 161 static void tx_release(struct tty_struct *tty);
 162
 163 static int  ioctl(struct tty_struct *tty, struct file *file, unsigned int cmd, unsigned long arg);
 164 static int  read_proc(char *page, char **start, off_t off, int count,int *eof, void *data);
 165 static int  chars_in_buffer(struct tty_struct *tty);
 166 static void throttle(struct tty_struct * tty);
 167 static void unthrottle(struct tty_struct * tty);
 168 static void set_break(struct tty_struct *tty, int break_state);
 169
 170 /*
 171  * generic HDLC support and callbacks
 172  */
 173 #if SYNCLINK_GENERIC_HDLC
 174 #define dev_to_port(D) (dev_to_hdlc(D)->priv)
 175 static void hdlcdev_tx_done(struct slgt_info *info);
 176 static void hdlcdev_rx(struct slgt_info *info, char *buf, int size);
 177 static int  hdlcdev_init(struct slgt_info *info);
 178 static void hdlcdev_exit(struct slgt_info *info);
 179 #endif
 180
 181
 182 /*
 183  * device specific structures, macros and functions
 184  */
 185
 186 #define SLGT_MAX_PORTS 4
 187 #define SLGT_REG_SIZE  256
 188
 189 /*
 190  * conditional wait facility
 191  */
 192 struct cond_wait {
 193         struct cond_wait *next;
 194         wait_queue_head_t q;
 195         wait_queue_t wait;
 196         unsigned int data;
 197 };
 198 static void init_cond_wait(struct cond_wait *w, unsigned int data);
 199 static void add_cond_wait(struct cond_wait **head, struct cond_wait *w);
 200 static void remove_cond_wait(struct cond_wait **head, struct cond_wait *w);
 201 static void flush_cond_wait(struct cond_wait **head);
 202
 203 /*
 204  * DMA buffer descriptor and access macros
 205  */
 206 struct slgt_desc
 207 {
 208         __le16 count;
 209         __le16 status;
 210         __le32 pbuf;  /* physical address of data buffer */
 211         __le32 next;  /* physical address of next descriptor */
 212
 213         /* driver book keeping */
 214         char *buf;          /* virtual  address of data buffer */
 215         unsigned int pdesc; /* physical address of this descriptor */
 216         dma_addr_t buf_dma_addr;
 217 };
 218
 219 #define set_desc_buffer(a,b) (a).pbuf = cpu_to_le32((unsigned int)(b))
 220 #define set_desc_next(a,b) (a).next   = cpu_to_le32((unsigned int)(b))
 221 #define set_desc_count(a,b)(a).count  = cpu_to_le16((unsigned short)(b))
 222 #define set_desc_eof(a,b)  (a).status = cpu_to_le16((b) ? (le16_to_cpu((a).status) | BIT0) : (le16_to_cpu((a).status) & ~BIT0))
 223 #define desc_count(a)      (le16_to_cpu((a).count))
 224 #define desc_status(a)     (le16_to_cpu((a).status))
 225 #define desc_complete(a)   (le16_to_cpu((a).status) & BIT15)
 226 #define desc_eof(a)        (le16_to_cpu((a).status) & BIT2)
 227 #define desc_crc_error(a)  (le16_to_cpu((a).status) & BIT1)
 228 #define desc_abort(a)      (le16_to_cpu((a).status) & BIT0)
 229 #define desc_residue(a)    ((le16_to_cpu((a).status) & 0x38) >> 3)
 230
 231 struct _input_signal_events {
 232         int ri_up;
 233         int ri_down;
 234         int dsr_up;
 235         int dsr_down;
 236         int dcd_up;
 237         int dcd_down;
 238         int cts_up;
 239         int cts_down;
 240 };
 241
 242 /*
 243  * device instance data structure
 244  */
 245 struct slgt_info {
 246         void *if_ptr;           /* General purpose pointer (used by SPPP) */
 247         struct tty_port port;
 248
 249         struct slgt_info *next_device;  /* device list link */
 250
 251         int magic;
 252
 253         char device_name[25];
 254         struct pci_dev *pdev;
 255
 256         int port_count;  /* count of ports on adapter */
 257         int adapter_num; /* adapter instance number */
 258         int port_num;    /* port instance number */
 259
 260         /* array of pointers to port contexts on this adapter */
 261         struct slgt_info *port_array[SLGT_MAX_PORTS];
 262
 263         int                     line;           /* tty line instance number */
 264
 265         struct mgsl_icount      icount;
 266
 267         int                     timeout;
 268         int                     x_char;         /* xon/xoff character */
 269         unsigned int            read_status_mask;
 270         unsigned int            ignore_status_mask;
 271
 272         wait_queue_head_t       status_event_wait_q;
 273         wait_queue_head_t       event_wait_q;
 274         struct timer_list       tx_timer;
 275         struct timer_list       rx_timer;
 276
 277         unsigned int            gpio_present;
 278         struct cond_wait        *gpio_wait_q;
 279
 280         spinlock_t lock;        /* spinlock for synchronizing with ISR */
 281
 282         struct work_struct task;
 283         u32 pending_bh;
 284         bool bh_requested;
 285         bool bh_running;
 286
 287         int isr_overflow;
 288         bool irq_requested;     /* true if IRQ requested */
 289         bool irq_occurred;      /* for diagnostics use */
 290
 291         /* device configuration */
 292
 293         unsigned int bus_type;
 294         unsigned int irq_level;
 295         unsigned long irq_flags;
 296
 297         unsigned char __iomem * reg_addr;  /* memory mapped registers address */
 298         u32 phys_reg_addr;
 299         bool reg_addr_requested;
 300
 301         MGSL_PARAMS params;       /* communications parameters */
 302         u32 idle_mode;
 303         u32 max_frame_size;       /* as set by device config */
 304
 305         unsigned int raw_rx_size;
 306         unsigned int if_mode;
 307
 308         /* device status */
 309
 310         bool rx_enabled;
 311         bool rx_restart;
 312
 313         bool tx_enabled;
 314         bool tx_active;
 315
 316         unsigned char signals;    /* serial signal states */
 317         int init_error;  /* initialization error */
 318
 319         unsigned char *tx_buf;
 320         int tx_count;
 321
 322         char flag_buf[MAX_ASYNC_BUFFER_SIZE];
 323         char char_buf[MAX_ASYNC_BUFFER_SIZE];
 324         bool drop_rts_on_tx_done;
 325         struct  _input_signal_events    input_signal_events;
 326
 327         int dcd_chkcount;       /* check counts to prevent */
 328         int cts_chkcount;       /* too many IRQs if a signal */
 329         int dsr_chkcount;       /* is floating */
 330         int ri_chkcount;
 331
 332         char *bufs;             /* virtual address of DMA buffer lists */
 333         dma_addr_t bufs_dma_addr; /* physical address of buffer descriptors */
 334
 335         unsigned int rbuf_count;
 336         struct slgt_desc *rbufs;
 337         unsigned int rbuf_current;
 338         unsigned int rbuf_index;
 339
 340         unsigned int tbuf_count;
 341         struct slgt_desc *tbufs;
 342         unsigned int tbuf_current;
 343         unsigned int tbuf_start;
 344
 345         unsigned char *tmp_rbuf;
 346         unsigned int tmp_rbuf_count;
 347
 348         /* SPPP/Cisco HDLC device parts */
 349
 350         int netcount;
 351         int dosyncppp;
 352         spinlock_t netlock;
 353 #if SYNCLINK_GENERIC_HDLC
 354         struct net_device *netdev;
 355 #endif
 356
 357 };
 358
 359 static MGSL_PARAMS default_params = {
 360         .mode            = MGSL_MODE_HDLC,
 361         .loopback        = 0,
 362         .flags           = HDLC_FLAG_UNDERRUN_ABORT15,
 363         .encoding        = HDLC_ENCODING_NRZI_SPACE,
 364         .clock_speed     = 0,
 365         .addr_filter     = 0xff,
 366         .crc_type        = HDLC_CRC_16_CCITT,
 367         .preamble_length = HDLC_PREAMBLE_LENGTH_8BITS,
 368         .preamble        = HDLC_PREAMBLE_PATTERN_NONE,
 369         .data_rate       = 9600,
 370         .data_bits       = 8,
 371         .stop_bits       = 1,
 372         .parity          = ASYNC_PARITY_NONE
 373 };
 374
 375
 376 #define BH_RECEIVE  1
 377 #define BH_TRANSMIT 2
 378 #define BH_STATUS   4
 379 #define IO_PIN_SHUTDOWN_LIMIT 100
 380
 381 #define DMABUFSIZE 256
 382 #define DESC_LIST_SIZE 4096
 383
 384 #define MASK_PARITY  BIT1
 385 #define MASK_FRAMING BIT0
 386 #define MASK_BREAK   BIT14
 387 #define MASK_OVERRUN BIT4
 388
 389 #define GSR   0x00 /* global status */
 390 #define JCR   0x04 /* JTAG control */
 391 #define IODR  0x08 /* GPIO direction */
 392 #define IOER  0x0c /* GPIO interrupt enable */
 393 #define IOVR  0x10 /* GPIO value */
 394 #define IOSR  0x14 /* GPIO interrupt status */
 395 #define TDR   0x80 /* tx data */
 396 #define RDR   0x80 /* rx data */
 397 #define TCR   0x82 /* tx control */
 398 #define TIR   0x84 /* tx idle */
 399 #define TPR   0x85 /* tx preamble */
 400 #define RCR   0x86 /* rx control */
 401 #define VCR   0x88 /* V.24 control */
 402 #define CCR   0x89 /* clock control */
 403 #define BDR   0x8a /* baud divisor */
 404 #define SCR   0x8c /* serial control */
 405 #define SSR   0x8e /* serial status */
 406 #define RDCSR 0x90 /* rx DMA control/status */
 407 #define TDCSR 0x94 /* tx DMA control/status */
 408 #define RDDAR 0x98 /* rx DMA descriptor address */
 409 #define TDDAR 0x9c /* tx DMA descriptor address */
 410
 411 #define RXIDLE      BIT14
 412 #define RXBREAK     BIT14
 413 #define IRQ_TXDATA  BIT13
 414 #define IRQ_TXIDLE  BIT12
 415 #define IRQ_TXUNDER BIT11 /* HDLC */
 416 #define IRQ_RXDATA  BIT10
 417 #define IRQ_RXIDLE  BIT9  /* HDLC */
 418 #define IRQ_RXBREAK BIT9  /* async */
 419 #define IRQ_RXOVER  BIT8
 420 #define IRQ_DSR     BIT7
 421 #define IRQ_CTS     BIT6
 422 #define IRQ_DCD     BIT5
 423 #define IRQ_RI      BIT4
 424 #define IRQ_ALL     0x3ff0
 425 #define IRQ_MASTER  BIT0
 426
 427 #define slgt_irq_on(info, mask) \
 428         wr_reg16((info), SCR, (unsigned short)(rd_reg16((info), SCR) | (mask)))
 429 #define slgt_irq_off(info, mask) \
 430         wr_reg16((info), SCR, (unsigned short)(rd_reg16((info), SCR) & ~(mask)))
 431
 432 static __u8  rd_reg8(struct slgt_info *info, unsigned int addr);
 433 static void  wr_reg8(struct slgt_info *info, unsigned int addr, __u8 value);
 434 static __u16 rd_reg16(struct slgt_info *info, unsigned int addr);
 435 static void  wr_reg16(struct slgt_info *info, unsigned int addr, __u16 value);
 436 static __u32 rd_reg32(struct slgt_info *info, unsigned int addr);
 437 static void  wr_reg32(struct slgt_info *info, unsigned int addr, __u32 value);
 438
 439 static void  msc_set_vcr(struct slgt_info *info);
 440
 441 static int  startup(struct slgt_info *info);
 442 static int  block_til_ready(struct tty_struct *tty, struct file * filp,struct slgt_info *info);
 443 static void shutdown(struct slgt_info *info);
 444 static void program_hw(struct slgt_info *info);
 445 static void change_params(struct slgt_info *info);
 446
 447 static int  register_test(struct slgt_info *info);
 448 static int  irq_test(struct slgt_info *info);
 449 static int  loopback_test(struct slgt_info *info);
 450 static int  adapter_test(struct slgt_info *info);
 451
 452 static void reset_adapter(struct slgt_info *info);
 453 static void reset_port(struct slgt_info *info);
 454 static void async_mode(struct slgt_info *info);
 455 static void sync_mode(struct slgt_info *info);
 456
 457 static void rx_stop(struct slgt_info *info);
 458 static void rx_start(struct slgt_info *info);
 459 static void reset_rbufs(struct slgt_info *info);
 460 static void free_rbufs(struct slgt_info *info, unsigned int first, unsigned int last);
 461 static void rdma_reset(struct slgt_info *info);
 462 static bool rx_get_frame(struct slgt_info *info);
 463 static bool rx_get_buf(struct slgt_info *info);
 464
 465 static void tx_start(struct slgt_info *info);
 466 static void tx_stop(struct slgt_info *info);
 467 static void tx_set_idle(struct slgt_info *info);
 468 static unsigned int free_tbuf_count(struct slgt_info *info);
 469 static void reset_tbufs(struct slgt_info *info);
 470 static void tdma_reset(struct slgt_info *info);
 471 static void tdma_start(struct slgt_info *info);
 472 static void tx_load(struct slgt_info *info, const char *buf, unsigned int count);
 473
 474 static void get_signals(struct slgt_info *info);
 475 static void set_signals(struct slgt_info *info);
 476 static void enable_loopback(struct slgt_info *info);
 477 static void set_rate(struct slgt_info *info, u32 data_rate);
 478
 479 static int  bh_action(struct slgt_info *info);
 480 static void bh_handler(struct work_struct *work);
 481 static void bh_transmit(struct slgt_info *info);
 482 static void isr_serial(struct slgt_info *info);
 483 static void isr_rdma(struct slgt_info *info);
 484 static void isr_txeom(struct slgt_info *info, unsigned short status);
 485 static void isr_tdma(struct slgt_info *info);
 486
 487 static int  alloc_dma_bufs(struct slgt_info *info);
 488 static void free_dma_bufs(struct slgt_info *info);
 489 static int  alloc_desc(struct slgt_info *info);
 490 static void free_desc(struct slgt_info *info);
 491 static int  alloc_bufs(struct slgt_info *info, struct slgt_desc *bufs, int count);
 492 static void free_bufs(struct slgt_info *info, struct slgt_desc *bufs, int count);
 493
 494 static int  alloc_tmp_rbuf(struct slgt_info *info);
 495 static void free_tmp_rbuf(struct slgt_info *info);
 496
 497 static void tx_timeout(unsigned long context);
 498 static void rx_timeout(unsigned long context);
 499
 500 /*
 501  * ioctl handlers
 502  */
 503 static int  get_stats(struct slgt_info *info, struct mgsl_icount __user *user_icount);
 504 static int  get_params(struct slgt_info *info, MGSL_PARAMS __user *params);
 505 static int  set_params(struct slgt_info *info, MGSL_PARAMS __user *params);
 506 static int  get_txidle(struct slgt_info *info, int __user *idle_mode);
 507 static int  set_txidle(struct slgt_info *info, int idle_mode);
 508 static int  tx_enable(struct slgt_info *info, int enable);
 509 static int  tx_abort(struct slgt_info *info);
 510 static int  rx_enable(struct slgt_info *info, int enable);
 511 static int  modem_input_wait(struct slgt_info *info,int arg);
 512 static int  wait_mgsl_event(struct slgt_info *info, int __user *mask_ptr);
 513 static int  tiocmget(struct tty_struct *tty, struct file *file);
 514 static int  tiocmset(struct tty_struct *tty, struct file *file,
 515                      unsigned int set, unsigned int clear);
 516 static void set_break(struct tty_struct *tty, int break_state);
 517 static int  get_interface(struct slgt_info *info, int __user *if_mode);
 518 static int  set_interface(struct slgt_info *info, int if_mode);
 519 static int  set_gpio(struct slgt_info *info, struct gpio_desc __user *gpio);
 520 static int  get_gpio(struct slgt_info *info, struct gpio_desc __user *gpio);
 521 static int  wait_gpio(struct slgt_info *info, struct gpio_desc __user *gpio);
 522
 523 /*
 524  * driver functions
 525  */
 526 static void add_device(struct slgt_info *info);
 527 static void device_init(int adapter_num, struct pci_dev *pdev);
 528 static int  claim_resources(struct slgt_info *info);
 529 static void release_resources(struct slgt_info *info);
 530
 531 /*
 532  * DEBUG OUTPUT CODE
 533  */
 534 #ifndef DBGINFO
 535 #define DBGINFO(fmt)
 536 #endif
 537 #ifndef DBGERR
 538 #define DBGERR(fmt)
 539 #endif
 540 #ifndef DBGBH
 541 #define DBGBH(fmt)
 542 #endif
 543 #ifndef DBGISR
 544 #define DBGISR(fmt)
 545 #endif
 546
 547 #ifdef DBGDATA
 548 static void trace_block(struct slgt_info *info, const char *data, int count, const char *label)
 549 {
 550         int i;
 551         int linecount;
 552         printk("%s %s data:\n",info->device_name, label);
 553         while(count) {
 554                 linecount = (count > 16) ? 16 : count;
 555                 for(i=0; i < linecount; i++)
 556                         printk("%02X ",(unsigned char)data[i]);
 557                 for(;i<17;i++)
 558                         printk("   ");
 559                 for(i=0;i<linecount;i++) {
 560                         if (data[i]>=040 && data[i]<=0176)
 561                                 printk("%c",data[i]);
 562                         else
 563                                 printk(".");
 564                 }
 565                 printk("\n");
 566                 data  += linecount;
 567                 count -= linecount;
 568         }
 569 }
 570 #else
 571 #define DBGDATA(info, buf, size, label)
 572 #endif
 573
 574 #ifdef DBGTBUF
 575 static void dump_tbufs(struct slgt_info *info)
 576 {
 577         int i;
 578         printk("tbuf_current=%d\n", info->tbuf_current);
 579         for (i=0 ; i < info->tbuf_count ; i++) {
 580                 printk("%d: count=%04X status=%04X\n",
 581                         i, le16_to_cpu(info->tbufs[i].count), le16_to_cpu(info->tbufs[i].status));
 582         }
 583 }
 584 #else
 585 #define DBGTBUF(info)
 586 #endif
 587
 588 #ifdef DBGRBUF
 589 static void dump_rbufs(struct slgt_info *info)
 590 {
 591         int i;
 592         printk("rbuf_current=%d\n", info->rbuf_current);
 593         for (i=0 ; i < info->rbuf_count ; i++) {
 594                 printk("%d: count=%04X status=%04X\n",
 595                         i, le16_to_cpu(info->rbufs[i].count), le16_to_cpu(info->rbufs[i].status));
 596         }
 597 }
 598 #else
 599 #define DBGRBUF(info)
 600 #endif
 601
 602 static inline int sanity_check(struct slgt_info *info, char *devname, const char *name)
 603 {
 604 #ifdef SANITY_CHECK
 605         if (!info) {
 606                 printk("null struct slgt_info for (%s) in %s\n", devname, name);
 607                 return 1;
 608         }
 609         if (info->magic != MGSL_MAGIC) {
 610                 printk("bad magic number struct slgt_info (%s) in %s\n", devname, name);
 611                 return 1;
 612         }
 613 #else
 614         if (!info)
 615                 return 1;
 616 #endif
 617         return 0;
 618 }
 619
 620 /**
 621  * line discipline callback wrappers
 622  *
 623  * The wrappers maintain line discipline references
 624  * while calling into the line discipline.
 625  *
 626  * ldisc_receive_buf  - pass receive data to line discipline
 627  */
 628 static void ldisc_receive_buf(struct tty_struct *tty,
 629                               const __u8 *data, char *flags, int count)
 630 {
 631         struct tty_ldisc *ld;
 632         if (!tty)
 633                 return;
 634         ld = tty_ldisc_ref(tty);
 635         if (ld) {
 636                 if (ld->ops->receive_buf)
 637                         ld->ops->receive_buf(tty, data, flags, count);
 638                 tty_ldisc_deref(ld);
 639         }
 640 }
 641
 642 /* tty callbacks */
 643
 644 static int open(struct tty_struct *tty, struct file *filp)
 645 {
 646         struct slgt_info *info;
 647         int retval, line;
 648         unsigned long flags;
 649
 650         line = tty->index;
 651         if ((line < 0) || (line >= slgt_device_count)) {
 652                 DBGERR(("%s: open with invalid line #%d.\n", driver_name, line));
 653                 return -ENODEV;
 654         }
 655
 656         info = slgt_device_list;
 657         while(info && info->line != line)
 658                 info = info->next_device;
 659         if (sanity_check(info, tty->name, "open"))
 660                 return -ENODEV;
 661         if (info->init_error) {
 662                 DBGERR(("%s init error=%d\n", info->device_name, info->init_error));
 663                 return -ENODEV;
 664         }
 665
 666         tty->driver_data = info;
 667         info->port.tty = tty;
 668
 669         DBGINFO(("%s open, old ref count = %d\n", info->device_name, info->port.count));
 670
 671         /* If port is closing, signal caller to try again */
 672         if (tty_hung_up_p(filp) || info->port.flags & ASYNC_CLOSING){
 673                 if (info->port.flags & ASYNC_CLOSING)
 674                         interruptible_sleep_on(&info->port.close_wait);
 675                 retval = ((info->port.flags & ASYNC_HUP_NOTIFY) ?
 676                         -EAGAIN : -ERESTARTSYS);
 677                 goto cleanup;
 678         }
 679
 680         info->port.tty->low_latency = (info->port.flags & ASYNC_LOW_LATENCY) ? 1 : 0;
 681
 682         spin_lock_irqsave(&info->netlock, flags);
 683         if (info->netcount) {
 684                 retval = -EBUSY;
 685                 spin_unlock_irqrestore(&info->netlock, flags);
 686                 goto cleanup;
 687         }
 688         info->port.count++;
 689         spin_unlock_irqrestore(&info->netlock, flags);
 690
 691         if (info->port.count == 1) {
 692                 /* 1st open on this device, init hardware */
 693                 retval = startup(info);
 694                 if (retval < 0)
 695                         goto cleanup;
 696         }
 697
 698         retval = block_til_ready(tty, filp, info);
 699         if (retval) {
 700                 DBGINFO(("%s block_til_ready rc=%d\n", info->device_name, retval));
 701                 goto cleanup;
 702         }
 703
 704         retval = 0;
 705
 706 cleanup:
 707         if (retval) {
 708                 if (tty->count == 1)
 709                         info->port.tty = NULL; /* tty layer will release tty struct */
 710                 if(info->port.count)
 711                         info->port.count--;
 712         }
 713
 714         DBGINFO(("%s open rc=%d\n", info->device_name, retval));
 715         return retval;
 716 }
 717
 718 static void close(struct tty_struct *tty, struct file *filp)
 719 {
 720         struct slgt_info *info = tty->driver_data;
 721
 722         if (sanity_check(info, tty->name, "close"))
 723                 return;
 724         DBGINFO(("%s close entry, count=%d\n", info->device_name, info->port.count));
 725
 726         if (!info->port.count)
 727                 return;
 728
 729         if (tty_hung_up_p(filp))
 730                 goto cleanup;
 731
 732         if ((tty->count == 1) && (info->port.count != 1)) {
 733                 /*
 734                  * tty->count is 1 and the tty structure will be freed.
 735                  * info->port.count should be one in this case.
 736                  * if it's not, correct it so that the port is shutdown.
 737                  */
 738                 DBGERR(("%s close: bad refcount; tty->count=1, "
 739                        "info->port.count=%d\n", info->device_name, info->port.count));
 740                 info->port.count = 1;
 741         }
 742
 743         info->port.count--;
 744
 745         /* if at least one open remaining, leave hardware active */
 746         if (info->port.count)
 747                 goto cleanup;
 748
 749         info->port.flags |= ASYNC_CLOSING;
 750
 751         /* set tty->closing to notify line discipline to
 752          * only process XON/XOFF characters. Only the N_TTY
 753          * discipline appears to use this (ppp does not).
 754          */
 755         tty->closing = 1;
 756
 757         /* wait for transmit data to clear all layers */
 758
 759         if (info->port.closing_wait != ASYNC_CLOSING_WAIT_NONE) {
 760                 DBGINFO(("%s call tty_wait_until_sent\n", info->device_name));
 761                 tty_wait_until_sent(tty, info->port.closing_wait);
 762         }
 763
 764         if (info->port.flags & ASYNC_INITIALIZED)
 765                 wait_until_sent(tty, info->timeout);
 766         flush_buffer(tty);
 767         tty_ldisc_flush(tty);
 768
 769         shutdown(info);
 770
 771         tty->closing = 0;
 772         info->port.tty = NULL;
 773
 774         if (info->port.blocked_open) {
 775                 if (info->port.close_delay) {
 776                         msleep_interruptible(jiffies_to_msecs(info->port.close_delay));
 777                 }
 778                 wake_up_interruptible(&info->port.open_wait);
 779         }
 780
 781         info->port.flags &= ~(ASYNC_NORMAL_ACTIVE|ASYNC_CLOSING);
 782
 783         wake_up_interruptible(&info->port.close_wait);
 784
 785 cleanup:
 786         DBGINFO(("%s close exit, count=%d\n", tty->driver->name, info->port.count));
 787 }
 788
 789 static void hangup(struct tty_struct *tty)
 790 {
 791         struct slgt_info *info = tty->driver_data;
 792
 793         if (sanity_check(info, tty->name, "hangup"))
 794                 return;
 795         DBGINFO(("%s hangup\n", info->device_name));
 796
 797         flush_buffer(tty);
 798         shutdown(info);
 799
 800         info->port.count = 0;
 801         info->port.flags &= ~ASYNC_NORMAL_ACTIVE;
 802         info->port.tty = NULL;
 803
 804         wake_up_interruptible(&info->port.open_wait);
 805 }
 806
 807 static void set_termios(struct tty_struct *tty, struct ktermios *old_termios)
 808 {
 809         struct slgt_info *info = tty->driver_data;
 810         unsigned long flags;
 811
 812         DBGINFO(("%s set_termios\n", tty->driver->name));
 813
 814         change_params(info);
 815
 816         /* Handle transition to B0 status */
 817         if (old_termios->c_cflag & CBAUD &&
 818             !(tty->termios->c_cflag & CBAUD)) {
 819                 info->signals &= ~(SerialSignal_RTS + SerialSignal_DTR);
 820                 spin_lock_irqsave(&info->lock,flags);
 821                 set_signals(info);
 822                 spin_unlock_irqrestore(&info->lock,flags);
 823         }
 824
 825         /* Handle transition away from B0 status */
 826         if (!(old_termios->c_cflag & CBAUD) &&
 827             tty->termios->c_cflag & CBAUD) {
 828                 info->signals |= SerialSignal_DTR;
 829                 if (!(tty->termios->c_cflag & CRTSCTS) ||
 830                     !test_bit(TTY_THROTTLED, &tty->flags)) {
 831                         info->signals |= SerialSignal_RTS;
 832                 }
 833                 spin_lock_irqsave(&info->lock,flags);
 834                 set_signals(info);
 835                 spin_unlock_irqrestore(&info->lock,flags);
 836         }
 837
 838         /* Handle turning off CRTSCTS */
 839         if (old_termios->c_cflag & CRTSCTS &&
 840             !(tty->termios->c_cflag & CRTSCTS)) {
 841                 tty->hw_stopped = 0;
 842                 tx_release(tty);
 843         }
 844 }
 845
 846 static int write(struct tty_struct *tty,
 847                  const unsigned char *buf, int count)
 848 {
 849         int ret = 0;
 850         struct slgt_info *info = tty->driver_data;
 851         unsigned long flags;
 852
 853         if (sanity_check(info, tty->name, "write"))
 854                 goto cleanup;
 855         DBGINFO(("%s write count=%d\n", info->device_name, count));
 856
 857         if (!info->tx_buf)
 858                 goto cleanup;
 859
 860         if (count > info->max_frame_size) {
 861                 ret = -EIO;
 862                 goto cleanup;
 863         }
 864
 865         if (!count)
 866                 goto cleanup;
 867
 868         if (info->params.mode == MGSL_MODE_RAW ||
 869             info->params.mode == MGSL_MODE_MONOSYNC ||
 870             info->params.mode == MGSL_MODE_BISYNC) {
 871                 unsigned int bufs_needed = (count/DMABUFSIZE);
 872                 unsigned int bufs_free = free_tbuf_count(info);
 873                 if (count % DMABUFSIZE)
 874                         ++bufs_needed;
 875                 if (bufs_needed > bufs_free)
 876                         goto cleanup;
 877         } else {
 878                 if (info->tx_active)
 879                         goto cleanup;
 880                 if (info->tx_count) {
 881                         /* send accumulated data from send_char() calls */
 882                         /* as frame and wait before accepting more data. */
 883                         tx_load(info, info->tx_buf, info->tx_count);
 884                         goto start;
 885                 }
 886         }
 887
 888         ret = info->tx_count = count;
 889         tx_load(info, buf, count);
 890         goto start;
 891
 892 start:
 893         if (info->tx_count && !tty->stopped && !tty->hw_stopped) {
 894                 spin_lock_irqsave(&info->lock,flags);
 895                 if (!info->tx_active)
 896                         tx_start(info);
 897                 else
 898                         tdma_start(info);
 899                 spin_unlock_irqrestore(&info->lock,flags);
 900         }
 901
 902 cleanup:
 903         DBGINFO(("%s write rc=%d\n", info->device_name, ret));
 904         return ret;
 905 }
 906
 907 static int put_char(struct tty_struct *tty, unsigned char ch)
 908 {
 909         struct slgt_info *info = tty->driver_data;
 910         unsigned long flags;
 911         int ret = 0;
 912
 913         if (sanity_check(info, tty->name, "put_char"))
 914                 return 0;
 915         DBGINFO(("%s put_char(%d)\n", info->device_name, ch));
 916         if (!info->tx_buf)
 917                 return 0;
 918         spin_lock_irqsave(&info->lock,flags);
 919         if (!info->tx_active && (info->tx_count < info->max_frame_size)) {
 920                 info->tx_buf[info->tx_count++] = ch;
 921                 ret = 1;
 922         }
 923         spin_unlock_irqrestore(&info->lock,flags);
 924         return ret;
 925 }
 926
 927 static void send_xchar(struct tty_struct *tty, char ch)
 928 {
 929         struct slgt_info *info = tty->driver_data;
 930         unsigned long flags;
 931
 932         if (sanity_check(info, tty->name, "send_xchar"))
 933                 return;
 934         DBGINFO(("%s send_xchar(%d)\n", info->device_name, ch));
 935         info->x_char = ch;
 936         if (ch) {
 937                 spin_lock_irqsave(&info->lock,flags);
 938                 if (!info->tx_enabled)
 939                         tx_start(info);
 940                 spin_unlock_irqrestore(&info->lock,flags);
 941         }
 942 }
 943
 944 static void wait_until_sent(struct tty_struct *tty, int timeout)
 945 {
 946         struct slgt_info *info = tty->driver_data;
 947         unsigned long orig_jiffies, char_time;
 948
 949         if (!info )
 950                 return;
 951         if (sanity_check(info, tty->name, "wait_until_sent"))
 952                 return;
 953         DBGINFO(("%s wait_until_sent entry\n", info->device_name));
 954         if (!(info->port.flags & ASYNC_INITIALIZED))
 955                 goto exit;
 956
 957         orig_jiffies = jiffies;
 958
 959         /* Set check interval to 1/5 of estimated time to
 960          * send a character, and make it at least 1. The check
 961          * interval should also be less than the timeout.
 962          * Note: use tight timings here to satisfy the NIST-PCTS.
 963          */
 964
 965         lock_kernel();
 966
 967         if (info->params.data_rate) {
 968                 char_time = info->timeout/(32 * 5);
 969                 if (!char_time)
 970                         char_time++;
 971         } else
 972                 char_time = 1;
 973
 974         if (timeout)
 975                 char_time = min_t(unsigned long, char_time, timeout);
 976
 977         while (info->tx_active) {
 978                 msleep_interruptible(jiffies_to_msecs(char_time));
 979                 if (signal_pending(current))
 980                         break;
 981                 if (timeout && time_after(jiffies, orig_jiffies + timeout))
 982                         break;
 983         }
 984         unlock_kernel();
 985
 986 exit:
 987         DBGINFO(("%s wait_until_sent exit\n", info->device_name));
 988 }
 989
 990 static int write_room(struct tty_struct *tty)
 991 {
 992         struct slgt_info *info = tty->driver_data;
 993         int ret;
 994
 995         if (sanity_check(info, tty->name, "write_room"))
 996                 return 0;
 997         ret = (info->tx_active) ? 0 : HDLC_MAX_FRAME_SIZE;
 998         DBGINFO(("%s write_room=%d\n", info->device_name, ret));
 999         return ret;
1000 }
1001
1002 static void flush_chars(struct tty_struct *tty)
1003 {
1004         struct slgt_info *info = tty->driver_data;
1005         unsigned long flags;
1006
1007         if (sanity_check(info, tty->name, "flush_chars"))
1008                 return;
1009         DBGINFO(("%s flush_chars entry tx_count=%d\n", info->device_name, info->tx_count));
1010
1011         if (info->tx_count <= 0 || tty->stopped ||
1012             tty->hw_stopped || !info->tx_buf)
1013                 return;
1014
1015         DBGINFO(("%s flush_chars start transmit\n", info->device_name));
1016
1017         spin_lock_irqsave(&info->lock,flags);
1018         if (!info->tx_active && info->tx_count) {
1019                 tx_load(info, info->tx_buf,info->tx_count);
1020                 tx_start(info);
1021         }
1022         spin_unlock_irqrestore(&info->lock,flags);
1023 }
1024
1025 static void flush_buffer(struct tty_struct *tty)
1026 {
1027         struct slgt_info *info = tty->driver_data;
1028         unsigned long flags;
1029
1030         if (sanity_check(info, tty->name, "flush_buffer"))
1031                 return;
1032         DBGINFO(("%s flush_buffer\n", info->device_name));
1033
1034         spin_lock_irqsave(&info->lock,flags);
1035         if (!info->tx_active)
1036                 info->tx_count = 0;
1037         spin_unlock_irqrestore(&info->lock,flags);
1038
1039         tty_wakeup(tty);
1040 }
1041
1042 /*
1043  * throttle (stop) transmitter
1044  */
1045 static void tx_hold(struct tty_struct *tty)
1046 {
1047         struct slgt_info *info = tty->driver_data;
1048         unsigned long flags;
1049
1050         if (sanity_check(info, tty->name, "tx_hold"))
1051                 return;
1052         DBGINFO(("%s tx_hold\n", info->device_name));
1053         spin_lock_irqsave(&info->lock,flags);
1054         if (info->tx_enabled && info->params.mode == MGSL_MODE_ASYNC)
1055                 tx_stop(info);
1056         spin_unlock_irqrestore(&info->lock,flags);
1057 }
1058
1059 /*
1060  * release (start) transmitter
1061  */
1062 static void tx_release(struct tty_struct *tty)
1063 {
1064         struct slgt_info *info = tty->driver_data;
1065         unsigned long flags;
1066
1067         if (sanity_check(info, tty->name, "tx_release"))
1068                 return;
1069         DBGINFO(("%s tx_release\n", info->device_name));
1070         spin_lock_irqsave(&info->lock,flags);
1071         if (!info->tx_active && info->tx_count) {
1072                 tx_load(info, info->tx_buf, info->tx_count);
1073                 tx_start(info);
1074         }
1075         spin_unlock_irqrestore(&info->lock,flags);
1076 }
1077
1078 /*
1079  * Service an IOCTL request
1080  *
1081  * Arguments
1082  *
1083  *      tty     pointer to tty instance data
1084  *      file    pointer to associated file object for device
1085  *      cmd     IOCTL command code
1086  *      arg     command argument/context
1087  *
1088  * Return 0 if success, otherwise error code
1089  */
1090 static int ioctl(struct tty_struct *tty, struct file *file,
1091                  unsigned int cmd, unsigned long arg)
1092 {
1093         struct slgt_info *info = tty->driver_data;
1094         struct mgsl_icount cnow;        /* kernel counter temps */
1095         struct serial_icounter_struct __user *p_cuser;  /* user space */
1096         unsigned long flags;
1097         void __user *argp = (void __user *)arg;
1098         int ret;
1099
1100         if (sanity_check(info, tty->name, "ioctl"))
1101                 return -ENODEV;
1102         DBGINFO(("%s ioctl() cmd=%08X\n", info->device_name, cmd));
1103
1104         if ((cmd != TIOCGSERIAL) && (cmd != TIOCSSERIAL) &&
1105             (cmd != TIOCMIWAIT) && (cmd != TIOCGICOUNT)) {
1106                 if (tty->flags & (1 << TTY_IO_ERROR))
1107                     return -EIO;
1108         }
1109
1110         lock_kernel();
1111
1112         switch (cmd) {
1113         case MGSL_IOCGPARAMS:
1114                 ret = get_params(info, argp);
1115                 break;
1116         case MGSL_IOCSPARAMS:
1117                 ret = set_params(info, argp);
1118                 break;
1119         case MGSL_IOCGTXIDLE:
1120                 ret = get_txidle(info, argp);
1121                 break;
1122         case MGSL_IOCSTXIDLE:
1123                 ret = set_txidle(info, (int)arg);
1124                 break;
1125         case MGSL_IOCTXENABLE:
1126                 ret = tx_enable(info, (int)arg);
1127                 break;
1128         case MGSL_IOCRXENABLE:
1129                 ret = rx_enable(info, (int)arg);
1130                 break;
1131         case MGSL_IOCTXABORT:
1132                 ret = tx_abort(info);
1133                 break;
1134         case MGSL_IOCGSTATS:
1135                 ret = get_stats(info, argp);
1136                 break;
1137         case MGSL_IOCWAITEVENT:
1138                 ret = wait_mgsl_event(info, argp);
1139                 break;
1140         case TIOCMIWAIT:
1141                 ret = modem_input_wait(info,(int)arg);
1142                 break;
1143         case MGSL_IOCGIF:
1144                 ret = get_interface(info, argp);
1145                 break;
1146         case MGSL_IOCSIF:
1147                 ret = set_interface(info,(int)arg);
1148                 break;
1149         case MGSL_IOCSGPIO:
1150                 ret = set_gpio(info, argp);
1151                 break;
1152         case MGSL_IOCGGPIO:
1153                 ret = get_gpio(info, argp);
1154                 break;
1155         case MGSL_IOCWAITGPIO:
1156                 ret = wait_gpio(info, argp);
1157                 break;
1158         case TIOCGICOUNT:
1159                 spin_lock_irqsave(&info->lock,flags);
1160                 cnow = info->icount;
1161                 spin_unlock_irqrestore(&info->lock,flags);
1162                 p_cuser = argp;
1163                 if (put_user(cnow.cts, &p_cuser->cts) ||
1164                     put_user(cnow.dsr, &p_cuser->dsr) ||
1165                     put_user(cnow.rng, &p_cuser->rng) ||
1166                     put_user(cnow.dcd, &p_cuser->dcd) ||
1167                     put_user(cnow.rx, &p_cuser->rx) ||
1168                     put_user(cnow.tx, &p_cuser->tx) ||
1169                     put_user(cnow.frame, &p_cuser->frame) ||
1170                     put_user(cnow.overrun, &p_cuser->overrun) ||
1171                     put_user(cnow.parity, &p_cuser->parity) ||
1172                     put_user(cnow.brk, &p_cuser->brk) ||
1173                     put_user(cnow.buf_overrun, &p_cuser->buf_overrun))
1174                         ret = -EFAULT;
1175                 ret = 0;
1176                 break;
1177         default:
1178                 ret = -ENOIOCTLCMD;
1179         }
1180         unlock_kernel();
1181         return ret;
1182 }
1183
1184 /*
1185  * support for 32 bit ioctl calls on 64 bit systems
1186  */
1187 #ifdef CONFIG_COMPAT
1188 static long get_params32(struct slgt_info *info, struct MGSL_PARAMS32 __user *user_params)
1189 {
1190         struct MGSL_PARAMS32 tmp_params;
1191
1192         DBGINFO(("%s get_params32\n", info->device_name));
1193         tmp_params.mode            = (compat_ulong_t)info->params.mode;
1194         tmp_params.loopback        = info->params.loopback;
1195         tmp_params.flags           = info->params.flags;
1196         tmp_params.encoding        = info->params.encoding;
1197         tmp_params.clock_speed     = (compat_ulong_t)info->params.clock_speed;
1198         tmp_params.addr_filter     = info->params.addr_filter;
1199         tmp_params.crc_type        = info->params.crc_type;
1200         tmp_params.preamble_length = info->params.preamble_length;
1201         tmp_params.preamble        = info->params.preamble;
1202         tmp_params.data_rate       = (compat_ulong_t)info->params.data_rate;
1203         tmp_params.data_bits       = info->params.data_bits;
1204         tmp_params.stop_bits       = info->params.stop_bits;
1205         tmp_params.parity          = info->params.parity;
1206         if (copy_to_user(user_params, &tmp_params, sizeof(struct MGSL_PARAMS32)))
1207                 return -EFAULT;
1208         return 0;
1209 }
1210
1211 static long set_params32(struct slgt_info *info, struct MGSL_PARAMS32 __user *new_params)
1212 {
1213         struct MGSL_PARAMS32 tmp_params;
1214
1215         DBGINFO(("%s set_params32\n", info->device_name));
1216         if (copy_from_user(&tmp_params, new_params, sizeof(struct MGSL_PARAMS32)))
1217                 return -EFAULT;
1218
1219         spin_lock(&info->lock);
1220         info->params.mode            = tmp_params.mode;
1221         info->params.loopback        = tmp_params.loopback;
1222         info->params.flags           = tmp_params.flags;
1223         info->params.encoding        = tmp_params.encoding;
1224         info->params.clock_speed     = tmp_params.clock_speed;
1225         info->params.addr_filter     = tmp_params.addr_filter;
1226         info->params.crc_type        = tmp_params.crc_type;
1227         info->params.preamble_length = tmp_params.preamble_length;
1228         info->params.preamble        = tmp_params.preamble;
1229         info->params.data_rate       = tmp_params.data_rate;
1230         info->params.data_bits       = tmp_params.data_bits;
1231         info->params.stop_bits       = tmp_params.stop_bits;
1232         info->params.parity          = tmp_params.parity;
1233         spin_unlock(&info->lock);
1234
1235         change_params(info);
1236
1237         return 0;
1238 }
1239
1240 static long slgt_compat_ioctl(struct tty_struct *tty, struct file *file,
1241                          unsigned int cmd, unsigned long arg)
1242 {
1243         struct slgt_info *info = tty->driver_data;
1244         int rc = -ENOIOCTLCMD;
1245
1246         if (sanity_check(info, tty->name, "compat_ioctl"))
1247                 return -ENODEV;
1248         DBGINFO(("%s compat_ioctl() cmd=%08X\n", info->device_name, cmd));
1249
1250         switch (cmd) {
1251
1252         case MGSL_IOCSPARAMS32:
1253                 rc = set_params32(info, compat_ptr(arg));
1254                 break;
1255
1256         case MGSL_IOCGPARAMS32:
1257                 rc = get_params32(info, compat_ptr(arg));
1258                 break;
1259
1260         case MGSL_IOCGPARAMS:
1261         case MGSL_IOCSPARAMS:
1262         case MGSL_IOCGTXIDLE:
1263         case MGSL_IOCGSTATS:
1264         case MGSL_IOCWAITEVENT:
1265         case MGSL_IOCGIF:
1266         case MGSL_IOCSGPIO:
1267         case MGSL_IOCGGPIO:
1268         case MGSL_IOCWAITGPIO:
1269         case TIOCGICOUNT:
1270                 rc = ioctl(tty, file, cmd, (unsigned long)(compat_ptr(arg)));
1271                 break;
1272
1273         case MGSL_IOCSTXIDLE:
1274         case MGSL_IOCTXENABLE:
1275         case MGSL_IOCRXENABLE:
1276         case MGSL_IOCTXABORT:
1277         case TIOCMIWAIT:
1278         case MGSL_IOCSIF:
1279                 rc = ioctl(tty, file, cmd, arg);
1280                 break;
1281         }
1282
1283         DBGINFO(("%s compat_ioctl() cmd=%08X rc=%d\n", info->device_name, cmd, rc));
1284         return rc;
1285 }
1286 #else
1287 #define slgt_compat_ioctl NULL
1288 #endif /* ifdef CONFIG_COMPAT */
1289
1290 /*
1291  * proc fs support
1292  */
1293 static inline int line_info(char *buf, struct slgt_info *info)
1294 {
1295         char stat_buf[30];
1296         int ret;
1297         unsigned long flags;
1298
1299         ret = sprintf(buf, "%s: IO=%08X IRQ=%d MaxFrameSize=%u\n",
1300                       info->device_name, info->phys_reg_addr,
1301                       info->irq_level, info->max_frame_size);
1302
1303         /* output current serial signal states */
1304         spin_lock_irqsave(&info->lock,flags);
1305         get_signals(info);
1306         spin_unlock_irqrestore(&info->lock,flags);
1307
1308         stat_buf[0] = 0;
1309         stat_buf[1] = 0;
1310         if (info->signals & SerialSignal_RTS)
1311                 strcat(stat_buf, "|RTS");
1312         if (info->signals & SerialSignal_CTS)
1313                 strcat(stat_buf, "|CTS");
1314         if (info->signals & SerialSignal_DTR)
1315                 strcat(stat_buf, "|DTR");
1316         if (info->signals & SerialSignal_DSR)
1317                 strcat(stat_buf, "|DSR");
1318         if (info->signals & SerialSignal_DCD)
1319                 strcat(stat_buf, "|CD");
1320         if (info->signals & SerialSignal_RI)
1321                 strcat(stat_buf, "|RI");
1322
1323         if (info->params.mode != MGSL_MODE_ASYNC) {
1324                 ret += sprintf(buf+ret, "\tHDLC txok:%d rxok:%d",
1325                                info->icount.txok, info->icount.rxok);
1326                 if (info->icount.txunder)
1327                         ret += sprintf(buf+ret, " txunder:%d", info->icount.txunder);
1328                 if (info->icount.txabort)
1329                         ret += sprintf(buf+ret, " txabort:%d", info->icount.txabort);
1330                 if (info->icount.rxshort)
1331                         ret += sprintf(buf+ret, " rxshort:%d", info->icount.rxshort);
1332                 if (info->icount.rxlong)
1333                         ret += sprintf(buf+ret, " rxlong:%d", info->icount.rxlong);
1334                 if (info->icount.rxover)
1335                         ret += sprintf(buf+ret, " rxover:%d", info->icount.rxover);
1336                 if (info->icount.rxcrc)
1337                         ret += sprintf(buf+ret, " rxcrc:%d", info->icount.rxcrc);
1338         } else {
1339                 ret += sprintf(buf+ret, "\tASYNC tx:%d rx:%d",
1340                                info->icount.tx, info->icount.rx);
1341                 if (info->icount.frame)
1342                         ret += sprintf(buf+ret, " fe:%d", info->icount.frame);
1343                 if (info->icount.parity)
1344                         ret += sprintf(buf+ret, " pe:%d", info->icount.parity);
1345                 if (info->icount.brk)
1346                         ret += sprintf(buf+ret, " brk:%d", info->icount.brk);
1347                 if (info->icount.overrun)
1348                         ret += sprintf(buf+ret, " oe:%d", info->icount.overrun);
1349         }
1350
1351         /* Append serial signal status to end */
1352         ret += sprintf(buf+ret, " %s\n", stat_buf+1);
1353
1354         ret += sprintf(buf+ret, "\ttxactive=%d bh_req=%d bh_run=%d pending_bh=%x\n",
1355                        info->tx_active,info->bh_requested,info->bh_running,
1356                        info->pending_bh);
1357
1358         return ret;
1359 }
1360
1361 /* Called to print information about devices
1362  */
1363 static int read_proc(char *page, char **start, off_t off, int count,
1364                      int *eof, void *data)
1365 {
1366         int len = 0, l;
1367         off_t   begin = 0;
1368         struct slgt_info *info;
1369
1370         len += sprintf(page, "synclink_gt driver:%s\n", driver_version);
1371
1372         info = slgt_device_list;
1373         while( info ) {
1374                 l = line_info(page + len, info);
1375                 len += l;
1376                 if (len+begin > off+count)
1377                         goto done;
1378                 if (len+begin < off) {
1379                         begin += len;
1380                         len = 0;
1381                 }
1382                 info = info->next_device;
1383         }
1384
1385         *eof = 1;
1386 done:
1387         if (off >= len+begin)
1388                 return 0;
1389         *start = page + (off-begin);
1390         return ((count < begin+len-off) ? count : begin+len-off);
1391 }
1392
1393 /*
1394  * return count of bytes in transmit buffer
1395  */
1396 static int chars_in_buffer(struct tty_struct *tty)
1397 {
1398         struct slgt_info *info = tty->driver_data;
1399         if (sanity_check(info, tty->name, "chars_in_buffer"))
1400                 return 0;
1401         DBGINFO(("%s chars_in_buffer()=%d\n", info->device_name, info->tx_count));
1402         return info->tx_count;
1403 }
1404
1405 /*
1406  * signal remote device to throttle send data (our receive data)
1407  */
1408 static void throttle(struct tty_struct * tty)
1409 {
1410         struct slgt_info *info = tty->driver_data;
1411         unsigned long flags;
1412
1413         if (sanity_check(info, tty->name, "throttle"))
1414                 return;
1415         DBGINFO(("%s throttle\n", info->device_name));
1416         if (I_IXOFF(tty))
1417                 send_xchar(tty, STOP_CHAR(tty));
1418         if (tty->termios->c_cflag & CRTSCTS) {
1419                 spin_lock_irqsave(&info->lock,flags);
1420                 info->signals &= ~SerialSignal_RTS;
1421                 set_signals(info);
1422                 spin_unlock_irqrestore(&info->lock,flags);
1423         }
1424 }
1425
1426 /*
1427  * signal remote device to stop throttling send data (our receive data)
1428  */
1429 static void unthrottle(struct tty_struct * tty)
1430 {
1431         struct slgt_info *info = tty->driver_data;
1432         unsigned long flags;
1433
1434         if (sanity_check(info, tty->name, "unthrottle"))
1435                 return;
1436         DBGINFO(("%s unthrottle\n", info->device_name));
1437         if (I_IXOFF(tty)) {
1438                 if (info->x_char)
1439                         info->x_char = 0;
1440                 else
1441                         send_xchar(tty, START_CHAR(tty));
1442         }
1443         if (tty->termios->c_cflag & CRTSCTS) {
1444                 spin_lock_irqsave(&info->lock,flags);
1445                 info->signals |= SerialSignal_RTS;
1446                 set_signals(info);
1447                 spin_unlock_irqrestore(&info->lock,flags);
1448         }
1449 }
1450
1451 /*
1452  * set or clear transmit break condition
1453  * break_state  -1=set break condition, 0=clear
1454  */
1455 static void set_break(struct tty_struct *tty, int break_state)
1456 {
1457         struct slgt_info *info = tty->driver_data;
1458         unsigned short value;
1459         unsigned long flags;
1460
1461         if (sanity_check(info, tty->name, "set_break"))
1462                 return;
1463         DBGINFO(("%s set_break(%d)\n", info->device_name, break_state));
1464
1465         spin_lock_irqsave(&info->lock,flags);
1466         value = rd_reg16(info, TCR);
1467         if (break_state == -1)
1468                 value |= BIT6;
1469         else
1470                 value &= ~BIT6;
1471         wr_reg16(info, TCR, value);
1472         spin_unlock_irqrestore(&info->lock,flags);
1473 }
1474
1475 #if SYNCLINK_GENERIC_HDLC
1476
1477 /**
1478  * called by generic HDLC layer when protocol selected (PPP, frame relay, etc.)
1479  * set encoding and frame check sequence (FCS) options
1480  *
1481  * dev       pointer to network device structure
1482  * encoding  serial encoding setting
1483  * parity    FCS setting
1484  *
1485  * returns 0 if success, otherwise error code
1486  */
1487 static int hdlcdev_attach(struct net_device *dev, unsigned short encoding,
1488                           unsigned short parity)
1489 {
1490         struct slgt_info *info = dev_to_port(dev);
1491         unsigned char  new_encoding;
1492         unsigned short new_crctype;
1493
1494         /* return error if TTY interface open */
1495         if (info->port.count)
1496                 return -EBUSY;
1497
1498         DBGINFO(("%s hdlcdev_attach\n", info->device_name));
1499
1500         switch (encoding)
1501         {
1502         case ENCODING_NRZ:        new_encoding = HDLC_ENCODING_NRZ; break;
1503         case ENCODING_NRZI:       new_encoding = HDLC_ENCODING_NRZI_SPACE; break;
1504         case ENCODING_FM_MARK:    new_encoding = HDLC_ENCODING_BIPHASE_MARK; break;
1505         case ENCODING_FM_SPACE:   new_encoding = HDLC_ENCODING_BIPHASE_SPACE; break;
1506         case ENCODING_MANCHESTER: new_encoding = HDLC_ENCODING_BIPHASE_LEVEL; break;
1507         default: return -EINVAL;
1508         }
1509
1510         switch (parity)
1511         {
1512         case PARITY_NONE:            new_crctype = HDLC_CRC_NONE; break;
1513         case PARITY_CRC16_PR1_CCITT: new_crctype = HDLC_CRC_16_CCITT; break;
1514         case PARITY_CRC32_PR1_CCITT: new_crctype = HDLC_CRC_32_CCITT; break;
1515         default: return -EINVAL;
1516         }
1517
1518         info->params.encoding = new_encoding;
1519         info->params.crc_type = new_crctype;
1520
1521         /* if network interface up, reprogram hardware */
1522         if (info->netcount)
1523                 program_hw(info);
1524
1525         return 0;
1526 }
1527
1528 /**
1529  * called by generic HDLC layer to send frame
1530  *
1531  * skb  socket buffer containing HDLC frame
1532  * dev  pointer to network device structure
1533  *
1534  * returns 0 if success, otherwise error code
1535  */
1536 static int hdlcdev_xmit(struct sk_buff *skb, struct net_device *dev)
1537 {
1538         struct slgt_info *info = dev_to_port(dev);
1539         unsigned long flags;
1540
1541         DBGINFO(("%s hdlc_xmit\n", dev->name));
1542
1543         /* stop sending until this frame completes */
1544         netif_stop_queue(dev);
1545
1546         /* copy data to device buffers */
1547         info->tx_count = skb->len;
1548         tx_load(info, skb->data, skb->len);
1549
1550         /* update network statistics */
1551         dev->stats.tx_packets++;
1552         dev->stats.tx_bytes += skb->len;
1553
1554         /* done with socket buffer, so free it */
1555         dev_kfree_skb(skb);
1556
1557         /* save start time for transmit timeout detection */
1558         dev->trans_start = jiffies;
1559
1560         /* start hardware transmitter if necessary */
1561         spin_lock_irqsave(&info->lock,flags);
1562         if (!info->tx_active)
1563                 tx_start(info);
1564         spin_unlock_irqrestore(&info->lock,flags);
1565
1566         return 0;
1567 }
1568
1569 /**
1570  * called by network layer when interface enabled
1571  * claim resources and initialize hardware
1572  *
1573  * dev  pointer to network device structure
1574  *
1575  * returns 0 if success, otherwise error code
1576  */
1577 static int hdlcdev_open(struct net_device *dev)
1578 {
1579         struct slgt_info *info = dev_to_port(dev);
1580         int rc;
1581         unsigned long flags;
1582
1583         if (!try_module_get(THIS_MODULE))
1584                 return -EBUSY;
1585
1586         DBGINFO(("%s hdlcdev_open\n", dev->name));
1587
1588         /* generic HDLC layer open processing */
1589         if ((rc = hdlc_open(dev)))
1590                 return rc;
1591
1592         /* arbitrate between network and tty opens */
1593         spin_lock_irqsave(&info->netlock, flags);
1594         if (info->port.count != 0 || info->netcount != 0) {
1595                 DBGINFO(("%s hdlc_open busy\n", dev->name));
1596                 spin_unlock_irqrestore(&info->netlock, flags);
1597                 return -EBUSY;
1598         }
1599         info->netcount=1;
1600         spin_unlock_irqrestore(&info->netlock, flags);
1601
1602         /* claim resources and init adapter */
1603         if ((rc = startup(info)) != 0) {
1604                 spin_lock_irqsave(&info->netlock, flags);
1605                 info->netcount=0;
1606                 spin_unlock_irqrestore(&info->netlock, flags);
1607                 return rc;
1608         }
1609
1610         /* assert DTR and RTS, apply hardware settings */
1611         info->signals |= SerialSignal_RTS + SerialSignal_DTR;
1612         program_hw(info);
1613
1614         /* enable network layer transmit */
1615         dev->trans_start = jiffies;
1616         netif_start_queue(dev);
1617
1618         /* inform generic HDLC layer of current DCD status */
1619         spin_lock_irqsave(&info->lock, flags);
1620         get_signals(info);
1621         spin_unlock_irqrestore(&info->lock, flags);
1622         if (info->signals & SerialSignal_DCD)
1623                 netif_carrier_on(dev);
1624         else
1625                 netif_carrier_off(dev);
1626         return 0;
1627 }
1628
1629 /**
1630  * called by network layer when interface is disabled
1631  * shutdown hardware and release resources
1632  *
1633  * dev  pointer to network device structure
1634  *
1635  * returns 0 if success, otherwise error code
1636  */
1637 static int hdlcdev_close(struct net_device *dev)
1638 {
1639         struct slgt_info *info = dev_to_port(dev);
1640         unsigned long flags;
1641
1642         DBGINFO(("%s hdlcdev_close\n", dev->name));
1643
1644         netif_stop_queue(dev);
1645
1646         /* shutdown adapter and release resources */
1647         shutdown(info);
1648
1649         hdlc_close(dev);
1650
1651         spin_lock_irqsave(&info->netlock, flags);
1652         info->netcount=0;
1653         spin_unlock_irqrestore(&info->netlock, flags);
1654
1655         module_put(THIS_MODULE);
1656         return 0;
1657 }
1658
1659 /**
1660  * called by network layer to process IOCTL call to network device
1661  *
1662  * dev  pointer to network device structure
1663  * ifr  pointer to network interface request structure
1664  * cmd  IOCTL command code
1665  *
1666  * returns 0 if success, otherwise error code
1667  */
1668 static int hdlcdev_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd)
1669 {
1670         const size_t size = sizeof(sync_serial_settings);
1671         sync_serial_settings new_line;
1672         sync_serial_settings __user *line = ifr->ifr_settings.ifs_ifsu.sync;
1673         struct slgt_info *info = dev_to_port(dev);
1674         unsigned int flags;
1675
1676         DBGINFO(("%s hdlcdev_ioctl\n", dev->name));
1677
1678         /* return error if TTY interface open */
1679         if (info->port.count)
1680                 return -EBUSY;
1681
1682         if (cmd != SIOCWANDEV)
1683                 return hdlc_ioctl(dev, ifr, cmd);
1684
1685         switch(ifr->ifr_settings.type) {
1686         case IF_GET_IFACE: /* return current sync_serial_settings */
1687
1688                 ifr->ifr_settings.type = IF_IFACE_SYNC_SERIAL;
1689                 if (ifr->ifr_settings.size < size) {
1690                         ifr->ifr_settings.size = size; /* data size wanted */
1691                         return -ENOBUFS;
1692                 }
1693
1694                 flags = info->params.flags & (HDLC_FLAG_RXC_RXCPIN | HDLC_FLAG_RXC_DPLL |
1695                                               HDLC_FLAG_RXC_BRG    | HDLC_FLAG_RXC_TXCPIN |
1696                                               HDLC_FLAG_TXC_TXCPIN | HDLC_FLAG_TXC_DPLL |
1697                                               HDLC_FLAG_TXC_BRG    | HDLC_FLAG_TXC_RXCPIN);
1698
1699                 switch (flags){
1700                 case (HDLC_FLAG_RXC_RXCPIN | HDLC_FLAG_TXC_TXCPIN): new_line.clock_type = CLOCK_EXT; break;
1701                 case (HDLC_FLAG_RXC_BRG    | HDLC_FLAG_TXC_BRG):    new_line.clock_type = CLOCK_INT; break;
1702                 case (HDLC_FLAG_RXC_RXCPIN | HDLC_FLAG_TXC_BRG):    new_line.clock_type = CLOCK_TXINT; break;
1703                 case (HDLC_FLAG_RXC_RXCPIN | HDLC_FLAG_TXC_RXCPIN): new_line.clock_type = CLOCK_TXFROMRX; break;
1704                 default: new_line.clock_type = CLOCK_DEFAULT;
1705                 }
1706
1707                 new_line.clock_rate = info->params.clock_speed;
1708                 new_line.loopback   = info->params.loopback ? 1:0;
1709
1710                 if (copy_to_user(line, &new_line, size))
1711                         return -EFAULT;
1712                 return 0;
1713
1714         case IF_IFACE_SYNC_SERIAL: /* set sync_serial_settings */
1715
1716                 if(!capable(CAP_NET_ADMIN))
1717                         return -EPERM;
1718                 if (copy_from_user(&new_line, line, size))
1719                         return -EFAULT;
1720
1721                 switch (new_line.clock_type)
1722                 {
1723                 case CLOCK_EXT:      flags = HDLC_FLAG_RXC_RXCPIN | HDLC_FLAG_TXC_TXCPIN; break;
1724                 case CLOCK_TXFROMRX: flags = HDLC_FLAG_RXC_RXCPIN | HDLC_FLAG_TXC_RXCPIN; break;
1725                 case CLOCK_INT:      flags = HDLC_FLAG_RXC_BRG    | HDLC_FLAG_TXC_BRG;    break;
1726                 case CLOCK_TXINT:    flags = HDLC_FLAG_RXC_RXCPIN | HDLC_FLAG_TXC_BRG;    break;
1727                 case CLOCK_DEFAULT:  flags = info->params.flags &
1728                                              (HDLC_FLAG_RXC_RXCPIN | HDLC_FLAG_RXC_DPLL |
1729                                               HDLC_FLAG_RXC_BRG    | HDLC_FLAG_RXC_TXCPIN |
1730                                               HDLC_FLAG_TXC_TXCPIN | HDLC_FLAG_TXC_DPLL |
1731                                               HDLC_FLAG_TXC_BRG    | HDLC_FLAG_TXC_RXCPIN); break;
1732                 default: return -EINVAL;
1733                 }
1734
1735                 if (new_line.loopback != 0 && new_line.loopback != 1)
1736                         return -EINVAL;
1737
1738                 info->params.flags &= ~(HDLC_FLAG_RXC_RXCPIN | HDLC_FLAG_RXC_DPLL |
1739                                         HDLC_FLAG_RXC_BRG    | HDLC_FLAG_RXC_TXCPIN |
1740                                         HDLC_FLAG_TXC_TXCPIN | HDLC_FLAG_TXC_DPLL |
1741                                         HDLC_FLAG_TXC_BRG    | HDLC_FLAG_TXC_RXCPIN);
1742                 info->params.flags |= flags;
1743
1744                 info->params.loopback = new_line.loopback;
1745
1746                 if (flags & (HDLC_FLAG_RXC_BRG | HDLC_FLAG_TXC_BRG))
1747                         info->params.clock_speed = new_line.clock_rate;
1748                 else
1749                         info->params.clock_speed = 0;
1750
1751                 /* if network interface up, reprogram hardware */
1752                 if (info->netcount)
1753                         program_hw(info);
1754                 return 0;
1755
1756         default:
1757                 return hdlc_ioctl(dev, ifr, cmd);
1758         }
1759 }
1760
1761 /**
1762  * called by network layer when transmit timeout is detected
1763  *
1764  * dev  pointer to network device structure
1765  */
1766 static void hdlcdev_tx_timeout(struct net_device *dev)
1767 {
1768         struct slgt_info *info = dev_to_port(dev);
1769         unsigned long flags;
1770
1771         DBGINFO(("%s hdlcdev_tx_timeout\n", dev->name));
1772
1773         dev->stats.tx_errors++;
1774         dev->stats.tx_aborted_errors++;
1775
1776         spin_lock_irqsave(&info->lock,flags);
1777         tx_stop(info);
1778         spin_unlock_irqrestore(&info->lock,flags);
1779
1780         netif_wake_queue(dev);
1781 }
1782
1783 /**
1784  * called by device driver when transmit completes
1785  * reenable network layer transmit if stopped
1786  *
1787  * info  pointer to device instance information
1788  */
1789 static void hdlcdev_tx_done(struct slgt_info *info)
1790 {
1791         if (netif_queue_stopped(info->netdev))
1792                 netif_wake_queue(info->netdev);
1793 }
1794
1795 /**
1796  * called by device driver when frame received
1797  * pass frame to network layer
1798  *
1799  * info  pointer to device instance information
1800  * buf   pointer to buffer contianing frame data
1801  * size  count of data bytes in buf
1802  */
1803 static void hdlcdev_rx(struct slgt_info *info, char *buf, int size)
1804 {
1805         struct sk_buff *skb = dev_alloc_skb(size);
1806         struct net_device *dev = info->netdev;
1807
1808         DBGINFO(("%s hdlcdev_rx\n", dev->name));
1809
1810         if (skb == NULL) {
1811                 DBGERR(("%s: can't alloc skb, drop packet\n", dev->name));
1812                 dev->stats.rx_dropped++;
1813                 return;
1814         }
1815
1816         memcpy(skb_put(skb, size), buf, size);
1817
1818         skb->protocol = hdlc_type_trans(skb, dev);
1819
1820         dev->stats.rx_packets++;
1821         dev->stats.rx_bytes += size;
1822
1823         netif_rx(skb);
1824
1825         dev->last_rx = jiffies;
1826 }
1827
1828 /**
1829  * called by device driver when adding device instance
1830  * do generic HDLC initialization
1831  *
1832  * info  pointer to device instance information
1833  *
1834  * returns 0 if success, otherwise error code
1835  */
1836 static int hdlcdev_init(struct slgt_info *info)
1837 {
1838         int rc;
1839         struct net_device *dev;
1840         hdlc_device *hdlc;
1841
1842         /* allocate and initialize network and HDLC layer objects */
1843
1844         if (!(dev = alloc_hdlcdev(info))) {
1845                 printk(KERN_ERR "%s hdlc device alloc failure\n", info->device_name);
1846                 return -ENOMEM;
1847         }
1848
1849         /* for network layer reporting purposes only */
1850         dev->mem_start = info->phys_reg_addr;
1851         dev->mem_end   = info->phys_reg_addr + SLGT_REG_SIZE - 1;
1852         dev->irq       = info->irq_level;
1853
1854         /* network layer callbacks and settings */
1855         dev->do_ioctl       = hdlcdev_ioctl;
1856         dev->open           = hdlcdev_open;
1857         dev->stop           = hdlcdev_close;
1858         dev->tx_timeout     = hdlcdev_tx_timeout;
1859         dev->watchdog_timeo = 10*HZ;
1860         dev->tx_queue_len   = 50;
1861
1862         /* generic HDLC layer callbacks and settings */
1863         hdlc         = dev_to_hdlc(dev);
1864         hdlc->attach = hdlcdev_attach;
1865         hdlc->xmit   = hdlcdev_xmit;
1866
1867         /* register objects with HDLC layer */
1868         if ((rc = register_hdlc_device(dev))) {
1869                 printk(KERN_WARNING "%s:unable to register hdlc device\n",__FILE__);
1870                 free_netdev(dev);
1871                 return rc;
1872         }
1873
1874         info->netdev = dev;
1875         return 0;
1876 }
1877
1878 /**
1879  * called by device driver when removing device instance
1880  * do generic HDLC cleanup
1881  *
1882  * info  pointer to device instance information
1883  */
1884 static void hdlcdev_exit(struct slgt_info *info)
1885 {
1886         unregister_hdlc_device(info->netdev);
1887         free_netdev(info->netdev);
1888         info->netdev = NULL;
1889 }
1890
1891 #endif /* ifdef CONFIG_HDLC */
1892
1893 /*
1894  * get async data from rx DMA buffers
1895  */
1896 static void rx_async(struct slgt_info *info)
1897 {
1898         struct tty_struct *tty = info->port.tty;
1899         struct mgsl_icount *icount = &info->icount;
1900         unsigned int start, end;
1901         unsigned char *p;
1902         unsigned char status;
1903         struct slgt_desc *bufs = info->rbufs;
1904         int i, count;
1905         int chars = 0;
1906         int stat;
1907         unsigned char ch;
1908
1909         start = end = info->rbuf_current;
1910
1911         while(desc_complete(bufs[end])) {
1912                 count = desc_count(bufs[end]) - info->rbuf_index;
1913                 p     = bufs[end].buf + info->rbuf_index;
1914
1915                 DBGISR(("%s rx_async count=%d\n", info->device_name, count));
1916                 DBGDATA(info, p, count, "rx");
1917
1918                 for(i=0 ; i < count; i+=2, p+=2) {
1919                         ch = *p;
1920                         icount->rx++;
1921
1922                         stat = 0;
1923
1924                         if ((status = *(p+1) & (BIT1 + BIT0))) {
1925                                 if (status & BIT1)
1926                                         icount->parity++;
1927                                 else if (status & BIT0)
1928                                         icount->frame++;
1929                                 /* discard char if tty control flags say so */
1930                                 if (status & info->ignore_status_mask)
1931                                         continue;
1932                                 if (status & BIT1)
1933                                         stat = TTY_PARITY;
1934                                 else if (status & BIT0)
1935                                         stat = TTY_FRAME;
1936                         }
1937                         if (tty) {
1938                                 tty_insert_flip_char(tty, ch, stat);
1939                                 chars++;
1940                         }
1941                 }
1942
1943                 if (i < count) {
1944                         /* receive buffer not completed */
1945                         info->rbuf_index += i;
1946                         mod_timer(&info->rx_timer, jiffies + 1);
1947                         break;
1948                 }
1949
1950                 info->rbuf_index = 0;
1951                 free_rbufs(info, end, end);
1952
1953                 if (++end == info->rbuf_count)
1954                         end = 0;
1955
1956                 /* if entire list searched then no frame available */
1957                 if (end == start)
1958                         break;
1959         }
1960
1961         if (tty && chars)
1962                 tty_flip_buffer_push(tty);
1963 }
1964
1965 /*
1966  * return next bottom half action to perform
1967  */
1968 static int bh_action(struct slgt_info *info)
1969 {
1970         unsigned long flags;
1971         int rc;
1972
1973         spin_lock_irqsave(&info->lock,flags);
1974
1975         if (info->pending_bh & BH_RECEIVE) {
1976                 info->pending_bh &= ~BH_RECEIVE;
1977                 rc = BH_RECEIVE;
1978         } else if (info->pending_bh & BH_TRANSMIT) {
1979                 info->pending_bh &= ~BH_TRANSMIT;
1980                 rc = BH_TRANSMIT;
1981         } else if (info->pending_bh & BH_STATUS) {
1982                 info->pending_bh &= ~BH_STATUS;
1983                 rc = BH_STATUS;
1984         } else {
1985                 /* Mark BH routine as complete */
1986                 info->bh_running = false;
1987                 info->bh_requested = false;
1988                 rc = 0;
1989         }
1990
1991         spin_unlock_irqrestore(&info->lock,flags);
1992
1993         return rc;
1994 }
1995
1996 /*
1997  * perform bottom half processing
1998  */
1999 static void bh_handler(struct work_struct *work)
2000 {
2001         struct slgt_info *info = container_of(work, struct slgt_info, task);
2002         int action;
2003
2004         if (!info)
2005                 return;
2006         info->bh_running = true;
2007
2008         while((action = bh_action(info))) {
2009                 switch (action) {
2010                 case BH_RECEIVE:
2011                         DBGBH(("%s bh receive\n", info->device_name));
2012                         switch(info->params.mode) {
2013                         case MGSL_MODE_ASYNC:
2014                                 rx_async(info);
2015                                 break;
2016                         case MGSL_MODE_HDLC:
2017                                 while(rx_get_frame(info));
2018                                 break;
2019                         case MGSL_MODE_RAW:
2020                         case MGSL_MODE_MONOSYNC:
2021                         case MGSL_MODE_BISYNC:
2022                                 while(rx_get_buf(info));
2023                                 break;
2024                         }
2025                         /* restart receiver if rx DMA buffers exhausted */
2026                         if (info->rx_restart)
2027                                 rx_start(info);
2028                         break;
2029                 case BH_TRANSMIT:
2030                         bh_transmit(info);
2031                         break;
2032                 case BH_STATUS:
2033                         DBGBH(("%s bh status\n", info->device_name));
2034                         info->ri_chkcount = 0;
2035                         info->dsr_chkcount = 0;
2036                         info->dcd_chkcount = 0;
2037                         info->cts_chkcount = 0;
2038                         break;
2039                 default:
2040                         DBGBH(("%s unknown action\n", info->device_name));
2041                         break;
2042                 }
2043         }
2044         DBGBH(("%s bh_handler exit\n", info->device_name));
2045 }
2046
2047 static void bh_transmit(struct slgt_info *info)
2048 {
2049         struct tty_struct *tty = info->port.tty;
2050
2051         DBGBH(("%s bh_transmit\n", info->device_name));
2052         if (tty)
2053                 tty_wakeup(tty);
2054 }
2055
2056 static void dsr_change(struct slgt_info *info, unsigned short status)
2057 {
2058         if (status & BIT3) {
2059                 info->signals |= SerialSignal_DSR;
2060                 info->input_signal_events.dsr_up++;
2061         } else {
2062                 info->signals &= ~SerialSignal_DSR;
2063                 info->input_signal_events.dsr_down++;
2064         }
2065         DBGISR(("dsr_change %s signals=%04X\n", info->device_name, info->signals));
2066         if ((info->dsr_chkcount)++ == IO_PIN_SHUTDOWN_LIMIT) {
2067                 slgt_irq_off(info, IRQ_DSR);
2068                 return;
2069         }
2070         info->icount.dsr++;
2071         wake_up_interruptible(&info->status_event_wait_q);
2072         wake_up_interruptible(&info->event_wait_q);
2073         info->pending_bh |= BH_STATUS;
2074 }
2075
2076 static void cts_change(struct slgt_info *info, unsigned short status)
2077 {
2078         if (status & BIT2) {
2079                 info->signals |= SerialSignal_CTS;
2080                 info->input_signal_events.cts_up++;
2081         } else {
2082                 info->signals &= ~SerialSignal_CTS;
2083                 info->input_signal_events.cts_down++;
2084         }
2085         DBGISR(("cts_change %s signals=%04X\n", info->device_name, info->signals));
2086         if ((info->cts_chkcount)++ == IO_PIN_SHUTDOWN_LIMIT) {
2087                 slgt_irq_off(info, IRQ_CTS);
2088                 return;
2089         }
2090         info->icount.cts++;
2091         wake_up_interruptible(&info->status_event_wait_q);
2092         wake_up_interruptible(&info->event_wait_q);
2093         info->pending_bh |= BH_STATUS;
2094
2095         if (info->port.flags & ASYNC_CTS_FLOW) {
2096                 if (info->port.tty) {
2097                         if (info->port.tty->hw_stopped) {
2098                                 if (info->signals & SerialSignal_CTS) {
2099                                         info->port.tty->hw_stopped = 0;
2100                                         info->pending_bh |= BH_TRANSMIT;
2101                                         return;
2102                                 }
2103                         } else {
2104                                 if (!(info->signals & SerialSignal_CTS))
2105                                         info->port.tty->hw_stopped = 1;
2106                         }
2107                 }
2108         }
2109 }
2110
2111 static void dcd_change(struct slgt_info *info, unsigned short status)
2112 {
2113         if (status & BIT1) {
2114                 info->signals |= SerialSignal_DCD;
2115                 info->input_signal_events.dcd_up++;
2116         } else {
2117                 info->signals &= ~SerialSignal_DCD;
2118                 info->input_signal_events.dcd_down++;
2119         }
2120         DBGISR(("dcd_change %s signals=%04X\n", info->device_name, info->signals));
2121         if ((info->dcd_chkcount)++ == IO_PIN_SHUTDOWN_LIMIT) {
2122                 slgt_irq_off(info, IRQ_DCD);
2123                 return;
2124         }
2125         info->icount.dcd++;
2126 #if SYNCLINK_GENERIC_HDLC
2127         if (info->netcount) {
2128                 if (info->signals & SerialSignal_DCD)
2129                         netif_carrier_on(info->netdev);
2130                 else
2131                         netif_carrier_off(info->netdev);
2132         }
2133 #endif
2134         wake_up_interruptible(&info->status_event_wait_q);
2135         wake_up_interruptible(&info->event_wait_q);
2136         info->pending_bh |= BH_STATUS;
2137
2138         if (info->port.flags & ASYNC_CHECK_CD) {
2139                 if (info->signals & SerialSignal_DCD)
2140                         wake_up_interruptible(&info->port.open_wait);
2141                 else {
2142                         if (info->port.tty)
2143                                 tty_hangup(info->port.tty);
2144                 }
2145         }
2146 }
2147
2148 static void ri_change(struct slgt_info *info, unsigned short status)
2149 {
2150         if (status & BIT0) {
2151                 info->signals |= SerialSignal_RI;
2152                 info->input_signal_events.ri_up++;
2153         } else {
2154                 info->signals &= ~SerialSignal_RI;
2155                 info->input_signal_events.ri_down++;
2156         }
2157         DBGISR(("ri_change %s signals=%04X\n", info->device_name, info->signals));
2158         if ((info->ri_chkcount)++ == IO_PIN_SHUTDOWN_LIMIT) {
2159                 slgt_irq_off(info, IRQ_RI);
2160                 return;
2161         }
2162         info->icount.rng++;
2163         wake_up_interruptible(&info->status_event_wait_q);
2164         wake_up_interruptible(&info->event_wait_q);
2165         info->pending_bh |= BH_STATUS;
2166 }
2167
2168 static void isr_serial(struct slgt_info *info)
2169 {
2170         unsigned short status = rd_reg16(info, SSR);
2171
2172         DBGISR(("%s isr_serial status=%04X\n", info->device_name, status));
2173
2174         wr_reg16(info, SSR, status); /* clear pending */
2175
2176         info->irq_occurred = true;
2177
2178         if (info->params.mode == MGSL_MODE_ASYNC) {
2179                 if (status & IRQ_TXIDLE) {
2180                         if (info->tx_count)
2181                                 isr_txeom(info, status);
2182                 }
2183                 if ((status & IRQ_RXBREAK) && (status & RXBREAK)) {
2184                         info->icount.brk++;
2185                         /* process break detection if tty control allows */
2186                         if (info->port.tty) {
2187                                 if (!(status & info->ignore_status_mask)) {
2188                                         if (info->read_status_mask & MASK_BREAK) {
2189                                                 tty_insert_flip_char(info->port.tty, 0, TTY_BREAK);
2190                                                 if (info->port.flags & ASYNC_SAK)
2191                                                         do_SAK(info->port.tty);
2192                                         }
2193                                 }
2194                         }
2195                 }
2196         } else {
2197                 if (status & (IRQ_TXIDLE + IRQ_TXUNDER))
2198                         isr_txeom(info, status);
2199
2200                 if (status & IRQ_RXIDLE) {
2201                         if (status & RXIDLE)
2202                                 info->icount.rxidle++;
2203                         else
2204                                 info->icount.exithunt++;
2205                         wake_up_interruptible(&info->event_wait_q);
2206                 }
2207
2208                 if (status & IRQ_RXOVER)
2209                         rx_start(info);
2210         }
2211
2212         if (status & IRQ_DSR)
2213                 dsr_change(info, status);
2214         if (status & IRQ_CTS)
2215                 cts_change(info, status);
2216         if (status & IRQ_DCD)
2217                 dcd_change(info, status);
2218         if (status & IRQ_RI)
2219                 ri_change(info, status);
2220 }
2221
2222 static void isr_rdma(struct slgt_info *info)
2223 {
2224         unsigned int status = rd_reg32(info, RDCSR);
2225
2226         DBGISR(("%s isr_rdma status=%08x\n", info->device_name, status));
2227
2228         /* RDCSR (rx DMA control/status)
2229          *
2230          * 31..07  reserved
2231          * 06      save status byte to DMA buffer
2232          * 05      error
2233          * 04      eol (end of list)
2234          * 03      eob (end of buffer)
2235          * 02      IRQ enable
2236          * 01      reset
2237          * 00      enable
2238          */
2239         wr_reg32(info, RDCSR, status);  /* clear pending */
2240
2241         if (status & (BIT5 + BIT4)) {
2242                 DBGISR(("%s isr_rdma rx_restart=1\n", info->device_name));
2243                 info->rx_restart = true;
2244         }
2245         info->pending_bh |= BH_RECEIVE;
2246 }
2247
2248 static void isr_tdma(struct slgt_info *info)
2249 {
2250         unsigned int status = rd_reg32(info, TDCSR);
2251
2252         DBGISR(("%s isr_tdma status=%08x\n", info->device_name, status));
2253
2254         /* TDCSR (tx DMA control/status)
2255          *
2256          * 31..06  reserved
2257          * 05      error
2258          * 04      eol (end of list)
2259          * 03      eob (end of buffer)
2260          * 02      IRQ enable
2261          * 01      reset
2262          * 00      enable
2263          */
2264         wr_reg32(info, TDCSR, status);  /* clear pending */
2265
2266         if (status & (BIT5 + BIT4 + BIT3)) {
2267                 // another transmit buffer has completed
2268                 // run bottom half to get more send data from user
2269                 info->pending_bh |= BH_TRANSMIT;
2270         }
2271 }
2272
2273 static void isr_txeom(struct slgt_info *info, unsigned short status)
2274 {
2275         DBGISR(("%s txeom status=%04x\n", info->device_name, status));
2276
2277         slgt_irq_off(info, IRQ_TXDATA + IRQ_TXIDLE + IRQ_TXUNDER);
2278         tdma_reset(info);
2279         reset_tbufs(info);
2280         if (status & IRQ_TXUNDER) {
2281                 unsigned short val = rd_reg16(info, TCR);
2282                 wr_reg16(info, TCR, (unsigned short)(val | BIT2)); /* set reset bit */
2283                 wr_reg16(info, TCR, val); /* clear reset bit */
2284         }
2285
2286         if (info->tx_active) {
2287                 if (info->params.mode != MGSL_MODE_ASYNC) {
2288                         if (status & IRQ_TXUNDER)
2289                                 info->icount.txunder++;
2290                         else if (status & IRQ_TXIDLE)
2291                                 info->icount.txok++;
2292                 }
2293
2294                 info->tx_active = false;
2295                 info->tx_count = 0;
2296
2297                 del_timer(&info->tx_timer);
2298
2299                 if (info->params.mode != MGSL_MODE_ASYNC && info->drop_rts_on_tx_done) {
2300                         info->signals &= ~SerialSignal_RTS;
2301                         info->drop_rts_on_tx_done = false;
2302                         set_signals(info);
2303                 }
2304
2305 #if SYNCLINK_GENERIC_HDLC
2306                 if (info->netcount)
2307                         hdlcdev_tx_done(info);
2308                 else
2309 #endif
2310                 {
2311                         if (info->port.tty && (info->port.tty->stopped || info->port.tty->hw_stopped)) {
2312                                 tx_stop(info);
2313                                 return;
2314                         }
2315                         info->pending_bh |= BH_TRANSMIT;
2316                 }
2317         }
2318 }
2319
2320 static void isr_gpio(struct slgt_info *info, unsigned int changed, unsigned int state)
2321 {
2322         struct cond_wait *w, *prev;
2323
2324         /* wake processes waiting for specific transitions */
2325         for (w = info->gpio_wait_q, prev = NULL ; w != NULL ; w = w->next) {
2326                 if (w->data & changed) {
2327                         w->data = state;
2328                         wake_up_interruptible(&w->q);
2329                         if (prev != NULL)
2330                                 prev->next = w->next;
2331                         else
2332                                 info->gpio_wait_q = w->next;
2333                 } else
2334                         prev = w;
2335         }
2336 }
2337
2338 /* interrupt service routine
2339  *
2340  *      irq     interrupt number
2341  *      dev_id  device ID supplied during interrupt registration
2342  */
2343 static irqreturn_t slgt_interrupt(int dummy, void *dev_id)
2344 {
2345         struct slgt_info *info = dev_id;
2346         unsigned int gsr;
2347         unsigned int i;
2348
2349         DBGISR(("slgt_interrupt irq=%d entry\n", info->irq_level));
2350
2351         spin_lock(&info->lock);
2352
2353         while((gsr = rd_reg32(info, GSR) & 0xffffff00)) {
2354                 DBGISR(("%s gsr=%08x\n", info->device_name, gsr));
2355                 info->irq_occurred = true;
2356                 for(i=0; i < info->port_count ; i++) {
2357                         if (info->port_array[i] == NULL)
2358                                 continue;
2359                         if (gsr & (BIT8 << i))
2360                                 isr_serial(info->port_array[i]);
2361                         if (gsr & (BIT16 << (i*2)))
2362                                 isr_rdma(info->port_array[i]);
2363                         if (gsr & (BIT17 << (i*2)))
2364                                 isr_tdma(info->port_array[i]);
2365                 }
2366         }
2367
2368         if (info->gpio_present) {
2369                 unsigned int state;
2370                 unsigned int changed;
2371                 while ((changed = rd_reg32(info, IOSR)) != 0) {
2372                         DBGISR(("%s iosr=%08x\n", info->device_name, changed));
2373                         /* read latched state of GPIO signals */
2374                         state = rd_reg32(info, IOVR);
2375                         /* clear pending GPIO interrupt bits */
2376                         wr_reg32(info, IOSR, changed);
2377                         for (i=0 ; i < info->port_count ; i++) {
2378                                 if (info->port_array[i] != NULL)
2379                                         isr_gpio(info->port_array[i], changed, state);
2380                         }
2381                 }
2382         }
2383
2384         for(i=0; i < info->port_count ; i++) {
2385                 struct slgt_info *port = info->port_array[i];
2386
2387                 if (port && (port->port.count || port->netcount) &&
2388                     port->pending_bh && !port->bh_running &&
2389                     !port->bh_requested) {
2390                         DBGISR(("%s bh queued\n", port->device_name));
2391                         schedule_work(&port->task);
2392                         port->bh_requested = true;
2393                 }
2394         }
2395
2396         spin_unlock(&info->lock);
2397
2398         DBGISR(("slgt_interrupt irq=%d exit\n", info->irq_level));
2399         return IRQ_HANDLED;
2400 }
2401
2402 static int startup(struct slgt_info *info)
2403 {
2404         DBGINFO(("%s startup\n", info->device_name));
2405
2406         if (info->port.flags & ASYNC_INITIALIZED)
2407                 return 0;
2408
2409         if (!info->tx_buf) {
2410                 info->tx_buf = kmalloc(info->max_frame_size, GFP_KERNEL);
2411                 if (!info->tx_buf) {
2412                         DBGERR(("%s can't allocate tx buffer\n", info->device_name));
2413                         return -ENOMEM;
2414                 }
2415         }
2416
2417         info->pending_bh = 0;
2418
2419         memset(&info->icount, 0, sizeof(info->icount));
2420
2421         /* program hardware for current parameters */
2422         change_params(info);
2423
2424         if (info->port.tty)
2425                 clear_bit(TTY_IO_ERROR, &info->port.tty->flags);
2426
2427         info->port.flags |= ASYNC_INITIALIZED;
2428
2429         return 0;
2430 }
2431
2432 /*
2433  *  called by close() and hangup() to shutdown hardware
2434  */
2435 static void shutdown(struct slgt_info *info)
2436 {
2437         unsigned long flags;
2438
2439         if (!(info->port.flags & ASYNC_INITIALIZED))
2440                 return;
2441
2442         DBGINFO(("%s shutdown\n", info->device_name));
2443
2444         /* clear status wait queue because status changes */
2445         /* can't happen after shutting down the hardware */
2446         wake_up_interruptible(&info->status_event_wait_q);
2447         wake_up_interruptible(&info->event_wait_q);
2448
2449         del_timer_sync(&info->tx_timer);
2450         del_timer_sync(&info->rx_timer);
2451
2452         kfree(info->tx_buf);
2453         info->tx_buf = NULL;
2454
2455         spin_lock_irqsave(&info->lock,flags);
2456
2457         tx_stop(info);
2458         rx_stop(info);
2459
2460         slgt_irq_off(info, IRQ_ALL | IRQ_MASTER);
2461
2462         if (!info->port.tty || info->port.tty->termios->c_cflag & HUPCL) {
2463                 info->signals &= ~(SerialSignal_DTR + SerialSignal_RTS);
2464                 set_signals(info);
2465         }
2466
2467         flush_cond_wait(&info->gpio_wait_q);
2468
2469         spin_unlock_irqrestore(&info->lock,flags);
2470
2471         if (info->port.tty)
2472                 set_bit(TTY_IO_ERROR, &info->port.tty->flags);
2473
2474         info->port.flags &= ~ASYNC_INITIALIZED;
2475 }
2476
2477 static void program_hw(struct slgt_info *info)
2478 {
2479         unsigned long flags;
2480
2481         spin_lock_irqsave(&info->lock,flags);
2482
2483         rx_stop(info);
2484         tx_stop(info);
2485
2486         if (info->params.mode != MGSL_MODE_ASYNC ||
2487             info->netcount)
2488                 sync_mode(info);
2489         else
2490                 async_mode(info);
2491
2492         set_signals(info);
2493
2494         info->dcd_chkcount = 0;
2495         info->cts_chkcount = 0;
2496         info->ri_chkcount = 0;
2497         info->dsr_chkcount = 0;
2498
2499         slgt_irq_on(info, IRQ_DCD | IRQ_CTS | IRQ_DSR);
2500         get_signals(info);
2501
2502         if (info->netcount ||
2503             (info->port.tty && info->port.tty->termios->c_cflag & CREAD))
2504                 rx_start(info);
2505
2506         spin_unlock_irqrestore(&info->lock,flags);
2507 }
2508
2509 /*
2510  * reconfigure adapter based on new parameters
2511  */
2512 static void change_params(struct slgt_info *info)
2513 {
2514         unsigned cflag;
2515         int bits_per_char;
2516
2517         if (!info->port.tty || !info->port.tty->termios)
2518                 return;
2519         DBGINFO(("%s change_params\n", info->device_name));
2520
2521         cflag = info->port.tty->termios->c_cflag;
2522
2523         /* if B0 rate (hangup) specified then negate DTR and RTS */
2524         /* otherwise assert DTR and RTS */
2525         if (cflag & CBAUD)
2526                 info->signals |= SerialSignal_RTS + SerialSignal_DTR;
2527         else
2528                 info->signals &= ~(SerialSignal_RTS + SerialSignal_DTR);
2529
2530         /* byte size and parity */
2531
2532         switch (cflag & CSIZE) {
2533         case CS5: info->params.data_bits = 5; break;
2534         case CS6: info->params.data_bits = 6; break;
2535         case CS7: info->params.data_bits = 7; break;
2536         case CS8: info->params.data_bits = 8; break;
2537         default:  info->params.data_bits = 7; break;
2538         }
2539
2540         info->params.stop_bits = (cflag & CSTOPB) ? 2 : 1;
2541
2542         if (cflag & PARENB)
2543                 info->params.parity = (cflag & PARODD) ? ASYNC_PARITY_ODD : ASYNC_PARITY_EVEN;
2544         else
2545                 info->params.parity = ASYNC_PARITY_NONE;
2546
2547         /* calculate number of jiffies to transmit a full
2548          * FIFO (32 bytes) at specified data rate
2549          */
2550         bits_per_char = info->params.data_bits +
2551                         info->params.stop_bits + 1;
2552
2553         info->params.data_rate = tty_get_baud_rate(info->port.tty);
2554
2555         if (info->params.data_rate) {
2556                 info->timeout = (32*HZ*bits_per_char) /
2557                                 info->params.data_rate;
2558         }
2559         info->timeout += HZ/50;         /* Add .02 seconds of slop */
2560
2561         if (cflag & CRTSCTS)
2562                 info->port.flags |= ASYNC_CTS_FLOW;
2563         else
2564                 info->port.flags &= ~ASYNC_CTS_FLOW;
2565
2566         if (cflag & CLOCAL)
2567                 info->port.flags &= ~ASYNC_CHECK_CD;
2568         else
2569                 info->port.flags |= ASYNC_CHECK_CD;
2570
2571         /* process tty input control flags */
2572
2573         info->read_status_mask = IRQ_RXOVER;
2574         if (I_INPCK(info->port.tty))
2575                 info->read_status_mask |= MASK_PARITY | MASK_FRAMING;
2576         if (I_BRKINT(info->port.tty) || I_PARMRK(info->port.tty))
2577                 info->read_status_mask |= MASK_BREAK;
2578         if (I_IGNPAR(info->port.tty))
2579                 info->ignore_status_mask |= MASK_PARITY | MASK_FRAMING;
2580         if (I_IGNBRK(info->port.tty)) {
2581                 info->ignore_status_mask |= MASK_BREAK;
2582                 /* If ignoring parity and break indicators, ignore
2583                  * overruns too.  (For real raw support).
2584                  */
2585                 if (I_IGNPAR(info->port.tty))
2586                         info->ignore_status_mask |= MASK_OVERRUN;
2587         }
2588
2589         program_hw(info);
2590 }
2591
2592 static int get_stats(struct slgt_info *info, struct mgsl_icount __user *user_icount)
2593 {
2594         DBGINFO(("%s get_stats\n",  info->device_name));
2595         if (!user_icount) {
2596                 memset(&info->icount, 0, sizeof(info->icount));
2597         } else {
2598                 if (copy_to_user(user_icount, &info->icount, sizeof(struct mgsl_icount)))
2599                         return -EFAULT;
2600         }
2601         return 0;
2602 }
2603
2604 static int get_params(struct slgt_info *info, MGSL_PARAMS __user *user_params)
2605 {
2606         DBGINFO(("%s get_params\n", info->device_name));
2607         if (copy_to_user(user_params, &info->params, sizeof(MGSL_PARAMS)))
2608                 return -EFAULT;
2609         return 0;
2610 }
2611
2612 static int set_params(struct slgt_info *info, MGSL_PARAMS __user *new_params)
2613 {
2614         unsigned long flags;
2615         MGSL_PARAMS tmp_params;
2616
2617         DBGINFO(("%s set_params\n", info->device_name));
2618         if (copy_from_user(&tmp_params, new_params, sizeof(MGSL_PARAMS)))
2619                 return -EFAULT;
2620
2621         spin_lock_irqsave(&info->lock, flags);
2622         memcpy(&info->params, &tmp_params, sizeof(MGSL_PARAMS));
2623         spin_unlock_irqrestore(&info->lock, flags);
2624
2625         change_params(info);
2626
2627         return 0;
2628 }
2629
2630 static int get_txidle(struct slgt_info *info, int __user *idle_mode)
2631 {
2632         DBGINFO(("%s get_txidle=%d\n", info->device_name, info->idle_mode));
2633         if (put_user(info->idle_mode, idle_mode))
2634                 return -EFAULT;
2635         return 0;
2636 }
2637
2638 static int set_txidle(struct slgt_info *info, int idle_mode)
2639 {
2640         unsigned long flags;
2641         DBGINFO(("%s set_txidle(%d)\n", info->device_name, idle_mode));
2642         spin_lock_irqsave(&info->lock,flags);
2643         info->idle_mode = idle_mode;
2644         if (info->params.mode != MGSL_MODE_ASYNC)
2645                 tx_set_idle(info);
2646         spin_unlock_irqrestore(&info->lock,flags);
2647         return 0;
2648 }
2649
2650 static int tx_enable(struct slgt_info *info, int enable)
2651 {
2652         unsigned long flags;
2653         DBGINFO(("%s tx_enable(%d)\n", info->device_name, enable));
2654         spin_lock_irqsave(&info->lock,flags);
2655         if (enable) {
2656                 if (!info->tx_enabled)
2657                         tx_start(info);
2658         } else {
2659                 if (info->tx_enabled)
2660                         tx_stop(info);
2661         }
2662         spin_unlock_irqrestore(&info->lock,flags);
2663         return 0;
2664 }
2665
2666 /*
2667  * abort transmit HDLC frame
2668  */
2669 static int tx_abort(struct slgt_info *info)
2670 {
2671         unsigned long flags;
2672         DBGINFO(("%s tx_abort\n", info->device_name));
2673         spin_lock_irqsave(&info->lock,flags);
2674         tdma_reset(info);
2675         spin_unlock_irqrestore(&info->lock,flags);
2676         return 0;
2677 }
2678
2679 static int rx_enable(struct slgt_info *info, int enable)
2680 {
2681         unsigned long flags;
2682         DBGINFO(("%s rx_enable(%d)\n", info->device_name, enable));
2683         spin_lock_irqsave(&info->lock,flags);
2684         if (enable) {
2685                 if (!info->rx_enabled)
2686                         rx_start(info);
2687                 else if (enable == 2) {
2688                         /* force hunt mode (write 1 to RCR[3]) */
2689                         wr_reg16(info, RCR, rd_reg16(info, RCR) | BIT3);
2690                 }
2691         } else {
2692                 if (info->rx_enabled)
2693                         rx_stop(info);
2694         }
2695         spin_unlock_irqrestore(&info->lock,flags);
2696         return 0;
2697 }
2698
2699 /*
2700  *  wait for specified event to occur
2701  */
2702 static int wait_mgsl_event(struct slgt_info *info, int __user *mask_ptr)
2703 {
2704         unsigned long flags;
2705         int s;
2706         int rc=0;
2707         struct mgsl_icount cprev, cnow;
2708         int events;
2709         int mask;
2710         struct  _input_signal_events oldsigs, newsigs;
2711         DECLARE_WAITQUEUE(wait, current);
2712
2713         if (get_user(mask, mask_ptr))
2714                 return -EFAULT;
2715
2716         DBGINFO(("%s wait_mgsl_event(%d)\n", info->device_name, mask));
2717
2718         spin_lock_irqsave(&info->lock,flags);
2719
2720         /* return immediately if state matches requested events */
2721         get_signals(info);
2722         s = info->signals;
2723
2724         events = mask &
2725                 ( ((s & SerialSignal_DSR) ? MgslEvent_DsrActive:MgslEvent_DsrInactive) +
2726                   ((s & SerialSignal_DCD) ? MgslEvent_DcdActive:MgslEvent_DcdInactive) +
2727                   ((s & SerialSignal_CTS) ? MgslEvent_CtsActive:MgslEvent_CtsInactive) +
2728                   ((s & SerialSignal_RI)  ? MgslEvent_RiActive :MgslEvent_RiInactive) );
2729         if (events) {
2730                 spin_unlock_irqrestore(&info->lock,flags);
2731                 goto exit;
2732         }
2733
2734         /* save current irq counts */
2735         cprev = info->icount;
2736         oldsigs = info->input_signal_events;
2737
2738         /* enable hunt and idle irqs if needed */
2739         if (mask & (MgslEvent_ExitHuntMode+MgslEvent_IdleReceived)) {
2740                 unsigned short val = rd_reg16(info, SCR);
2741                 if (!(val & IRQ_RXIDLE))
2742                         wr_reg16(info, SCR, (unsigned short)(val | IRQ_RXIDLE));
2743         }
2744
2745         set_current_state(TASK_INTERRUPTIBLE);
2746         add_wait_queue(&info->event_wait_q, &wait);
2747
2748         spin_unlock_irqrestore(&info->lock,flags);
2749
2750         for(;;) {
2751                 schedule();
2752                 if (signal_pending(current)) {
2753                         rc = -ERESTARTSYS;
2754                         break;
2755                 }
2756
2757                 /* get current irq counts */
2758                 spin_lock_irqsave(&info->lock,flags);
2759                 cnow = info->icount;
2760                 newsigs = info->input_signal_events;
2761                 set_current_state(TASK_INTERRUPTIBLE);
2762                 spin_unlock_irqrestore(&info->lock,flags);
2763
2764                 /* if no change, wait aborted for some reason */
2765                 if (newsigs.dsr_up   == oldsigs.dsr_up   &&
2766                     newsigs.dsr_down == oldsigs.dsr_down &&
2767                     newsigs.dcd_up   == oldsigs.dcd_up   &&
2768                     newsigs.dcd_down == oldsigs.dcd_down &&
2769                     newsigs.cts_up   == oldsigs.cts_up   &&
2770                     newsigs.cts_down == oldsigs.cts_down &&
2771                     newsigs.ri_up    == oldsigs.ri_up    &&
2772                     newsigs.ri_down  == oldsigs.ri_down  &&
2773                     cnow.exithunt    == cprev.exithunt   &&
2774                     cnow.rxidle      == cprev.rxidle) {
2775                         rc = -EIO;
2776                         break;
2777                 }
2778
2779                 events = mask &
2780                         ( (newsigs.dsr_up   != oldsigs.dsr_up   ? MgslEvent_DsrActive:0)   +
2781                           (newsigs.dsr_down != oldsigs.dsr_down ? MgslEvent_DsrInactive:0) +
2782                           (newsigs.dcd_up   != oldsigs.dcd_up   ? MgslEvent_DcdActive:0)   +
2783                           (newsigs.dcd_down != oldsigs.dcd_down ? MgslEvent_DcdInactive:0) +
2784                           (newsigs.cts_up   != oldsigs.cts_up   ? MgslEvent_CtsActive:0)   +
2785                           (newsigs.cts_down != oldsigs.cts_down ? MgslEvent_CtsInactive:0) +
2786                           (newsigs.ri_up    != oldsigs.ri_up    ? MgslEvent_RiActive:0)    +
2787                           (newsigs.ri_down  != oldsigs.ri_down  ? MgslEvent_RiInactive:0)  +
2788                           (cnow.exithunt    != cprev.exithunt   ? MgslEvent_ExitHuntMode:0) +
2789                           (cnow.rxidle      != cprev.rxidle     ? MgslEvent_IdleReceived:0) );
2790                 if (events)
2791                         break;
2792
2793                 cprev = cnow;
2794                 oldsigs = newsigs;
2795         }
2796
2797         remove_wait_queue(&info->event_wait_q, &wait);
2798         set_current_state(TASK_RUNNING);
2799
2800
2801         if (mask & (MgslEvent_ExitHuntMode + MgslEvent_IdleReceived)) {
2802                 spin_lock_irqsave(&info->lock,flags);
2803                 if (!waitqueue_active(&info->event_wait_q)) {
2804                         /* disable enable exit hunt mode/idle rcvd IRQs */
2805                         wr_reg16(info, SCR,
2806                                 (unsigned short)(rd_reg16(info, SCR) & ~IRQ_RXIDLE));
2807                 }
2808                 spin_unlock_irqrestore(&info->lock,flags);
2809         }
2810 exit:
2811         if (rc == 0)
2812                 rc = put_user(events, mask_ptr);
2813         return rc;
2814 }
2815
2816 static int get_interface(struct slgt_info *info, int __user *if_mode)
2817 {
2818         DBGINFO(("%s get_interface=%x\n", info->device_name, info->if_mode));
2819         if (put_user(info->if_mode, if_mode))
2820                 return -EFAULT;
2821         return 0;
2822 }
2823
2824 static int set_interface(struct slgt_info *info, int if_mode)
2825 {
2826         unsigned long flags;
2827         unsigned short val;
2828
2829         DBGINFO(("%s set_interface=%x)\n", info->device_name, if_mode));
2830         spin_lock_irqsave(&info->lock,flags);
2831         info->if_mode = if_mode;
2832
2833         msc_set_vcr(info);
2834
2835         /* TCR (tx control) 07  1=RTS driver control */
2836         val = rd_reg16(info, TCR);
2837         if (info->if_mode & MGSL_INTERFACE_RTS_EN)
2838                 val |= BIT7;
2839         else
2840                 val &= ~BIT7;
2841         wr_reg16(info, TCR, val);
2842
2843         spin_unlock_irqrestore(&info->lock,flags);
2844         return 0;
2845 }
2846
2847 /*
2848  * set general purpose IO pin state and direction
2849  *
2850  * user_gpio fields:
2851  * state   each bit indicates a pin state
2852  * smask   set bit indicates pin state to set
2853  * dir     each bit indicates a pin direction (0=input, 1=output)
2854  * dmask   set bit indicates pin direction to set
2855  */
2856 static int set_gpio(struct slgt_info *info, struct gpio_desc __user *user_gpio)
2857 {
2858         unsigned long flags;
2859         struct gpio_desc gpio;
2860         __u32 data;
2861
2862         if (!info->gpio_present)
2863                 return -EINVAL;
2864         if (copy_from_user(&gpio, user_gpio, sizeof(gpio)))
2865                 return -EFAULT;
2866         DBGINFO(("%s set_gpio state=%08x smask=%08x dir=%08x dmask=%08x\n",
2867                  info->device_name, gpio.state, gpio.smask,
2868                  gpio.dir, gpio.dmask));
2869
2870         spin_lock_irqsave(&info->lock,flags);
2871         if (gpio.dmask) {
2872                 data = rd_reg32(info, IODR);
2873                 data |= gpio.dmask & gpio.dir;
2874                 data &= ~(gpio.dmask & ~gpio.dir);
2875                 wr_reg32(info, IODR, data);
2876         }
2877         if (gpio.smask) {
2878                 data = rd_reg32(info, IOVR);
2879                 data |= gpio.smask & gpio.state;
2880                 data &= ~(gpio.smask & ~gpio.state);
2881                 wr_reg32(info, IOVR, data);
2882         }
2883         spin_unlock_irqrestore(&info->lock,flags);
2884
2885         return 0;
2886 }
2887
2888 /*
2889  * get general purpose IO pin state and direction
2890  */
2891 static int get_gpio(struct slgt_info *info, struct gpio_desc __user *user_gpio)
2892 {
2893         struct gpio_desc gpio;
2894         if (!info->gpio_present)
2895                 return -EINVAL;
2896         gpio.state = rd_reg32(info, IOVR);
2897         gpio.smask = 0xffffffff;
2898         gpio.dir   = rd_reg32(info, IODR);
2899         gpio.dmask = 0xffffffff;
2900         if (copy_to_user(user_gpio, &gpio, sizeof(gpio)))
2901                 return -EFAULT;
2902         DBGINFO(("%s get_gpio state=%08x dir=%08x\n",
2903                  info->device_name, gpio.state, gpio.dir));
2904         return 0;
2905 }
2906
2907 /*
2908  * conditional wait facility
2909  */
2910 static void init_cond_wait(struct cond_wait *w, unsigned int data)
2911 {
2912         init_waitqueue_head(&w->q);
2913         init_waitqueue_entry(&w->wait, current);
2914         w->data = data;
2915 }
2916
2917 static void add_cond_wait(struct cond_wait **head, struct cond_wait *w)
2918 {
2919         set_current_state(TASK_INTERRUPTIBLE);
2920         add_wait_queue(&w->q, &w->wait);
2921         w->next = *head;
2922         *head = w;
2923 }
2924
2925 static void remove_cond_wait(struct cond_wait **head, struct cond_wait *cw)
2926 {
2927         struct cond_wait *w, *prev;
2928         remove_wait_queue(&cw->q, &cw->wait);
2929         set_current_state(TASK_RUNNING);
2930         for (w = *head, prev = NULL ; w != NULL ; prev = w, w = w->next) {
2931                 if (w == cw) {
2932                         if (prev != NULL)
2933                                 prev->next = w->next;
2934                         else
2935                                 *head = w->next;
2936                         break;
2937                 }
2938         }
2939 }
2940
2941 static void flush_cond_wait(struct cond_wait **head)
2942 {
2943         while (*head != NULL) {
2944                 wake_up_interruptible(&(*head)->q);
2945                 *head = (*head)->next;
2946         }
2947 }
2948
2949 /*
2950  * wait for general purpose I/O pin(s) to enter specified state
2951  *
2952  * user_gpio fields:
2953  * state - bit indicates target pin state
2954  * smask - set bit indicates watched pin
2955  *
2956  * The wait ends when at least one watched pin enters the specified
2957  * state. When 0 (no error) is returned, user_gpio->state is set to the
2958  * state of all GPIO pins when the wait ends.
2959  *
2960  * Note: Each pin may be a dedicated input, dedicated output, or
2961  * configurable input/output. The number and configuration of pins
2962  * varies with the specific adapter model. Only input pins (dedicated
2963  * or configured) can be monitored with this function.
2964  */
2965 static int wait_gpio(struct slgt_info *info, struct gpio_desc __user *user_gpio)
2966 {
2967         unsigned long flags;
2968         int rc = 0;
2969         struct gpio_desc gpio;
2970         struct cond_wait wait;
2971         u32 state;
2972
2973         if (!info->gpio_present)
2974                 return -EINVAL;
2975         if (copy_from_user(&gpio, user_gpio, sizeof(gpio)))
2976                 return -EFAULT;
2977         DBGINFO(("%s wait_gpio() state=%08x smask=%08x\n",
2978                  info->device_name, gpio.state, gpio.smask));
2979         /* ignore output pins identified by set IODR bit */
2980         if ((gpio.smask &= ~rd_reg32(info, IODR)) == 0)
2981                 return -EINVAL;
2982         init_cond_wait(&wait, gpio.smask);
2983
2984         spin_lock_irqsave(&info->lock, flags);
2985         /* enable interrupts for watched pins */
2986         wr_reg32(info, IOER, rd_reg32(info, IOER) | gpio.smask);
2987         /* get current pin states */
2988         state = rd_reg32(info, IOVR);
2989
2990         if (gpio.smask & ~(state ^ gpio.state)) {
2991                 /* already in target state */
2992                 gpio.state = state;
2993         } else {
2994                 /* wait for target state */
2995                 add_cond_wait(&info->gpio_wait_q, &wait);
2996                 spin_unlock_irqrestore(&info->lock, flags);
2997                 schedule();
2998                 if (signal_pending(current))
2999                         rc = -ERESTARTSYS;
3000                 else
3001                         gpio.state = wait.data;
3002                 spin_lock_irqsave(&info->lock, flags);
3003                 remove_cond_wait(&info->gpio_wait_q, &wait);
3004         }
3005
3006         /* disable all GPIO interrupts if no waiting processes */
3007         if (info->gpio_wait_q == NULL)
3008                 wr_reg32(info, IOER, 0);
3009         spin_unlock_irqrestore(&info->lock,flags);
3010
3011         if ((rc == 0) && copy_to_user(user_gpio, &gpio, sizeof(gpio)))
3012                 rc = -EFAULT;
3013         return rc;
3014 }
3015
3016 static int modem_input_wait(struct slgt_info *info,int arg)
3017 {
3018         unsigned long flags;
3019         int rc;
3020         struct mgsl_icount cprev, cnow;
3021         DECLARE_WAITQUEUE(wait, current);
3022
3023         /* save current irq counts */
3024         spin_lock_irqsave(&info->lock,flags);
3025         cprev = info->icount;
3026         add_wait_queue(&info->status_event_wait_q, &wait);
3027         set_current_state(TASK_INTERRUPTIBLE);
3028         spin_unlock_irqrestore(&info->lock,flags);
3029
3030         for(;;) {
3031                 schedule();
3032                 if (signal_pending(current)) {
3033                         rc = -ERESTARTSYS;
3034                         break;
3035                 }
3036
3037                 /* get new irq counts */
3038                 spin_lock_irqsave(&info->lock,flags);
3039                 cnow = info->icount;
3040                 set_current_state(TASK_INTERRUPTIBLE);
3041                 spin_unlock_irqrestore(&info->lock,flags);
3042
3043                 /* if no change, wait aborted for some reason */
3044                 if (cnow.rng == cprev.rng && cnow.dsr == cprev.dsr &&
3045                     cnow.dcd == cprev.dcd && cnow.cts == cprev.cts) {
3046                         rc = -EIO;
3047                         break;
3048                 }
3049
3050                 /* check for change in caller specified modem input */
3051                 if ((arg & TIOCM_RNG && cnow.rng != cprev.rng) ||
3052                     (arg & TIOCM_DSR && cnow.dsr != cprev.dsr) ||
3053                     (arg & TIOCM_CD  && cnow.dcd != cprev.dcd) ||
3054                     (arg & TIOCM_CTS && cnow.cts != cprev.cts)) {
3055                         rc = 0;
3056                         break;
3057                 }
3058
3059                 cprev = cnow;
3060         }
3061         remove_wait_queue(&info->status_event_wait_q, &wait);
3062         set_current_state(TASK_RUNNING);
3063         return rc;
3064 }
3065
3066 /*
3067  *  return state of serial control and status signals
3068  */
3069 static int tiocmget(struct tty_struct *tty, struct file *file)
3070 {
3071         struct slgt_info *info = tty->driver_data;
3072         unsigned int result;
3073         unsigned long flags;
3074
3075         spin_lock_irqsave(&info->lock,flags);
3076         get_signals(info);
3077         spin_unlock_irqrestore(&info->lock,flags);
3078
3079         result = ((info->signals & SerialSignal_RTS) ? TIOCM_RTS:0) +
3080                 ((info->signals & SerialSignal_DTR) ? TIOCM_DTR:0) +
3081                 ((info->signals & SerialSignal_DCD) ? TIOCM_CAR:0) +
3082                 ((info->signals & SerialSignal_RI)  ? TIOCM_RNG:0) +
3083                 ((info->signals & SerialSignal_DSR) ? TIOCM_DSR:0) +
3084                 ((info->signals & SerialSignal_CTS) ? TIOCM_CTS:0);
3085
3086         DBGINFO(("%s tiocmget value=%08X\n", info->device_name, result));
3087         return result;
3088 }
3089
3090 /*
3091  * set modem control signals (DTR/RTS)
3092  *
3093  *      cmd     signal command: TIOCMBIS = set bit TIOCMBIC = clear bit
3094  *              TIOCMSET = set/clear signal values
3095  *      value   bit mask for command
3096  */
3097 static int tiocmset(struct tty_struct *tty, struct file *file,
3098                     unsigned int set, unsigned int clear)
3099 {
3100         struct slgt_info *info = tty->driver_data;
3101         unsigned long flags;
3102
3103         DBGINFO(("%s tiocmset(%x,%x)\n", info->device_name, set, clear));
3104
3105         if (set & TIOCM_RTS)
3106                 info->signals |= SerialSignal_RTS;
3107         if (set & TIOCM_DTR)
3108                 info->signals |= SerialSignal_DTR;
3109         if (clear & TIOCM_RTS)
3110                 info->signals &= ~SerialSignal_RTS;
3111         if (clear & TIOCM_DTR)
3112                 info->signals &= ~SerialSignal_DTR;
3113
3114         spin_lock_irqsave(&info->lock,flags);
3115         set_signals(info);
3116         spin_unlock_irqrestore(&info->lock,flags);
3117         return 0;
3118 }
3119
3120 /*
3121  *  block current process until the device is ready to open
3122  */
3123 static int block_til_ready(struct tty_struct *tty, struct file *filp,
3124                            struct slgt_info *info)
3125 {
3126         DECLARE_WAITQUEUE(wait, current);
3127         int             retval;
3128         bool            do_clocal = false;
3129         bool            extra_count = false;
3130         unsigned long   flags;
3131
3132         DBGINFO(("%s block_til_ready\n", tty->driver->name));
3133
3134         if (filp->f_flags & O_NONBLOCK || tty->flags & (1 << TTY_IO_ERROR)){
3135                 /* nonblock mode is set or port is not enabled */
3136                 info->port.flags |= ASYNC_NORMAL_ACTIVE;
3137                 return 0;
3138         }
3139
3140         if (tty->termios->c_cflag & CLOCAL)
3141                 do_clocal = true;
3142
3143         /* Wait for carrier detect and the line to become
3144          * free (i.e., not in use by the callout).  While we are in
3145          * this loop, info->port.count is dropped by one, so that
3146          * close() knows when to free things.  We restore it upon
3147          * exit, either normal or abnormal.
3148          */
3149
3150         retval = 0;
3151         add_wait_queue(&info->port.open_wait, &wait);
3152
3153         spin_lock_irqsave(&info->lock, flags);
3154         if (!tty_hung_up_p(filp)) {
3155                 extra_count = true;
3156                 info->port.count--;
3157         }
3158         spin_unlock_irqrestore(&info->lock, flags);
3159         info->port.blocked_open++;
3160
3161         while (1) {
3162                 if ((tty->termios->c_cflag & CBAUD)) {
3163                         spin_lock_irqsave(&info->lock,flags);
3164                         info->signals |= SerialSignal_RTS + SerialSignal_DTR;
3165                         set_signals(info);
3166                         spin_unlock_irqrestore(&info->lock,flags);
3167                 }
3168
3169                 set_current_state(TASK_INTERRUPTIBLE);
3170
3171                 if (tty_hung_up_p(filp) || !(info->port.flags & ASYNC_INITIALIZED)){
3172                         retval = (info->port.flags & ASYNC_HUP_NOTIFY) ?
3173                                         -EAGAIN : -ERESTARTSYS;
3174                         break;
3175                 }
3176
3177                 spin_lock_irqsave(&info->lock,flags);
3178                 get_signals(info);
3179                 spin_unlock_irqrestore(&info->lock,flags);
3180
3181                 if (!(info->port.flags & ASYNC_CLOSING) &&
3182                     (do_clocal || (info->signals & SerialSignal_DCD)) ) {
3183                         break;
3184                 }
3185
3186                 if (signal_pending(current)) {
3187                         retval = -ERESTARTSYS;
3188                         break;
3189                 }
3190
3191                 DBGINFO(("%s block_til_ready wait\n", tty->driver->name));
3192                 schedule();
3193         }
3194
3195         set_current_state(TASK_RUNNING);
3196         remove_wait_queue(&info->port.open_wait, &wait);
3197
3198         if (extra_count)
3199                 info->port.count++;
3200         info->port.blocked_open--;
3201
3202         if (!retval)
3203                 info->port.flags |= ASYNC_NORMAL_ACTIVE;
3204
3205         DBGINFO(("%s block_til_ready ready, rc=%d\n", tty->driver->name, retval));
3206         return retval;
3207 }
3208
3209 static int alloc_tmp_rbuf(struct slgt_info *info)
3210 {
3211         info->tmp_rbuf = kmalloc(info->max_frame_size + 5, GFP_KERNEL);
3212         if (info->tmp_rbuf == NULL)
3213                 return -ENOMEM;
3214         return 0;
3215 }
3216
3217 static void free_tmp_rbuf(struct slgt_info *info)
3218 {
3219         kfree(info->tmp_rbuf);
3220         info->tmp_rbuf = NULL;
3221 }
3222
3223 /*
3224  * allocate DMA descriptor lists.
3225  */
3226 static int alloc_desc(struct slgt_info *info)
3227 {
3228         unsigned int i;
3229         unsigned int pbufs;
3230
3231         /* allocate memory to hold descriptor lists */
3232         info->bufs = pci_alloc_consistent(info->pdev, DESC_LIST_SIZE, &info->bufs_dma_addr);
3233         if (info->bufs == NULL)
3234                 return -ENOMEM;
3235
3236         memset(info->bufs, 0, DESC_LIST_SIZE);
3237
3238         info->rbufs = (struct slgt_desc*)info->bufs;
3239         info->tbufs = ((struct slgt_desc*)info->bufs) + info->rbuf_count;
3240
3241         pbufs = (unsigned int)info->bufs_dma_addr;
3242
3243         /*
3244          * Build circular lists of descriptors
3245          */
3246
3247         for (i=0; i < info->rbuf_count; i++) {
3248                 /* physical address of this descriptor */
3249                 info->rbufs[i].pdesc = pbufs + (i * sizeof(struct slgt_desc));
3250
3251                 /* physical address of next descriptor */
3252                 if (i == info->rbuf_count - 1)
3253                         info->rbufs[i].next = cpu_to_le32(pbufs);
3254                 else
3255                         info->rbufs[i].next = cpu_to_le32(pbufs + ((i+1) * sizeof(struct slgt_desc)));
3256                 set_desc_count(info->rbufs[i], DMABUFSIZE);
3257         }
3258
3259         for (i=0; i < info->tbuf_count; i++) {
3260                 /* physical address of this descriptor */
3261                 info->tbufs[i].pdesc = pbufs + ((info->rbuf_count + i) * sizeof(struct slgt_desc));
3262
3263                 /* physical address of next descriptor */
3264                 if (i == info->tbuf_count - 1)
3265                         info->tbufs[i].next = cpu_to_le32(pbufs + info->rbuf_count * sizeof(struct slgt_desc));
3266                 else
3267                         info->tbufs[i].next = cpu_to_le32(pbufs + ((info->rbuf_count + i + 1) * sizeof(struct slgt_desc)));
3268         }
3269
3270         return 0;
3271 }
3272
3273 static void free_desc(struct slgt_info *info)
3274 {
3275         if (info->bufs != NULL) {
3276                 pci_free_consistent(info->pdev, DESC_LIST_SIZE, info->bufs, info->bufs_dma_addr);
3277                 info->bufs  = NULL;
3278                 info->rbufs = NULL;
3279                 info->tbufs = NULL;
3280         }
3281 }
3282
3283 static int alloc_bufs(struct slgt_info *info, struct slgt_desc *bufs, int count)
3284 {
3285         int i;
3286         for (i=0; i < count; i++) {
3287                 if ((bufs[i].buf = pci_alloc_consistent(info->pdev, DMABUFSIZE, &bufs[i].buf_dma_addr)) == NULL)
3288                         return -ENOMEM;
3289                 bufs[i].pbuf  = cpu_to_le32((unsigned int)bufs[i].buf_dma_addr);
3290         }
3291         return 0;
3292 }
3293
3294 static void free_bufs(struct slgt_info *info, struct slgt_desc *bufs, int count)
3295 {
3296         int i;
3297         for (i=0; i < count; i++) {
3298                 if (bufs[i].buf == NULL)
3299                         continue;
3300                 pci_free_consistent(info->pdev, DMABUFSIZE, bufs[i].buf, bufs[i].buf_dma_addr);
3301                 bufs[i].buf = NULL;
3302         }
3303 }
3304
3305 static int alloc_dma_bufs(struct slgt_info *info)
3306 {
3307         info->rbuf_count = 32;
3308         info->tbuf_count = 32;
3309
3310         if (alloc_desc(info) < 0 ||
3311             alloc_bufs(info, info->rbufs, info->rbuf_count) < 0 ||
3312             alloc_bufs(info, info->tbufs, info->tbuf_count) < 0 ||
3313             alloc_tmp_rbuf(info) < 0) {
3314                 DBGERR(("%s DMA buffer alloc fail\n", info->device_name));
3315                 return -ENOMEM;
3316         }
3317         reset_rbufs(info);
3318         return 0;
3319 }
3320
3321 static void free_dma_bufs(struct slgt_info *info)
3322 {
3323         if (info->bufs) {
3324                 free_bufs(info, info->rbufs, info->rbuf_count);
3325                 free_bufs(info, info->tbufs, info->tbuf_count);
3326                 free_desc(info);
3327         }
3328         free_tmp_rbuf(info);
3329 }
3330
3331 static int claim_resources(struct slgt_info *info)
3332 {
3333         if (request_mem_region(info->phys_reg_addr, SLGT_REG_SIZE, "synclink_gt") == NULL) {
3334                 DBGERR(("%s reg addr conflict, addr=%08X\n",
3335                         info->device_name, info->phys_reg_addr));
3336                 info->init_error = DiagStatus_AddressConflict;
3337                 goto errout;
3338         }
3339         else
3340                 info->reg_addr_requested = true;
3341
3342         info->reg_addr = ioremap_nocache(info->phys_reg_addr, SLGT_REG_SIZE);
3343         if (!info->reg_addr) {
3344                 DBGERR(("%s cant map device registers, addr=%08X\n",
3345                         info->device_name, info->phys_reg_addr));
3346                 info->init_error = DiagStatus_CantAssignPciResources;
3347                 goto errout;
3348         }
3349         return 0;
3350
3351 errout:
3352         release_resources(info);
3353         return -ENODEV;
3354 }
3355
3356 static void release_resources(struct slgt_info *info)
3357 {
3358         if (info->irq_requested) {
3359                 free_irq(info->irq_level, info);
3360                 info->irq_requested = false;
3361         }
3362
3363         if (info->reg_addr_requested) {
3364                 release_mem_region(info->phys_reg_addr, SLGT_REG_SIZE);
3365                 info->reg_addr_requested = false;
3366         }
3367
3368         if (info->reg_addr) {
3369                 iounmap(info->reg_addr);
3370                 info->reg_addr = NULL;
3371         }
3372 }
3373
3374 /* Add the specified device instance data structure to the
3375  * global linked list of devices and increment the device count.
3376  */
3377 static void add_device(struct slgt_info *info)
3378 {
3379         char *devstr;
3380
3381         info->next_device = NULL;
3382         info->line = slgt_device_count;
3383         sprintf(info->device_name, "%s%d", tty_dev_prefix, info->line);
3384
3385         if (info->line < MAX_DEVICES) {
3386                 if (maxframe[info->line])
3387                         info->max_frame_size = maxframe[info->line];
3388                 info->dosyncppp = dosyncppp[info->line];
3389         }
3390
3391         slgt_device_count++;
3392
3393         if (!slgt_device_list)
3394                 slgt_device_list = info;
3395         else {
3396                 struct slgt_info *current_dev = slgt_device_list;
3397                 while(current_dev->next_device)
3398                         current_dev = current_dev->next_device;
3399                 current_dev->next_device = info;
3400         }
3401
3402         if (info->max_frame_size < 4096)
3403                 info->max_frame_size = 4096;
3404         else if (info->max_frame_size > 65535)
3405                 info->max_frame_size = 65535;
3406
3407         switch(info->pdev->device) {
3408         case SYNCLINK_GT_DEVICE_ID:
3409                 devstr = "GT";
3410                 break;
3411         case SYNCLINK_GT2_DEVICE_ID:
3412                 devstr = "GT2";
3413                 break;
3414         case SYNCLINK_GT4_DEVICE_ID:
3415                 devstr = "GT4";
3416                 break;
3417         case SYNCLINK_AC_DEVICE_ID:
3418                 devstr = "AC";
3419                 info->params.mode = MGSL_MODE_ASYNC;
3420                 break;
3421         default:
3422                 devstr = "(unknown model)";
3423         }
3424         printk("SyncLink %s %s IO=%08x IRQ=%d MaxFrameSize=%u\n",
3425                 devstr, info->device_name, info->phys_reg_addr,
3426                 info->irq_level, info->max_frame_size);
3427
3428 #if SYNCLINK_GENERIC_HDLC
3429         hdlcdev_init(info);
3430 #endif
3431 }
3432
3433 /*
3434  *  allocate device instance structure, return NULL on failure
3435  */
3436 static struct slgt_info *alloc_dev(int adapter_num, int port_num, struct pci_dev *pdev)
3437 {
3438         struct slgt_info *info;
3439
3440         info = kzalloc(sizeof(struct slgt_info), GFP_KERNEL);
3441
3442         if (!info) {
3443                 DBGERR(("%s device alloc failed adapter=%d port=%d\n",
3444                         driver_name, adapter_num, port_num));
3445         } else {
3446                 tty_port_init(&info->port);
3447                 info->magic = MGSL_MAGIC;
3448                 INIT_WORK(&info->task, bh_handler);
3449                 info->max_frame_size = 4096;
3450                 info->raw_rx_size = DMABUFSIZE;
3451                 info->port.close_delay = 5*HZ/10;
3452                 info->port.closing_wait = 30*HZ;
3453                 init_waitqueue_head(&info->status_event_wait_q);
3454                 init_waitqueue_head(&info->event_wait_q);
3455                 spin_lock_init(&info->netlock);
3456                 memcpy(&info->params,&default_params,sizeof(MGSL_PARAMS));
3457                 info->idle_mode = HDLC_TXIDLE_FLAGS;
3458                 info->adapter_num = adapter_num;
3459                 info->port_num = port_num;
3460
3461                 setup_timer(&info->tx_timer, tx_timeout, (unsigned long)info);
3462                 setup_timer(&info->rx_timer, rx_timeout, (unsigned long)info);
3463
3464                 /* Copy configuration info to device instance data */
3465                 info->pdev = pdev;
3466                 info->irq_level = pdev->irq;
3467                 info->phys_reg_addr = pci_resource_start(pdev,0);
3468
3469                 info->bus_type = MGSL_BUS_TYPE_PCI;
3470                 info->irq_flags = IRQF_SHARED;
3471
3472                 info->init_error = -1; /* assume error, set to 0 on successful init */
3473         }
3474
3475         return info;
3476 }
3477
3478 static void device_init(int adapter_num, struct pci_dev *pdev)
3479 {
3480         struct slgt_info *port_array[SLGT_MAX_PORTS];
3481         int i;
3482         int port_count = 1;
3483
3484         if (pdev->device == SYNCLINK_GT2_DEVICE_ID)
3485                 port_count = 2;
3486         else if (pdev->device == SYNCLINK_GT4_DEVICE_ID)
3487                 port_count = 4;
3488
3489         /* allocate device instances for all ports */
3490         for (i=0; i < port_count; ++i) {
3491                 port_array[i] = alloc_dev(adapter_num, i, pdev);
3492                 if (port_array[i] == NULL) {
3493                         for (--i; i >= 0; --i)
3494                                 kfree(port_array[i]);
3495                         return;
3496                 }
3497         }
3498
3499         /* give copy of port_array to all ports and add to device list  */
3500         for (i=0; i < port_count; ++i) {
3501                 memcpy(port_array[i]->port_array, port_array, sizeof(port_array));
3502                 add_device(port_array[i]);
3503                 port_array[i]->port_count = port_count;
3504                 spin_lock_init(&port_array[i]->lock);
3505         }
3506
3507         /* Allocate and claim adapter resources */
3508         if (!claim_resources(port_array[0])) {
3509
3510                 alloc_dma_bufs(port_array[0]);
3511
3512                 /* copy resource information from first port to others */
3513                 for (i = 1; i < port_count; ++i) {
3514                         port_array[i]->lock      = port_array[0]->lock;
3515                         port_array[i]->irq_level = port_array[0]->irq_level;
3516                         port_array[i]->reg_addr  = port_array[0]->reg_addr;
3517                         alloc_dma_bufs(port_array[i]);
3518                 }
3519
3520                 if (request_irq(port_array[0]->irq_level,
3521                                         slgt_interrupt,
3522                                         port_array[0]->irq_flags,
3523                                         port_array[0]->device_name,
3524                                         port_array[0]) < 0) {
3525                         DBGERR(("%s request_irq failed IRQ=%d\n",
3526                                 port_array[0]->device_name,
3527                                 port_array[0]->irq_level));
3528                 } else {
3529                         port_array[0]->irq_requested = true;
3530                         adapter_test(port_array[0]);
3531                         for (i=1 ; i < port_count ; i++) {
3532                                 port_array[i]->init_error = port_array[0]->init_error;
3533                                 port_array[i]->gpio_present = port_array[0]->gpio_present;
3534                         }
3535                 }
3536         }
3537
3538         for (i=0; i < port_count; ++i)
3539                 tty_register_device(serial_driver, port_array[i]->line, &(port_array[i]->pdev->dev));
3540 }
3541
3542 static int __devinit init_one(struct pci_dev *dev,
3543                               const struct pci_device_id *ent)
3544 {
3545         if (pci_enable_device(dev)) {
3546                 printk("error enabling pci device %p\n", dev);
3547                 return -EIO;
3548         }
3549         pci_set_master(dev);
3550         device_init(slgt_device_count, dev);
3551         return 0;
3552 }
3553
3554 static void __devexit remove_one(struct pci_dev *dev)
3555 {
3556 }
3557
3558 static const struct tty_operations ops = {
3559         .open = open,
3560         .close = close,
3561         .write = write,
3562         .put_char = put_char,
3563         .flush_chars = flush_chars,
3564         .write_room = write_room,
3565         .chars_in_buffer = chars_in_buffer,
3566         .flush_buffer = flush_buffer,
3567         .ioctl = ioctl,
3568         .compat_ioctl = slgt_compat_ioctl,
3569         .throttle = throttle,
3570         .unthrottle = unthrottle,
3571         .send_xchar = send_xchar,
3572         .break_ctl = set_break,
3573         .wait_until_sent = wait_until_sent,
3574         .read_proc = read_proc,
3575         .set_termios = set_termios,
3576         .stop = tx_hold,
3577         .start = tx_release,
3578         .hangup = hangup,
3579         .tiocmget = tiocmget,
3580         .tiocmset = tiocmset,
3581 };
3582
3583 static void slgt_cleanup(void)
3584 {
3585         int rc;
3586         struct slgt_info *info;
3587         struct slgt_info *tmp;
3588
3589         printk("unload %s %s\n", driver_name, driver_version);
3590
3591         if (serial_driver) {
3592                 for (info=slgt_device_list ; info != NULL ; info=info->next_device)
3593                         tty_unregister_device(serial_driver, info->line);
3594                 if ((rc = tty_unregister_driver(serial_driver)))
3595                         DBGERR(("tty_unregister_driver error=%d\n", rc));
3596                 put_tty_driver(serial_driver);
3597         }
3598
3599         /* reset devices */
3600         info = slgt_device_list;
3601         while(info) {
3602                 reset_port(info);
3603                 info = info->next_device;
3604         }
3605
3606         /* release devices */
3607         info = slgt_device_list;
3608         while(info) {
3609 #if SYNCLINK_GENERIC_HDLC
3610                 hdlcdev_exit(info);
3611 #endif
3612                 free_dma_bufs(info);
3613                 free_tmp_rbuf(info);
3614                 if (info->port_num == 0)
3615                         release_resources(info);
3616                 tmp = info;
3617                 info = info->next_device;
3618                 kfree(tmp);
3619         }
3620
3621         if (pci_registered)
3622                 pci_unregister_driver(&pci_driver);
3623 }
3624
3625 /*
3626  *  Driver initialization entry point.
3627  */
3628 static int __init slgt_init(void)
3629 {
3630         int rc;
3631
3632         printk("%s %s\n", driver_name, driver_version);
3633
3634         serial_driver = alloc_tty_driver(MAX_DEVICES);
3635         if (!serial_driver) {
3636                 printk("%s can't allocate tty driver\n", driver_name);
3637                 return -ENOMEM;
3638         }
3639
3640         /* Initialize the tty_driver structure */
3641
3642         serial_driver->owner = THIS_MODULE;
3643         serial_driver->driver_name = tty_driver_name;
3644         serial_driver->name = tty_dev_prefix;
3645         serial_driver->major = ttymajor;
3646         serial_driver->minor_start = 64;
3647         serial_driver->type = TTY_DRIVER_TYPE_SERIAL;
3648         serial_driver->subtype = SERIAL_TYPE_NORMAL;
3649         serial_driver->init_termios = tty_std_termios;
3650         serial_driver->init_termios.c_cflag =
3651                 B9600 | CS8 | CREAD | HUPCL | CLOCAL;
3652         serial_driver->init_termios.c_ispeed = 9600;
3653         serial_driver->init_termios.c_ospeed = 9600;
3654         serial_driver->flags = TTY_DRIVER_REAL_RAW | TTY_DRIVER_DYNAMIC_DEV;
3655         tty_set_operations(serial_driver, &ops);
3656         if ((rc = tty_register_driver(serial_driver)) < 0) {
3657                 DBGERR(("%s can't register serial driver\n", driver_name));
3658                 put_tty_driver(serial_driver);
3659                 serial_driver = NULL;
3660                 goto error;
3661         }
3662
3663         printk("%s %s, tty major#%d\n",
3664                 driver_name, driver_version,
3665                 serial_driver->major);
3666
3667         slgt_device_count = 0;
3668         if ((rc = pci_register_driver(&pci_driver)) < 0) {
3669                 printk("%s pci_register_driver error=%d\n", driver_name, rc);
3670                 goto error;
3671         }
3672         pci_registered = true;
3673
3674         if (!slgt_device_list)
3675                 printk("%s no devices found\n",driver_name);
3676
3677         return 0;
3678
3679 error:
3680         slgt_cleanup();
3681         return rc;
3682 }
3683
3684 static void __exit slgt_exit(void)
3685 {
3686         slgt_cleanup();
3687 }
3688
3689 module_init(slgt_init);
3690 module_exit(slgt_exit);
3691
3692 /*
3693  * register access routines
3694  */
3695
3696 #define CALC_REGADDR() \
3697         unsigned long reg_addr = ((unsigned long)info->reg_addr) + addr; \
3698         if (addr >= 0x80) \
3699                 reg_addr += (info->port_num) * 32;
3700
3701 static __u8 rd_reg8(struct slgt_info *info, unsigned int addr)
3702 {
3703         CALC_REGADDR();
3704         return readb((void __iomem *)reg_addr);
3705 }
3706
3707 static void wr_reg8(struct slgt_info *info, unsigned int addr, __u8 value)
3708 {
3709         CALC_REGADDR();
3710         writeb(value, (void __iomem *)reg_addr);
3711 }
3712
3713 static __u16 rd_reg16(struct slgt_info *info, unsigned int addr)
3714 {
3715         CALC_REGADDR();
3716         return readw((void __iomem *)reg_addr);
3717 }
3718
3719 static void wr_reg16(struct slgt_info *info, unsigned int addr, __u16 value)
3720 {
3721         CALC_REGADDR();
3722         writew(value, (void __iomem *)reg_addr);
3723 }
3724
3725 static __u32 rd_reg32(struct slgt_info *info, unsigned int addr)
3726 {
3727         CALC_REGADDR();
3728         return readl((void __iomem *)reg_addr);
3729 }
3730
3731 static void wr_reg32(struct slgt_info *info, unsigned int addr, __u32 value)
3732 {
3733         CALC_REGADDR();
3734         writel(value, (void __iomem *)reg_addr);
3735 }
3736
3737 static void rdma_reset(struct slgt_info *info)
3738 {
3739         unsigned int i;
3740
3741         /* set reset bit */
3742         wr_reg32(info, RDCSR, BIT1);
3743
3744         /* wait for enable bit cleared */
3745         for(i=0 ; i < 1000 ; i++)
3746                 if (!(rd_reg32(info, RDCSR) & BIT0))
3747                         break;
3748 }
3749
3750 static void tdma_reset(struct slgt_info *info)
3751 {
3752         unsigned int i;
3753
3754         /* set reset bit */
3755         wr_reg32(info, TDCSR, BIT1);
3756
3757         /* wait for enable bit cleared */
3758         for(i=0 ; i < 1000 ; i++)
3759                 if (!(rd_reg32(info, TDCSR) & BIT0))
3760                         break;
3761 }
3762
3763 /*
3764  * enable internal loopback
3765  * TxCLK and RxCLK are generated from BRG
3766  * and TxD is looped back to RxD internally.
3767  */
3768 static void enable_loopback(struct slgt_info *info)
3769 {
3770         /* SCR (serial control) BIT2=looopback enable */
3771         wr_reg16(info, SCR, (unsigned short)(rd_reg16(info, SCR) | BIT2));
3772
3773         if (info->params.mode != MGSL_MODE_ASYNC) {
3774                 /* CCR (clock control)
3775                  * 07..05  tx clock source (010 = BRG)
3776                  * 04..02  rx clock source (010 = BRG)
3777                  * 01      auxclk enable   (0 = disable)
3778                  * 00      BRG enable      (1 = enable)
3779                  *
3780                  * 0100 1001
3781                  */
3782                 wr_reg8(info, CCR, 0x49);
3783
3784                 /* set speed if available, otherwise use default */
3785                 if (info->params.clock_speed)
3786                         set_rate(info, info->params.clock_speed);
3787                 else
3788                         set_rate(info, 3686400);
3789         }
3790 }
3791
3792 /*
3793  *  set baud rate generator to specified rate
3794  */
3795 static void set_rate(struct slgt_info *info, u32 rate)
3796 {
3797         unsigned int div;
3798         static unsigned int osc = 14745600;
3799
3800         /* div = osc/rate - 1
3801          *
3802          * Round div up if osc/rate is not integer to
3803          * force to next slowest rate.
3804          */
3805
3806         if (rate) {
3807                 div = osc/rate;
3808                 if (!(osc % rate) && div)
3809                         div--;
3810                 wr_reg16(info, BDR, (unsigned short)div);
3811         }
3812 }
3813
3814 static void rx_stop(struct slgt_info *info)
3815 {
3816         unsigned short val;
3817
3818         /* disable and reset receiver */
3819         val = rd_reg16(info, RCR) & ~BIT1;          /* clear enable bit */
3820         wr_reg16(info, RCR, (unsigned short)(val | BIT2)); /* set reset bit */
3821         wr_reg16(info, RCR, val);                  /* clear reset bit */
3822
3823         slgt_irq_off(info, IRQ_RXOVER + IRQ_RXDATA + IRQ_RXIDLE);
3824
3825         /* clear pending rx interrupts */
3826         wr_reg16(info, SSR, IRQ_RXIDLE + IRQ_RXOVER);
3827
3828         rdma_reset(info);
3829
3830         info->rx_enabled = false;
3831         info->rx_restart = false;
3832 }
3833
3834 static void rx_start(struct slgt_info *info)
3835 {
3836         unsigned short val;
3837
3838         slgt_irq_off(info, IRQ_RXOVER + IRQ_RXDATA);
3839
3840         /* clear pending rx overrun IRQ */
3841         wr_reg16(info, SSR, IRQ_RXOVER);
3842
3843         /* reset and disable receiver */
3844         val = rd_reg16(info, RCR) & ~BIT1; /* clear enable bit */
3845         wr_reg16(info, RCR, (unsigned short)(val | BIT2)); /* set reset bit */
3846         wr_reg16(info, RCR, val);                  /* clear reset bit */
3847
3848         rdma_reset(info);
3849         reset_rbufs(info);
3850
3851         /* set 1st descriptor address */
3852         wr_reg32(info, RDDAR, info->rbufs[0].pdesc);
3853
3854         if (info->params.mode != MGSL_MODE_ASYNC) {
3855                 /* enable rx DMA and DMA interrupt */
3856                 wr_reg32(info, RDCSR, (BIT2 + BIT0));
3857         } else {
3858                 /* enable saving of rx status, rx DMA and DMA interrupt */
3859                 wr_reg32(info, RDCSR, (BIT6 + BIT2 + BIT0));
3860         }
3861
3862         slgt_irq_on(info, IRQ_RXOVER);
3863
3864         /* enable receiver */
3865         wr_reg16(info, RCR, (unsigned short)(rd_reg16(info, RCR) | BIT1));
3866
3867         info->rx_restart = false;
3868         info->rx_enabled = true;
3869 }
3870
3871 static void tx_start(struct slgt_info *info)
3872 {
3873         if (!info->tx_enabled) {
3874                 wr_reg16(info, TCR,
3875                          (unsigned short)((rd_reg16(info, TCR) | BIT1) & ~BIT2));
3876                 info->tx_enabled = true;
3877         }
3878
3879         if (info->tx_count) {
3880                 info->drop_rts_on_tx_done = false;
3881
3882                 if (info->params.mode != MGSL_MODE_ASYNC) {
3883                         if (info->params.flags & HDLC_FLAG_AUTO_RTS) {
3884                                 get_signals(info);
3885                                 if (!(info->signals & SerialSignal_RTS)) {
3886                                         info->signals |= SerialSignal_RTS;
3887                                         set_signals(info);
3888                                         info->drop_rts_on_tx_done = true;
3889                                 }
3890                         }
3891
3892                         slgt_irq_off(info, IRQ_TXDATA);
3893                         slgt_irq_on(info, IRQ_TXUNDER + IRQ_TXIDLE);
3894                         /* clear tx idle and underrun status bits */
3895                         wr_reg16(info, SSR, (unsigned short)(IRQ_TXIDLE + IRQ_TXUNDER));
3896                         if (info->params.mode == MGSL_MODE_HDLC)
3897                                 mod_timer(&info->tx_timer, jiffies +
3898                                                 msecs_to_jiffies(5000));
3899                 } else {
3900                         slgt_irq_off(info, IRQ_TXDATA);
3901                         slgt_irq_on(info, IRQ_TXIDLE);
3902                         /* clear tx idle status bit */
3903                         wr_reg16(info, SSR, IRQ_TXIDLE);
3904                 }
3905                 tdma_start(info);
3906                 info->tx_active = true;
3907         }
3908 }
3909
3910 /*
3911  * start transmit DMA if inactive and there are unsent buffers
3912  */
3913 static void tdma_start(struct slgt_info *info)
3914 {
3915         unsigned int i;
3916
3917         if (rd_reg32(info, TDCSR) & BIT0)
3918                 return;
3919
3920         /* transmit DMA inactive, check for unsent buffers */
3921         i = info->tbuf_start;
3922         while (!desc_count(info->tbufs[i])) {
3923                 if (++i == info->tbuf_count)
3924                         i = 0;
3925                 if (i == info->tbuf_current)
3926                         return;
3927         }
3928         info->tbuf_start = i;
3929
3930         /* there are unsent buffers, start transmit DMA */
3931
3932         /* reset needed if previous error condition */
3933         tdma_reset(info);
3934
3935         /* set 1st descriptor address */
3936         wr_reg32(info, TDDAR, info->tbufs[info->tbuf_start].pdesc);
3937         switch(info->params.mode) {
3938         case MGSL_MODE_RAW:
3939         case MGSL_MODE_MONOSYNC:
3940         case MGSL_MODE_BISYNC:
3941                 wr_reg32(info, TDCSR, BIT2 + BIT0); /* IRQ + DMA enable */
3942                 break;
3943         default:
3944                 wr_reg32(info, TDCSR, BIT0); /* DMA enable */
3945         }
3946 }
3947
3948 static void tx_stop(struct slgt_info *info)
3949 {
3950         unsigned short val;
3951
3952         del_timer(&info->tx_timer);
3953
3954         tdma_reset(info);
3955
3956         /* reset and disable transmitter */
3957         val = rd_reg16(info, TCR) & ~BIT1;          /* clear enable bit */
3958         wr_reg16(info, TCR, (unsigned short)(val | BIT2)); /* set reset bit */
3959
3960         slgt_irq_off(info, IRQ_TXDATA + IRQ_TXIDLE + IRQ_TXUNDER);
3961
3962         /* clear tx idle and underrun status bit */
3963         wr_reg16(info, SSR, (unsigned short)(IRQ_TXIDLE + IRQ_TXUNDER));
3964
3965         reset_tbufs(info);
3966
3967         info->tx_enabled = false;
3968         info->tx_active = false;
3969 }
3970
3971 static void reset_port(struct slgt_info *info)
3972 {
3973         if (!info->reg_addr)
3974                 return;
3975
3976         tx_stop(info);
3977         rx_stop(info);
3978
3979         info->signals &= ~(SerialSignal_DTR + SerialSignal_RTS);
3980         set_signals(info);
3981
3982         slgt_irq_off(info, IRQ_ALL | IRQ_MASTER);
3983 }
3984
3985 static void reset_adapter(struct slgt_info *info)
3986 {
3987         int i;
3988         for (i=0; i < info->port_count; ++i) {
3989                 if (info->port_array[i])
3990                         reset_port(info->port_array[i]);
3991         }
3992 }
3993
3994 static void async_mode(struct slgt_info *info)
3995 {
3996         unsigned short val;
3997
3998         slgt_irq_off(info, IRQ_ALL | IRQ_MASTER);
3999         tx_stop(info);
4000         rx_stop(info);
4001
4002         /* TCR (tx control)
4003          *
4004          * 15..13  mode, 010=async
4005          * 12..10  encoding, 000=NRZ
4006          * 09      parity enable
4007          * 08      1=odd parity, 0=even parity
4008          * 07      1=RTS driver control
4009          * 06      1=break enable
4010          * 05..04  character length
4011          *         00=5 bits
4012          *         01=6 bits
4013          *         10=7 bits
4014          *         11=8 bits
4015          * 03      0=1 stop bit, 1=2 stop bits
4016          * 02      reset
4017          * 01      enable
4018          * 00      auto-CTS enable
4019          */
4020         val = 0x4000;
4021
4022         if (info->if_mode & MGSL_INTERFACE_RTS_EN)
4023                 val |= BIT7;
4024
4025         if (info->params.parity != ASYNC_PARITY_NONE) {
4026                 val |= BIT9;
4027                 if (info->params.parity == ASYNC_PARITY_ODD)
4028                         val |= BIT8;
4029         }
4030
4031         switch (info->params.data_bits)
4032         {
4033         case 6: val |= BIT4; break;
4034         case 7: val |= BIT5; break;
4035         case 8: val |= BIT5 + BIT4; break;
4036         }
4037
4038         if (info->params.stop_bits != 1)
4039                 val |= BIT3;
4040
4041         if (info->params.flags & HDLC_FLAG_AUTO_CTS)
4042                 val |= BIT0;
4043
4044         wr_reg16(info, TCR, val);
4045
4046         /* RCR (rx control)
4047          *
4048          * 15..13  mode, 010=async
4049          * 12..10  encoding, 000=NRZ
4050          * 09      parity enable
4051          * 08      1=odd parity, 0=even parity
4052          * 07..06  reserved, must be 0
4053          * 05..04  character length
4054          *         00=5 bits
4055          *         01=6 bits
4056          *         10=7 bits
4057          *         11=8 bits
4058          * 03      reserved, must be zero
4059          * 02      reset
4060          * 01      enable
4061          * 00      auto-DCD enable
4062          */
4063         val = 0x4000;
4064
4065         if (info->params.parity != ASYNC_PARITY_NONE) {
4066                 val |= BIT9;
4067                 if (info->params.parity == ASYNC_PARITY_ODD)
4068                         val |= BIT8;
4069         }
4070
4071         switch (info->params.data_bits)
4072         {
4073         case 6: val |= BIT4; break;
4074         case 7: val |= BIT5; break;
4075         case 8: val |= BIT5 + BIT4; break;
4076         }
4077
4078         if (info->params.flags & HDLC_FLAG_AUTO_DCD)
4079                 val |= BIT0;
4080
4081         wr_reg16(info, RCR, val);
4082
4083         /* CCR (clock control)
4084          *
4085          * 07..05  011 = tx clock source is BRG/16
4086          * 04..02  010 = rx clock source is BRG
4087          * 01      0 = auxclk disabled
4088          * 00      1 = BRG enabled
4089          *
4090          * 0110 1001
4091          */
4092         wr_reg8(info, CCR, 0x69);
4093
4094         msc_set_vcr(info);
4095
4096         /* SCR (serial control)
4097          *
4098          * 15  1=tx req on FIFO half empty
4099          * 14  1=rx req on FIFO half full
4100          * 13  tx data  IRQ enable
4101          * 12  tx idle  IRQ enable
4102          * 11  rx break on IRQ enable
4103          * 10  rx data  IRQ enable
4104          * 09  rx break off IRQ enable
4105          * 08  overrun  IRQ enable
4106          * 07  DSR      IRQ enable
4107          * 06  CTS      IRQ enable
4108          * 05  DCD      IRQ enable
4109          * 04  RI       IRQ enable
4110          * 03  reserved, must be zero
4111          * 02  1=txd->rxd internal loopback enable
4112          * 01  reserved, must be zero
4113          * 00  1=master IRQ enable
4114          */
4115         val = BIT15 + BIT14 + BIT0;
4116         wr_reg16(info, SCR, val);
4117
4118         slgt_irq_on(info, IRQ_RXBREAK | IRQ_RXOVER);
4119
4120         set_rate(info, info->params.data_rate * 16);
4121
4122         if (info->params.loopback)
4123                 enable_loopback(info);
4124 }
4125
4126 static void sync_mode(struct slgt_info *info)
4127 {
4128         unsigned short val;
4129
4130         slgt_irq_off(info, IRQ_ALL | IRQ_MASTER);
4131         tx_stop(info);
4132         rx_stop(info);
4133
4134         /* TCR (tx control)
4135          *
4136          * 15..13  mode, 000=HDLC 001=raw 010=async 011=monosync 100=bisync
4137          * 12..10  encoding
4138          * 09      CRC enable
4139          * 08      CRC32
4140          * 07      1=RTS driver control
4141          * 06      preamble enable
4142          * 05..04  preamble length
4143          * 03      share open/close flag
4144          * 02      reset
4145          * 01      enable
4146          * 00      auto-CTS enable
4147          */
4148         val = 0;
4149
4150         switch(info->params.mode) {
4151         case MGSL_MODE_MONOSYNC: val |= BIT14 + BIT13; break;
4152         case MGSL_MODE_BISYNC:   val |= BIT15; break;
4153         case MGSL_MODE_RAW:      val |= BIT13; break;
4154         }
4155         if (info->if_mode & MGSL_INTERFACE_RTS_EN)
4156                 val |= BIT7;
4157
4158         switch(info->params.encoding)
4159         {
4160         case HDLC_ENCODING_NRZB:          val |= BIT10; break;
4161         case HDLC_ENCODING_NRZI_MARK:     val |= BIT11; break;
4162         case HDLC_ENCODING_NRZI:          val |= BIT11 + BIT10; break;
4163         case HDLC_ENCODING_BIPHASE_MARK:  val |= BIT12; break;
4164         case HDLC_ENCODING_BIPHASE_SPACE: val |= BIT12 + BIT10; break;
4165         case HDLC_ENCODING_BIPHASE_LEVEL: val |= BIT12 + BIT11; break;
4166         case HDLC_ENCODING_DIFF_BIPHASE_LEVEL: val |= BIT12 + BIT11 + BIT10; break;
4167         }
4168
4169         switch (info->params.crc_type & HDLC_CRC_MASK)
4170         {
4171         case HDLC_CRC_16_CCITT: val |= BIT9; break;
4172         case HDLC_CRC_32_CCITT: val |= BIT9 + BIT8; break;
4173         }
4174
4175         if (info->params.preamble != HDLC_PREAMBLE_PATTERN_NONE)
4176                 val |= BIT6;
4177
4178         switch (info->params.preamble_length)
4179         {
4180         case HDLC_PREAMBLE_LENGTH_16BITS: val |= BIT5; break;
4181         case HDLC_PREAMBLE_LENGTH_32BITS: val |= BIT4; break;
4182         case HDLC_PREAMBLE_LENGTH_64BITS: val |= BIT5 + BIT4; break;
4183         }
4184
4185         if (info->params.flags & HDLC_FLAG_AUTO_CTS)
4186                 val |= BIT0;
4187
4188         wr_reg16(info, TCR, val);
4189
4190         /* TPR (transmit preamble) */
4191
4192         switch (info->params.preamble)
4193         {
4194         case HDLC_PREAMBLE_PATTERN_FLAGS: val = 0x7e; break;
4195         case HDLC_PREAMBLE_PATTERN_ONES:  val = 0xff; break;
4196         case HDLC_PREAMBLE_PATTERN_ZEROS: val = 0x00; break;
4197         case HDLC_PREAMBLE_PATTERN_10:    val = 0x55; break;
4198         case HDLC_PREAMBLE_PATTERN_01:    val = 0xaa; break;
4199         default:                          val = 0x7e; break;
4200         }
4201         wr_reg8(info, TPR, (unsigned char)val);
4202
4203         /* RCR (rx control)
4204          *
4205          * 15..13  mode, 000=HDLC 001=raw 010=async 011=monosync 100=bisync
4206          * 12..10  encoding
4207          * 09      CRC enable
4208          * 08      CRC32
4209          * 07..03  reserved, must be 0
4210          * 02      reset
4211          * 01      enable
4212          * 00      auto-DCD enable
4213          */
4214         val = 0;
4215
4216         switch(info->params.mode) {
4217         case MGSL_MODE_MONOSYNC: val |= BIT14 + BIT13; break;
4218         case MGSL_MODE_BISYNC:   val |= BIT15; break;
4219         case MGSL_MODE_RAW:      val |= BIT13; break;
4220         }
4221
4222         switch(info->params.encoding)
4223         {
4224         case HDLC_ENCODING_NRZB:          val |= BIT10; break;
4225         case HDLC_ENCODING_NRZI_MARK:     val |= BIT11; break;
4226         case HDLC_ENCODING_NRZI:          val |= BIT11 + BIT10; break;
4227         case HDLC_ENCODING_BIPHASE_MARK:  val |= BIT12; break;
4228         case HDLC_ENCODING_BIPHASE_SPACE: val |= BIT12 + BIT10; break;
4229         case HDLC_ENCODING_BIPHASE_LEVEL: val |= BIT12 + BIT11; break;
4230         case HDLC_ENCODING_DIFF_BIPHASE_LEVEL: val |= BIT12 + BIT11 + BIT10; break;
4231         }
4232
4233         switch (info->params.crc_type & HDLC_CRC_MASK)
4234         {
4235         case HDLC_CRC_16_CCITT: val |= BIT9; break;
4236         case HDLC_CRC_32_CCITT: val |= BIT9 + BIT8; break;
4237         }
4238
4239         if (info->params.flags & HDLC_FLAG_AUTO_DCD)
4240                 val |= BIT0;
4241
4242         wr_reg16(info, RCR, val);
4243
4244         /* CCR (clock control)
4245          *
4246          * 07..05  tx clock source
4247          * 04..02  rx clock source
4248          * 01      auxclk enable
4249          * 00      BRG enable
4250          */
4251         val = 0;
4252
4253         if (info->params.flags & HDLC_FLAG_TXC_BRG)
4254         {
4255                 // when RxC source is DPLL, BRG generates 16X DPLL
4256                 // reference clock, so take TxC from BRG/16 to get
4257                 // transmit clock at actual data rate
4258                 if (info->params.flags & HDLC_FLAG_RXC_DPLL)
4259                         val |= BIT6 + BIT5;     /* 011, txclk = BRG/16 */
4260                 else
4261                         val |= BIT6;    /* 010, txclk = BRG */
4262         }
4263         else if (info->params.flags & HDLC_FLAG_TXC_DPLL)
4264                 val |= BIT7;    /* 100, txclk = DPLL Input */
4265         else if (info->params.flags & HDLC_FLAG_TXC_RXCPIN)
4266                 val |= BIT5;    /* 001, txclk = RXC Input */
4267
4268         if (info->params.flags & HDLC_FLAG_RXC_BRG)
4269                 val |= BIT3;    /* 010, rxclk = BRG */
4270         else if (info->params.flags & HDLC_FLAG_RXC_DPLL)
4271                 val |= BIT4;    /* 100, rxclk = DPLL */
4272         else if (info->params.flags & HDLC_FLAG_RXC_TXCPIN)
4273                 val |= BIT2;    /* 001, rxclk = TXC Input */
4274
4275         if (info->params.clock_speed)
4276                 val |= BIT1 + BIT0;
4277
4278         wr_reg8(info, CCR, (unsigned char)val);
4279
4280         if (info->params.flags & (HDLC_FLAG_TXC_DPLL + HDLC_FLAG_RXC_DPLL))
4281         {
4282                 // program DPLL mode
4283                 switch(info->params.encoding)
4284                 {
4285                 case HDLC_ENCODING_BIPHASE_MARK:
4286                 case HDLC_ENCODING_BIPHASE_SPACE:
4287                         val = BIT7; break;
4288                 case HDLC_ENCODING_BIPHASE_LEVEL:
4289                 case HDLC_ENCODING_DIFF_BIPHASE_LEVEL:
4290                         val = BIT7 + BIT6; break;
4291                 default: val = BIT6;    // NRZ encodings
4292                 }
4293                 wr_reg16(info, RCR, (unsigned short)(rd_reg16(info, RCR) | val));
4294
4295                 // DPLL requires a 16X reference clock from BRG
4296                 set_rate(info, info->params.clock_speed * 16);
4297         }
4298         else
4299                 set_rate(info, info->params.clock_speed);
4300
4301         tx_set_idle(info);
4302
4303         msc_set_vcr(info);
4304
4305         /* SCR (serial control)
4306          *
4307          * 15  1=tx req on FIFO half empty
4308          * 14  1=rx req on FIFO half full
4309          * 13  tx data  IRQ enable
4310          * 12  tx idle  IRQ enable
4311          * 11  underrun IRQ enable
4312          * 10  rx data  IRQ enable
4313          * 09  rx idle  IRQ enable
4314          * 08  overrun  IRQ enable
4315          * 07  DSR      IRQ enable
4316          * 06  CTS      IRQ enable
4317          * 05  DCD      IRQ enable
4318          * 04  RI       IRQ enable
4319          * 03  reserved, must be zero
4320          * 02  1=txd->rxd internal loopback enable
4321          * 01  reserved, must be zero
4322          * 00  1=master IRQ enable
4323          */
4324         wr_reg16(info, SCR, BIT15 + BIT14 + BIT0);
4325
4326         if (info->params.loopback)
4327                 enable_loopback(info);
4328 }
4329
4330 /*
4331  *  set transmit idle mode
4332  */
4333 static void tx_set_idle(struct slgt_info *info)
4334 {
4335         unsigned char val;
4336         unsigned short tcr;
4337
4338         /* if preamble enabled (tcr[6] == 1) then tx idle size = 8 bits
4339          * else tcr[5:4] = tx idle size: 00 = 8 bits, 01 = 16 bits
4340          */
4341         tcr = rd_reg16(info, TCR);
4342         if (info->idle_mode & HDLC_TXIDLE_CUSTOM_16) {
4343                 /* disable preamble, set idle size to 16 bits */
4344                 tcr = (tcr & ~(BIT6 + BIT5)) | BIT4;
4345                 /* MSB of 16 bit idle specified in tx preamble register (TPR) */
4346                 wr_reg8(info, TPR, (unsigned char)((info->idle_mode >> 8) & 0xff));
4347         } else if (!(tcr & BIT6)) {
4348                 /* preamble is disabled, set idle size to 8 bits */
4349                 tcr &= ~(BIT5 + BIT4);
4350         }
4351         wr_reg16(info, TCR, tcr);
4352
4353         if (info->idle_mode & (HDLC_TXIDLE_CUSTOM_8 | HDLC_TXIDLE_CUSTOM_16)) {
4354                 /* LSB of custom tx idle specified in tx idle register */
4355                 val = (unsigned char)(info->idle_mode & 0xff);
4356         } else {
4357                 /* standard 8 bit idle patterns */
4358                 switch(info->idle_mode)
4359                 {
4360                 case HDLC_TXIDLE_FLAGS:          val = 0x7e; break;
4361                 case HDLC_TXIDLE_ALT_ZEROS_ONES:
4362                 case HDLC_TXIDLE_ALT_MARK_SPACE: val = 0xaa; break;
4363                 case HDLC_TXIDLE_ZEROS:
4364                 case HDLC_TXIDLE_SPACE:          val = 0x00; break;
4365                 default:                         val = 0xff;
4366                 }
4367         }
4368
4369         wr_reg8(info, TIR, val);
4370 }
4371
4372 /*
4373  * get state of V24 status (input) signals
4374  */
4375 static void get_signals(struct slgt_info *info)
4376 {
4377         unsigned short status = rd_reg16(info, SSR);
4378
4379         /* clear all serial signals except DTR and RTS */
4380         info->signals &= SerialSignal_DTR + SerialSignal_RTS;
4381
4382         if (status & BIT3)
4383                 info->signals |= SerialSignal_DSR;
4384         if (status & BIT2)
4385                 info->signals |= SerialSignal_CTS;
4386         if (status & BIT1)
4387                 info->signals |= SerialSignal_DCD;
4388         if (status & BIT0)
4389                 info->signals |= SerialSignal_RI;
4390 }
4391
4392 /*
4393  * set V.24 Control Register based on current configuration
4394  */
4395 static void msc_set_vcr(struct slgt_info *info)
4396 {
4397         unsigned char val = 0;
4398
4399         /* VCR (V.24 control)
4400          *
4401          * 07..04  serial IF select
4402          * 03      DTR
4403          * 02      RTS
4404          * 01      LL
4405          * 00      RL
4406          */
4407
4408         switch(info->if_mode & MGSL_INTERFACE_MASK)
4409         {
4410         case MGSL_INTERFACE_RS232:
4411                 val |= BIT5; /* 0010 */
4412                 break;
4413         case MGSL_INTERFACE_V35:
4414                 val |= BIT7 + BIT6 + BIT5; /* 1110 */
4415                 break;
4416         case MGSL_INTERFACE_RS422:
4417                 val |= BIT6; /* 0100 */
4418                 break;
4419         }
4420
4421         if (info->signals & SerialSignal_DTR)
4422                 val |= BIT3;
4423         if (info->signals & SerialSignal_RTS)
4424                 val |= BIT2;
4425         if (info->if_mode & MGSL_INTERFACE_LL)
4426                 val |= BIT1;
4427         if (info->if_mode & MGSL_INTERFACE_RL)
4428                 val |= BIT0;
4429         wr_reg8(info, VCR, val);
4430 }
4431
4432 /*
4433  * set state of V24 control (output) signals
4434  */
4435 static void set_signals(struct slgt_info *info)
4436 {
4437         unsigned char val = rd_reg8(info, VCR);
4438         if (info->signals & SerialSignal_DTR)
4439                 val |= BIT3;
4440         else
4441                 val &= ~BIT3;
4442         if (info->signals & SerialSignal_RTS)
4443                 val |= BIT2;
4444         else
4445                 val &= ~BIT2;
4446         wr_reg8(info, VCR, val);
4447 }
4448
4449 /*
4450  * free range of receive DMA buffers (i to last)
4451  */
4452 static void free_rbufs(struct slgt_info *info, unsigned int i, unsigned int last)
4453 {
4454         int done = 0;
4455
4456         while(!done) {
4457                 /* reset current buffer for reuse */
4458                 info->rbufs[i].status = 0;
4459                 switch(info->params.mode) {
4460                 case MGSL_MODE_RAW:
4461                 case MGSL_MODE_MONOSYNC:
4462                 case MGSL_MODE_BISYNC:
4463                         set_desc_count(info->rbufs[i], info->raw_rx_size);
4464                         break;
4465                 default:
4466                         set_desc_count(info->rbufs[i], DMABUFSIZE);
4467                 }
4468
4469                 if (i == last)
4470                         done = 1;
4471                 if (++i == info->rbuf_count)
4472                         i = 0;
4473         }
4474         info->rbuf_current = i;
4475 }
4476
4477 /*
4478  * mark all receive DMA buffers as free
4479  */
4480 static void reset_rbufs(struct slgt_info *info)
4481 {
4482         free_rbufs(info, 0, info->rbuf_count - 1);
4483 }
4484
4485 /*
4486  * pass receive HDLC frame to upper layer
4487  *
4488  * return true if frame available, otherwise false
4489  */
4490 static bool rx_get_frame(struct slgt_info *info)
4491 {
4492         unsigned int start, end;
4493         unsigned short status;
4494         unsigned int framesize = 0;
4495         unsigned long flags;
4496         struct tty_struct *tty = info->port.tty;
4497         unsigned char addr_field = 0xff;
4498         unsigned int crc_size = 0;
4499
4500         switch (info->params.crc_type & HDLC_CRC_MASK) {
4501         case HDLC_CRC_16_CCITT: crc_size = 2; break;
4502         case HDLC_CRC_32_CCITT: crc_size = 4; break;
4503         }
4504
4505 check_again:
4506
4507         framesize = 0;
4508         addr_field = 0xff;
4509         start = end = info->rbuf_current;
4510
4511         for (;;) {
4512                 if (!desc_complete(info->rbufs[end]))
4513                         goto cleanup;
4514
4515                 if (framesize == 0 && info->params.addr_filter != 0xff)
4516                         addr_field = info->rbufs[end].buf[0];
4517
4518                 framesize += desc_count(info->rbufs[end]);
4519
4520                 if (desc_eof(info->rbufs[end]))
4521                         break;
4522
4523                 if (++end == info->rbuf_count)
4524                         end = 0;
4525
4526                 if (end == info->rbuf_current) {
4527                         if (info->rx_enabled){
4528                                 spin_lock_irqsave(&info->lock,flags);
4529                                 rx_start(info);
4530                                 spin_unlock_irqrestore(&info->lock,flags);
4531                         }
4532                         goto cleanup;
4533                 }
4534         }
4535
4536         /* status
4537          *
4538          * 15      buffer complete
4539          * 14..06  reserved
4540          * 05..04  residue
4541          * 02      eof (end of frame)
4542          * 01      CRC error
4543          * 00      abort
4544          */
4545         status = desc_status(info->rbufs[end]);
4546
4547         /* ignore CRC bit if not using CRC (bit is undefined) */
4548         if ((info->params.crc_type & HDLC_CRC_MASK) == HDLC_CRC_NONE)
4549                 status &= ~BIT1;
4550
4551         if (framesize == 0 ||
4552                  (addr_field != 0xff && addr_field != info->params.addr_filter)) {
4553                 free_rbufs(info, start, end);
4554                 goto check_again;
4555         }
4556
4557         if (framesize < (2 + crc_size) || status & BIT0) {
4558                 info->icount.rxshort++;
4559                 framesize = 0;
4560         } else if (status & BIT1) {
4561                 info->icount.rxcrc++;
4562                 if (!(info->params.crc_type & HDLC_CRC_RETURN_EX))
4563                         framesize = 0;
4564         }
4565
4566 #if SYNCLINK_GENERIC_HDLC
4567         if (framesize == 0) {
4568                 info->netdev->stats.rx_errors++;
4569                 info->netdev->stats.rx_frame_errors++;
4570         }
4571 #endif
4572
4573         DBGBH(("%s rx frame status=%04X size=%d\n",
4574                 info->device_name, status, framesize));
4575         DBGDATA(info, info->rbufs[start].buf, min_t(int, framesize, DMABUFSIZE), "rx");
4576
4577         if (framesize) {
4578                 if (!(info->params.crc_type & HDLC_CRC_RETURN_EX)) {
4579                         framesize -= crc_size;
4580                         crc_size = 0;
4581                 }
4582
4583                 if (framesize > info->max_frame_size + crc_size)
4584                         info->icount.rxlong++;
4585                 else {
4586                         /* copy dma buffer(s) to contiguous temp buffer */
4587                         int copy_count = framesize;
4588                         int i = start;
4589                         unsigned char *p = info->tmp_rbuf;
4590                         info->tmp_rbuf_count = framesize;
4591
4592                         info->icount.rxok++;
4593
4594                         while(copy_count) {
4595                                 int partial_count = min(copy_count, DMABUFSIZE);
4596                                 memcpy(p, info->rbufs[i].buf, partial_count);
4597                                 p += partial_count;
4598                                 copy_count -= partial_count;
4599                                 if (++i == info->rbuf_count)
4600                                         i = 0;
4601                         }
4602
4603                         if (info->params.crc_type & HDLC_CRC_RETURN_EX) {
4604                                 *p = (status & BIT1) ? RX_CRC_ERROR : RX_OK;
4605                                 framesize++;
4606                         }
4607
4608 #if SYNCLINK_GENERIC_HDLC
4609                         if (info->netcount)
4610                                 hdlcdev_rx(info,info->tmp_rbuf, framesize);
4611                         else
4612 #endif
4613                                 ldisc_receive_buf(tty, info->tmp_rbuf, info->flag_buf, framesize);
4614                 }
4615         }
4616         free_rbufs(info, start, end);
4617         return true;
4618
4619 cleanup:
4620         return false;
4621 }
4622
4623 /*
4624  * pass receive buffer (RAW synchronous mode) to tty layer
4625  * return true if buffer available, otherwise false
4626  */
4627 static bool rx_get_buf(struct slgt_info *info)
4628 {
4629         unsigned int i = info->rbuf_current;
4630         unsigned int count;
4631
4632         if (!desc_complete(info->rbufs[i]))
4633                 return false;
4634         count = desc_count(info->rbufs[i]);
4635         switch(info->params.mode) {
4636         case MGSL_MODE_MONOSYNC:
4637         case MGSL_MODE_BISYNC:
4638                 /* ignore residue in byte synchronous modes */
4639                 if (desc_residue(info->rbufs[i]))
4640                         count--;
4641                 break;
4642         }
4643         DBGDATA(info, info->rbufs[i].buf, count, "rx");
4644         DBGINFO(("rx_get_buf size=%d\n", count));
4645         if (count)
4646                 ldisc_receive_buf(info->port.tty, info->rbufs[i].buf,
4647                                   info->flag_buf, count);
4648         free_rbufs(info, i, i);
4649         return true;
4650 }
4651
4652 static void reset_tbufs(struct slgt_info *info)
4653 {
4654         unsigned int i;
4655         info->tbuf_current = 0;
4656         for (i=0 ; i < info->tbuf_count ; i++) {
4657                 info->tbufs[i].status = 0;
4658                 info->tbufs[i].count  = 0;
4659         }
4660 }
4661
4662 /*
4663  * return number of free transmit DMA buffers
4664  */
4665 static unsigned int free_tbuf_count(struct slgt_info *info)
4666 {
4667         unsigned int count = 0;
4668         unsigned int i = info->tbuf_current;
4669
4670         do
4671         {
4672                 if (desc_count(info->tbufs[i]))
4673                         break; /* buffer in use */
4674                 ++count;
4675                 if (++i == info->tbuf_count)
4676                         i=0;
4677         } while (i != info->tbuf_current);
4678
4679         /* if tx DMA active, last zero count buffer is in use */
4680         if (count && (rd_reg32(info, TDCSR) & BIT0))
4681                 --count;
4682
4683         return count;
4684 }
4685
4686 /*
4687  * load transmit DMA buffer(s) with data
4688  */
4689 static void tx_load(struct slgt_info *info, const char *buf, unsigned int size)
4690 {
4691         unsigned short count;
4692         unsigned int i;
4693         struct slgt_desc *d;
4694
4695         if (size == 0)
4696                 return;
4697
4698         DBGDATA(info, buf, size, "tx");
4699
4700         info->tbuf_start = i = info->tbuf_current;
4701
4702         while (size) {
4703                 d = &info->tbufs[i];
4704                 if (++i == info->tbuf_count)
4705                         i = 0;
4706
4707                 count = (unsigned short)((size > DMABUFSIZE) ? DMABUFSIZE : size);
4708                 memcpy(d->buf, buf, count);
4709
4710                 size -= count;
4711                 buf  += count;
4712
4713                 /*
4714                  * set EOF bit for last buffer of HDLC frame or
4715                  * for every buffer in raw mode
4716                  */
4717                 if ((!size && info->params.mode == MGSL_MODE_HDLC) ||
4718                     info->params.mode == MGSL_MODE_RAW)
4719                         set_desc_eof(*d, 1);
4720                 else
4721                         set_desc_eof(*d, 0);
4722
4723                 set_desc_count(*d, count);
4724         }
4725
4726         info->tbuf_current = i;
4727 }
4728
4729 static int register_test(struct slgt_info *info)
4730 {
4731         static unsigned short patterns[] =
4732                 {0x0000, 0xffff, 0xaaaa, 0x5555, 0x6969, 0x9696};
4733         static unsigned int count = sizeof(patterns)/sizeof(patterns[0]);
4734         unsigned int i;
4735         int rc = 0;
4736
4737         for (i=0 ; i < count ; i++) {
4738                 wr_reg16(info, TIR, patterns[i]);
4739                 wr_reg16(info, BDR, patterns[(i+1)%count]);
4740                 if ((rd_reg16(info, TIR) != patterns[i]) ||
4741                     (rd_reg16(info, BDR) != patterns[(i+1)%count])) {
4742                         rc = -ENODEV;
4743                         break;
4744                 }
4745         }
4746         info->gpio_present = (rd_reg32(info, JCR) & BIT5) ? 1 : 0;
4747         info->init_error = rc ? 0 : DiagStatus_AddressFailure;
4748         return rc;
4749 }
4750
4751 static int irq_test(struct slgt_info *info)
4752 {
4753         unsigned long timeout;
4754         unsigned long flags;
4755         struct tty_struct *oldtty = info->port.tty;
4756         u32 speed = info->params.data_rate;
4757
4758         info->params.data_rate = 921600;
4759         info->port.tty = NULL;
4760
4761         spin_lock_irqsave(&info->lock, flags);
4762         async_mode(info);
4763         slgt_irq_on(info, IRQ_TXIDLE);
4764
4765         /* enable transmitter */
4766         wr_reg16(info, TCR,
4767                 (unsigned short)(rd_reg16(info, TCR) | BIT1));
4768
4769         /* write one byte and wait for tx idle */
4770         wr_reg16(info, TDR, 0);
4771
4772         /* assume failure */
4773         info->init_error = DiagStatus_IrqFailure;
4774         info->irq_occurred = false;
4775
4776         spin_unlock_irqrestore(&info->lock, flags);
4777
4778         timeout=100;
4779         while(timeout-- && !info->irq_occurred)
4780                 msleep_interruptible(10);
4781
4782         spin_lock_irqsave(&info->lock,flags);
4783         reset_port(info);
4784         spin_unlock_irqrestore(&info->lock,flags);
4785
4786         info->params.data_rate = speed;
4787         info->port.tty = oldtty;
4788
4789         info->init_error = info->irq_occurred ? 0 : DiagStatus_IrqFailure;
4790         return info->irq_occurred ? 0 : -ENODEV;
4791 }
4792
4793 static int loopback_test_rx(struct slgt_info *info)
4794 {
4795         unsigned char *src, *dest;
4796         int count;
4797
4798         if (desc_complete(info->rbufs[0])) {
4799                 count = desc_count(info->rbufs[0]);
4800                 src   = info->rbufs[0].buf;
4801                 dest  = info->tmp_rbuf;
4802
4803                 for( ; count ; count-=2, src+=2) {
4804                         /* src=data byte (src+1)=status byte */
4805                         if (!(*(src+1) & (BIT9 + BIT8))) {
4806                                 *dest = *src;
4807                                 dest++;
4808                                 info->tmp_rbuf_count++;
4809                         }
4810                 }
4811                 DBGDATA(info, info->tmp_rbuf, info->tmp_rbuf_count, "rx");
4812                 return 1;
4813         }
4814         return 0;
4815 }
4816
4817 static int loopback_test(struct slgt_info *info)
4818 {
4819 #define TESTFRAMESIZE 20
4820
4821         unsigned long timeout;
4822         u16 count = TESTFRAMESIZE;
4823         unsigned char buf[TESTFRAMESIZE];
4824         int rc = -ENODEV;
4825         unsigned long flags;
4826
4827         struct tty_struct *oldtty = info->port.tty;
4828         MGSL_PARAMS params;
4829
4830         memcpy(&params, &info->params, sizeof(params));
4831
4832         info->params.mode = MGSL_MODE_ASYNC;
4833         info->params.data_rate = 921600;
4834         info->params.loopback = 1;
4835         info->port.tty = NULL;
4836
4837         /* build and send transmit frame */
4838         for (count = 0; count < TESTFRAMESIZE; ++count)
4839                 buf[count] = (unsigned char)count;
4840
4841         info->tmp_rbuf_count = 0;
4842         memset(info->tmp_rbuf, 0, TESTFRAMESIZE);
4843
4844         /* program hardware for HDLC and enabled receiver */
4845         spin_lock_irqsave(&info->lock,flags);
4846         async_mode(info);
4847         rx_start(info);
4848         info->tx_count = count;
4849         tx_load(info, buf, count);
4850         tx_start(info);
4851         spin_unlock_irqrestore(&info->lock, flags);
4852
4853         /* wait for receive complete */
4854         for (timeout = 100; timeout; --timeout) {
4855                 msleep_interruptible(10);
4856                 if (loopback_test_rx(info)) {
4857                         rc = 0;
4858                         break;
4859                 }
4860         }
4861
4862         /* verify received frame length and contents */
4863         if (!rc && (info->tmp_rbuf_count != count ||
4864                   memcmp(buf, info->tmp_rbuf, count))) {
4865                 rc = -ENODEV;
4866         }
4867
4868         spin_lock_irqsave(&info->lock,flags);
4869         reset_adapter(info);
4870         spin_unlock_irqrestore(&info->lock,flags);
4871
4872         memcpy(&info->params, &params, sizeof(info->params));
4873         info->port.tty = oldtty;
4874
4875         info->init_error = rc ? DiagStatus_DmaFailure : 0;
4876         return rc;
4877 }
4878
4879 static int adapter_test(struct slgt_info *info)
4880 {
4881         DBGINFO(("testing %s\n", info->device_name));
4882         if (register_test(info) < 0) {
4883                 printk("register test failure %s addr=%08X\n",
4884                         info->device_name, info->phys_reg_addr);
4885         } else if (irq_test(info) < 0) {
4886                 printk("IRQ test failure %s IRQ=%d\n",
4887                         info->device_name, info->irq_level);
4888         } else if (loopback_test(info) < 0) {
4889                 printk("loopback test failure %s\n", info->device_name);
4890         }
4891         return info->init_error;
4892 }
4893
4894 /*
4895  * transmit timeout handler
4896  */
4897 static void tx_timeout(unsigned long context)
4898 {
4899         struct slgt_info *info = (struct slgt_info*)context;
4900         unsigned long flags;
4901
4902         DBGINFO(("%s tx_timeout\n", info->device_name));
4903         if(info->tx_active && info->params.mode == MGSL_MODE_HDLC) {
4904                 info->icount.txtimeout++;
4905         }
4906         spin_lock_irqsave(&info->lock,flags);
4907         info->tx_active = false;
4908         info->tx_count = 0;
4909         spin_unlock_irqrestore(&info->lock,flags);
4910
4911 #if SYNCLINK_GENERIC_HDLC
4912         if (info->netcount)
4913                 hdlcdev_tx_done(info);
4914         else
4915 #endif
4916                 bh_transmit(info);
4917 }
4918
4919 /*
4920  * receive buffer polling timer
4921  */
4922 static void rx_timeout(unsigned long context)
4923 {
4924         struct slgt_info *info = (struct slgt_info*)context;
4925         unsigned long flags;
4926
4927         DBGINFO(("%s rx_timeout\n", info->device_name));
4928         spin_lock_irqsave(&info->lock, flags);
4929         info->pending_bh |= BH_RECEIVE;
4930         spin_unlock_irqrestore(&info->lock, flags);
4931         bh_handler(&info->task);
4932 }
4933