err.no Git - linux-2.6/blob - drivers/char/synclink_gt.c

   1 /*
   2  * $Id: synclink_gt.c,v 4.50 2007/07/25 19:29:25 paulkf Exp $
   3  *
   4  * Device driver for Microgate SyncLink GT serial adapters.
   5  *
   6  * written by Paul Fulghum for Microgate Corporation
   7  * paulkf@microgate.com
   8  *
   9  * Microgate and SyncLink are trademarks of Microgate Corporation
  10  *
  11  * This code is released under the GNU General Public License (GPL)
  12  *
  13  * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED
  14  * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
  15  * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
  16  * DISCLAIMED.  IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT,
  17  * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
  18  * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
  19  * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
  20  * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
  21  * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
  22  * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED
  23  * OF THE POSSIBILITY OF SUCH DAMAGE.
  24  */
  25
  26 /*
  27  * DEBUG OUTPUT DEFINITIONS
  28  *
  29  * uncomment lines below to enable specific types of debug output
  30  *
  31  * DBGINFO   information - most verbose output
  32  * DBGERR    serious errors
  33  * DBGBH     bottom half service routine debugging
  34  * DBGISR    interrupt service routine debugging
  35  * DBGDATA   output receive and transmit data
  36  * DBGTBUF   output transmit DMA buffers and registers
  37  * DBGRBUF   output receive DMA buffers and registers
  38  */
  39
  40 #define DBGINFO(fmt) if (debug_level >= DEBUG_LEVEL_INFO) printk fmt
  41 #define DBGERR(fmt) if (debug_level >= DEBUG_LEVEL_ERROR) printk fmt
  42 #define DBGBH(fmt) if (debug_level >= DEBUG_LEVEL_BH) printk fmt
  43 #define DBGISR(fmt) if (debug_level >= DEBUG_LEVEL_ISR) printk fmt
  44 #define DBGDATA(info, buf, size, label) if (debug_level >= DEBUG_LEVEL_DATA) trace_block((info), (buf), (size), (label))
  45 //#define DBGTBUF(info) dump_tbufs(info)
  46 //#define DBGRBUF(info) dump_rbufs(info)
  47
  48
  49 #include <linux/module.h>
  50 #include <linux/version.h>
  51 #include <linux/errno.h>
  52 #include <linux/signal.h>
  53 #include <linux/sched.h>
  54 #include <linux/timer.h>
  55 #include <linux/interrupt.h>
  56 #include <linux/pci.h>
  57 #include <linux/tty.h>
  58 #include <linux/tty_flip.h>
  59 #include <linux/serial.h>
  60 #include <linux/major.h>
  61 #include <linux/string.h>
  62 #include <linux/fcntl.h>
  63 #include <linux/ptrace.h>
  64 #include <linux/ioport.h>
  65 #include <linux/mm.h>
  66 #include <linux/slab.h>
  67 #include <linux/netdevice.h>
  68 #include <linux/vmalloc.h>
  69 #include <linux/init.h>
  70 #include <linux/delay.h>
  71 #include <linux/ioctl.h>
  72 #include <linux/termios.h>
  73 #include <linux/bitops.h>
  74 #include <linux/workqueue.h>
  75 #include <linux/hdlc.h>
  76 #include <linux/synclink.h>
  77
  78 #include <asm/system.h>
  79 #include <asm/io.h>
  80 #include <asm/irq.h>
  81 #include <asm/dma.h>
  82 #include <asm/types.h>
  83 #include <asm/uaccess.h>
  84
  85 #if defined(CONFIG_HDLC) || (defined(CONFIG_HDLC_MODULE) && defined(CONFIG_SYNCLINK_GT_MODULE))
  86 #define SYNCLINK_GENERIC_HDLC 1
  87 #else
  88 #define SYNCLINK_GENERIC_HDLC 0
  89 #endif
  90
  91 /*
  92  * module identification
  93  */
  94 static char *driver_name     = "SyncLink GT";
  95 static char *driver_version  = "$Revision: 4.50 $";
  96 static char *tty_driver_name = "synclink_gt";
  97 static char *tty_dev_prefix  = "ttySLG";
  98 MODULE_LICENSE("GPL");
  99 #define MGSL_MAGIC 0x5401
 100 #define MAX_DEVICES 32
 101
 102 static struct pci_device_id pci_table[] = {
 103         {PCI_VENDOR_ID_MICROGATE, SYNCLINK_GT_DEVICE_ID, PCI_ANY_ID, PCI_ANY_ID,},
 104         {PCI_VENDOR_ID_MICROGATE, SYNCLINK_GT2_DEVICE_ID, PCI_ANY_ID, PCI_ANY_ID,},
 105         {PCI_VENDOR_ID_MICROGATE, SYNCLINK_GT4_DEVICE_ID, PCI_ANY_ID, PCI_ANY_ID,},
 106         {PCI_VENDOR_ID_MICROGATE, SYNCLINK_AC_DEVICE_ID, PCI_ANY_ID, PCI_ANY_ID,},
 107         {0,}, /* terminate list */
 108 };
 109 MODULE_DEVICE_TABLE(pci, pci_table);
 110
 111 static int  init_one(struct pci_dev *dev,const struct pci_device_id *ent);
 112 static void remove_one(struct pci_dev *dev);
 113 static struct pci_driver pci_driver = {
 114         .name           = "synclink_gt",
 115         .id_table       = pci_table,
 116         .probe          = init_one,
 117         .remove         = __devexit_p(remove_one),
 118 };
 119
 120 static bool pci_registered;
 121
 122 /*
 123  * module configuration and status
 124  */
 125 static struct slgt_info *slgt_device_list;
 126 static int slgt_device_count;
 127
 128 static int ttymajor;
 129 static int debug_level;
 130 static int maxframe[MAX_DEVICES];
 131 static int dosyncppp[MAX_DEVICES];
 132
 133 module_param(ttymajor, int, 0);
 134 module_param(debug_level, int, 0);
 135 module_param_array(maxframe, int, NULL, 0);
 136 module_param_array(dosyncppp, int, NULL, 0);
 137
 138 MODULE_PARM_DESC(ttymajor, "TTY major device number override: 0=auto assigned");
 139 MODULE_PARM_DESC(debug_level, "Debug syslog output: 0=disabled, 1 to 5=increasing detail");
 140 MODULE_PARM_DESC(maxframe, "Maximum frame size used by device (4096 to 65535)");
 141 MODULE_PARM_DESC(dosyncppp, "Enable synchronous net device, 0=disable 1=enable");
 142
 143 /*
 144  * tty support and callbacks
 145  */
 146 static struct tty_driver *serial_driver;
 147
 148 static int  open(struct tty_struct *tty, struct file * filp);
 149 static void close(struct tty_struct *tty, struct file * filp);
 150 static void hangup(struct tty_struct *tty);
 151 static void set_termios(struct tty_struct *tty, struct ktermios *old_termios);
 152
 153 static int  write(struct tty_struct *tty, const unsigned char *buf, int count);
 154 static int put_char(struct tty_struct *tty, unsigned char ch);
 155 static void send_xchar(struct tty_struct *tty, char ch);
 156 static void wait_until_sent(struct tty_struct *tty, int timeout);
 157 static int  write_room(struct tty_struct *tty);
 158 static void flush_chars(struct tty_struct *tty);
 159 static void flush_buffer(struct tty_struct *tty);
 160 static void tx_hold(struct tty_struct *tty);
 161 static void tx_release(struct tty_struct *tty);
 162
 163 static int  ioctl(struct tty_struct *tty, struct file *file, unsigned int cmd, unsigned long arg);
 164 static int  read_proc(char *page, char **start, off_t off, int count,int *eof, void *data);
 165 static int  chars_in_buffer(struct tty_struct *tty);
 166 static void throttle(struct tty_struct * tty);
 167 static void unthrottle(struct tty_struct * tty);
 168 static void set_break(struct tty_struct *tty, int break_state);
 169
 170 /*
 171  * generic HDLC support and callbacks
 172  */
 173 #if SYNCLINK_GENERIC_HDLC
 174 #define dev_to_port(D) (dev_to_hdlc(D)->priv)
 175 static void hdlcdev_tx_done(struct slgt_info *info);
 176 static void hdlcdev_rx(struct slgt_info *info, char *buf, int size);
 177 static int  hdlcdev_init(struct slgt_info *info);
 178 static void hdlcdev_exit(struct slgt_info *info);
 179 #endif
 180
 181
 182 /*
 183  * device specific structures, macros and functions
 184  */
 185
 186 #define SLGT_MAX_PORTS 4
 187 #define SLGT_REG_SIZE  256
 188
 189 /*
 190  * conditional wait facility
 191  */
 192 struct cond_wait {
 193         struct cond_wait *next;
 194         wait_queue_head_t q;
 195         wait_queue_t wait;
 196         unsigned int data;
 197 };
 198 static void init_cond_wait(struct cond_wait *w, unsigned int data);
 199 static void add_cond_wait(struct cond_wait **head, struct cond_wait *w);
 200 static void remove_cond_wait(struct cond_wait **head, struct cond_wait *w);
 201 static void flush_cond_wait(struct cond_wait **head);
 202
 203 /*
 204  * DMA buffer descriptor and access macros
 205  */
 206 struct slgt_desc
 207 {
 208         __le16 count;
 209         __le16 status;
 210         __le32 pbuf;  /* physical address of data buffer */
 211         __le32 next;  /* physical address of next descriptor */
 212
 213         /* driver book keeping */
 214         char *buf;          /* virtual  address of data buffer */
 215         unsigned int pdesc; /* physical address of this descriptor */
 216         dma_addr_t buf_dma_addr;
 217 };
 218
 219 #define set_desc_buffer(a,b) (a).pbuf = cpu_to_le32((unsigned int)(b))
 220 #define set_desc_next(a,b) (a).next   = cpu_to_le32((unsigned int)(b))
 221 #define set_desc_count(a,b)(a).count  = cpu_to_le16((unsigned short)(b))
 222 #define set_desc_eof(a,b)  (a).status = cpu_to_le16((b) ? (le16_to_cpu((a).status) | BIT0) : (le16_to_cpu((a).status) & ~BIT0))
 223 #define desc_count(a)      (le16_to_cpu((a).count))
 224 #define desc_status(a)     (le16_to_cpu((a).status))
 225 #define desc_complete(a)   (le16_to_cpu((a).status) & BIT15)
 226 #define desc_eof(a)        (le16_to_cpu((a).status) & BIT2)
 227 #define desc_crc_error(a)  (le16_to_cpu((a).status) & BIT1)
 228 #define desc_abort(a)      (le16_to_cpu((a).status) & BIT0)
 229 #define desc_residue(a)    ((le16_to_cpu((a).status) & 0x38) >> 3)
 230
 231 struct _input_signal_events {
 232         int ri_up;
 233         int ri_down;
 234         int dsr_up;
 235         int dsr_down;
 236         int dcd_up;
 237         int dcd_down;
 238         int cts_up;
 239         int cts_down;
 240 };
 241
 242 /*
 243  * device instance data structure
 244  */
 245 struct slgt_info {
 246         void *if_ptr;           /* General purpose pointer (used by SPPP) */
 247         struct tty_port port;
 248
 249         struct slgt_info *next_device;  /* device list link */
 250
 251         int magic;
 252
 253         char device_name[25];
 254         struct pci_dev *pdev;
 255
 256         int port_count;  /* count of ports on adapter */
 257         int adapter_num; /* adapter instance number */
 258         int port_num;    /* port instance number */
 259
 260         /* array of pointers to port contexts on this adapter */
 261         struct slgt_info *port_array[SLGT_MAX_PORTS];
 262
 263         int                     line;           /* tty line instance number */
 264         unsigned short          close_delay;
 265         unsigned short          closing_wait;   /* time to wait before closing */
 266
 267         struct mgsl_icount      icount;
 268
 269         int                     timeout;
 270         int                     x_char;         /* xon/xoff character */
 271         unsigned int            read_status_mask;
 272         unsigned int            ignore_status_mask;
 273
 274         wait_queue_head_t       status_event_wait_q;
 275         wait_queue_head_t       event_wait_q;
 276         struct timer_list       tx_timer;
 277         struct timer_list       rx_timer;
 278
 279         unsigned int            gpio_present;
 280         struct cond_wait        *gpio_wait_q;
 281
 282         spinlock_t lock;        /* spinlock for synchronizing with ISR */
 283
 284         struct work_struct task;
 285         u32 pending_bh;
 286         bool bh_requested;
 287         bool bh_running;
 288
 289         int isr_overflow;
 290         bool irq_requested;     /* true if IRQ requested */
 291         bool irq_occurred;      /* for diagnostics use */
 292
 293         /* device configuration */
 294
 295         unsigned int bus_type;
 296         unsigned int irq_level;
 297         unsigned long irq_flags;
 298
 299         unsigned char __iomem * reg_addr;  /* memory mapped registers address */
 300         u32 phys_reg_addr;
 301         bool reg_addr_requested;
 302
 303         MGSL_PARAMS params;       /* communications parameters */
 304         u32 idle_mode;
 305         u32 max_frame_size;       /* as set by device config */
 306
 307         unsigned int raw_rx_size;
 308         unsigned int if_mode;
 309
 310         /* device status */
 311
 312         bool rx_enabled;
 313         bool rx_restart;
 314
 315         bool tx_enabled;
 316         bool tx_active;
 317
 318         unsigned char signals;    /* serial signal states */
 319         int init_error;  /* initialization error */
 320
 321         unsigned char *tx_buf;
 322         int tx_count;
 323
 324         char flag_buf[MAX_ASYNC_BUFFER_SIZE];
 325         char char_buf[MAX_ASYNC_BUFFER_SIZE];
 326         bool drop_rts_on_tx_done;
 327         struct  _input_signal_events    input_signal_events;
 328
 329         int dcd_chkcount;       /* check counts to prevent */
 330         int cts_chkcount;       /* too many IRQs if a signal */
 331         int dsr_chkcount;       /* is floating */
 332         int ri_chkcount;
 333
 334         char *bufs;             /* virtual address of DMA buffer lists */
 335         dma_addr_t bufs_dma_addr; /* physical address of buffer descriptors */
 336
 337         unsigned int rbuf_count;
 338         struct slgt_desc *rbufs;
 339         unsigned int rbuf_current;
 340         unsigned int rbuf_index;
 341
 342         unsigned int tbuf_count;
 343         struct slgt_desc *tbufs;
 344         unsigned int tbuf_current;
 345         unsigned int tbuf_start;
 346
 347         unsigned char *tmp_rbuf;
 348         unsigned int tmp_rbuf_count;
 349
 350         /* SPPP/Cisco HDLC device parts */
 351
 352         int netcount;
 353         int dosyncppp;
 354         spinlock_t netlock;
 355 #if SYNCLINK_GENERIC_HDLC
 356         struct net_device *netdev;
 357 #endif
 358
 359 };
 360
 361 static MGSL_PARAMS default_params = {
 362         .mode            = MGSL_MODE_HDLC,
 363         .loopback        = 0,
 364         .flags           = HDLC_FLAG_UNDERRUN_ABORT15,
 365         .encoding        = HDLC_ENCODING_NRZI_SPACE,
 366         .clock_speed     = 0,
 367         .addr_filter     = 0xff,
 368         .crc_type        = HDLC_CRC_16_CCITT,
 369         .preamble_length = HDLC_PREAMBLE_LENGTH_8BITS,
 370         .preamble        = HDLC_PREAMBLE_PATTERN_NONE,
 371         .data_rate       = 9600,
 372         .data_bits       = 8,
 373         .stop_bits       = 1,
 374         .parity          = ASYNC_PARITY_NONE
 375 };
 376
 377
 378 #define BH_RECEIVE  1
 379 #define BH_TRANSMIT 2
 380 #define BH_STATUS   4
 381 #define IO_PIN_SHUTDOWN_LIMIT 100
 382
 383 #define DMABUFSIZE 256
 384 #define DESC_LIST_SIZE 4096
 385
 386 #define MASK_PARITY  BIT1
 387 #define MASK_FRAMING BIT0
 388 #define MASK_BREAK   BIT14
 389 #define MASK_OVERRUN BIT4
 390
 391 #define GSR   0x00 /* global status */
 392 #define JCR   0x04 /* JTAG control */
 393 #define IODR  0x08 /* GPIO direction */
 394 #define IOER  0x0c /* GPIO interrupt enable */
 395 #define IOVR  0x10 /* GPIO value */
 396 #define IOSR  0x14 /* GPIO interrupt status */
 397 #define TDR   0x80 /* tx data */
 398 #define RDR   0x80 /* rx data */
 399 #define TCR   0x82 /* tx control */
 400 #define TIR   0x84 /* tx idle */
 401 #define TPR   0x85 /* tx preamble */
 402 #define RCR   0x86 /* rx control */
 403 #define VCR   0x88 /* V.24 control */
 404 #define CCR   0x89 /* clock control */
 405 #define BDR   0x8a /* baud divisor */
 406 #define SCR   0x8c /* serial control */
 407 #define SSR   0x8e /* serial status */
 408 #define RDCSR 0x90 /* rx DMA control/status */
 409 #define TDCSR 0x94 /* tx DMA control/status */
 410 #define RDDAR 0x98 /* rx DMA descriptor address */
 411 #define TDDAR 0x9c /* tx DMA descriptor address */
 412
 413 #define RXIDLE      BIT14
 414 #define RXBREAK     BIT14
 415 #define IRQ_TXDATA  BIT13
 416 #define IRQ_TXIDLE  BIT12
 417 #define IRQ_TXUNDER BIT11 /* HDLC */
 418 #define IRQ_RXDATA  BIT10
 419 #define IRQ_RXIDLE  BIT9  /* HDLC */
 420 #define IRQ_RXBREAK BIT9  /* async */
 421 #define IRQ_RXOVER  BIT8
 422 #define IRQ_DSR     BIT7
 423 #define IRQ_CTS     BIT6
 424 #define IRQ_DCD     BIT5
 425 #define IRQ_RI      BIT4
 426 #define IRQ_ALL     0x3ff0
 427 #define IRQ_MASTER  BIT0
 428
 429 #define slgt_irq_on(info, mask) \
 430         wr_reg16((info), SCR, (unsigned short)(rd_reg16((info), SCR) | (mask)))
 431 #define slgt_irq_off(info, mask) \
 432         wr_reg16((info), SCR, (unsigned short)(rd_reg16((info), SCR) & ~(mask)))
 433
 434 static __u8  rd_reg8(struct slgt_info *info, unsigned int addr);
 435 static void  wr_reg8(struct slgt_info *info, unsigned int addr, __u8 value);
 436 static __u16 rd_reg16(struct slgt_info *info, unsigned int addr);
 437 static void  wr_reg16(struct slgt_info *info, unsigned int addr, __u16 value);
 438 static __u32 rd_reg32(struct slgt_info *info, unsigned int addr);
 439 static void  wr_reg32(struct slgt_info *info, unsigned int addr, __u32 value);
 440
 441 static void  msc_set_vcr(struct slgt_info *info);
 442
 443 static int  startup(struct slgt_info *info);
 444 static int  block_til_ready(struct tty_struct *tty, struct file * filp,struct slgt_info *info);
 445 static void shutdown(struct slgt_info *info);
 446 static void program_hw(struct slgt_info *info);
 447 static void change_params(struct slgt_info *info);
 448
 449 static int  register_test(struct slgt_info *info);
 450 static int  irq_test(struct slgt_info *info);
 451 static int  loopback_test(struct slgt_info *info);
 452 static int  adapter_test(struct slgt_info *info);
 453
 454 static void reset_adapter(struct slgt_info *info);
 455 static void reset_port(struct slgt_info *info);
 456 static void async_mode(struct slgt_info *info);
 457 static void sync_mode(struct slgt_info *info);
 458
 459 static void rx_stop(struct slgt_info *info);
 460 static void rx_start(struct slgt_info *info);
 461 static void reset_rbufs(struct slgt_info *info);
 462 static void free_rbufs(struct slgt_info *info, unsigned int first, unsigned int last);
 463 static void rdma_reset(struct slgt_info *info);
 464 static bool rx_get_frame(struct slgt_info *info);
 465 static bool rx_get_buf(struct slgt_info *info);
 466
 467 static void tx_start(struct slgt_info *info);
 468 static void tx_stop(struct slgt_info *info);
 469 static void tx_set_idle(struct slgt_info *info);
 470 static unsigned int free_tbuf_count(struct slgt_info *info);
 471 static void reset_tbufs(struct slgt_info *info);
 472 static void tdma_reset(struct slgt_info *info);
 473 static void tdma_start(struct slgt_info *info);
 474 static void tx_load(struct slgt_info *info, const char *buf, unsigned int count);
 475
 476 static void get_signals(struct slgt_info *info);
 477 static void set_signals(struct slgt_info *info);
 478 static void enable_loopback(struct slgt_info *info);
 479 static void set_rate(struct slgt_info *info, u32 data_rate);
 480
 481 static int  bh_action(struct slgt_info *info);
 482 static void bh_handler(struct work_struct *work);
 483 static void bh_transmit(struct slgt_info *info);
 484 static void isr_serial(struct slgt_info *info);
 485 static void isr_rdma(struct slgt_info *info);
 486 static void isr_txeom(struct slgt_info *info, unsigned short status);
 487 static void isr_tdma(struct slgt_info *info);
 488
 489 static int  alloc_dma_bufs(struct slgt_info *info);
 490 static void free_dma_bufs(struct slgt_info *info);
 491 static int  alloc_desc(struct slgt_info *info);
 492 static void free_desc(struct slgt_info *info);
 493 static int  alloc_bufs(struct slgt_info *info, struct slgt_desc *bufs, int count);
 494 static void free_bufs(struct slgt_info *info, struct slgt_desc *bufs, int count);
 495
 496 static int  alloc_tmp_rbuf(struct slgt_info *info);
 497 static void free_tmp_rbuf(struct slgt_info *info);
 498
 499 static void tx_timeout(unsigned long context);
 500 static void rx_timeout(unsigned long context);
 501
 502 /*
 503  * ioctl handlers
 504  */
 505 static int  get_stats(struct slgt_info *info, struct mgsl_icount __user *user_icount);
 506 static int  get_params(struct slgt_info *info, MGSL_PARAMS __user *params);
 507 static int  set_params(struct slgt_info *info, MGSL_PARAMS __user *params);
 508 static int  get_txidle(struct slgt_info *info, int __user *idle_mode);
 509 static int  set_txidle(struct slgt_info *info, int idle_mode);
 510 static int  tx_enable(struct slgt_info *info, int enable);
 511 static int  tx_abort(struct slgt_info *info);
 512 static int  rx_enable(struct slgt_info *info, int enable);
 513 static int  modem_input_wait(struct slgt_info *info,int arg);
 514 static int  wait_mgsl_event(struct slgt_info *info, int __user *mask_ptr);
 515 static int  tiocmget(struct tty_struct *tty, struct file *file);
 516 static int  tiocmset(struct tty_struct *tty, struct file *file,
 517                      unsigned int set, unsigned int clear);
 518 static void set_break(struct tty_struct *tty, int break_state);
 519 static int  get_interface(struct slgt_info *info, int __user *if_mode);
 520 static int  set_interface(struct slgt_info *info, int if_mode);
 521 static int  set_gpio(struct slgt_info *info, struct gpio_desc __user *gpio);
 522 static int  get_gpio(struct slgt_info *info, struct gpio_desc __user *gpio);
 523 static int  wait_gpio(struct slgt_info *info, struct gpio_desc __user *gpio);
 524
 525 /*
 526  * driver functions
 527  */
 528 static void add_device(struct slgt_info *info);
 529 static void device_init(int adapter_num, struct pci_dev *pdev);
 530 static int  claim_resources(struct slgt_info *info);
 531 static void release_resources(struct slgt_info *info);
 532
 533 /*
 534  * DEBUG OUTPUT CODE
 535  */
 536 #ifndef DBGINFO
 537 #define DBGINFO(fmt)
 538 #endif
 539 #ifndef DBGERR
 540 #define DBGERR(fmt)
 541 #endif
 542 #ifndef DBGBH
 543 #define DBGBH(fmt)
 544 #endif
 545 #ifndef DBGISR
 546 #define DBGISR(fmt)
 547 #endif
 548
 549 #ifdef DBGDATA
 550 static void trace_block(struct slgt_info *info, const char *data, int count, const char *label)
 551 {
 552         int i;
 553         int linecount;
 554         printk("%s %s data:\n",info->device_name, label);
 555         while(count) {
 556                 linecount = (count > 16) ? 16 : count;
 557                 for(i=0; i < linecount; i++)
 558                         printk("%02X ",(unsigned char)data[i]);
 559                 for(;i<17;i++)
 560                         printk("   ");
 561                 for(i=0;i<linecount;i++) {
 562                         if (data[i]>=040 && data[i]<=0176)
 563                                 printk("%c",data[i]);
 564                         else
 565                                 printk(".");
 566                 }
 567                 printk("\n");
 568                 data  += linecount;
 569                 count -= linecount;
 570         }
 571 }
 572 #else
 573 #define DBGDATA(info, buf, size, label)
 574 #endif
 575
 576 #ifdef DBGTBUF
 577 static void dump_tbufs(struct slgt_info *info)
 578 {
 579         int i;
 580         printk("tbuf_current=%d\n", info->tbuf_current);
 581         for (i=0 ; i < info->tbuf_count ; i++) {
 582                 printk("%d: count=%04X status=%04X\n",
 583                         i, le16_to_cpu(info->tbufs[i].count), le16_to_cpu(info->tbufs[i].status));
 584         }
 585 }
 586 #else
 587 #define DBGTBUF(info)
 588 #endif
 589
 590 #ifdef DBGRBUF
 591 static void dump_rbufs(struct slgt_info *info)
 592 {
 593         int i;
 594         printk("rbuf_current=%d\n", info->rbuf_current);
 595         for (i=0 ; i < info->rbuf_count ; i++) {
 596                 printk("%d: count=%04X status=%04X\n",
 597                         i, le16_to_cpu(info->rbufs[i].count), le16_to_cpu(info->rbufs[i].status));
 598         }
 599 }
 600 #else
 601 #define DBGRBUF(info)
 602 #endif
 603
 604 static inline int sanity_check(struct slgt_info *info, char *devname, const char *name)
 605 {
 606 #ifdef SANITY_CHECK
 607         if (!info) {
 608                 printk("null struct slgt_info for (%s) in %s\n", devname, name);
 609                 return 1;
 610         }
 611         if (info->magic != MGSL_MAGIC) {
 612                 printk("bad magic number struct slgt_info (%s) in %s\n", devname, name);
 613                 return 1;
 614         }
 615 #else
 616         if (!info)
 617                 return 1;
 618 #endif
 619         return 0;
 620 }
 621
 622 /**
 623  * line discipline callback wrappers
 624  *
 625  * The wrappers maintain line discipline references
 626  * while calling into the line discipline.
 627  *
 628  * ldisc_receive_buf  - pass receive data to line discipline
 629  */
 630 static void ldisc_receive_buf(struct tty_struct *tty,
 631                               const __u8 *data, char *flags, int count)
 632 {
 633         struct tty_ldisc *ld;
 634         if (!tty)
 635                 return;
 636         ld = tty_ldisc_ref(tty);
 637         if (ld) {
 638                 if (ld->ops->receive_buf)
 639                         ld->ops->receive_buf(tty, data, flags, count);
 640                 tty_ldisc_deref(ld);
 641         }
 642 }
 643
 644 /* tty callbacks */
 645
 646 static int open(struct tty_struct *tty, struct file *filp)
 647 {
 648         struct slgt_info *info;
 649         int retval, line;
 650         unsigned long flags;
 651
 652         line = tty->index;
 653         if ((line < 0) || (line >= slgt_device_count)) {
 654                 DBGERR(("%s: open with invalid line #%d.\n", driver_name, line));
 655                 return -ENODEV;
 656         }
 657
 658         info = slgt_device_list;
 659         while(info && info->line != line)
 660                 info = info->next_device;
 661         if (sanity_check(info, tty->name, "open"))
 662                 return -ENODEV;
 663         if (info->init_error) {
 664                 DBGERR(("%s init error=%d\n", info->device_name, info->init_error));
 665                 return -ENODEV;
 666         }
 667
 668         tty->driver_data = info;
 669         info->port.tty = tty;
 670
 671         DBGINFO(("%s open, old ref count = %d\n", info->device_name, info->port.count));
 672
 673         /* If port is closing, signal caller to try again */
 674         if (tty_hung_up_p(filp) || info->port.flags & ASYNC_CLOSING){
 675                 if (info->port.flags & ASYNC_CLOSING)
 676                         interruptible_sleep_on(&info->port.close_wait);
 677                 retval = ((info->port.flags & ASYNC_HUP_NOTIFY) ?
 678                         -EAGAIN : -ERESTARTSYS);
 679                 goto cleanup;
 680         }
 681
 682         info->port.tty->low_latency = (info->port.flags & ASYNC_LOW_LATENCY) ? 1 : 0;
 683
 684         spin_lock_irqsave(&info->netlock, flags);
 685         if (info->netcount) {
 686                 retval = -EBUSY;
 687                 spin_unlock_irqrestore(&info->netlock, flags);
 688                 goto cleanup;
 689         }
 690         info->port.count++;
 691         spin_unlock_irqrestore(&info->netlock, flags);
 692
 693         if (info->port.count == 1) {
 694                 /* 1st open on this device, init hardware */
 695                 retval = startup(info);
 696                 if (retval < 0)
 697                         goto cleanup;
 698         }
 699
 700         retval = block_til_ready(tty, filp, info);
 701         if (retval) {
 702                 DBGINFO(("%s block_til_ready rc=%d\n", info->device_name, retval));
 703                 goto cleanup;
 704         }
 705
 706         retval = 0;
 707
 708 cleanup:
 709         if (retval) {
 710                 if (tty->count == 1)
 711                         info->port.tty = NULL; /* tty layer will release tty struct */
 712                 if(info->port.count)
 713                         info->port.count--;
 714         }
 715
 716         DBGINFO(("%s open rc=%d\n", info->device_name, retval));
 717         return retval;
 718 }
 719
 720 static void close(struct tty_struct *tty, struct file *filp)
 721 {
 722         struct slgt_info *info = tty->driver_data;
 723
 724         if (sanity_check(info, tty->name, "close"))
 725                 return;
 726         DBGINFO(("%s close entry, count=%d\n", info->device_name, info->port.count));
 727
 728         if (!info->port.count)
 729                 return;
 730
 731         if (tty_hung_up_p(filp))
 732                 goto cleanup;
 733
 734         if ((tty->count == 1) && (info->port.count != 1)) {
 735                 /*
 736                  * tty->count is 1 and the tty structure will be freed.
 737                  * info->port.count should be one in this case.
 738                  * if it's not, correct it so that the port is shutdown.
 739                  */
 740                 DBGERR(("%s close: bad refcount; tty->count=1, "
 741                        "info->port.count=%d\n", info->device_name, info->port.count));
 742                 info->port.count = 1;
 743         }
 744
 745         info->port.count--;
 746
 747         /* if at least one open remaining, leave hardware active */
 748         if (info->port.count)
 749                 goto cleanup;
 750
 751         info->port.flags |= ASYNC_CLOSING;
 752
 753         /* set tty->closing to notify line discipline to
 754          * only process XON/XOFF characters. Only the N_TTY
 755          * discipline appears to use this (ppp does not).
 756          */
 757         tty->closing = 1;
 758
 759         /* wait for transmit data to clear all layers */
 760
 761         if (info->closing_wait != ASYNC_CLOSING_WAIT_NONE) {
 762                 DBGINFO(("%s call tty_wait_until_sent\n", info->device_name));
 763                 tty_wait_until_sent(tty, info->closing_wait);
 764         }
 765
 766         if (info->port.flags & ASYNC_INITIALIZED)
 767                 wait_until_sent(tty, info->timeout);
 768         flush_buffer(tty);
 769         tty_ldisc_flush(tty);
 770
 771         shutdown(info);
 772
 773         tty->closing = 0;
 774         info->port.tty = NULL;
 775
 776         if (info->port.blocked_open) {
 777                 if (info->close_delay) {
 778                         msleep_interruptible(jiffies_to_msecs(info->close_delay));
 779                 }
 780                 wake_up_interruptible(&info->port.open_wait);
 781         }
 782
 783         info->port.flags &= ~(ASYNC_NORMAL_ACTIVE|ASYNC_CLOSING);
 784
 785         wake_up_interruptible(&info->port.close_wait);
 786
 787 cleanup:
 788         DBGINFO(("%s close exit, count=%d\n", tty->driver->name, info->port.count));
 789 }
 790
 791 static void hangup(struct tty_struct *tty)
 792 {
 793         struct slgt_info *info = tty->driver_data;
 794
 795         if (sanity_check(info, tty->name, "hangup"))
 796                 return;
 797         DBGINFO(("%s hangup\n", info->device_name));
 798
 799         flush_buffer(tty);
 800         shutdown(info);
 801
 802         info->port.count = 0;
 803         info->port.flags &= ~ASYNC_NORMAL_ACTIVE;
 804         info->port.tty = NULL;
 805
 806         wake_up_interruptible(&info->port.open_wait);
 807 }
 808
 809 static void set_termios(struct tty_struct *tty, struct ktermios *old_termios)
 810 {
 811         struct slgt_info *info = tty->driver_data;
 812         unsigned long flags;
 813
 814         DBGINFO(("%s set_termios\n", tty->driver->name));
 815
 816         change_params(info);
 817
 818         /* Handle transition to B0 status */
 819         if (old_termios->c_cflag & CBAUD &&
 820             !(tty->termios->c_cflag & CBAUD)) {
 821                 info->signals &= ~(SerialSignal_RTS + SerialSignal_DTR);
 822                 spin_lock_irqsave(&info->lock,flags);
 823                 set_signals(info);
 824                 spin_unlock_irqrestore(&info->lock,flags);
 825         }
 826
 827         /* Handle transition away from B0 status */
 828         if (!(old_termios->c_cflag & CBAUD) &&
 829             tty->termios->c_cflag & CBAUD) {
 830                 info->signals |= SerialSignal_DTR;
 831                 if (!(tty->termios->c_cflag & CRTSCTS) ||
 832                     !test_bit(TTY_THROTTLED, &tty->flags)) {
 833                         info->signals |= SerialSignal_RTS;
 834                 }
 835                 spin_lock_irqsave(&info->lock,flags);
 836                 set_signals(info);
 837                 spin_unlock_irqrestore(&info->lock,flags);
 838         }
 839
 840         /* Handle turning off CRTSCTS */
 841         if (old_termios->c_cflag & CRTSCTS &&
 842             !(tty->termios->c_cflag & CRTSCTS)) {
 843                 tty->hw_stopped = 0;
 844                 tx_release(tty);
 845         }
 846 }
 847
 848 static int write(struct tty_struct *tty,
 849                  const unsigned char *buf, int count)
 850 {
 851         int ret = 0;
 852         struct slgt_info *info = tty->driver_data;
 853         unsigned long flags;
 854
 855         if (sanity_check(info, tty->name, "write"))
 856                 goto cleanup;
 857         DBGINFO(("%s write count=%d\n", info->device_name, count));
 858
 859         if (!info->tx_buf)
 860                 goto cleanup;
 861
 862         if (count > info->max_frame_size) {
 863                 ret = -EIO;
 864                 goto cleanup;
 865         }
 866
 867         if (!count)
 868                 goto cleanup;
 869
 870         if (info->params.mode == MGSL_MODE_RAW ||
 871             info->params.mode == MGSL_MODE_MONOSYNC ||
 872             info->params.mode == MGSL_MODE_BISYNC) {
 873                 unsigned int bufs_needed = (count/DMABUFSIZE);
 874                 unsigned int bufs_free = free_tbuf_count(info);
 875                 if (count % DMABUFSIZE)
 876                         ++bufs_needed;
 877                 if (bufs_needed > bufs_free)
 878                         goto cleanup;
 879         } else {
 880                 if (info->tx_active)
 881                         goto cleanup;
 882                 if (info->tx_count) {
 883                         /* send accumulated data from send_char() calls */
 884                         /* as frame and wait before accepting more data. */
 885                         tx_load(info, info->tx_buf, info->tx_count);
 886                         goto start;
 887                 }
 888         }
 889
 890         ret = info->tx_count = count;
 891         tx_load(info, buf, count);
 892         goto start;
 893
 894 start:
 895         if (info->tx_count && !tty->stopped && !tty->hw_stopped) {
 896                 spin_lock_irqsave(&info->lock,flags);
 897                 if (!info->tx_active)
 898                         tx_start(info);
 899                 else
 900                         tdma_start(info);
 901                 spin_unlock_irqrestore(&info->lock,flags);
 902         }
 903
 904 cleanup:
 905         DBGINFO(("%s write rc=%d\n", info->device_name, ret));
 906         return ret;
 907 }
 908
 909 static int put_char(struct tty_struct *tty, unsigned char ch)
 910 {
 911         struct slgt_info *info = tty->driver_data;
 912         unsigned long flags;
 913         int ret = 0;
 914
 915         if (sanity_check(info, tty->name, "put_char"))
 916                 return 0;
 917         DBGINFO(("%s put_char(%d)\n", info->device_name, ch));
 918         if (!info->tx_buf)
 919                 return 0;
 920         spin_lock_irqsave(&info->lock,flags);
 921         if (!info->tx_active && (info->tx_count < info->max_frame_size)) {
 922                 info->tx_buf[info->tx_count++] = ch;
 923                 ret = 1;
 924         }
 925         spin_unlock_irqrestore(&info->lock,flags);
 926         return ret;
 927 }
 928
 929 static void send_xchar(struct tty_struct *tty, char ch)
 930 {
 931         struct slgt_info *info = tty->driver_data;
 932         unsigned long flags;
 933
 934         if (sanity_check(info, tty->name, "send_xchar"))
 935                 return;
 936         DBGINFO(("%s send_xchar(%d)\n", info->device_name, ch));
 937         info->x_char = ch;
 938         if (ch) {
 939                 spin_lock_irqsave(&info->lock,flags);
 940                 if (!info->tx_enabled)
 941                         tx_start(info);
 942                 spin_unlock_irqrestore(&info->lock,flags);
 943         }
 944 }
 945
 946 static void wait_until_sent(struct tty_struct *tty, int timeout)
 947 {
 948         struct slgt_info *info = tty->driver_data;
 949         unsigned long orig_jiffies, char_time;
 950
 951         if (!info )
 952                 return;
 953         if (sanity_check(info, tty->name, "wait_until_sent"))
 954                 return;
 955         DBGINFO(("%s wait_until_sent entry\n", info->device_name));
 956         if (!(info->port.flags & ASYNC_INITIALIZED))
 957                 goto exit;
 958
 959         orig_jiffies = jiffies;
 960
 961         /* Set check interval to 1/5 of estimated time to
 962          * send a character, and make it at least 1. The check
 963          * interval should also be less than the timeout.
 964          * Note: use tight timings here to satisfy the NIST-PCTS.
 965          */
 966
 967         lock_kernel();
 968
 969         if (info->params.data_rate) {
 970                 char_time = info->timeout/(32 * 5);
 971                 if (!char_time)
 972                         char_time++;
 973         } else
 974                 char_time = 1;
 975
 976         if (timeout)
 977                 char_time = min_t(unsigned long, char_time, timeout);
 978
 979         while (info->tx_active) {
 980                 msleep_interruptible(jiffies_to_msecs(char_time));
 981                 if (signal_pending(current))
 982                         break;
 983                 if (timeout && time_after(jiffies, orig_jiffies + timeout))
 984                         break;
 985         }
 986         unlock_kernel();
 987
 988 exit:
 989         DBGINFO(("%s wait_until_sent exit\n", info->device_name));
 990 }
 991
 992 static int write_room(struct tty_struct *tty)
 993 {
 994         struct slgt_info *info = tty->driver_data;
 995         int ret;
 996
 997         if (sanity_check(info, tty->name, "write_room"))
 998                 return 0;
 999         ret = (info->tx_active) ? 0 : HDLC_MAX_FRAME_SIZE;
1000         DBGINFO(("%s write_room=%d\n", info->device_name, ret));
1001         return ret;
1002 }
1003
1004 static void flush_chars(struct tty_struct *tty)
1005 {
1006         struct slgt_info *info = tty->driver_data;
1007         unsigned long flags;
1008
1009         if (sanity_check(info, tty->name, "flush_chars"))
1010                 return;
1011         DBGINFO(("%s flush_chars entry tx_count=%d\n", info->device_name, info->tx_count));
1012
1013         if (info->tx_count <= 0 || tty->stopped ||
1014             tty->hw_stopped || !info->tx_buf)
1015                 return;
1016
1017         DBGINFO(("%s flush_chars start transmit\n", info->device_name));
1018
1019         spin_lock_irqsave(&info->lock,flags);
1020         if (!info->tx_active && info->tx_count) {
1021                 tx_load(info, info->tx_buf,info->tx_count);
1022                 tx_start(info);
1023         }
1024         spin_unlock_irqrestore(&info->lock,flags);
1025 }
1026
1027 static void flush_buffer(struct tty_struct *tty)
1028 {
1029         struct slgt_info *info = tty->driver_data;
1030         unsigned long flags;
1031
1032         if (sanity_check(info, tty->name, "flush_buffer"))
1033                 return;
1034         DBGINFO(("%s flush_buffer\n", info->device_name));
1035
1036         spin_lock_irqsave(&info->lock,flags);
1037         if (!info->tx_active)
1038                 info->tx_count = 0;
1039         spin_unlock_irqrestore(&info->lock,flags);
1040
1041         tty_wakeup(tty);
1042 }
1043
1044 /*
1045  * throttle (stop) transmitter
1046  */
1047 static void tx_hold(struct tty_struct *tty)
1048 {
1049         struct slgt_info *info = tty->driver_data;
1050         unsigned long flags;
1051
1052         if (sanity_check(info, tty->name, "tx_hold"))
1053                 return;
1054         DBGINFO(("%s tx_hold\n", info->device_name));
1055         spin_lock_irqsave(&info->lock,flags);
1056         if (info->tx_enabled && info->params.mode == MGSL_MODE_ASYNC)
1057                 tx_stop(info);
1058         spin_unlock_irqrestore(&info->lock,flags);
1059 }
1060
1061 /*
1062  * release (start) transmitter
1063  */
1064 static void tx_release(struct tty_struct *tty)
1065 {
1066         struct slgt_info *info = tty->driver_data;
1067         unsigned long flags;
1068
1069         if (sanity_check(info, tty->name, "tx_release"))
1070                 return;
1071         DBGINFO(("%s tx_release\n", info->device_name));
1072         spin_lock_irqsave(&info->lock,flags);
1073         if (!info->tx_active && info->tx_count) {
1074                 tx_load(info, info->tx_buf, info->tx_count);
1075                 tx_start(info);
1076         }
1077         spin_unlock_irqrestore(&info->lock,flags);
1078 }
1079
1080 /*
1081  * Service an IOCTL request
1082  *
1083  * Arguments
1084  *
1085  *      tty     pointer to tty instance data
1086  *      file    pointer to associated file object for device
1087  *      cmd     IOCTL command code
1088  *      arg     command argument/context
1089  *
1090  * Return 0 if success, otherwise error code
1091  */
1092 static int ioctl(struct tty_struct *tty, struct file *file,
1093                  unsigned int cmd, unsigned long arg)
1094 {
1095         struct slgt_info *info = tty->driver_data;
1096         struct mgsl_icount cnow;        /* kernel counter temps */
1097         struct serial_icounter_struct __user *p_cuser;  /* user space */
1098         unsigned long flags;
1099         void __user *argp = (void __user *)arg;
1100         int ret;
1101
1102         if (sanity_check(info, tty->name, "ioctl"))
1103                 return -ENODEV;
1104         DBGINFO(("%s ioctl() cmd=%08X\n", info->device_name, cmd));
1105
1106         if ((cmd != TIOCGSERIAL) && (cmd != TIOCSSERIAL) &&
1107             (cmd != TIOCMIWAIT) && (cmd != TIOCGICOUNT)) {
1108                 if (tty->flags & (1 << TTY_IO_ERROR))
1109                     return -EIO;
1110         }
1111
1112         lock_kernel();
1113
1114         switch (cmd) {
1115         case MGSL_IOCGPARAMS:
1116                 ret = get_params(info, argp);
1117                 break;
1118         case MGSL_IOCSPARAMS:
1119                 ret = set_params(info, argp);
1120                 break;
1121         case MGSL_IOCGTXIDLE:
1122                 ret = get_txidle(info, argp);
1123                 break;
1124         case MGSL_IOCSTXIDLE:
1125                 ret = set_txidle(info, (int)arg);
1126                 break;
1127         case MGSL_IOCTXENABLE:
1128                 ret = tx_enable(info, (int)arg);
1129                 break;
1130         case MGSL_IOCRXENABLE:
1131                 ret = rx_enable(info, (int)arg);
1132                 break;
1133         case MGSL_IOCTXABORT:
1134                 ret = tx_abort(info);
1135                 break;
1136         case MGSL_IOCGSTATS:
1137                 ret = get_stats(info, argp);
1138                 break;
1139         case MGSL_IOCWAITEVENT:
1140                 ret = wait_mgsl_event(info, argp);
1141                 break;
1142         case TIOCMIWAIT:
1143                 ret = modem_input_wait(info,(int)arg);
1144                 break;
1145         case MGSL_IOCGIF:
1146                 ret = get_interface(info, argp);
1147                 break;
1148         case MGSL_IOCSIF:
1149                 ret = set_interface(info,(int)arg);
1150                 break;
1151         case MGSL_IOCSGPIO:
1152                 ret = set_gpio(info, argp);
1153                 break;
1154         case MGSL_IOCGGPIO:
1155                 ret = get_gpio(info, argp);
1156                 break;
1157         case MGSL_IOCWAITGPIO:
1158                 ret = wait_gpio(info, argp);
1159                 break;
1160         case TIOCGICOUNT:
1161                 spin_lock_irqsave(&info->lock,flags);
1162                 cnow = info->icount;
1163                 spin_unlock_irqrestore(&info->lock,flags);
1164                 p_cuser = argp;
1165                 if (put_user(cnow.cts, &p_cuser->cts) ||
1166                     put_user(cnow.dsr, &p_cuser->dsr) ||
1167                     put_user(cnow.rng, &p_cuser->rng) ||
1168                     put_user(cnow.dcd, &p_cuser->dcd) ||
1169                     put_user(cnow.rx, &p_cuser->rx) ||
1170                     put_user(cnow.tx, &p_cuser->tx) ||
1171                     put_user(cnow.frame, &p_cuser->frame) ||
1172                     put_user(cnow.overrun, &p_cuser->overrun) ||
1173                     put_user(cnow.parity, &p_cuser->parity) ||
1174                     put_user(cnow.brk, &p_cuser->brk) ||
1175                     put_user(cnow.buf_overrun, &p_cuser->buf_overrun))
1176                         ret = -EFAULT;
1177                 ret = 0;
1178                 break;
1179         default:
1180                 ret = -ENOIOCTLCMD;
1181         }
1182         unlock_kernel();
1183         return ret;
1184 }
1185
1186 /*
1187  * support for 32 bit ioctl calls on 64 bit systems
1188  */
1189 #ifdef CONFIG_COMPAT
1190 static long get_params32(struct slgt_info *info, struct MGSL_PARAMS32 __user *user_params)
1191 {
1192         struct MGSL_PARAMS32 tmp_params;
1193
1194         DBGINFO(("%s get_params32\n", info->device_name));
1195         tmp_params.mode            = (compat_ulong_t)info->params.mode;
1196         tmp_params.loopback        = info->params.loopback;
1197         tmp_params.flags           = info->params.flags;
1198         tmp_params.encoding        = info->params.encoding;
1199         tmp_params.clock_speed     = (compat_ulong_t)info->params.clock_speed;
1200         tmp_params.addr_filter     = info->params.addr_filter;
1201         tmp_params.crc_type        = info->params.crc_type;
1202         tmp_params.preamble_length = info->params.preamble_length;
1203         tmp_params.preamble        = info->params.preamble;
1204         tmp_params.data_rate       = (compat_ulong_t)info->params.data_rate;
1205         tmp_params.data_bits       = info->params.data_bits;
1206         tmp_params.stop_bits       = info->params.stop_bits;
1207         tmp_params.parity          = info->params.parity;
1208         if (copy_to_user(user_params, &tmp_params, sizeof(struct MGSL_PARAMS32)))
1209                 return -EFAULT;
1210         return 0;
1211 }
1212
1213 static long set_params32(struct slgt_info *info, struct MGSL_PARAMS32 __user *new_params)
1214 {
1215         struct MGSL_PARAMS32 tmp_params;
1216
1217         DBGINFO(("%s set_params32\n", info->device_name));
1218         if (copy_from_user(&tmp_params, new_params, sizeof(struct MGSL_PARAMS32)))
1219                 return -EFAULT;
1220
1221         spin_lock(&info->lock);
1222         info->params.mode            = tmp_params.mode;
1223         info->params.loopback        = tmp_params.loopback;
1224         info->params.flags           = tmp_params.flags;
1225         info->params.encoding        = tmp_params.encoding;
1226         info->params.clock_speed     = tmp_params.clock_speed;
1227         info->params.addr_filter     = tmp_params.addr_filter;
1228         info->params.crc_type        = tmp_params.crc_type;
1229         info->params.preamble_length = tmp_params.preamble_length;
1230         info->params.preamble        = tmp_params.preamble;
1231         info->params.data_rate       = tmp_params.data_rate;
1232         info->params.data_bits       = tmp_params.data_bits;
1233         info->params.stop_bits       = tmp_params.stop_bits;
1234         info->params.parity          = tmp_params.parity;
1235         spin_unlock(&info->lock);
1236
1237         change_params(info);
1238
1239         return 0;
1240 }
1241
1242 static long slgt_compat_ioctl(struct tty_struct *tty, struct file *file,
1243                          unsigned int cmd, unsigned long arg)
1244 {
1245         struct slgt_info *info = tty->driver_data;
1246         int rc = -ENOIOCTLCMD;
1247
1248         if (sanity_check(info, tty->name, "compat_ioctl"))
1249                 return -ENODEV;
1250         DBGINFO(("%s compat_ioctl() cmd=%08X\n", info->device_name, cmd));
1251
1252         switch (cmd) {
1253
1254         case MGSL_IOCSPARAMS32:
1255                 rc = set_params32(info, compat_ptr(arg));
1256                 break;
1257
1258         case MGSL_IOCGPARAMS32:
1259                 rc = get_params32(info, compat_ptr(arg));
1260                 break;
1261
1262         case MGSL_IOCGPARAMS:
1263         case MGSL_IOCSPARAMS:
1264         case MGSL_IOCGTXIDLE:
1265         case MGSL_IOCGSTATS:
1266         case MGSL_IOCWAITEVENT:
1267         case MGSL_IOCGIF:
1268         case MGSL_IOCSGPIO:
1269         case MGSL_IOCGGPIO:
1270         case MGSL_IOCWAITGPIO:
1271         case TIOCGICOUNT:
1272                 rc = ioctl(tty, file, cmd, (unsigned long)(compat_ptr(arg)));
1273                 break;
1274
1275         case MGSL_IOCSTXIDLE:
1276         case MGSL_IOCTXENABLE:
1277         case MGSL_IOCRXENABLE:
1278         case MGSL_IOCTXABORT:
1279         case TIOCMIWAIT:
1280         case MGSL_IOCSIF:
1281                 rc = ioctl(tty, file, cmd, arg);
1282                 break;
1283         }
1284
1285         DBGINFO(("%s compat_ioctl() cmd=%08X rc=%d\n", info->device_name, cmd, rc));
1286         return rc;
1287 }
1288 #else
1289 #define slgt_compat_ioctl NULL
1290 #endif /* ifdef CONFIG_COMPAT */
1291
1292 /*
1293  * proc fs support
1294  */
1295 static inline int line_info(char *buf, struct slgt_info *info)
1296 {
1297         char stat_buf[30];
1298         int ret;
1299         unsigned long flags;
1300
1301         ret = sprintf(buf, "%s: IO=%08X IRQ=%d MaxFrameSize=%u\n",
1302                       info->device_name, info->phys_reg_addr,
1303                       info->irq_level, info->max_frame_size);
1304
1305         /* output current serial signal states */
1306         spin_lock_irqsave(&info->lock,flags);
1307         get_signals(info);
1308         spin_unlock_irqrestore(&info->lock,flags);
1309
1310         stat_buf[0] = 0;
1311         stat_buf[1] = 0;
1312         if (info->signals & SerialSignal_RTS)
1313                 strcat(stat_buf, "|RTS");
1314         if (info->signals & SerialSignal_CTS)
1315                 strcat(stat_buf, "|CTS");
1316         if (info->signals & SerialSignal_DTR)
1317                 strcat(stat_buf, "|DTR");
1318         if (info->signals & SerialSignal_DSR)
1319                 strcat(stat_buf, "|DSR");
1320         if (info->signals & SerialSignal_DCD)
1321                 strcat(stat_buf, "|CD");
1322         if (info->signals & SerialSignal_RI)
1323                 strcat(stat_buf, "|RI");
1324
1325         if (info->params.mode != MGSL_MODE_ASYNC) {
1326                 ret += sprintf(buf+ret, "\tHDLC txok:%d rxok:%d",
1327                                info->icount.txok, info->icount.rxok);
1328                 if (info->icount.txunder)
1329                         ret += sprintf(buf+ret, " txunder:%d", info->icount.txunder);
1330                 if (info->icount.txabort)
1331                         ret += sprintf(buf+ret, " txabort:%d", info->icount.txabort);
1332                 if (info->icount.rxshort)
1333                         ret += sprintf(buf+ret, " rxshort:%d", info->icount.rxshort);
1334                 if (info->icount.rxlong)
1335                         ret += sprintf(buf+ret, " rxlong:%d", info->icount.rxlong);
1336                 if (info->icount.rxover)
1337                         ret += sprintf(buf+ret, " rxover:%d", info->icount.rxover);
1338                 if (info->icount.rxcrc)
1339                         ret += sprintf(buf+ret, " rxcrc:%d", info->icount.rxcrc);
1340         } else {
1341                 ret += sprintf(buf+ret, "\tASYNC tx:%d rx:%d",
1342                                info->icount.tx, info->icount.rx);
1343                 if (info->icount.frame)
1344                         ret += sprintf(buf+ret, " fe:%d", info->icount.frame);
1345                 if (info->icount.parity)
1346                         ret += sprintf(buf+ret, " pe:%d", info->icount.parity);
1347                 if (info->icount.brk)
1348                         ret += sprintf(buf+ret, " brk:%d", info->icount.brk);
1349                 if (info->icount.overrun)
1350                         ret += sprintf(buf+ret, " oe:%d", info->icount.overrun);
1351         }
1352
1353         /* Append serial signal status to end */
1354         ret += sprintf(buf+ret, " %s\n", stat_buf+1);
1355
1356         ret += sprintf(buf+ret, "\ttxactive=%d bh_req=%d bh_run=%d pending_bh=%x\n",
1357                        info->tx_active,info->bh_requested,info->bh_running,
1358                        info->pending_bh);
1359
1360         return ret;
1361 }
1362
1363 /* Called to print information about devices
1364  */
1365 static int read_proc(char *page, char **start, off_t off, int count,
1366                      int *eof, void *data)
1367 {
1368         int len = 0, l;
1369         off_t   begin = 0;
1370         struct slgt_info *info;
1371
1372         len += sprintf(page, "synclink_gt driver:%s\n", driver_version);
1373
1374         info = slgt_device_list;
1375         while( info ) {
1376                 l = line_info(page + len, info);
1377                 len += l;
1378                 if (len+begin > off+count)
1379                         goto done;
1380                 if (len+begin < off) {
1381                         begin += len;
1382                         len = 0;
1383                 }
1384                 info = info->next_device;
1385         }
1386
1387         *eof = 1;
1388 done:
1389         if (off >= len+begin)
1390                 return 0;
1391         *start = page + (off-begin);
1392         return ((count < begin+len-off) ? count : begin+len-off);
1393 }
1394
1395 /*
1396  * return count of bytes in transmit buffer
1397  */
1398 static int chars_in_buffer(struct tty_struct *tty)
1399 {
1400         struct slgt_info *info = tty->driver_data;
1401         if (sanity_check(info, tty->name, "chars_in_buffer"))
1402                 return 0;
1403         DBGINFO(("%s chars_in_buffer()=%d\n", info->device_name, info->tx_count));
1404         return info->tx_count;
1405 }
1406
1407 /*
1408  * signal remote device to throttle send data (our receive data)
1409  */
1410 static void throttle(struct tty_struct * tty)
1411 {
1412         struct slgt_info *info = tty->driver_data;
1413         unsigned long flags;
1414
1415         if (sanity_check(info, tty->name, "throttle"))
1416                 return;
1417         DBGINFO(("%s throttle\n", info->device_name));
1418         if (I_IXOFF(tty))
1419                 send_xchar(tty, STOP_CHAR(tty));
1420         if (tty->termios->c_cflag & CRTSCTS) {
1421                 spin_lock_irqsave(&info->lock,flags);
1422                 info->signals &= ~SerialSignal_RTS;
1423                 set_signals(info);
1424                 spin_unlock_irqrestore(&info->lock,flags);
1425         }
1426 }
1427
1428 /*
1429  * signal remote device to stop throttling send data (our receive data)
1430  */
1431 static void unthrottle(struct tty_struct * tty)
1432 {
1433         struct slgt_info *info = tty->driver_data;
1434         unsigned long flags;
1435
1436         if (sanity_check(info, tty->name, "unthrottle"))
1437                 return;
1438         DBGINFO(("%s unthrottle\n", info->device_name));
1439         if (I_IXOFF(tty)) {
1440                 if (info->x_char)
1441                         info->x_char = 0;
1442                 else
1443                         send_xchar(tty, START_CHAR(tty));
1444         }
1445         if (tty->termios->c_cflag & CRTSCTS) {
1446                 spin_lock_irqsave(&info->lock,flags);
1447                 info->signals |= SerialSignal_RTS;
1448                 set_signals(info);
1449                 spin_unlock_irqrestore(&info->lock,flags);
1450         }
1451 }
1452
1453 /*
1454  * set or clear transmit break condition
1455  * break_state  -1=set break condition, 0=clear
1456  */
1457 static void set_break(struct tty_struct *tty, int break_state)
1458 {
1459         struct slgt_info *info = tty->driver_data;
1460         unsigned short value;
1461         unsigned long flags;
1462
1463         if (sanity_check(info, tty->name, "set_break"))
1464                 return;
1465         DBGINFO(("%s set_break(%d)\n", info->device_name, break_state));
1466
1467         spin_lock_irqsave(&info->lock,flags);
1468         value = rd_reg16(info, TCR);
1469         if (break_state == -1)
1470                 value |= BIT6;
1471         else
1472                 value &= ~BIT6;
1473         wr_reg16(info, TCR, value);
1474         spin_unlock_irqrestore(&info->lock,flags);
1475 }
1476
1477 #if SYNCLINK_GENERIC_HDLC
1478
1479 /**
1480  * called by generic HDLC layer when protocol selected (PPP, frame relay, etc.)
1481  * set encoding and frame check sequence (FCS) options
1482  *
1483  * dev       pointer to network device structure
1484  * encoding  serial encoding setting
1485  * parity    FCS setting
1486  *
1487  * returns 0 if success, otherwise error code
1488  */
1489 static int hdlcdev_attach(struct net_device *dev, unsigned short encoding,
1490                           unsigned short parity)
1491 {
1492         struct slgt_info *info = dev_to_port(dev);
1493         unsigned char  new_encoding;
1494         unsigned short new_crctype;
1495
1496         /* return error if TTY interface open */
1497         if (info->port.count)
1498                 return -EBUSY;
1499
1500         DBGINFO(("%s hdlcdev_attach\n", info->device_name));
1501
1502         switch (encoding)
1503         {
1504         case ENCODING_NRZ:        new_encoding = HDLC_ENCODING_NRZ; break;
1505         case ENCODING_NRZI:       new_encoding = HDLC_ENCODING_NRZI_SPACE; break;
1506         case ENCODING_FM_MARK:    new_encoding = HDLC_ENCODING_BIPHASE_MARK; break;
1507         case ENCODING_FM_SPACE:   new_encoding = HDLC_ENCODING_BIPHASE_SPACE; break;
1508         case ENCODING_MANCHESTER: new_encoding = HDLC_ENCODING_BIPHASE_LEVEL; break;
1509         default: return -EINVAL;
1510         }
1511
1512         switch (parity)
1513         {
1514         case PARITY_NONE:            new_crctype = HDLC_CRC_NONE; break;
1515         case PARITY_CRC16_PR1_CCITT: new_crctype = HDLC_CRC_16_CCITT; break;
1516         case PARITY_CRC32_PR1_CCITT: new_crctype = HDLC_CRC_32_CCITT; break;
1517         default: return -EINVAL;
1518         }
1519
1520         info->params.encoding = new_encoding;
1521         info->params.crc_type = new_crctype;
1522
1523         /* if network interface up, reprogram hardware */
1524         if (info->netcount)
1525                 program_hw(info);
1526
1527         return 0;
1528 }
1529
1530 /**
1531  * called by generic HDLC layer to send frame
1532  *
1533  * skb  socket buffer containing HDLC frame
1534  * dev  pointer to network device structure
1535  *
1536  * returns 0 if success, otherwise error code
1537  */
1538 static int hdlcdev_xmit(struct sk_buff *skb, struct net_device *dev)
1539 {
1540         struct slgt_info *info = dev_to_port(dev);
1541         struct net_device_stats *stats = hdlc_stats(dev);
1542         unsigned long flags;
1543
1544         DBGINFO(("%s hdlc_xmit\n", dev->name));
1545
1546         /* stop sending until this frame completes */
1547         netif_stop_queue(dev);
1548
1549         /* copy data to device buffers */
1550         info->tx_count = skb->len;
1551         tx_load(info, skb->data, skb->len);
1552
1553         /* update network statistics */
1554         stats->tx_packets++;
1555         stats->tx_bytes += skb->len;
1556
1557         /* done with socket buffer, so free it */
1558         dev_kfree_skb(skb);
1559
1560         /* save start time for transmit timeout detection */
1561         dev->trans_start = jiffies;
1562
1563         /* start hardware transmitter if necessary */
1564         spin_lock_irqsave(&info->lock,flags);
1565         if (!info->tx_active)
1566                 tx_start(info);
1567         spin_unlock_irqrestore(&info->lock,flags);
1568
1569         return 0;
1570 }
1571
1572 /**
1573  * called by network layer when interface enabled
1574  * claim resources and initialize hardware
1575  *
1576  * dev  pointer to network device structure
1577  *
1578  * returns 0 if success, otherwise error code
1579  */
1580 static int hdlcdev_open(struct net_device *dev)
1581 {
1582         struct slgt_info *info = dev_to_port(dev);
1583         int rc;
1584         unsigned long flags;
1585
1586         if (!try_module_get(THIS_MODULE))
1587                 return -EBUSY;
1588
1589         DBGINFO(("%s hdlcdev_open\n", dev->name));
1590
1591         /* generic HDLC layer open processing */
1592         if ((rc = hdlc_open(dev)))
1593                 return rc;
1594
1595         /* arbitrate between network and tty opens */
1596         spin_lock_irqsave(&info->netlock, flags);
1597         if (info->port.count != 0 || info->netcount != 0) {
1598                 DBGINFO(("%s hdlc_open busy\n", dev->name));
1599                 spin_unlock_irqrestore(&info->netlock, flags);
1600                 return -EBUSY;
1601         }
1602         info->netcount=1;
1603         spin_unlock_irqrestore(&info->netlock, flags);
1604
1605         /* claim resources and init adapter */
1606         if ((rc = startup(info)) != 0) {
1607                 spin_lock_irqsave(&info->netlock, flags);
1608                 info->netcount=0;
1609                 spin_unlock_irqrestore(&info->netlock, flags);
1610                 return rc;
1611         }
1612
1613         /* assert DTR and RTS, apply hardware settings */
1614         info->signals |= SerialSignal_RTS + SerialSignal_DTR;
1615         program_hw(info);
1616
1617         /* enable network layer transmit */
1618         dev->trans_start = jiffies;
1619         netif_start_queue(dev);
1620
1621         /* inform generic HDLC layer of current DCD status */
1622         spin_lock_irqsave(&info->lock, flags);
1623         get_signals(info);
1624         spin_unlock_irqrestore(&info->lock, flags);
1625         if (info->signals & SerialSignal_DCD)
1626                 netif_carrier_on(dev);
1627         else
1628                 netif_carrier_off(dev);
1629         return 0;
1630 }
1631
1632 /**
1633  * called by network layer when interface is disabled
1634  * shutdown hardware and release resources
1635  *
1636  * dev  pointer to network device structure
1637  *
1638  * returns 0 if success, otherwise error code
1639  */
1640 static int hdlcdev_close(struct net_device *dev)
1641 {
1642         struct slgt_info *info = dev_to_port(dev);
1643         unsigned long flags;
1644
1645         DBGINFO(("%s hdlcdev_close\n", dev->name));
1646
1647         netif_stop_queue(dev);
1648
1649         /* shutdown adapter and release resources */
1650         shutdown(info);
1651
1652         hdlc_close(dev);
1653
1654         spin_lock_irqsave(&info->netlock, flags);
1655         info->netcount=0;
1656         spin_unlock_irqrestore(&info->netlock, flags);
1657
1658         module_put(THIS_MODULE);
1659         return 0;
1660 }
1661
1662 /**
1663  * called by network layer to process IOCTL call to network device
1664  *
1665  * dev  pointer to network device structure
1666  * ifr  pointer to network interface request structure
1667  * cmd  IOCTL command code
1668  *
1669  * returns 0 if success, otherwise error code
1670  */
1671 static int hdlcdev_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd)
1672 {
1673         const size_t size = sizeof(sync_serial_settings);
1674         sync_serial_settings new_line;
1675         sync_serial_settings __user *line = ifr->ifr_settings.ifs_ifsu.sync;
1676         struct slgt_info *info = dev_to_port(dev);
1677         unsigned int flags;
1678
1679         DBGINFO(("%s hdlcdev_ioctl\n", dev->name));
1680
1681         /* return error if TTY interface open */
1682         if (info->port.count)
1683                 return -EBUSY;
1684
1685         if (cmd != SIOCWANDEV)
1686                 return hdlc_ioctl(dev, ifr, cmd);
1687
1688         switch(ifr->ifr_settings.type) {
1689         case IF_GET_IFACE: /* return current sync_serial_settings */
1690
1691                 ifr->ifr_settings.type = IF_IFACE_SYNC_SERIAL;
1692                 if (ifr->ifr_settings.size < size) {
1693                         ifr->ifr_settings.size = size; /* data size wanted */
1694                         return -ENOBUFS;
1695                 }
1696
1697                 flags = info->params.flags & (HDLC_FLAG_RXC_RXCPIN | HDLC_FLAG_RXC_DPLL |
1698                                               HDLC_FLAG_RXC_BRG    | HDLC_FLAG_RXC_TXCPIN |
1699                                               HDLC_FLAG_TXC_TXCPIN | HDLC_FLAG_TXC_DPLL |
1700                                               HDLC_FLAG_TXC_BRG    | HDLC_FLAG_TXC_RXCPIN);
1701
1702                 switch (flags){
1703                 case (HDLC_FLAG_RXC_RXCPIN | HDLC_FLAG_TXC_TXCPIN): new_line.clock_type = CLOCK_EXT; break;
1704                 case (HDLC_FLAG_RXC_BRG    | HDLC_FLAG_TXC_BRG):    new_line.clock_type = CLOCK_INT; break;
1705                 case (HDLC_FLAG_RXC_RXCPIN | HDLC_FLAG_TXC_BRG):    new_line.clock_type = CLOCK_TXINT; break;
1706                 case (HDLC_FLAG_RXC_RXCPIN | HDLC_FLAG_TXC_RXCPIN): new_line.clock_type = CLOCK_TXFROMRX; break;
1707                 default: new_line.clock_type = CLOCK_DEFAULT;
1708                 }
1709
1710                 new_line.clock_rate = info->params.clock_speed;
1711                 new_line.loopback   = info->params.loopback ? 1:0;
1712
1713                 if (copy_to_user(line, &new_line, size))
1714                         return -EFAULT;
1715                 return 0;
1716
1717         case IF_IFACE_SYNC_SERIAL: /* set sync_serial_settings */
1718
1719                 if(!capable(CAP_NET_ADMIN))
1720                         return -EPERM;
1721                 if (copy_from_user(&new_line, line, size))
1722                         return -EFAULT;
1723
1724                 switch (new_line.clock_type)
1725                 {
1726                 case CLOCK_EXT:      flags = HDLC_FLAG_RXC_RXCPIN | HDLC_FLAG_TXC_TXCPIN; break;
1727                 case CLOCK_TXFROMRX: flags = HDLC_FLAG_RXC_RXCPIN | HDLC_FLAG_TXC_RXCPIN; break;
1728                 case CLOCK_INT:      flags = HDLC_FLAG_RXC_BRG    | HDLC_FLAG_TXC_BRG;    break;
1729                 case CLOCK_TXINT:    flags = HDLC_FLAG_RXC_RXCPIN | HDLC_FLAG_TXC_BRG;    break;
1730                 case CLOCK_DEFAULT:  flags = info->params.flags &
1731                                              (HDLC_FLAG_RXC_RXCPIN | HDLC_FLAG_RXC_DPLL |
1732                                               HDLC_FLAG_RXC_BRG    | HDLC_FLAG_RXC_TXCPIN |
1733                                               HDLC_FLAG_TXC_TXCPIN | HDLC_FLAG_TXC_DPLL |
1734                                               HDLC_FLAG_TXC_BRG    | HDLC_FLAG_TXC_RXCPIN); break;
1735                 default: return -EINVAL;
1736                 }
1737
1738                 if (new_line.loopback != 0 && new_line.loopback != 1)
1739                         return -EINVAL;
1740
1741                 info->params.flags &= ~(HDLC_FLAG_RXC_RXCPIN | HDLC_FLAG_RXC_DPLL |
1742                                         HDLC_FLAG_RXC_BRG    | HDLC_FLAG_RXC_TXCPIN |
1743                                         HDLC_FLAG_TXC_TXCPIN | HDLC_FLAG_TXC_DPLL |
1744                                         HDLC_FLAG_TXC_BRG    | HDLC_FLAG_TXC_RXCPIN);
1745                 info->params.flags |= flags;
1746
1747                 info->params.loopback = new_line.loopback;
1748
1749                 if (flags & (HDLC_FLAG_RXC_BRG | HDLC_FLAG_TXC_BRG))
1750                         info->params.clock_speed = new_line.clock_rate;
1751                 else
1752                         info->params.clock_speed = 0;
1753
1754                 /* if network interface up, reprogram hardware */
1755                 if (info->netcount)
1756                         program_hw(info);
1757                 return 0;
1758
1759         default:
1760                 return hdlc_ioctl(dev, ifr, cmd);
1761         }
1762 }
1763
1764 /**
1765  * called by network layer when transmit timeout is detected
1766  *
1767  * dev  pointer to network device structure
1768  */
1769 static void hdlcdev_tx_timeout(struct net_device *dev)
1770 {
1771         struct slgt_info *info = dev_to_port(dev);
1772         struct net_device_stats *stats = hdlc_stats(dev);
1773         unsigned long flags;
1774
1775         DBGINFO(("%s hdlcdev_tx_timeout\n", dev->name));
1776
1777         stats->tx_errors++;
1778         stats->tx_aborted_errors++;
1779
1780         spin_lock_irqsave(&info->lock,flags);
1781         tx_stop(info);
1782         spin_unlock_irqrestore(&info->lock,flags);
1783
1784         netif_wake_queue(dev);
1785 }
1786
1787 /**
1788  * called by device driver when transmit completes
1789  * reenable network layer transmit if stopped
1790  *
1791  * info  pointer to device instance information
1792  */
1793 static void hdlcdev_tx_done(struct slgt_info *info)
1794 {
1795         if (netif_queue_stopped(info->netdev))
1796                 netif_wake_queue(info->netdev);
1797 }
1798
1799 /**
1800  * called by device driver when frame received
1801  * pass frame to network layer
1802  *
1803  * info  pointer to device instance information
1804  * buf   pointer to buffer contianing frame data
1805  * size  count of data bytes in buf
1806  */
1807 static void hdlcdev_rx(struct slgt_info *info, char *buf, int size)
1808 {
1809         struct sk_buff *skb = dev_alloc_skb(size);
1810         struct net_device *dev = info->netdev;
1811         struct net_device_stats *stats = hdlc_stats(dev);
1812
1813         DBGINFO(("%s hdlcdev_rx\n", dev->name));
1814
1815         if (skb == NULL) {
1816                 DBGERR(("%s: can't alloc skb, drop packet\n", dev->name));
1817                 stats->rx_dropped++;
1818                 return;
1819         }
1820
1821         memcpy(skb_put(skb, size),buf,size);
1822
1823         skb->protocol = hdlc_type_trans(skb, info->netdev);
1824
1825         stats->rx_packets++;
1826         stats->rx_bytes += size;
1827
1828         netif_rx(skb);
1829
1830         info->netdev->last_rx = jiffies;
1831 }
1832
1833 /**
1834  * called by device driver when adding device instance
1835  * do generic HDLC initialization
1836  *
1837  * info  pointer to device instance information
1838  *
1839  * returns 0 if success, otherwise error code
1840  */
1841 static int hdlcdev_init(struct slgt_info *info)
1842 {
1843         int rc;
1844         struct net_device *dev;
1845         hdlc_device *hdlc;
1846
1847         /* allocate and initialize network and HDLC layer objects */
1848
1849         if (!(dev = alloc_hdlcdev(info))) {
1850                 printk(KERN_ERR "%s hdlc device alloc failure\n", info->device_name);
1851                 return -ENOMEM;
1852         }
1853
1854         /* for network layer reporting purposes only */
1855         dev->mem_start = info->phys_reg_addr;
1856         dev->mem_end   = info->phys_reg_addr + SLGT_REG_SIZE - 1;
1857         dev->irq       = info->irq_level;
1858
1859         /* network layer callbacks and settings */
1860         dev->do_ioctl       = hdlcdev_ioctl;
1861         dev->open           = hdlcdev_open;
1862         dev->stop           = hdlcdev_close;
1863         dev->tx_timeout     = hdlcdev_tx_timeout;
1864         dev->watchdog_timeo = 10*HZ;
1865         dev->tx_queue_len   = 50;
1866
1867         /* generic HDLC layer callbacks and settings */
1868         hdlc         = dev_to_hdlc(dev);
1869         hdlc->attach = hdlcdev_attach;
1870         hdlc->xmit   = hdlcdev_xmit;
1871
1872         /* register objects with HDLC layer */
1873         if ((rc = register_hdlc_device(dev))) {
1874                 printk(KERN_WARNING "%s:unable to register hdlc device\n",__FILE__);
1875                 free_netdev(dev);
1876                 return rc;
1877         }
1878
1879         info->netdev = dev;
1880         return 0;
1881 }
1882
1883 /**
1884  * called by device driver when removing device instance
1885  * do generic HDLC cleanup
1886  *
1887  * info  pointer to device instance information
1888  */
1889 static void hdlcdev_exit(struct slgt_info *info)
1890 {
1891         unregister_hdlc_device(info->netdev);
1892         free_netdev(info->netdev);
1893         info->netdev = NULL;
1894 }
1895
1896 #endif /* ifdef CONFIG_HDLC */
1897
1898 /*
1899  * get async data from rx DMA buffers
1900  */
1901 static void rx_async(struct slgt_info *info)
1902 {
1903         struct tty_struct *tty = info->port.tty;
1904         struct mgsl_icount *icount = &info->icount;
1905         unsigned int start, end;
1906         unsigned char *p;
1907         unsigned char status;
1908         struct slgt_desc *bufs = info->rbufs;
1909         int i, count;
1910         int chars = 0;
1911         int stat;
1912         unsigned char ch;
1913
1914         start = end = info->rbuf_current;
1915
1916         while(desc_complete(bufs[end])) {
1917                 count = desc_count(bufs[end]) - info->rbuf_index;
1918                 p     = bufs[end].buf + info->rbuf_index;
1919
1920                 DBGISR(("%s rx_async count=%d\n", info->device_name, count));
1921                 DBGDATA(info, p, count, "rx");
1922
1923                 for(i=0 ; i < count; i+=2, p+=2) {
1924                         ch = *p;
1925                         icount->rx++;
1926
1927                         stat = 0;
1928
1929                         if ((status = *(p+1) & (BIT1 + BIT0))) {
1930                                 if (status & BIT1)
1931                                         icount->parity++;
1932                                 else if (status & BIT0)
1933                                         icount->frame++;
1934                                 /* discard char if tty control flags say so */
1935                                 if (status & info->ignore_status_mask)
1936                                         continue;
1937                                 if (status & BIT1)
1938                                         stat = TTY_PARITY;
1939                                 else if (status & BIT0)
1940                                         stat = TTY_FRAME;
1941                         }
1942                         if (tty) {
1943                                 tty_insert_flip_char(tty, ch, stat);
1944                                 chars++;
1945                         }
1946                 }
1947
1948                 if (i < count) {
1949                         /* receive buffer not completed */
1950                         info->rbuf_index += i;
1951                         mod_timer(&info->rx_timer, jiffies + 1);
1952                         break;
1953                 }
1954
1955                 info->rbuf_index = 0;
1956                 free_rbufs(info, end, end);
1957
1958                 if (++end == info->rbuf_count)
1959                         end = 0;
1960
1961                 /* if entire list searched then no frame available */
1962                 if (end == start)
1963                         break;
1964         }
1965
1966         if (tty && chars)
1967                 tty_flip_buffer_push(tty);
1968 }
1969
1970 /*
1971  * return next bottom half action to perform
1972  */
1973 static int bh_action(struct slgt_info *info)
1974 {
1975         unsigned long flags;
1976         int rc;
1977
1978         spin_lock_irqsave(&info->lock,flags);
1979
1980         if (info->pending_bh & BH_RECEIVE) {
1981                 info->pending_bh &= ~BH_RECEIVE;
1982                 rc = BH_RECEIVE;
1983         } else if (info->pending_bh & BH_TRANSMIT) {
1984                 info->pending_bh &= ~BH_TRANSMIT;
1985                 rc = BH_TRANSMIT;
1986         } else if (info->pending_bh & BH_STATUS) {
1987                 info->pending_bh &= ~BH_STATUS;
1988                 rc = BH_STATUS;
1989         } else {
1990                 /* Mark BH routine as complete */
1991                 info->bh_running = false;
1992                 info->bh_requested = false;
1993                 rc = 0;
1994         }
1995
1996         spin_unlock_irqrestore(&info->lock,flags);
1997
1998         return rc;
1999 }
2000
2001 /*
2002  * perform bottom half processing
2003  */
2004 static void bh_handler(struct work_struct *work)
2005 {
2006         struct slgt_info *info = container_of(work, struct slgt_info, task);
2007         int action;
2008
2009         if (!info)
2010                 return;
2011         info->bh_running = true;
2012
2013         while((action = bh_action(info))) {
2014                 switch (action) {
2015                 case BH_RECEIVE:
2016                         DBGBH(("%s bh receive\n", info->device_name));
2017                         switch(info->params.mode) {
2018                         case MGSL_MODE_ASYNC:
2019                                 rx_async(info);
2020                                 break;
2021                         case MGSL_MODE_HDLC:
2022                                 while(rx_get_frame(info));
2023                                 break;
2024                         case MGSL_MODE_RAW:
2025                         case MGSL_MODE_MONOSYNC:
2026                         case MGSL_MODE_BISYNC:
2027                                 while(rx_get_buf(info));
2028                                 break;
2029                         }
2030                         /* restart receiver if rx DMA buffers exhausted */
2031                         if (info->rx_restart)
2032                                 rx_start(info);
2033                         break;
2034                 case BH_TRANSMIT:
2035                         bh_transmit(info);
2036                         break;
2037                 case BH_STATUS:
2038                         DBGBH(("%s bh status\n", info->device_name));
2039                         info->ri_chkcount = 0;
2040                         info->dsr_chkcount = 0;
2041                         info->dcd_chkcount = 0;
2042                         info->cts_chkcount = 0;
2043                         break;
2044                 default:
2045                         DBGBH(("%s unknown action\n", info->device_name));
2046                         break;
2047                 }
2048         }
2049         DBGBH(("%s bh_handler exit\n", info->device_name));
2050 }
2051
2052 static void bh_transmit(struct slgt_info *info)
2053 {
2054         struct tty_struct *tty = info->port.tty;
2055
2056         DBGBH(("%s bh_transmit\n", info->device_name));
2057         if (tty)
2058                 tty_wakeup(tty);
2059 }
2060
2061 static void dsr_change(struct slgt_info *info, unsigned short status)
2062 {
2063         if (status & BIT3) {
2064                 info->signals |= SerialSignal_DSR;
2065                 info->input_signal_events.dsr_up++;
2066         } else {
2067                 info->signals &= ~SerialSignal_DSR;
2068                 info->input_signal_events.dsr_down++;
2069         }
2070         DBGISR(("dsr_change %s signals=%04X\n", info->device_name, info->signals));
2071         if ((info->dsr_chkcount)++ == IO_PIN_SHUTDOWN_LIMIT) {
2072                 slgt_irq_off(info, IRQ_DSR);
2073                 return;
2074         }
2075         info->icount.dsr++;
2076         wake_up_interruptible(&info->status_event_wait_q);
2077         wake_up_interruptible(&info->event_wait_q);
2078         info->pending_bh |= BH_STATUS;
2079 }
2080
2081 static void cts_change(struct slgt_info *info, unsigned short status)
2082 {
2083         if (status & BIT2) {
2084                 info->signals |= SerialSignal_CTS;
2085                 info->input_signal_events.cts_up++;
2086         } else {
2087                 info->signals &= ~SerialSignal_CTS;
2088                 info->input_signal_events.cts_down++;
2089         }
2090         DBGISR(("cts_change %s signals=%04X\n", info->device_name, info->signals));
2091         if ((info->cts_chkcount)++ == IO_PIN_SHUTDOWN_LIMIT) {
2092                 slgt_irq_off(info, IRQ_CTS);
2093                 return;
2094         }
2095         info->icount.cts++;
2096         wake_up_interruptible(&info->status_event_wait_q);
2097         wake_up_interruptible(&info->event_wait_q);
2098         info->pending_bh |= BH_STATUS;
2099
2100         if (info->port.flags & ASYNC_CTS_FLOW) {
2101                 if (info->port.tty) {
2102                         if (info->port.tty->hw_stopped) {
2103                                 if (info->signals & SerialSignal_CTS) {
2104                                         info->port.tty->hw_stopped = 0;
2105                                         info->pending_bh |= BH_TRANSMIT;
2106                                         return;
2107                                 }
2108                         } else {
2109                                 if (!(info->signals & SerialSignal_CTS))
2110                                         info->port.tty->hw_stopped = 1;
2111                         }
2112                 }
2113         }
2114 }
2115
2116 static void dcd_change(struct slgt_info *info, unsigned short status)
2117 {
2118         if (status & BIT1) {
2119                 info->signals |= SerialSignal_DCD;
2120                 info->input_signal_events.dcd_up++;
2121         } else {
2122                 info->signals &= ~SerialSignal_DCD;
2123                 info->input_signal_events.dcd_down++;
2124         }
2125         DBGISR(("dcd_change %s signals=%04X\n", info->device_name, info->signals));
2126         if ((info->dcd_chkcount)++ == IO_PIN_SHUTDOWN_LIMIT) {
2127                 slgt_irq_off(info, IRQ_DCD);
2128                 return;
2129         }
2130         info->icount.dcd++;
2131 #if SYNCLINK_GENERIC_HDLC
2132         if (info->netcount) {
2133                 if (info->signals & SerialSignal_DCD)
2134                         netif_carrier_on(info->netdev);
2135                 else
2136                         netif_carrier_off(info->netdev);
2137         }
2138 #endif
2139         wake_up_interruptible(&info->status_event_wait_q);
2140         wake_up_interruptible(&info->event_wait_q);
2141         info->pending_bh |= BH_STATUS;
2142
2143         if (info->port.flags & ASYNC_CHECK_CD) {
2144                 if (info->signals & SerialSignal_DCD)
2145                         wake_up_interruptible(&info->port.open_wait);
2146                 else {
2147                         if (info->port.tty)
2148                                 tty_hangup(info->port.tty);
2149                 }
2150         }
2151 }
2152
2153 static void ri_change(struct slgt_info *info, unsigned short status)
2154 {
2155         if (status & BIT0) {
2156                 info->signals |= SerialSignal_RI;
2157                 info->input_signal_events.ri_up++;
2158         } else {
2159                 info->signals &= ~SerialSignal_RI;
2160                 info->input_signal_events.ri_down++;
2161         }
2162         DBGISR(("ri_change %s signals=%04X\n", info->device_name, info->signals));
2163         if ((info->ri_chkcount)++ == IO_PIN_SHUTDOWN_LIMIT) {
2164                 slgt_irq_off(info, IRQ_RI);
2165                 return;
2166         }
2167         info->icount.rng++;
2168         wake_up_interruptible(&info->status_event_wait_q);
2169         wake_up_interruptible(&info->event_wait_q);
2170         info->pending_bh |= BH_STATUS;
2171 }
2172
2173 static void isr_serial(struct slgt_info *info)
2174 {
2175         unsigned short status = rd_reg16(info, SSR);
2176
2177         DBGISR(("%s isr_serial status=%04X\n", info->device_name, status));
2178
2179         wr_reg16(info, SSR, status); /* clear pending */
2180
2181         info->irq_occurred = true;
2182
2183         if (info->params.mode == MGSL_MODE_ASYNC) {
2184                 if (status & IRQ_TXIDLE) {
2185                         if (info->tx_count)
2186                                 isr_txeom(info, status);
2187                 }
2188                 if ((status & IRQ_RXBREAK) && (status & RXBREAK)) {
2189                         info->icount.brk++;
2190                         /* process break detection if tty control allows */
2191                         if (info->port.tty) {
2192                                 if (!(status & info->ignore_status_mask)) {
2193                                         if (info->read_status_mask & MASK_BREAK) {
2194                                                 tty_insert_flip_char(info->port.tty, 0, TTY_BREAK);
2195                                                 if (info->port.flags & ASYNC_SAK)
2196                                                         do_SAK(info->port.tty);
2197                                         }
2198                                 }
2199                         }
2200                 }
2201         } else {
2202                 if (status & (IRQ_TXIDLE + IRQ_TXUNDER))
2203                         isr_txeom(info, status);
2204
2205                 if (status & IRQ_RXIDLE) {
2206                         if (status & RXIDLE)
2207                                 info->icount.rxidle++;
2208                         else
2209                                 info->icount.exithunt++;
2210                         wake_up_interruptible(&info->event_wait_q);
2211                 }
2212
2213                 if (status & IRQ_RXOVER)
2214                         rx_start(info);
2215         }
2216
2217         if (status & IRQ_DSR)
2218                 dsr_change(info, status);
2219         if (status & IRQ_CTS)
2220                 cts_change(info, status);
2221         if (status & IRQ_DCD)
2222                 dcd_change(info, status);
2223         if (status & IRQ_RI)
2224                 ri_change(info, status);
2225 }
2226
2227 static void isr_rdma(struct slgt_info *info)
2228 {
2229         unsigned int status = rd_reg32(info, RDCSR);
2230
2231         DBGISR(("%s isr_rdma status=%08x\n", info->device_name, status));
2232
2233         /* RDCSR (rx DMA control/status)
2234          *
2235          * 31..07  reserved
2236          * 06      save status byte to DMA buffer
2237          * 05      error
2238          * 04      eol (end of list)
2239          * 03      eob (end of buffer)
2240          * 02      IRQ enable
2241          * 01      reset
2242          * 00      enable
2243          */
2244         wr_reg32(info, RDCSR, status);  /* clear pending */
2245
2246         if (status & (BIT5 + BIT4)) {
2247                 DBGISR(("%s isr_rdma rx_restart=1\n", info->device_name));
2248                 info->rx_restart = true;
2249         }
2250         info->pending_bh |= BH_RECEIVE;
2251 }
2252
2253 static void isr_tdma(struct slgt_info *info)
2254 {
2255         unsigned int status = rd_reg32(info, TDCSR);
2256
2257         DBGISR(("%s isr_tdma status=%08x\n", info->device_name, status));
2258
2259         /* TDCSR (tx DMA control/status)
2260          *
2261          * 31..06  reserved
2262          * 05      error
2263          * 04      eol (end of list)
2264          * 03      eob (end of buffer)
2265          * 02      IRQ enable
2266          * 01      reset
2267          * 00      enable
2268          */
2269         wr_reg32(info, TDCSR, status);  /* clear pending */
2270
2271         if (status & (BIT5 + BIT4 + BIT3)) {
2272                 // another transmit buffer has completed
2273                 // run bottom half to get more send data from user
2274                 info->pending_bh |= BH_TRANSMIT;
2275         }
2276 }
2277
2278 static void isr_txeom(struct slgt_info *info, unsigned short status)
2279 {
2280         DBGISR(("%s txeom status=%04x\n", info->device_name, status));
2281
2282         slgt_irq_off(info, IRQ_TXDATA + IRQ_TXIDLE + IRQ_TXUNDER);
2283         tdma_reset(info);
2284         reset_tbufs(info);
2285         if (status & IRQ_TXUNDER) {
2286                 unsigned short val = rd_reg16(info, TCR);
2287                 wr_reg16(info, TCR, (unsigned short)(val | BIT2)); /* set reset bit */
2288                 wr_reg16(info, TCR, val); /* clear reset bit */
2289         }
2290
2291         if (info->tx_active) {
2292                 if (info->params.mode != MGSL_MODE_ASYNC) {
2293                         if (status & IRQ_TXUNDER)
2294                                 info->icount.txunder++;
2295                         else if (status & IRQ_TXIDLE)
2296                                 info->icount.txok++;
2297                 }
2298
2299                 info->tx_active = false;
2300                 info->tx_count = 0;
2301
2302                 del_timer(&info->tx_timer);
2303
2304                 if (info->params.mode != MGSL_MODE_ASYNC && info->drop_rts_on_tx_done) {
2305                         info->signals &= ~SerialSignal_RTS;
2306                         info->drop_rts_on_tx_done = false;
2307                         set_signals(info);
2308                 }
2309
2310 #if SYNCLINK_GENERIC_HDLC
2311                 if (info->netcount)
2312                         hdlcdev_tx_done(info);
2313                 else
2314 #endif
2315                 {
2316                         if (info->port.tty && (info->port.tty->stopped || info->port.tty->hw_stopped)) {
2317                                 tx_stop(info);
2318                                 return;
2319                         }
2320                         info->pending_bh |= BH_TRANSMIT;
2321                 }
2322         }
2323 }
2324
2325 static void isr_gpio(struct slgt_info *info, unsigned int changed, unsigned int state)
2326 {
2327         struct cond_wait *w, *prev;
2328
2329         /* wake processes waiting for specific transitions */
2330         for (w = info->gpio_wait_q, prev = NULL ; w != NULL ; w = w->next) {
2331                 if (w->data & changed) {
2332                         w->data = state;
2333                         wake_up_interruptible(&w->q);
2334                         if (prev != NULL)
2335                                 prev->next = w->next;
2336                         else
2337                                 info->gpio_wait_q = w->next;
2338                 } else
2339                         prev = w;
2340         }
2341 }
2342
2343 /* interrupt service routine
2344  *
2345  *      irq     interrupt number
2346  *      dev_id  device ID supplied during interrupt registration
2347  */
2348 static irqreturn_t slgt_interrupt(int dummy, void *dev_id)
2349 {
2350         struct slgt_info *info = dev_id;
2351         unsigned int gsr;
2352         unsigned int i;
2353
2354         DBGISR(("slgt_interrupt irq=%d entry\n", info->irq_level));
2355
2356         spin_lock(&info->lock);
2357
2358         while((gsr = rd_reg32(info, GSR) & 0xffffff00)) {
2359                 DBGISR(("%s gsr=%08x\n", info->device_name, gsr));
2360                 info->irq_occurred = true;
2361                 for(i=0; i < info->port_count ; i++) {
2362                         if (info->port_array[i] == NULL)
2363                                 continue;
2364                         if (gsr & (BIT8 << i))
2365                                 isr_serial(info->port_array[i]);
2366                         if (gsr & (BIT16 << (i*2)))
2367                                 isr_rdma(info->port_array[i]);
2368                         if (gsr & (BIT17 << (i*2)))
2369                                 isr_tdma(info->port_array[i]);
2370                 }
2371         }
2372
2373         if (info->gpio_present) {
2374                 unsigned int state;
2375                 unsigned int changed;
2376                 while ((changed = rd_reg32(info, IOSR)) != 0) {
2377                         DBGISR(("%s iosr=%08x\n", info->device_name, changed));
2378                         /* read latched state of GPIO signals */
2379                         state = rd_reg32(info, IOVR);
2380                         /* clear pending GPIO interrupt bits */
2381                         wr_reg32(info, IOSR, changed);
2382                         for (i=0 ; i < info->port_count ; i++) {
2383                                 if (info->port_array[i] != NULL)
2384                                         isr_gpio(info->port_array[i], changed, state);
2385                         }
2386                 }
2387         }
2388
2389         for(i=0; i < info->port_count ; i++) {
2390                 struct slgt_info *port = info->port_array[i];
2391
2392                 if (port && (port->port.count || port->netcount) &&
2393                     port->pending_bh && !port->bh_running &&
2394                     !port->bh_requested) {
2395                         DBGISR(("%s bh queued\n", port->device_name));
2396                         schedule_work(&port->task);
2397                         port->bh_requested = true;
2398                 }
2399         }
2400
2401         spin_unlock(&info->lock);
2402
2403         DBGISR(("slgt_interrupt irq=%d exit\n", info->irq_level));
2404         return IRQ_HANDLED;
2405 }
2406
2407 static int startup(struct slgt_info *info)
2408 {
2409         DBGINFO(("%s startup\n", info->device_name));
2410
2411         if (info->port.flags & ASYNC_INITIALIZED)
2412                 return 0;
2413
2414         if (!info->tx_buf) {
2415                 info->tx_buf = kmalloc(info->max_frame_size, GFP_KERNEL);
2416                 if (!info->tx_buf) {
2417                         DBGERR(("%s can't allocate tx buffer\n", info->device_name));
2418                         return -ENOMEM;
2419                 }
2420         }
2421
2422         info->pending_bh = 0;
2423
2424         memset(&info->icount, 0, sizeof(info->icount));
2425
2426         /* program hardware for current parameters */
2427         change_params(info);
2428
2429         if (info->port.tty)
2430                 clear_bit(TTY_IO_ERROR, &info->port.tty->flags);
2431
2432         info->port.flags |= ASYNC_INITIALIZED;
2433
2434         return 0;
2435 }
2436
2437 /*
2438  *  called by close() and hangup() to shutdown hardware
2439  */
2440 static void shutdown(struct slgt_info *info)
2441 {
2442         unsigned long flags;
2443
2444         if (!(info->port.flags & ASYNC_INITIALIZED))
2445                 return;
2446
2447         DBGINFO(("%s shutdown\n", info->device_name));
2448
2449         /* clear status wait queue because status changes */
2450         /* can't happen after shutting down the hardware */
2451         wake_up_interruptible(&info->status_event_wait_q);
2452         wake_up_interruptible(&info->event_wait_q);
2453
2454         del_timer_sync(&info->tx_timer);
2455         del_timer_sync(&info->rx_timer);
2456
2457         kfree(info->tx_buf);
2458         info->tx_buf = NULL;
2459
2460         spin_lock_irqsave(&info->lock,flags);
2461
2462         tx_stop(info);
2463         rx_stop(info);
2464
2465         slgt_irq_off(info, IRQ_ALL | IRQ_MASTER);
2466
2467         if (!info->port.tty || info->port.tty->termios->c_cflag & HUPCL) {
2468                 info->signals &= ~(SerialSignal_DTR + SerialSignal_RTS);
2469                 set_signals(info);
2470         }
2471
2472         flush_cond_wait(&info->gpio_wait_q);
2473
2474         spin_unlock_irqrestore(&info->lock,flags);
2475
2476         if (info->port.tty)
2477                 set_bit(TTY_IO_ERROR, &info->port.tty->flags);
2478
2479         info->port.flags &= ~ASYNC_INITIALIZED;
2480 }
2481
2482 static void program_hw(struct slgt_info *info)
2483 {
2484         unsigned long flags;
2485
2486         spin_lock_irqsave(&info->lock,flags);
2487
2488         rx_stop(info);
2489         tx_stop(info);
2490
2491         if (info->params.mode != MGSL_MODE_ASYNC ||
2492             info->netcount)
2493                 sync_mode(info);
2494         else
2495                 async_mode(info);
2496
2497         set_signals(info);
2498
2499         info->dcd_chkcount = 0;
2500         info->cts_chkcount = 0;
2501         info->ri_chkcount = 0;
2502         info->dsr_chkcount = 0;
2503
2504         slgt_irq_on(info, IRQ_DCD | IRQ_CTS | IRQ_DSR);
2505         get_signals(info);
2506
2507         if (info->netcount ||
2508             (info->port.tty && info->port.tty->termios->c_cflag & CREAD))
2509                 rx_start(info);
2510
2511         spin_unlock_irqrestore(&info->lock,flags);
2512 }
2513
2514 /*
2515  * reconfigure adapter based on new parameters
2516  */
2517 static void change_params(struct slgt_info *info)
2518 {
2519         unsigned cflag;
2520         int bits_per_char;
2521
2522         if (!info->port.tty || !info->port.tty->termios)
2523                 return;
2524         DBGINFO(("%s change_params\n", info->device_name));
2525
2526         cflag = info->port.tty->termios->c_cflag;
2527
2528         /* if B0 rate (hangup) specified then negate DTR and RTS */
2529         /* otherwise assert DTR and RTS */
2530         if (cflag & CBAUD)
2531                 info->signals |= SerialSignal_RTS + SerialSignal_DTR;
2532         else
2533                 info->signals &= ~(SerialSignal_RTS + SerialSignal_DTR);
2534
2535         /* byte size and parity */
2536
2537         switch (cflag & CSIZE) {
2538         case CS5: info->params.data_bits = 5; break;
2539         case CS6: info->params.data_bits = 6; break;
2540         case CS7: info->params.data_bits = 7; break;
2541         case CS8: info->params.data_bits = 8; break;
2542         default:  info->params.data_bits = 7; break;
2543         }
2544
2545         info->params.stop_bits = (cflag & CSTOPB) ? 2 : 1;
2546
2547         if (cflag & PARENB)
2548                 info->params.parity = (cflag & PARODD) ? ASYNC_PARITY_ODD : ASYNC_PARITY_EVEN;
2549         else
2550                 info->params.parity = ASYNC_PARITY_NONE;
2551
2552         /* calculate number of jiffies to transmit a full
2553          * FIFO (32 bytes) at specified data rate
2554          */
2555         bits_per_char = info->params.data_bits +
2556                         info->params.stop_bits + 1;
2557
2558         info->params.data_rate = tty_get_baud_rate(info->port.tty);
2559
2560         if (info->params.data_rate) {
2561                 info->timeout = (32*HZ*bits_per_char) /
2562                                 info->params.data_rate;
2563         }
2564         info->timeout += HZ/50;         /* Add .02 seconds of slop */
2565
2566         if (cflag & CRTSCTS)
2567                 info->port.flags |= ASYNC_CTS_FLOW;
2568         else
2569                 info->port.flags &= ~ASYNC_CTS_FLOW;
2570
2571         if (cflag & CLOCAL)
2572                 info->port.flags &= ~ASYNC_CHECK_CD;
2573         else
2574                 info->port.flags |= ASYNC_CHECK_CD;
2575
2576         /* process tty input control flags */
2577
2578         info->read_status_mask = IRQ_RXOVER;
2579         if (I_INPCK(info->port.tty))
2580                 info->read_status_mask |= MASK_PARITY | MASK_FRAMING;
2581         if (I_BRKINT(info->port.tty) || I_PARMRK(info->port.tty))
2582                 info->read_status_mask |= MASK_BREAK;
2583         if (I_IGNPAR(info->port.tty))
2584                 info->ignore_status_mask |= MASK_PARITY | MASK_FRAMING;
2585         if (I_IGNBRK(info->port.tty)) {
2586                 info->ignore_status_mask |= MASK_BREAK;
2587                 /* If ignoring parity and break indicators, ignore
2588                  * overruns too.  (For real raw support).
2589                  */
2590                 if (I_IGNPAR(info->port.tty))
2591                         info->ignore_status_mask |= MASK_OVERRUN;
2592         }
2593
2594         program_hw(info);
2595 }
2596
2597 static int get_stats(struct slgt_info *info, struct mgsl_icount __user *user_icount)
2598 {
2599         DBGINFO(("%s get_stats\n",  info->device_name));
2600         if (!user_icount) {
2601                 memset(&info->icount, 0, sizeof(info->icount));
2602         } else {
2603                 if (copy_to_user(user_icount, &info->icount, sizeof(struct mgsl_icount)))
2604                         return -EFAULT;
2605         }
2606         return 0;
2607 }
2608
2609 static int get_params(struct slgt_info *info, MGSL_PARAMS __user *user_params)
2610 {
2611         DBGINFO(("%s get_params\n", info->device_name));
2612         if (copy_to_user(user_params, &info->params, sizeof(MGSL_PARAMS)))
2613                 return -EFAULT;
2614         return 0;
2615 }
2616
2617 static int set_params(struct slgt_info *info, MGSL_PARAMS __user *new_params)
2618 {
2619         unsigned long flags;
2620         MGSL_PARAMS tmp_params;
2621
2622         DBGINFO(("%s set_params\n", info->device_name));
2623         if (copy_from_user(&tmp_params, new_params, sizeof(MGSL_PARAMS)))
2624                 return -EFAULT;
2625
2626         spin_lock_irqsave(&info->lock, flags);
2627         memcpy(&info->params, &tmp_params, sizeof(MGSL_PARAMS));
2628         spin_unlock_irqrestore(&info->lock, flags);
2629
2630         change_params(info);
2631
2632         return 0;
2633 }
2634
2635 static int get_txidle(struct slgt_info *info, int __user *idle_mode)
2636 {
2637         DBGINFO(("%s get_txidle=%d\n", info->device_name, info->idle_mode));
2638         if (put_user(info->idle_mode, idle_mode))
2639                 return -EFAULT;
2640         return 0;
2641 }
2642
2643 static int set_txidle(struct slgt_info *info, int idle_mode)
2644 {
2645         unsigned long flags;
2646         DBGINFO(("%s set_txidle(%d)\n", info->device_name, idle_mode));
2647         spin_lock_irqsave(&info->lock,flags);
2648         info->idle_mode = idle_mode;
2649         if (info->params.mode != MGSL_MODE_ASYNC)
2650                 tx_set_idle(info);
2651         spin_unlock_irqrestore(&info->lock,flags);
2652         return 0;
2653 }
2654
2655 static int tx_enable(struct slgt_info *info, int enable)
2656 {
2657         unsigned long flags;
2658         DBGINFO(("%s tx_enable(%d)\n", info->device_name, enable));
2659         spin_lock_irqsave(&info->lock,flags);
2660         if (enable) {
2661                 if (!info->tx_enabled)
2662                         tx_start(info);
2663         } else {
2664                 if (info->tx_enabled)
2665                         tx_stop(info);
2666         }
2667         spin_unlock_irqrestore(&info->lock,flags);
2668         return 0;
2669 }
2670
2671 /*
2672  * abort transmit HDLC frame
2673  */
2674 static int tx_abort(struct slgt_info *info)
2675 {
2676         unsigned long flags;
2677         DBGINFO(("%s tx_abort\n", info->device_name));
2678         spin_lock_irqsave(&info->lock,flags);
2679         tdma_reset(info);
2680         spin_unlock_irqrestore(&info->lock,flags);
2681         return 0;
2682 }
2683
2684 static int rx_enable(struct slgt_info *info, int enable)
2685 {
2686         unsigned long flags;
2687         DBGINFO(("%s rx_enable(%d)\n", info->device_name, enable));
2688         spin_lock_irqsave(&info->lock,flags);
2689         if (enable) {
2690                 if (!info->rx_enabled)
2691                         rx_start(info);
2692                 else if (enable == 2) {
2693                         /* force hunt mode (write 1 to RCR[3]) */
2694                         wr_reg16(info, RCR, rd_reg16(info, RCR) | BIT3);
2695                 }
2696         } else {
2697                 if (info->rx_enabled)
2698                         rx_stop(info);
2699         }
2700         spin_unlock_irqrestore(&info->lock,flags);
2701         return 0;
2702 }
2703
2704 /*
2705  *  wait for specified event to occur
2706  */
2707 static int wait_mgsl_event(struct slgt_info *info, int __user *mask_ptr)
2708 {
2709         unsigned long flags;
2710         int s;
2711         int rc=0;
2712         struct mgsl_icount cprev, cnow;
2713         int events;
2714         int mask;
2715         struct  _input_signal_events oldsigs, newsigs;
2716         DECLARE_WAITQUEUE(wait, current);
2717
2718         if (get_user(mask, mask_ptr))
2719                 return -EFAULT;
2720
2721         DBGINFO(("%s wait_mgsl_event(%d)\n", info->device_name, mask));
2722
2723         spin_lock_irqsave(&info->lock,flags);
2724
2725         /* return immediately if state matches requested events */
2726         get_signals(info);
2727         s = info->signals;
2728
2729         events = mask &
2730                 ( ((s & SerialSignal_DSR) ? MgslEvent_DsrActive:MgslEvent_DsrInactive) +
2731                   ((s & SerialSignal_DCD) ? MgslEvent_DcdActive:MgslEvent_DcdInactive) +
2732                   ((s & SerialSignal_CTS) ? MgslEvent_CtsActive:MgslEvent_CtsInactive) +
2733                   ((s & SerialSignal_RI)  ? MgslEvent_RiActive :MgslEvent_RiInactive) );
2734         if (events) {
2735                 spin_unlock_irqrestore(&info->lock,flags);
2736                 goto exit;
2737         }
2738
2739         /* save current irq counts */
2740         cprev = info->icount;
2741         oldsigs = info->input_signal_events;
2742
2743         /* enable hunt and idle irqs if needed */
2744         if (mask & (MgslEvent_ExitHuntMode+MgslEvent_IdleReceived)) {
2745                 unsigned short val = rd_reg16(info, SCR);
2746                 if (!(val & IRQ_RXIDLE))
2747                         wr_reg16(info, SCR, (unsigned short)(val | IRQ_RXIDLE));
2748         }
2749
2750         set_current_state(TASK_INTERRUPTIBLE);
2751         add_wait_queue(&info->event_wait_q, &wait);
2752
2753         spin_unlock_irqrestore(&info->lock,flags);
2754
2755         for(;;) {
2756                 schedule();
2757                 if (signal_pending(current)) {
2758                         rc = -ERESTARTSYS;
2759                         break;
2760                 }
2761
2762                 /* get current irq counts */
2763                 spin_lock_irqsave(&info->lock,flags);
2764                 cnow = info->icount;
2765                 newsigs = info->input_signal_events;
2766                 set_current_state(TASK_INTERRUPTIBLE);
2767                 spin_unlock_irqrestore(&info->lock,flags);
2768
2769                 /* if no change, wait aborted for some reason */
2770                 if (newsigs.dsr_up   == oldsigs.dsr_up   &&
2771                     newsigs.dsr_down == oldsigs.dsr_down &&
2772                     newsigs.dcd_up   == oldsigs.dcd_up   &&
2773                     newsigs.dcd_down == oldsigs.dcd_down &&
2774                     newsigs.cts_up   == oldsigs.cts_up   &&
2775                     newsigs.cts_down == oldsigs.cts_down &&
2776                     newsigs.ri_up    == oldsigs.ri_up    &&
2777                     newsigs.ri_down  == oldsigs.ri_down  &&
2778                     cnow.exithunt    == cprev.exithunt   &&
2779                     cnow.rxidle      == cprev.rxidle) {
2780                         rc = -EIO;
2781                         break;
2782                 }
2783
2784                 events = mask &
2785                         ( (newsigs.dsr_up   != oldsigs.dsr_up   ? MgslEvent_DsrActive:0)   +
2786                           (newsigs.dsr_down != oldsigs.dsr_down ? MgslEvent_DsrInactive:0) +
2787                           (newsigs.dcd_up   != oldsigs.dcd_up   ? MgslEvent_DcdActive:0)   +
2788                           (newsigs.dcd_down != oldsigs.dcd_down ? MgslEvent_DcdInactive:0) +
2789                           (newsigs.cts_up   != oldsigs.cts_up   ? MgslEvent_CtsActive:0)   +
2790                           (newsigs.cts_down != oldsigs.cts_down ? MgslEvent_CtsInactive:0) +
2791                           (newsigs.ri_up    != oldsigs.ri_up    ? MgslEvent_RiActive:0)    +
2792                           (newsigs.ri_down  != oldsigs.ri_down  ? MgslEvent_RiInactive:0)  +
2793                           (cnow.exithunt    != cprev.exithunt   ? MgslEvent_ExitHuntMode:0) +
2794                           (cnow.rxidle      != cprev.rxidle     ? MgslEvent_IdleReceived:0) );
2795                 if (events)
2796                         break;
2797
2798                 cprev = cnow;
2799                 oldsigs = newsigs;
2800         }
2801
2802         remove_wait_queue(&info->event_wait_q, &wait);
2803         set_current_state(TASK_RUNNING);
2804
2805
2806         if (mask & (MgslEvent_ExitHuntMode + MgslEvent_IdleReceived)) {
2807                 spin_lock_irqsave(&info->lock,flags);
2808                 if (!waitqueue_active(&info->event_wait_q)) {
2809                         /* disable enable exit hunt mode/idle rcvd IRQs */
2810                         wr_reg16(info, SCR,
2811                                 (unsigned short)(rd_reg16(info, SCR) & ~IRQ_RXIDLE));
2812                 }
2813                 spin_unlock_irqrestore(&info->lock,flags);
2814         }
2815 exit:
2816         if (rc == 0)
2817                 rc = put_user(events, mask_ptr);
2818         return rc;
2819 }
2820
2821 static int get_interface(struct slgt_info *info, int __user *if_mode)
2822 {
2823         DBGINFO(("%s get_interface=%x\n", info->device_name, info->if_mode));
2824         if (put_user(info->if_mode, if_mode))
2825                 return -EFAULT;
2826         return 0;
2827 }
2828
2829 static int set_interface(struct slgt_info *info, int if_mode)
2830 {
2831         unsigned long flags;
2832         unsigned short val;
2833
2834         DBGINFO(("%s set_interface=%x)\n", info->device_name, if_mode));
2835         spin_lock_irqsave(&info->lock,flags);
2836         info->if_mode = if_mode;
2837
2838         msc_set_vcr(info);
2839
2840         /* TCR (tx control) 07  1=RTS driver control */
2841         val = rd_reg16(info, TCR);
2842         if (info->if_mode & MGSL_INTERFACE_RTS_EN)
2843                 val |= BIT7;
2844         else
2845                 val &= ~BIT7;
2846         wr_reg16(info, TCR, val);
2847
2848         spin_unlock_irqrestore(&info->lock,flags);
2849         return 0;
2850 }
2851
2852 /*
2853  * set general purpose IO pin state and direction
2854  *
2855  * user_gpio fields:
2856  * state   each bit indicates a pin state
2857  * smask   set bit indicates pin state to set
2858  * dir     each bit indicates a pin direction (0=input, 1=output)
2859  * dmask   set bit indicates pin direction to set
2860  */
2861 static int set_gpio(struct slgt_info *info, struct gpio_desc __user *user_gpio)
2862 {
2863         unsigned long flags;
2864         struct gpio_desc gpio;
2865         __u32 data;
2866
2867         if (!info->gpio_present)
2868                 return -EINVAL;
2869         if (copy_from_user(&gpio, user_gpio, sizeof(gpio)))
2870                 return -EFAULT;
2871         DBGINFO(("%s set_gpio state=%08x smask=%08x dir=%08x dmask=%08x\n",
2872                  info->device_name, gpio.state, gpio.smask,
2873                  gpio.dir, gpio.dmask));
2874
2875         spin_lock_irqsave(&info->lock,flags);
2876         if (gpio.dmask) {
2877                 data = rd_reg32(info, IODR);
2878                 data |= gpio.dmask & gpio.dir;
2879                 data &= ~(gpio.dmask & ~gpio.dir);
2880                 wr_reg32(info, IODR, data);
2881         }
2882         if (gpio.smask) {
2883                 data = rd_reg32(info, IOVR);
2884                 data |= gpio.smask & gpio.state;
2885                 data &= ~(gpio.smask & ~gpio.state);
2886                 wr_reg32(info, IOVR, data);
2887         }
2888         spin_unlock_irqrestore(&info->lock,flags);
2889
2890         return 0;
2891 }
2892
2893 /*
2894  * get general purpose IO pin state and direction
2895  */
2896 static int get_gpio(struct slgt_info *info, struct gpio_desc __user *user_gpio)
2897 {
2898         struct gpio_desc gpio;
2899         if (!info->gpio_present)
2900                 return -EINVAL;
2901         gpio.state = rd_reg32(info, IOVR);
2902         gpio.smask = 0xffffffff;
2903         gpio.dir   = rd_reg32(info, IODR);
2904         gpio.dmask = 0xffffffff;
2905         if (copy_to_user(user_gpio, &gpio, sizeof(gpio)))
2906                 return -EFAULT;
2907         DBGINFO(("%s get_gpio state=%08x dir=%08x\n",
2908                  info->device_name, gpio.state, gpio.dir));
2909         return 0;
2910 }
2911
2912 /*
2913  * conditional wait facility
2914  */
2915 static void init_cond_wait(struct cond_wait *w, unsigned int data)
2916 {
2917         init_waitqueue_head(&w->q);
2918         init_waitqueue_entry(&w->wait, current);
2919         w->data = data;
2920 }
2921
2922 static void add_cond_wait(struct cond_wait **head, struct cond_wait *w)
2923 {
2924         set_current_state(TASK_INTERRUPTIBLE);
2925         add_wait_queue(&w->q, &w->wait);
2926         w->next = *head;
2927         *head = w;
2928 }
2929
2930 static void remove_cond_wait(struct cond_wait **head, struct cond_wait *cw)
2931 {
2932         struct cond_wait *w, *prev;
2933         remove_wait_queue(&cw->q, &cw->wait);
2934         set_current_state(TASK_RUNNING);
2935         for (w = *head, prev = NULL ; w != NULL ; prev = w, w = w->next) {
2936                 if (w == cw) {
2937                         if (prev != NULL)
2938                                 prev->next = w->next;
2939                         else
2940                                 *head = w->next;
2941                         break;
2942                 }
2943         }
2944 }
2945
2946 static void flush_cond_wait(struct cond_wait **head)
2947 {
2948         while (*head != NULL) {
2949                 wake_up_interruptible(&(*head)->q);
2950                 *head = (*head)->next;
2951         }
2952 }
2953
2954 /*
2955  * wait for general purpose I/O pin(s) to enter specified state
2956  *
2957  * user_gpio fields:
2958  * state - bit indicates target pin state
2959  * smask - set bit indicates watched pin
2960  *
2961  * The wait ends when at least one watched pin enters the specified
2962  * state. When 0 (no error) is returned, user_gpio->state is set to the
2963  * state of all GPIO pins when the wait ends.
2964  *
2965  * Note: Each pin may be a dedicated input, dedicated output, or
2966  * configurable input/output. The number and configuration of pins
2967  * varies with the specific adapter model. Only input pins (dedicated
2968  * or configured) can be monitored with this function.
2969  */
2970 static int wait_gpio(struct slgt_info *info, struct gpio_desc __user *user_gpio)
2971 {
2972         unsigned long flags;
2973         int rc = 0;
2974         struct gpio_desc gpio;
2975         struct cond_wait wait;
2976         u32 state;
2977
2978         if (!info->gpio_present)
2979                 return -EINVAL;
2980         if (copy_from_user(&gpio, user_gpio, sizeof(gpio)))
2981                 return -EFAULT;
2982         DBGINFO(("%s wait_gpio() state=%08x smask=%08x\n",
2983                  info->device_name, gpio.state, gpio.smask));
2984         /* ignore output pins identified by set IODR bit */
2985         if ((gpio.smask &= ~rd_reg32(info, IODR)) == 0)
2986                 return -EINVAL;
2987         init_cond_wait(&wait, gpio.smask);
2988
2989         spin_lock_irqsave(&info->lock, flags);
2990         /* enable interrupts for watched pins */
2991         wr_reg32(info, IOER, rd_reg32(info, IOER) | gpio.smask);
2992         /* get current pin states */
2993         state = rd_reg32(info, IOVR);
2994
2995         if (gpio.smask & ~(state ^ gpio.state)) {
2996                 /* already in target state */
2997                 gpio.state = state;
2998         } else {
2999                 /* wait for target state */
3000                 add_cond_wait(&info->gpio_wait_q, &wait);
3001                 spin_unlock_irqrestore(&info->lock, flags);
3002                 schedule();
3003                 if (signal_pending(current))
3004                         rc = -ERESTARTSYS;
3005                 else
3006                         gpio.state = wait.data;
3007                 spin_lock_irqsave(&info->lock, flags);
3008                 remove_cond_wait(&info->gpio_wait_q, &wait);
3009         }
3010
3011         /* disable all GPIO interrupts if no waiting processes */
3012         if (info->gpio_wait_q == NULL)
3013                 wr_reg32(info, IOER, 0);
3014         spin_unlock_irqrestore(&info->lock,flags);
3015
3016         if ((rc == 0) && copy_to_user(user_gpio, &gpio, sizeof(gpio)))
3017                 rc = -EFAULT;
3018         return rc;
3019 }
3020
3021 static int modem_input_wait(struct slgt_info *info,int arg)
3022 {
3023         unsigned long flags;
3024         int rc;
3025         struct mgsl_icount cprev, cnow;
3026         DECLARE_WAITQUEUE(wait, current);
3027
3028         /* save current irq counts */
3029         spin_lock_irqsave(&info->lock,flags);
3030         cprev = info->icount;
3031         add_wait_queue(&info->status_event_wait_q, &wait);
3032         set_current_state(TASK_INTERRUPTIBLE);
3033         spin_unlock_irqrestore(&info->lock,flags);
3034
3035         for(;;) {
3036                 schedule();
3037                 if (signal_pending(current)) {
3038                         rc = -ERESTARTSYS;
3039                         break;
3040                 }
3041
3042                 /* get new irq counts */
3043                 spin_lock_irqsave(&info->lock,flags);
3044                 cnow = info->icount;
3045                 set_current_state(TASK_INTERRUPTIBLE);
3046                 spin_unlock_irqrestore(&info->lock,flags);
3047
3048                 /* if no change, wait aborted for some reason */
3049                 if (cnow.rng == cprev.rng && cnow.dsr == cprev.dsr &&
3050                     cnow.dcd == cprev.dcd && cnow.cts == cprev.cts) {
3051                         rc = -EIO;
3052                         break;
3053                 }
3054
3055                 /* check for change in caller specified modem input */
3056                 if ((arg & TIOCM_RNG && cnow.rng != cprev.rng) ||
3057                     (arg & TIOCM_DSR && cnow.dsr != cprev.dsr) ||
3058                     (arg & TIOCM_CD  && cnow.dcd != cprev.dcd) ||
3059                     (arg & TIOCM_CTS && cnow.cts != cprev.cts)) {
3060                         rc = 0;
3061                         break;
3062                 }
3063
3064                 cprev = cnow;
3065         }
3066         remove_wait_queue(&info->status_event_wait_q, &wait);
3067         set_current_state(TASK_RUNNING);
3068         return rc;
3069 }
3070
3071 /*
3072  *  return state of serial control and status signals
3073  */
3074 static int tiocmget(struct tty_struct *tty, struct file *file)
3075 {
3076         struct slgt_info *info = tty->driver_data;
3077         unsigned int result;
3078         unsigned long flags;
3079
3080         spin_lock_irqsave(&info->lock,flags);
3081         get_signals(info);
3082         spin_unlock_irqrestore(&info->lock,flags);
3083
3084         result = ((info->signals & SerialSignal_RTS) ? TIOCM_RTS:0) +
3085                 ((info->signals & SerialSignal_DTR) ? TIOCM_DTR:0) +
3086                 ((info->signals & SerialSignal_DCD) ? TIOCM_CAR:0) +
3087                 ((info->signals & SerialSignal_RI)  ? TIOCM_RNG:0) +
3088                 ((info->signals & SerialSignal_DSR) ? TIOCM_DSR:0) +
3089                 ((info->signals & SerialSignal_CTS) ? TIOCM_CTS:0);
3090
3091         DBGINFO(("%s tiocmget value=%08X\n", info->device_name, result));
3092         return result;
3093 }
3094
3095 /*
3096  * set modem control signals (DTR/RTS)
3097  *
3098  *      cmd     signal command: TIOCMBIS = set bit TIOCMBIC = clear bit
3099  *              TIOCMSET = set/clear signal values
3100  *      value   bit mask for command
3101  */
3102 static int tiocmset(struct tty_struct *tty, struct file *file,
3103                     unsigned int set, unsigned int clear)
3104 {
3105         struct slgt_info *info = tty->driver_data;
3106         unsigned long flags;
3107
3108         DBGINFO(("%s tiocmset(%x,%x)\n", info->device_name, set, clear));
3109
3110         if (set & TIOCM_RTS)
3111                 info->signals |= SerialSignal_RTS;
3112         if (set & TIOCM_DTR)
3113                 info->signals |= SerialSignal_DTR;
3114         if (clear & TIOCM_RTS)
3115                 info->signals &= ~SerialSignal_RTS;
3116         if (clear & TIOCM_DTR)
3117                 info->signals &= ~SerialSignal_DTR;
3118
3119         spin_lock_irqsave(&info->lock,flags);
3120         set_signals(info);
3121         spin_unlock_irqrestore(&info->lock,flags);
3122         return 0;
3123 }
3124
3125 /*
3126  *  block current process until the device is ready to open
3127  */
3128 static int block_til_ready(struct tty_struct *tty, struct file *filp,
3129                            struct slgt_info *info)
3130 {
3131         DECLARE_WAITQUEUE(wait, current);
3132         int             retval;
3133         bool            do_clocal = false;
3134         bool            extra_count = false;
3135         unsigned long   flags;
3136
3137         DBGINFO(("%s block_til_ready\n", tty->driver->name));
3138
3139         if (filp->f_flags & O_NONBLOCK || tty->flags & (1 << TTY_IO_ERROR)){
3140                 /* nonblock mode is set or port is not enabled */
3141                 info->port.flags |= ASYNC_NORMAL_ACTIVE;
3142                 return 0;
3143         }
3144
3145         if (tty->termios->c_cflag & CLOCAL)
3146                 do_clocal = true;
3147
3148         /* Wait for carrier detect and the line to become
3149          * free (i.e., not in use by the callout).  While we are in
3150          * this loop, info->port.count is dropped by one, so that
3151          * close() knows when to free things.  We restore it upon
3152          * exit, either normal or abnormal.
3153          */
3154
3155         retval = 0;
3156         add_wait_queue(&info->port.open_wait, &wait);
3157
3158         spin_lock_irqsave(&info->lock, flags);
3159         if (!tty_hung_up_p(filp)) {
3160                 extra_count = true;
3161                 info->port.count--;
3162         }
3163         spin_unlock_irqrestore(&info->lock, flags);
3164         info->port.blocked_open++;
3165
3166         while (1) {
3167                 if ((tty->termios->c_cflag & CBAUD)) {
3168                         spin_lock_irqsave(&info->lock,flags);
3169                         info->signals |= SerialSignal_RTS + SerialSignal_DTR;
3170                         set_signals(info);
3171                         spin_unlock_irqrestore(&info->lock,flags);
3172                 }
3173
3174                 set_current_state(TASK_INTERRUPTIBLE);
3175
3176                 if (tty_hung_up_p(filp) || !(info->port.flags & ASYNC_INITIALIZED)){
3177                         retval = (info->port.flags & ASYNC_HUP_NOTIFY) ?
3178                                         -EAGAIN : -ERESTARTSYS;
3179                         break;
3180                 }
3181
3182                 spin_lock_irqsave(&info->lock,flags);
3183                 get_signals(info);
3184                 spin_unlock_irqrestore(&info->lock,flags);
3185
3186                 if (!(info->port.flags & ASYNC_CLOSING) &&
3187                     (do_clocal || (info->signals & SerialSignal_DCD)) ) {
3188                         break;
3189                 }
3190
3191                 if (signal_pending(current)) {
3192                         retval = -ERESTARTSYS;
3193                         break;
3194                 }
3195
3196                 DBGINFO(("%s block_til_ready wait\n", tty->driver->name));
3197                 schedule();
3198         }
3199
3200         set_current_state(TASK_RUNNING);
3201         remove_wait_queue(&info->port.open_wait, &wait);
3202
3203         if (extra_count)
3204                 info->port.count++;
3205         info->port.blocked_open--;
3206
3207         if (!retval)
3208                 info->port.flags |= ASYNC_NORMAL_ACTIVE;
3209
3210         DBGINFO(("%s block_til_ready ready, rc=%d\n", tty->driver->name, retval));
3211         return retval;
3212 }
3213
3214 static int alloc_tmp_rbuf(struct slgt_info *info)
3215 {
3216         info->tmp_rbuf = kmalloc(info->max_frame_size + 5, GFP_KERNEL);
3217         if (info->tmp_rbuf == NULL)
3218                 return -ENOMEM;
3219         return 0;
3220 }
3221
3222 static void free_tmp_rbuf(struct slgt_info *info)
3223 {
3224         kfree(info->tmp_rbuf);
3225         info->tmp_rbuf = NULL;
3226 }
3227
3228 /*
3229  * allocate DMA descriptor lists.
3230  */
3231 static int alloc_desc(struct slgt_info *info)
3232 {
3233         unsigned int i;
3234         unsigned int pbufs;
3235
3236         /* allocate memory to hold descriptor lists */
3237         info->bufs = pci_alloc_consistent(info->pdev, DESC_LIST_SIZE, &info->bufs_dma_addr);
3238         if (info->bufs == NULL)
3239                 return -ENOMEM;
3240
3241         memset(info->bufs, 0, DESC_LIST_SIZE);
3242
3243         info->rbufs = (struct slgt_desc*)info->bufs;
3244         info->tbufs = ((struct slgt_desc*)info->bufs) + info->rbuf_count;
3245
3246         pbufs = (unsigned int)info->bufs_dma_addr;
3247
3248         /*
3249          * Build circular lists of descriptors
3250          */
3251
3252         for (i=0; i < info->rbuf_count; i++) {
3253                 /* physical address of this descriptor */
3254                 info->rbufs[i].pdesc = pbufs + (i * sizeof(struct slgt_desc));
3255
3256                 /* physical address of next descriptor */
3257                 if (i == info->rbuf_count - 1)
3258                         info->rbufs[i].next = cpu_to_le32(pbufs);
3259                 else
3260                         info->rbufs[i].next = cpu_to_le32(pbufs + ((i+1) * sizeof(struct slgt_desc)));
3261                 set_desc_count(info->rbufs[i], DMABUFSIZE);
3262         }
3263
3264         for (i=0; i < info->tbuf_count; i++) {
3265                 /* physical address of this descriptor */
3266                 info->tbufs[i].pdesc = pbufs + ((info->rbuf_count + i) * sizeof(struct slgt_desc));
3267
3268                 /* physical address of next descriptor */
3269                 if (i == info->tbuf_count - 1)
3270                         info->tbufs[i].next = cpu_to_le32(pbufs + info->rbuf_count * sizeof(struct slgt_desc));
3271                 else
3272                         info->tbufs[i].next = cpu_to_le32(pbufs + ((info->rbuf_count + i + 1) * sizeof(struct slgt_desc)));
3273         }
3274
3275         return 0;
3276 }
3277
3278 static void free_desc(struct slgt_info *info)
3279 {
3280         if (info->bufs != NULL) {
3281                 pci_free_consistent(info->pdev, DESC_LIST_SIZE, info->bufs, info->bufs_dma_addr);
3282                 info->bufs  = NULL;
3283                 info->rbufs = NULL;
3284                 info->tbufs = NULL;
3285         }
3286 }
3287
3288 static int alloc_bufs(struct slgt_info *info, struct slgt_desc *bufs, int count)
3289 {
3290         int i;
3291         for (i=0; i < count; i++) {
3292                 if ((bufs[i].buf = pci_alloc_consistent(info->pdev, DMABUFSIZE, &bufs[i].buf_dma_addr)) == NULL)
3293                         return -ENOMEM;
3294                 bufs[i].pbuf  = cpu_to_le32((unsigned int)bufs[i].buf_dma_addr);
3295         }
3296         return 0;
3297 }
3298
3299 static void free_bufs(struct slgt_info *info, struct slgt_desc *bufs, int count)
3300 {
3301         int i;
3302         for (i=0; i < count; i++) {
3303                 if (bufs[i].buf == NULL)
3304                         continue;
3305                 pci_free_consistent(info->pdev, DMABUFSIZE, bufs[i].buf, bufs[i].buf_dma_addr);
3306                 bufs[i].buf = NULL;
3307         }
3308 }
3309
3310 static int alloc_dma_bufs(struct slgt_info *info)
3311 {
3312         info->rbuf_count = 32;
3313         info->tbuf_count = 32;
3314
3315         if (alloc_desc(info) < 0 ||
3316             alloc_bufs(info, info->rbufs, info->rbuf_count) < 0 ||
3317             alloc_bufs(info, info->tbufs, info->tbuf_count) < 0 ||
3318             alloc_tmp_rbuf(info) < 0) {
3319                 DBGERR(("%s DMA buffer alloc fail\n", info->device_name));
3320                 return -ENOMEM;
3321         }
3322         reset_rbufs(info);
3323         return 0;
3324 }
3325
3326 static void free_dma_bufs(struct slgt_info *info)
3327 {
3328         if (info->bufs) {
3329                 free_bufs(info, info->rbufs, info->rbuf_count);
3330                 free_bufs(info, info->tbufs, info->tbuf_count);
3331                 free_desc(info);
3332         }
3333         free_tmp_rbuf(info);
3334 }
3335
3336 static int claim_resources(struct slgt_info *info)
3337 {
3338         if (request_mem_region(info->phys_reg_addr, SLGT_REG_SIZE, "synclink_gt") == NULL) {
3339                 DBGERR(("%s reg addr conflict, addr=%08X\n",
3340                         info->device_name, info->phys_reg_addr));
3341                 info->init_error = DiagStatus_AddressConflict;
3342                 goto errout;
3343         }
3344         else
3345                 info->reg_addr_requested = true;
3346
3347         info->reg_addr = ioremap_nocache(info->phys_reg_addr, SLGT_REG_SIZE);
3348         if (!info->reg_addr) {
3349                 DBGERR(("%s cant map device registers, addr=%08X\n",
3350                         info->device_name, info->phys_reg_addr));
3351                 info->init_error = DiagStatus_CantAssignPciResources;
3352                 goto errout;
3353         }
3354         return 0;
3355
3356 errout:
3357         release_resources(info);
3358         return -ENODEV;
3359 }
3360
3361 static void release_resources(struct slgt_info *info)
3362 {
3363         if (info->irq_requested) {
3364                 free_irq(info->irq_level, info);
3365                 info->irq_requested = false;
3366         }
3367
3368         if (info->reg_addr_requested) {
3369                 release_mem_region(info->phys_reg_addr, SLGT_REG_SIZE);
3370                 info->reg_addr_requested = false;
3371         }
3372
3373         if (info->reg_addr) {
3374                 iounmap(info->reg_addr);
3375                 info->reg_addr = NULL;
3376         }
3377 }
3378
3379 /* Add the specified device instance data structure to the
3380  * global linked list of devices and increment the device count.
3381  */
3382 static void add_device(struct slgt_info *info)
3383 {
3384         char *devstr;
3385
3386         info->next_device = NULL;
3387         info->line = slgt_device_count;
3388         sprintf(info->device_name, "%s%d", tty_dev_prefix, info->line);
3389
3390         if (info->line < MAX_DEVICES) {
3391                 if (maxframe[info->line])
3392                         info->max_frame_size = maxframe[info->line];
3393                 info->dosyncppp = dosyncppp[info->line];
3394         }
3395
3396         slgt_device_count++;
3397
3398         if (!slgt_device_list)
3399                 slgt_device_list = info;
3400         else {
3401                 struct slgt_info *current_dev = slgt_device_list;
3402                 while(current_dev->next_device)
3403                         current_dev = current_dev->next_device;
3404                 current_dev->next_device = info;
3405         }
3406
3407         if (info->max_frame_size < 4096)
3408                 info->max_frame_size = 4096;
3409         else if (info->max_frame_size > 65535)
3410                 info->max_frame_size = 65535;
3411
3412         switch(info->pdev->device) {
3413         case SYNCLINK_GT_DEVICE_ID:
3414                 devstr = "GT";
3415                 break;
3416         case SYNCLINK_GT2_DEVICE_ID:
3417                 devstr = "GT2";
3418                 break;
3419         case SYNCLINK_GT4_DEVICE_ID:
3420                 devstr = "GT4";
3421                 break;
3422         case SYNCLINK_AC_DEVICE_ID:
3423                 devstr = "AC";
3424                 info->params.mode = MGSL_MODE_ASYNC;
3425                 break;
3426         default:
3427                 devstr = "(unknown model)";
3428         }
3429         printk("SyncLink %s %s IO=%08x IRQ=%d MaxFrameSize=%u\n",
3430                 devstr, info->device_name, info->phys_reg_addr,
3431                 info->irq_level, info->max_frame_size);
3432
3433 #if SYNCLINK_GENERIC_HDLC
3434         hdlcdev_init(info);
3435 #endif
3436 }
3437
3438 /*
3439  *  allocate device instance structure, return NULL on failure
3440  */
3441 static struct slgt_info *alloc_dev(int adapter_num, int port_num, struct pci_dev *pdev)
3442 {
3443         struct slgt_info *info;
3444
3445         info = kzalloc(sizeof(struct slgt_info), GFP_KERNEL);
3446
3447         if (!info) {
3448                 DBGERR(("%s device alloc failed adapter=%d port=%d\n",
3449                         driver_name, adapter_num, port_num));
3450         } else {
3451                 info->magic = MGSL_MAGIC;
3452                 INIT_WORK(&info->task, bh_handler);
3453                 info->max_frame_size = 4096;
3454                 info->raw_rx_size = DMABUFSIZE;
3455                 info->close_delay = 5*HZ/10;
3456                 info->closing_wait = 30*HZ;
3457                 tty_port_init(&info->port);
3458                 init_waitqueue_head(&info->status_event_wait_q);
3459                 init_waitqueue_head(&info->event_wait_q);
3460                 spin_lock_init(&info->netlock);
3461                 memcpy(&info->params,&default_params,sizeof(MGSL_PARAMS));
3462                 info->idle_mode = HDLC_TXIDLE_FLAGS;
3463                 info->adapter_num = adapter_num;
3464                 info->port_num = port_num;
3465
3466                 setup_timer(&info->tx_timer, tx_timeout, (unsigned long)info);
3467                 setup_timer(&info->rx_timer, rx_timeout, (unsigned long)info);
3468
3469                 /* Copy configuration info to device instance data */
3470                 info->pdev = pdev;
3471                 info->irq_level = pdev->irq;
3472                 info->phys_reg_addr = pci_resource_start(pdev,0);
3473
3474                 info->bus_type = MGSL_BUS_TYPE_PCI;
3475                 info->irq_flags = IRQF_SHARED;
3476
3477                 info->init_error = -1; /* assume error, set to 0 on successful init */
3478         }
3479
3480         return info;
3481 }
3482
3483 static void device_init(int adapter_num, struct pci_dev *pdev)
3484 {
3485         struct slgt_info *port_array[SLGT_MAX_PORTS];
3486         int i;
3487         int port_count = 1;
3488
3489         if (pdev->device == SYNCLINK_GT2_DEVICE_ID)
3490                 port_count = 2;
3491         else if (pdev->device == SYNCLINK_GT4_DEVICE_ID)
3492                 port_count = 4;
3493
3494         /* allocate device instances for all ports */
3495         for (i=0; i < port_count; ++i) {
3496                 port_array[i] = alloc_dev(adapter_num, i, pdev);
3497                 if (port_array[i] == NULL) {
3498                         for (--i; i >= 0; --i)
3499                                 kfree(port_array[i]);
3500                         return;
3501                 }
3502         }
3503
3504         /* give copy of port_array to all ports and add to device list  */
3505         for (i=0; i < port_count; ++i) {
3506                 memcpy(port_array[i]->port_array, port_array, sizeof(port_array));
3507                 add_device(port_array[i]);
3508                 port_array[i]->port_count = port_count;
3509                 spin_lock_init(&port_array[i]->lock);
3510         }
3511
3512         /* Allocate and claim adapter resources */
3513         if (!claim_resources(port_array[0])) {
3514
3515                 alloc_dma_bufs(port_array[0]);
3516
3517                 /* copy resource information from first port to others */
3518                 for (i = 1; i < port_count; ++i) {
3519                         port_array[i]->lock      = port_array[0]->lock;
3520                         port_array[i]->irq_level = port_array[0]->irq_level;
3521                         port_array[i]->reg_addr  = port_array[0]->reg_addr;
3522                         alloc_dma_bufs(port_array[i]);
3523                 }
3524
3525                 if (request_irq(port_array[0]->irq_level,
3526                                         slgt_interrupt,
3527                                         port_array[0]->irq_flags,
3528                                         port_array[0]->device_name,
3529                                         port_array[0]) < 0) {
3530                         DBGERR(("%s request_irq failed IRQ=%d\n",
3531                                 port_array[0]->device_name,
3532                                 port_array[0]->irq_level));
3533                 } else {
3534                         port_array[0]->irq_requested = true;
3535                         adapter_test(port_array[0]);
3536                         for (i=1 ; i < port_count ; i++) {
3537                                 port_array[i]->init_error = port_array[0]->init_error;
3538                                 port_array[i]->gpio_present = port_array[0]->gpio_present;
3539                         }
3540                 }
3541         }
3542
3543         for (i=0; i < port_count; ++i)
3544                 tty_register_device(serial_driver, port_array[i]->line, &(port_array[i]->pdev->dev));
3545 }
3546
3547 static int __devinit init_one(struct pci_dev *dev,
3548                               const struct pci_device_id *ent)
3549 {
3550         if (pci_enable_device(dev)) {
3551                 printk("error enabling pci device %p\n", dev);
3552                 return -EIO;
3553         }
3554         pci_set_master(dev);
3555         device_init(slgt_device_count, dev);
3556         return 0;
3557 }
3558
3559 static void __devexit remove_one(struct pci_dev *dev)
3560 {
3561 }
3562
3563 static const struct tty_operations ops = {
3564         .open = open,
3565         .close = close,
3566         .write = write,
3567         .put_char = put_char,
3568         .flush_chars = flush_chars,
3569         .write_room = write_room,
3570         .chars_in_buffer = chars_in_buffer,
3571         .flush_buffer = flush_buffer,
3572         .ioctl = ioctl,
3573         .compat_ioctl = slgt_compat_ioctl,
3574         .throttle = throttle,
3575         .unthrottle = unthrottle,
3576         .send_xchar = send_xchar,
3577         .break_ctl = set_break,
3578         .wait_until_sent = wait_until_sent,
3579         .read_proc = read_proc,
3580         .set_termios = set_termios,
3581         .stop = tx_hold,
3582         .start = tx_release,
3583         .hangup = hangup,
3584         .tiocmget = tiocmget,
3585         .tiocmset = tiocmset,
3586 };
3587
3588 static void slgt_cleanup(void)
3589 {
3590         int rc;
3591         struct slgt_info *info;
3592         struct slgt_info *tmp;
3593
3594         printk("unload %s %s\n", driver_name, driver_version);
3595
3596         if (serial_driver) {
3597                 for (info=slgt_device_list ; info != NULL ; info=info->next_device)
3598                         tty_unregister_device(serial_driver, info->line);
3599                 if ((rc = tty_unregister_driver(serial_driver)))
3600                         DBGERR(("tty_unregister_driver error=%d\n", rc));
3601                 put_tty_driver(serial_driver);
3602         }
3603
3604         /* reset devices */
3605         info = slgt_device_list;
3606         while(info) {
3607                 reset_port(info);
3608                 info = info->next_device;
3609         }
3610
3611         /* release devices */
3612         info = slgt_device_list;
3613         while(info) {
3614 #if SYNCLINK_GENERIC_HDLC
3615                 hdlcdev_exit(info);
3616 #endif
3617                 free_dma_bufs(info);
3618                 free_tmp_rbuf(info);
3619                 if (info->port_num == 0)
3620                         release_resources(info);
3621                 tmp = info;
3622                 info = info->next_device;
3623                 kfree(tmp);
3624         }
3625
3626         if (pci_registered)
3627                 pci_unregister_driver(&pci_driver);
3628 }
3629
3630 /*
3631  *  Driver initialization entry point.
3632  */
3633 static int __init slgt_init(void)
3634 {
3635         int rc;
3636
3637         printk("%s %s\n", driver_name, driver_version);
3638
3639         serial_driver = alloc_tty_driver(MAX_DEVICES);
3640         if (!serial_driver) {
3641                 printk("%s can't allocate tty driver\n", driver_name);
3642                 return -ENOMEM;
3643         }
3644
3645         /* Initialize the tty_driver structure */
3646
3647         serial_driver->owner = THIS_MODULE;
3648         serial_driver->driver_name = tty_driver_name;
3649         serial_driver->name = tty_dev_prefix;
3650         serial_driver->major = ttymajor;
3651         serial_driver->minor_start = 64;
3652         serial_driver->type = TTY_DRIVER_TYPE_SERIAL;
3653         serial_driver->subtype = SERIAL_TYPE_NORMAL;
3654         serial_driver->init_termios = tty_std_termios;
3655         serial_driver->init_termios.c_cflag =
3656                 B9600 | CS8 | CREAD | HUPCL | CLOCAL;
3657         serial_driver->init_termios.c_ispeed = 9600;
3658         serial_driver->init_termios.c_ospeed = 9600;
3659         serial_driver->flags = TTY_DRIVER_REAL_RAW | TTY_DRIVER_DYNAMIC_DEV;
3660         tty_set_operations(serial_driver, &ops);
3661         if ((rc = tty_register_driver(serial_driver)) < 0) {
3662                 DBGERR(("%s can't register serial driver\n", driver_name));
3663                 put_tty_driver(serial_driver);
3664                 serial_driver = NULL;
3665                 goto error;
3666         }
3667
3668         printk("%s %s, tty major#%d\n",
3669                 driver_name, driver_version,
3670                 serial_driver->major);
3671
3672         slgt_device_count = 0;
3673         if ((rc = pci_register_driver(&pci_driver)) < 0) {
3674                 printk("%s pci_register_driver error=%d\n", driver_name, rc);
3675                 goto error;
3676         }
3677         pci_registered = true;
3678
3679         if (!slgt_device_list)
3680                 printk("%s no devices found\n",driver_name);
3681
3682         return 0;
3683
3684 error:
3685         slgt_cleanup();
3686         return rc;
3687 }
3688
3689 static void __exit slgt_exit(void)
3690 {
3691         slgt_cleanup();
3692 }
3693
3694 module_init(slgt_init);
3695 module_exit(slgt_exit);
3696
3697 /*
3698  * register access routines
3699  */
3700
3701 #define CALC_REGADDR() \
3702         unsigned long reg_addr = ((unsigned long)info->reg_addr) + addr; \
3703         if (addr >= 0x80) \
3704                 reg_addr += (info->port_num) * 32;
3705
3706 static __u8 rd_reg8(struct slgt_info *info, unsigned int addr)
3707 {
3708         CALC_REGADDR();
3709         return readb((void __iomem *)reg_addr);
3710 }
3711
3712 static void wr_reg8(struct slgt_info *info, unsigned int addr, __u8 value)
3713 {
3714         CALC_REGADDR();
3715         writeb(value, (void __iomem *)reg_addr);
3716 }
3717
3718 static __u16 rd_reg16(struct slgt_info *info, unsigned int addr)
3719 {
3720         CALC_REGADDR();
3721         return readw((void __iomem *)reg_addr);
3722 }
3723
3724 static void wr_reg16(struct slgt_info *info, unsigned int addr, __u16 value)
3725 {
3726         CALC_REGADDR();
3727         writew(value, (void __iomem *)reg_addr);
3728 }
3729
3730 static __u32 rd_reg32(struct slgt_info *info, unsigned int addr)
3731 {
3732         CALC_REGADDR();
3733         return readl((void __iomem *)reg_addr);
3734 }
3735
3736 static void wr_reg32(struct slgt_info *info, unsigned int addr, __u32 value)
3737 {
3738         CALC_REGADDR();
3739         writel(value, (void __iomem *)reg_addr);
3740 }
3741
3742 static void rdma_reset(struct slgt_info *info)
3743 {
3744         unsigned int i;
3745
3746         /* set reset bit */
3747         wr_reg32(info, RDCSR, BIT1);
3748
3749         /* wait for enable bit cleared */
3750         for(i=0 ; i < 1000 ; i++)
3751                 if (!(rd_reg32(info, RDCSR) & BIT0))
3752                         break;
3753 }
3754
3755 static void tdma_reset(struct slgt_info *info)
3756 {
3757         unsigned int i;
3758
3759         /* set reset bit */
3760         wr_reg32(info, TDCSR, BIT1);
3761
3762         /* wait for enable bit cleared */
3763         for(i=0 ; i < 1000 ; i++)
3764                 if (!(rd_reg32(info, TDCSR) & BIT0))
3765                         break;
3766 }
3767
3768 /*
3769  * enable internal loopback
3770  * TxCLK and RxCLK are generated from BRG
3771  * and TxD is looped back to RxD internally.
3772  */
3773 static void enable_loopback(struct slgt_info *info)
3774 {
3775         /* SCR (serial control) BIT2=looopback enable */
3776         wr_reg16(info, SCR, (unsigned short)(rd_reg16(info, SCR) | BIT2));
3777
3778         if (info->params.mode != MGSL_MODE_ASYNC) {
3779                 /* CCR (clock control)
3780                  * 07..05  tx clock source (010 = BRG)
3781                  * 04..02  rx clock source (010 = BRG)
3782                  * 01      auxclk enable   (0 = disable)
3783                  * 00      BRG enable      (1 = enable)
3784                  *
3785                  * 0100 1001
3786                  */
3787                 wr_reg8(info, CCR, 0x49);
3788
3789                 /* set speed if available, otherwise use default */
3790                 if (info->params.clock_speed)
3791                         set_rate(info, info->params.clock_speed);
3792                 else
3793                         set_rate(info, 3686400);
3794         }
3795 }
3796
3797 /*
3798  *  set baud rate generator to specified rate
3799  */
3800 static void set_rate(struct slgt_info *info, u32 rate)
3801 {
3802         unsigned int div;
3803         static unsigned int osc = 14745600;
3804
3805         /* div = osc/rate - 1
3806          *
3807          * Round div up if osc/rate is not integer to
3808          * force to next slowest rate.
3809          */
3810
3811         if (rate) {
3812                 div = osc/rate;
3813                 if (!(osc % rate) && div)
3814                         div--;
3815                 wr_reg16(info, BDR, (unsigned short)div);
3816         }
3817 }
3818
3819 static void rx_stop(struct slgt_info *info)
3820 {
3821         unsigned short val;
3822
3823         /* disable and reset receiver */
3824         val = rd_reg16(info, RCR) & ~BIT1;          /* clear enable bit */
3825         wr_reg16(info, RCR, (unsigned short)(val | BIT2)); /* set reset bit */
3826         wr_reg16(info, RCR, val);                  /* clear reset bit */
3827
3828         slgt_irq_off(info, IRQ_RXOVER + IRQ_RXDATA + IRQ_RXIDLE);
3829
3830         /* clear pending rx interrupts */
3831         wr_reg16(info, SSR, IRQ_RXIDLE + IRQ_RXOVER);
3832
3833         rdma_reset(info);
3834
3835         info->rx_enabled = false;
3836         info->rx_restart = false;
3837 }
3838
3839 static void rx_start(struct slgt_info *info)
3840 {
3841         unsigned short val;
3842
3843         slgt_irq_off(info, IRQ_RXOVER + IRQ_RXDATA);
3844
3845         /* clear pending rx overrun IRQ */
3846         wr_reg16(info, SSR, IRQ_RXOVER);
3847
3848         /* reset and disable receiver */
3849         val = rd_reg16(info, RCR) & ~BIT1; /* clear enable bit */
3850         wr_reg16(info, RCR, (unsigned short)(val | BIT2)); /* set reset bit */
3851         wr_reg16(info, RCR, val);                  /* clear reset bit */
3852
3853         rdma_reset(info);
3854         reset_rbufs(info);
3855
3856         /* set 1st descriptor address */
3857         wr_reg32(info, RDDAR, info->rbufs[0].pdesc);
3858
3859         if (info->params.mode != MGSL_MODE_ASYNC) {
3860                 /* enable rx DMA and DMA interrupt */
3861                 wr_reg32(info, RDCSR, (BIT2 + BIT0));
3862         } else {
3863                 /* enable saving of rx status, rx DMA and DMA interrupt */
3864                 wr_reg32(info, RDCSR, (BIT6 + BIT2 + BIT0));
3865         }
3866
3867         slgt_irq_on(info, IRQ_RXOVER);
3868
3869         /* enable receiver */
3870         wr_reg16(info, RCR, (unsigned short)(rd_reg16(info, RCR) | BIT1));
3871
3872         info->rx_restart = false;
3873         info->rx_enabled = true;
3874 }
3875
3876 static void tx_start(struct slgt_info *info)
3877 {
3878         if (!info->tx_enabled) {
3879                 wr_reg16(info, TCR,
3880                          (unsigned short)((rd_reg16(info, TCR) | BIT1) & ~BIT2));
3881                 info->tx_enabled = true;
3882         }
3883
3884         if (info->tx_count) {
3885                 info->drop_rts_on_tx_done = false;
3886
3887                 if (info->params.mode != MGSL_MODE_ASYNC) {
3888                         if (info->params.flags & HDLC_FLAG_AUTO_RTS) {
3889                                 get_signals(info);
3890                                 if (!(info->signals & SerialSignal_RTS)) {
3891                                         info->signals |= SerialSignal_RTS;
3892                                         set_signals(info);
3893                                         info->drop_rts_on_tx_done = true;
3894                                 }
3895                         }
3896
3897                         slgt_irq_off(info, IRQ_TXDATA);
3898                         slgt_irq_on(info, IRQ_TXUNDER + IRQ_TXIDLE);
3899                         /* clear tx idle and underrun status bits */
3900                         wr_reg16(info, SSR, (unsigned short)(IRQ_TXIDLE + IRQ_TXUNDER));
3901                         if (info->params.mode == MGSL_MODE_HDLC)
3902                                 mod_timer(&info->tx_timer, jiffies +
3903                                                 msecs_to_jiffies(5000));
3904                 } else {
3905                         slgt_irq_off(info, IRQ_TXDATA);
3906                         slgt_irq_on(info, IRQ_TXIDLE);
3907                         /* clear tx idle status bit */
3908                         wr_reg16(info, SSR, IRQ_TXIDLE);
3909                 }
3910                 tdma_start(info);
3911                 info->tx_active = true;
3912         }
3913 }
3914
3915 /*
3916  * start transmit DMA if inactive and there are unsent buffers
3917  */
3918 static void tdma_start(struct slgt_info *info)
3919 {
3920         unsigned int i;
3921
3922         if (rd_reg32(info, TDCSR) & BIT0)
3923                 return;
3924
3925         /* transmit DMA inactive, check for unsent buffers */
3926         i = info->tbuf_start;
3927         while (!desc_count(info->tbufs[i])) {
3928                 if (++i == info->tbuf_count)
3929                         i = 0;
3930                 if (i == info->tbuf_current)
3931                         return;
3932         }
3933         info->tbuf_start = i;
3934
3935         /* there are unsent buffers, start transmit DMA */
3936
3937         /* reset needed if previous error condition */
3938         tdma_reset(info);
3939
3940         /* set 1st descriptor address */
3941         wr_reg32(info, TDDAR, info->tbufs[info->tbuf_start].pdesc);
3942         switch(info->params.mode) {
3943         case MGSL_MODE_RAW:
3944         case MGSL_MODE_MONOSYNC:
3945         case MGSL_MODE_BISYNC:
3946                 wr_reg32(info, TDCSR, BIT2 + BIT0); /* IRQ + DMA enable */
3947                 break;
3948         default:
3949                 wr_reg32(info, TDCSR, BIT0); /* DMA enable */
3950         }
3951 }
3952
3953 static void tx_stop(struct slgt_info *info)
3954 {
3955         unsigned short val;
3956
3957         del_timer(&info->tx_timer);
3958
3959         tdma_reset(info);
3960
3961         /* reset and disable transmitter */
3962         val = rd_reg16(info, TCR) & ~BIT1;          /* clear enable bit */
3963         wr_reg16(info, TCR, (unsigned short)(val | BIT2)); /* set reset bit */
3964
3965         slgt_irq_off(info, IRQ_TXDATA + IRQ_TXIDLE + IRQ_TXUNDER);
3966
3967         /* clear tx idle and underrun status bit */
3968         wr_reg16(info, SSR, (unsigned short)(IRQ_TXIDLE + IRQ_TXUNDER));
3969
3970         reset_tbufs(info);
3971
3972         info->tx_enabled = false;
3973         info->tx_active = false;
3974 }
3975
3976 static void reset_port(struct slgt_info *info)
3977 {
3978         if (!info->reg_addr)
3979                 return;
3980
3981         tx_stop(info);
3982         rx_stop(info);
3983
3984         info->signals &= ~(SerialSignal_DTR + SerialSignal_RTS);
3985         set_signals(info);
3986
3987         slgt_irq_off(info, IRQ_ALL | IRQ_MASTER);
3988 }
3989
3990 static void reset_adapter(struct slgt_info *info)
3991 {
3992         int i;
3993         for (i=0; i < info->port_count; ++i) {
3994                 if (info->port_array[i])
3995                         reset_port(info->port_array[i]);
3996         }
3997 }
3998
3999 static void async_mode(struct slgt_info *info)
4000 {
4001         unsigned short val;
4002
4003         slgt_irq_off(info, IRQ_ALL | IRQ_MASTER);
4004         tx_stop(info);
4005         rx_stop(info);
4006
4007         /* TCR (tx control)
4008          *
4009          * 15..13  mode, 010=async
4010          * 12..10  encoding, 000=NRZ
4011          * 09      parity enable
4012          * 08      1=odd parity, 0=even parity
4013          * 07      1=RTS driver control
4014          * 06      1=break enable
4015          * 05..04  character length
4016          *         00=5 bits
4017          *         01=6 bits
4018          *         10=7 bits
4019          *         11=8 bits
4020          * 03      0=1 stop bit, 1=2 stop bits
4021          * 02      reset
4022          * 01      enable
4023          * 00      auto-CTS enable
4024          */
4025         val = 0x4000;
4026
4027         if (info->if_mode & MGSL_INTERFACE_RTS_EN)
4028                 val |= BIT7;
4029
4030         if (info->params.parity != ASYNC_PARITY_NONE) {
4031                 val |= BIT9;
4032                 if (info->params.parity == ASYNC_PARITY_ODD)
4033                         val |= BIT8;
4034         }
4035
4036         switch (info->params.data_bits)
4037         {
4038         case 6: val |= BIT4; break;
4039         case 7: val |= BIT5; break;
4040         case 8: val |= BIT5 + BIT4; break;
4041         }
4042
4043         if (info->params.stop_bits != 1)
4044                 val |= BIT3;
4045
4046         if (info->params.flags & HDLC_FLAG_AUTO_CTS)
4047                 val |= BIT0;
4048
4049         wr_reg16(info, TCR, val);
4050
4051         /* RCR (rx control)
4052          *
4053          * 15..13  mode, 010=async
4054          * 12..10  encoding, 000=NRZ
4055          * 09      parity enable
4056          * 08      1=odd parity, 0=even parity
4057          * 07..06  reserved, must be 0
4058          * 05..04  character length
4059          *         00=5 bits
4060          *         01=6 bits
4061          *         10=7 bits
4062          *         11=8 bits
4063          * 03      reserved, must be zero
4064          * 02      reset
4065          * 01      enable
4066          * 00      auto-DCD enable
4067          */
4068         val = 0x4000;
4069
4070         if (info->params.parity != ASYNC_PARITY_NONE) {
4071                 val |= BIT9;
4072                 if (info->params.parity == ASYNC_PARITY_ODD)
4073                         val |= BIT8;
4074         }
4075
4076         switch (info->params.data_bits)
4077         {
4078         case 6: val |= BIT4; break;
4079         case 7: val |= BIT5; break;
4080         case 8: val |= BIT5 + BIT4; break;
4081         }
4082
4083         if (info->params.flags & HDLC_FLAG_AUTO_DCD)
4084                 val |= BIT0;
4085
4086         wr_reg16(info, RCR, val);
4087
4088         /* CCR (clock control)
4089          *
4090          * 07..05  011 = tx clock source is BRG/16
4091          * 04..02  010 = rx clock source is BRG
4092          * 01      0 = auxclk disabled
4093          * 00      1 = BRG enabled
4094          *
4095          * 0110 1001
4096          */
4097         wr_reg8(info, CCR, 0x69);
4098
4099         msc_set_vcr(info);
4100
4101         /* SCR (serial control)
4102          *
4103          * 15  1=tx req on FIFO half empty
4104          * 14  1=rx req on FIFO half full
4105          * 13  tx data  IRQ enable
4106          * 12  tx idle  IRQ enable
4107          * 11  rx break on IRQ enable
4108          * 10  rx data  IRQ enable
4109          * 09  rx break off IRQ enable
4110          * 08  overrun  IRQ enable
4111          * 07  DSR      IRQ enable
4112          * 06  CTS      IRQ enable
4113          * 05  DCD      IRQ enable
4114          * 04  RI       IRQ enable
4115          * 03  reserved, must be zero
4116          * 02  1=txd->rxd internal loopback enable
4117          * 01  reserved, must be zero
4118          * 00  1=master IRQ enable
4119          */
4120         val = BIT15 + BIT14 + BIT0;
4121         wr_reg16(info, SCR, val);
4122
4123         slgt_irq_on(info, IRQ_RXBREAK | IRQ_RXOVER);
4124
4125         set_rate(info, info->params.data_rate * 16);
4126
4127         if (info->params.loopback)
4128                 enable_loopback(info);
4129 }
4130
4131 static void sync_mode(struct slgt_info *info)
4132 {
4133         unsigned short val;
4134
4135         slgt_irq_off(info, IRQ_ALL | IRQ_MASTER);
4136         tx_stop(info);
4137         rx_stop(info);
4138
4139         /* TCR (tx control)
4140          *
4141          * 15..13  mode, 000=HDLC 001=raw 010=async 011=monosync 100=bisync
4142          * 12..10  encoding
4143          * 09      CRC enable
4144          * 08      CRC32
4145          * 07      1=RTS driver control
4146          * 06      preamble enable
4147          * 05..04  preamble length
4148          * 03      share open/close flag
4149          * 02      reset
4150          * 01      enable
4151          * 00      auto-CTS enable
4152          */
4153         val = 0;
4154
4155         switch(info->params.mode) {
4156         case MGSL_MODE_MONOSYNC: val |= BIT14 + BIT13; break;
4157         case MGSL_MODE_BISYNC:   val |= BIT15; break;
4158         case MGSL_MODE_RAW:      val |= BIT13; break;
4159         }
4160         if (info->if_mode & MGSL_INTERFACE_RTS_EN)
4161                 val |= BIT7;
4162
4163         switch(info->params.encoding)
4164         {
4165         case HDLC_ENCODING_NRZB:          val |= BIT10; break;
4166         case HDLC_ENCODING_NRZI_MARK:     val |= BIT11; break;
4167         case HDLC_ENCODING_NRZI:          val |= BIT11 + BIT10; break;
4168         case HDLC_ENCODING_BIPHASE_MARK:  val |= BIT12; break;
4169         case HDLC_ENCODING_BIPHASE_SPACE: val |= BIT12 + BIT10; break;
4170         case HDLC_ENCODING_BIPHASE_LEVEL: val |= BIT12 + BIT11; break;
4171         case HDLC_ENCODING_DIFF_BIPHASE_LEVEL: val |= BIT12 + BIT11 + BIT10; break;
4172         }
4173
4174         switch (info->params.crc_type & HDLC_CRC_MASK)
4175         {
4176         case HDLC_CRC_16_CCITT: val |= BIT9; break;
4177         case HDLC_CRC_32_CCITT: val |= BIT9 + BIT8; break;
4178         }
4179
4180         if (info->params.preamble != HDLC_PREAMBLE_PATTERN_NONE)
4181                 val |= BIT6;
4182
4183         switch (info->params.preamble_length)
4184         {
4185         case HDLC_PREAMBLE_LENGTH_16BITS: val |= BIT5; break;
4186         case HDLC_PREAMBLE_LENGTH_32BITS: val |= BIT4; break;
4187         case HDLC_PREAMBLE_LENGTH_64BITS: val |= BIT5 + BIT4; break;
4188         }
4189
4190         if (info->params.flags & HDLC_FLAG_AUTO_CTS)
4191                 val |= BIT0;
4192
4193         wr_reg16(info, TCR, val);
4194
4195         /* TPR (transmit preamble) */
4196
4197         switch (info->params.preamble)
4198         {
4199         case HDLC_PREAMBLE_PATTERN_FLAGS: val = 0x7e; break;
4200         case HDLC_PREAMBLE_PATTERN_ONES:  val = 0xff; break;
4201         case HDLC_PREAMBLE_PATTERN_ZEROS: val = 0x00; break;
4202         case HDLC_PREAMBLE_PATTERN_10:    val = 0x55; break;
4203         case HDLC_PREAMBLE_PATTERN_01:    val = 0xaa; break;
4204         default:                          val = 0x7e; break;
4205         }
4206         wr_reg8(info, TPR, (unsigned char)val);
4207
4208         /* RCR (rx control)
4209          *
4210          * 15..13  mode, 000=HDLC 001=raw 010=async 011=monosync 100=bisync
4211          * 12..10  encoding
4212          * 09      CRC enable
4213          * 08      CRC32
4214          * 07..03  reserved, must be 0
4215          * 02      reset
4216          * 01      enable
4217          * 00      auto-DCD enable
4218          */
4219         val = 0;
4220
4221         switch(info->params.mode) {
4222         case MGSL_MODE_MONOSYNC: val |= BIT14 + BIT13; break;
4223         case MGSL_MODE_BISYNC:   val |= BIT15; break;
4224         case MGSL_MODE_RAW:      val |= BIT13; break;
4225         }
4226
4227         switch(info->params.encoding)
4228         {
4229         case HDLC_ENCODING_NRZB:          val |= BIT10; break;
4230         case HDLC_ENCODING_NRZI_MARK:     val |= BIT11; break;
4231         case HDLC_ENCODING_NRZI:          val |= BIT11 + BIT10; break;
4232         case HDLC_ENCODING_BIPHASE_MARK:  val |= BIT12; break;
4233         case HDLC_ENCODING_BIPHASE_SPACE: val |= BIT12 + BIT10; break;
4234         case HDLC_ENCODING_BIPHASE_LEVEL: val |= BIT12 + BIT11; break;
4235         case HDLC_ENCODING_DIFF_BIPHASE_LEVEL: val |= BIT12 + BIT11 + BIT10; break;
4236         }
4237
4238         switch (info->params.crc_type & HDLC_CRC_MASK)
4239         {
4240         case HDLC_CRC_16_CCITT: val |= BIT9; break;
4241         case HDLC_CRC_32_CCITT: val |= BIT9 + BIT8; break;
4242         }
4243
4244         if (info->params.flags & HDLC_FLAG_AUTO_DCD)
4245                 val |= BIT0;
4246
4247         wr_reg16(info, RCR, val);
4248
4249         /* CCR (clock control)
4250          *
4251          * 07..05  tx clock source
4252          * 04..02  rx clock source
4253          * 01      auxclk enable
4254          * 00      BRG enable
4255          */
4256         val = 0;
4257
4258         if (info->params.flags & HDLC_FLAG_TXC_BRG)
4259         {
4260                 // when RxC source is DPLL, BRG generates 16X DPLL
4261                 // reference clock, so take TxC from BRG/16 to get
4262                 // transmit clock at actual data rate
4263                 if (info->params.flags & HDLC_FLAG_RXC_DPLL)
4264                         val |= BIT6 + BIT5;     /* 011, txclk = BRG/16 */
4265                 else
4266                         val |= BIT6;    /* 010, txclk = BRG */
4267         }
4268         else if (info->params.flags & HDLC_FLAG_TXC_DPLL)
4269                 val |= BIT7;    /* 100, txclk = DPLL Input */
4270         else if (info->params.flags & HDLC_FLAG_TXC_RXCPIN)
4271                 val |= BIT5;    /* 001, txclk = RXC Input */
4272
4273         if (info->params.flags & HDLC_FLAG_RXC_BRG)
4274                 val |= BIT3;    /* 010, rxclk = BRG */
4275         else if (info->params.flags & HDLC_FLAG_RXC_DPLL)
4276                 val |= BIT4;    /* 100, rxclk = DPLL */
4277         else if (info->params.flags & HDLC_FLAG_RXC_TXCPIN)
4278                 val |= BIT2;    /* 001, rxclk = TXC Input */
4279
4280         if (info->params.clock_speed)
4281                 val |= BIT1 + BIT0;
4282
4283         wr_reg8(info, CCR, (unsigned char)val);
4284
4285         if (info->params.flags & (HDLC_FLAG_TXC_DPLL + HDLC_FLAG_RXC_DPLL))
4286         {
4287                 // program DPLL mode
4288                 switch(info->params.encoding)
4289                 {
4290                 case HDLC_ENCODING_BIPHASE_MARK:
4291                 case HDLC_ENCODING_BIPHASE_SPACE:
4292                         val = BIT7; break;
4293                 case HDLC_ENCODING_BIPHASE_LEVEL:
4294                 case HDLC_ENCODING_DIFF_BIPHASE_LEVEL:
4295                         val = BIT7 + BIT6; break;
4296                 default: val = BIT6;    // NRZ encodings
4297                 }
4298                 wr_reg16(info, RCR, (unsigned short)(rd_reg16(info, RCR) | val));
4299
4300                 // DPLL requires a 16X reference clock from BRG
4301                 set_rate(info, info->params.clock_speed * 16);
4302         }
4303         else
4304                 set_rate(info, info->params.clock_speed);
4305
4306         tx_set_idle(info);
4307
4308         msc_set_vcr(info);
4309
4310         /* SCR (serial control)
4311          *
4312          * 15  1=tx req on FIFO half empty
4313          * 14  1=rx req on FIFO half full
4314          * 13  tx data  IRQ enable
4315          * 12  tx idle  IRQ enable
4316          * 11  underrun IRQ enable
4317          * 10  rx data  IRQ enable
4318          * 09  rx idle  IRQ enable
4319          * 08  overrun  IRQ enable
4320          * 07  DSR      IRQ enable
4321          * 06  CTS      IRQ enable
4322          * 05  DCD      IRQ enable
4323          * 04  RI       IRQ enable
4324          * 03  reserved, must be zero
4325          * 02  1=txd->rxd internal loopback enable
4326          * 01  reserved, must be zero
4327          * 00  1=master IRQ enable
4328          */
4329         wr_reg16(info, SCR, BIT15 + BIT14 + BIT0);
4330
4331         if (info->params.loopback)
4332                 enable_loopback(info);
4333 }
4334
4335 /*
4336  *  set transmit idle mode
4337  */
4338 static void tx_set_idle(struct slgt_info *info)
4339 {
4340         unsigned char val;
4341         unsigned short tcr;
4342
4343         /* if preamble enabled (tcr[6] == 1) then tx idle size = 8 bits
4344          * else tcr[5:4] = tx idle size: 00 = 8 bits, 01 = 16 bits
4345          */
4346         tcr = rd_reg16(info, TCR);
4347         if (info->idle_mode & HDLC_TXIDLE_CUSTOM_16) {
4348                 /* disable preamble, set idle size to 16 bits */
4349                 tcr = (tcr & ~(BIT6 + BIT5)) | BIT4;
4350                 /* MSB of 16 bit idle specified in tx preamble register (TPR) */
4351                 wr_reg8(info, TPR, (unsigned char)((info->idle_mode >> 8) & 0xff));
4352         } else if (!(tcr & BIT6)) {
4353                 /* preamble is disabled, set idle size to 8 bits */
4354                 tcr &= ~(BIT5 + BIT4);
4355         }
4356         wr_reg16(info, TCR, tcr);
4357
4358         if (info->idle_mode & (HDLC_TXIDLE_CUSTOM_8 | HDLC_TXIDLE_CUSTOM_16)) {
4359                 /* LSB of custom tx idle specified in tx idle register */
4360                 val = (unsigned char)(info->idle_mode & 0xff);
4361         } else {
4362                 /* standard 8 bit idle patterns */
4363                 switch(info->idle_mode)
4364                 {
4365                 case HDLC_TXIDLE_FLAGS:          val = 0x7e; break;
4366                 case HDLC_TXIDLE_ALT_ZEROS_ONES:
4367                 case HDLC_TXIDLE_ALT_MARK_SPACE: val = 0xaa; break;
4368                 case HDLC_TXIDLE_ZEROS:
4369                 case HDLC_TXIDLE_SPACE:          val = 0x00; break;
4370                 default:                         val = 0xff;
4371                 }
4372         }
4373
4374         wr_reg8(info, TIR, val);
4375 }
4376
4377 /*
4378  * get state of V24 status (input) signals
4379  */
4380 static void get_signals(struct slgt_info *info)
4381 {
4382         unsigned short status = rd_reg16(info, SSR);
4383
4384         /* clear all serial signals except DTR and RTS */
4385         info->signals &= SerialSignal_DTR + SerialSignal_RTS;
4386
4387         if (status & BIT3)
4388                 info->signals |= SerialSignal_DSR;
4389         if (status & BIT2)
4390                 info->signals |= SerialSignal_CTS;
4391         if (status & BIT1)
4392                 info->signals |= SerialSignal_DCD;
4393         if (status & BIT0)
4394                 info->signals |= SerialSignal_RI;
4395 }
4396
4397 /*
4398  * set V.24 Control Register based on current configuration
4399  */
4400 static void msc_set_vcr(struct slgt_info *info)
4401 {
4402         unsigned char val = 0;
4403
4404         /* VCR (V.24 control)
4405          *
4406          * 07..04  serial IF select
4407          * 03      DTR
4408          * 02      RTS
4409          * 01      LL
4410          * 00      RL
4411          */
4412
4413         switch(info->if_mode & MGSL_INTERFACE_MASK)
4414         {
4415         case MGSL_INTERFACE_RS232:
4416                 val |= BIT5; /* 0010 */
4417                 break;
4418         case MGSL_INTERFACE_V35:
4419                 val |= BIT7 + BIT6 + BIT5; /* 1110 */
4420                 break;
4421         case MGSL_INTERFACE_RS422:
4422                 val |= BIT6; /* 0100 */
4423                 break;
4424         }
4425
4426         if (info->signals & SerialSignal_DTR)
4427                 val |= BIT3;
4428         if (info->signals & SerialSignal_RTS)
4429                 val |= BIT2;
4430         if (info->if_mode & MGSL_INTERFACE_LL)
4431                 val |= BIT1;
4432         if (info->if_mode & MGSL_INTERFACE_RL)
4433                 val |= BIT0;
4434         wr_reg8(info, VCR, val);
4435 }
4436
4437 /*
4438  * set state of V24 control (output) signals
4439  */
4440 static void set_signals(struct slgt_info *info)
4441 {
4442         unsigned char val = rd_reg8(info, VCR);
4443         if (info->signals & SerialSignal_DTR)
4444                 val |= BIT3;
4445         else
4446                 val &= ~BIT3;
4447         if (info->signals & SerialSignal_RTS)
4448                 val |= BIT2;
4449         else
4450                 val &= ~BIT2;
4451         wr_reg8(info, VCR, val);
4452 }
4453
4454 /*
4455  * free range of receive DMA buffers (i to last)
4456  */
4457 static void free_rbufs(struct slgt_info *info, unsigned int i, unsigned int last)
4458 {
4459         int done = 0;
4460
4461         while(!done) {
4462                 /* reset current buffer for reuse */
4463                 info->rbufs[i].status = 0;
4464                 switch(info->params.mode) {
4465                 case MGSL_MODE_RAW:
4466                 case MGSL_MODE_MONOSYNC:
4467                 case MGSL_MODE_BISYNC:
4468                         set_desc_count(info->rbufs[i], info->raw_rx_size);
4469                         break;
4470                 default:
4471                         set_desc_count(info->rbufs[i], DMABUFSIZE);
4472                 }
4473
4474                 if (i == last)
4475                         done = 1;
4476                 if (++i == info->rbuf_count)
4477                         i = 0;
4478         }
4479         info->rbuf_current = i;
4480 }
4481
4482 /*
4483  * mark all receive DMA buffers as free
4484  */
4485 static void reset_rbufs(struct slgt_info *info)
4486 {
4487         free_rbufs(info, 0, info->rbuf_count - 1);
4488 }
4489
4490 /*
4491  * pass receive HDLC frame to upper layer
4492  *
4493  * return true if frame available, otherwise false
4494  */
4495 static bool rx_get_frame(struct slgt_info *info)
4496 {
4497         unsigned int start, end;
4498         unsigned short status;
4499         unsigned int framesize = 0;
4500         unsigned long flags;
4501         struct tty_struct *tty = info->port.tty;
4502         unsigned char addr_field = 0xff;
4503         unsigned int crc_size = 0;
4504
4505         switch (info->params.crc_type & HDLC_CRC_MASK) {
4506         case HDLC_CRC_16_CCITT: crc_size = 2; break;
4507         case HDLC_CRC_32_CCITT: crc_size = 4; break;
4508         }
4509
4510 check_again:
4511
4512         framesize = 0;
4513         addr_field = 0xff;
4514         start = end = info->rbuf_current;
4515
4516         for (;;) {
4517                 if (!desc_complete(info->rbufs[end]))
4518                         goto cleanup;
4519
4520                 if (framesize == 0 && info->params.addr_filter != 0xff)
4521                         addr_field = info->rbufs[end].buf[0];
4522
4523                 framesize += desc_count(info->rbufs[end]);
4524
4525                 if (desc_eof(info->rbufs[end]))
4526                         break;
4527
4528                 if (++end == info->rbuf_count)
4529                         end = 0;
4530
4531                 if (end == info->rbuf_current) {
4532                         if (info->rx_enabled){
4533                                 spin_lock_irqsave(&info->lock,flags);
4534                                 rx_start(info);
4535                                 spin_unlock_irqrestore(&info->lock,flags);
4536                         }
4537                         goto cleanup;
4538                 }
4539         }
4540
4541         /* status
4542          *
4543          * 15      buffer complete
4544          * 14..06  reserved
4545          * 05..04  residue
4546          * 02      eof (end of frame)
4547          * 01      CRC error
4548          * 00      abort
4549          */
4550         status = desc_status(info->rbufs[end]);
4551
4552         /* ignore CRC bit if not using CRC (bit is undefined) */
4553         if ((info->params.crc_type & HDLC_CRC_MASK) == HDLC_CRC_NONE)
4554                 status &= ~BIT1;
4555
4556         if (framesize == 0 ||
4557                  (addr_field != 0xff && addr_field != info->params.addr_filter)) {
4558                 free_rbufs(info, start, end);
4559                 goto check_again;
4560         }
4561
4562         if (framesize < (2 + crc_size) || status & BIT0) {
4563                 info->icount.rxshort++;
4564                 framesize = 0;
4565         } else if (status & BIT1) {
4566                 info->icount.rxcrc++;
4567                 if (!(info->params.crc_type & HDLC_CRC_RETURN_EX))
4568                         framesize = 0;
4569         }
4570
4571 #if SYNCLINK_GENERIC_HDLC
4572         if (framesize == 0) {
4573                 struct net_device_stats *stats = hdlc_stats(info->netdev);
4574                 stats->rx_errors++;
4575                 stats->rx_frame_errors++;
4576         }
4577 #endif
4578
4579         DBGBH(("%s rx frame status=%04X size=%d\n",
4580                 info->device_name, status, framesize));
4581         DBGDATA(info, info->rbufs[start].buf, min_t(int, framesize, DMABUFSIZE), "rx");
4582
4583         if (framesize) {
4584                 if (!(info->params.crc_type & HDLC_CRC_RETURN_EX)) {
4585                         framesize -= crc_size;
4586                         crc_size = 0;
4587                 }
4588
4589                 if (framesize > info->max_frame_size + crc_size)
4590                         info->icount.rxlong++;
4591                 else {
4592                         /* copy dma buffer(s) to contiguous temp buffer */
4593                         int copy_count = framesize;
4594                         int i = start;
4595                         unsigned char *p = info->tmp_rbuf;
4596                         info->tmp_rbuf_count = framesize;
4597
4598                         info->icount.rxok++;
4599
4600                         while(copy_count) {
4601                                 int partial_count = min(copy_count, DMABUFSIZE);
4602                                 memcpy(p, info->rbufs[i].buf, partial_count);
4603                                 p += partial_count;
4604                                 copy_count -= partial_count;
4605                                 if (++i == info->rbuf_count)
4606                                         i = 0;
4607                         }
4608
4609                         if (info->params.crc_type & HDLC_CRC_RETURN_EX) {
4610                                 *p = (status & BIT1) ? RX_CRC_ERROR : RX_OK;
4611                                 framesize++;
4612                         }
4613
4614 #if SYNCLINK_GENERIC_HDLC
4615                         if (info->netcount)
4616                                 hdlcdev_rx(info,info->tmp_rbuf, framesize);
4617                         else
4618 #endif
4619                                 ldisc_receive_buf(tty, info->tmp_rbuf, info->flag_buf, framesize);
4620                 }
4621         }
4622         free_rbufs(info, start, end);
4623         return true;
4624
4625 cleanup:
4626         return false;
4627 }
4628
4629 /*
4630  * pass receive buffer (RAW synchronous mode) to tty layer
4631  * return true if buffer available, otherwise false
4632  */
4633 static bool rx_get_buf(struct slgt_info *info)
4634 {
4635         unsigned int i = info->rbuf_current;
4636         unsigned int count;
4637
4638         if (!desc_complete(info->rbufs[i]))
4639                 return false;
4640         count = desc_count(info->rbufs[i]);
4641         switch(info->params.mode) {
4642         case MGSL_MODE_MONOSYNC:
4643         case MGSL_MODE_BISYNC:
4644                 /* ignore residue in byte synchronous modes */
4645                 if (desc_residue(info->rbufs[i]))
4646                         count--;
4647                 break;
4648         }
4649         DBGDATA(info, info->rbufs[i].buf, count, "rx");
4650         DBGINFO(("rx_get_buf size=%d\n", count));
4651         if (count)
4652                 ldisc_receive_buf(info->port.tty, info->rbufs[i].buf,
4653                                   info->flag_buf, count);
4654         free_rbufs(info, i, i);
4655         return true;
4656 }
4657
4658 static void reset_tbufs(struct slgt_info *info)
4659 {
4660         unsigned int i;
4661         info->tbuf_current = 0;
4662         for (i=0 ; i < info->tbuf_count ; i++) {
4663                 info->tbufs[i].status = 0;
4664                 info->tbufs[i].count  = 0;
4665         }
4666 }
4667
4668 /*
4669  * return number of free transmit DMA buffers
4670  */
4671 static unsigned int free_tbuf_count(struct slgt_info *info)
4672 {
4673         unsigned int count = 0;
4674         unsigned int i = info->tbuf_current;
4675
4676         do
4677         {
4678                 if (desc_count(info->tbufs[i]))
4679                         break; /* buffer in use */
4680                 ++count;
4681                 if (++i == info->tbuf_count)
4682                         i=0;
4683         } while (i != info->tbuf_current);
4684
4685         /* if tx DMA active, last zero count buffer is in use */
4686         if (count && (rd_reg32(info, TDCSR) & BIT0))
4687                 --count;
4688
4689         return count;
4690 }
4691
4692 /*
4693  * load transmit DMA buffer(s) with data
4694  */
4695 static void tx_load(struct slgt_info *info, const char *buf, unsigned int size)
4696 {
4697         unsigned short count;
4698         unsigned int i;
4699         struct slgt_desc *d;
4700
4701         if (size == 0)
4702                 return;
4703
4704         DBGDATA(info, buf, size, "tx");
4705
4706         info->tbuf_start = i = info->tbuf_current;
4707
4708         while (size) {
4709                 d = &info->tbufs[i];
4710                 if (++i == info->tbuf_count)
4711                         i = 0;
4712
4713                 count = (unsigned short)((size > DMABUFSIZE) ? DMABUFSIZE : size);
4714                 memcpy(d->buf, buf, count);
4715
4716                 size -= count;
4717                 buf  += count;
4718
4719                 /*
4720                  * set EOF bit for last buffer of HDLC frame or
4721                  * for every buffer in raw mode
4722                  */
4723                 if ((!size && info->params.mode == MGSL_MODE_HDLC) ||
4724                     info->params.mode == MGSL_MODE_RAW)
4725                         set_desc_eof(*d, 1);
4726                 else
4727                         set_desc_eof(*d, 0);
4728
4729                 set_desc_count(*d, count);
4730         }
4731
4732         info->tbuf_current = i;
4733 }
4734
4735 static int register_test(struct slgt_info *info)
4736 {
4737         static unsigned short patterns[] =
4738                 {0x0000, 0xffff, 0xaaaa, 0x5555, 0x6969, 0x9696};
4739         static unsigned int count = sizeof(patterns)/sizeof(patterns[0]);
4740         unsigned int i;
4741         int rc = 0;
4742
4743         for (i=0 ; i < count ; i++) {
4744                 wr_reg16(info, TIR, patterns[i]);
4745                 wr_reg16(info, BDR, patterns[(i+1)%count]);
4746                 if ((rd_reg16(info, TIR) != patterns[i]) ||
4747                     (rd_reg16(info, BDR) != patterns[(i+1)%count])) {
4748                         rc = -ENODEV;
4749                         break;
4750                 }
4751         }
4752         info->gpio_present = (rd_reg32(info, JCR) & BIT5) ? 1 : 0;
4753         info->init_error = rc ? 0 : DiagStatus_AddressFailure;
4754         return rc;
4755 }
4756
4757 static int irq_test(struct slgt_info *info)
4758 {
4759         unsigned long timeout;
4760         unsigned long flags;
4761         struct tty_struct *oldtty = info->port.tty;
4762         u32 speed = info->params.data_rate;
4763
4764         info->params.data_rate = 921600;
4765         info->port.tty = NULL;
4766
4767         spin_lock_irqsave(&info->lock, flags);
4768         async_mode(info);
4769         slgt_irq_on(info, IRQ_TXIDLE);
4770
4771         /* enable transmitter */
4772         wr_reg16(info, TCR,
4773                 (unsigned short)(rd_reg16(info, TCR) | BIT1));
4774
4775         /* write one byte and wait for tx idle */
4776         wr_reg16(info, TDR, 0);
4777
4778         /* assume failure */
4779         info->init_error = DiagStatus_IrqFailure;
4780         info->irq_occurred = false;
4781
4782         spin_unlock_irqrestore(&info->lock, flags);
4783
4784         timeout=100;
4785         while(timeout-- && !info->irq_occurred)
4786                 msleep_interruptible(10);
4787
4788         spin_lock_irqsave(&info->lock,flags);
4789         reset_port(info);
4790         spin_unlock_irqrestore(&info->lock,flags);
4791
4792         info->params.data_rate = speed;
4793         info->port.tty = oldtty;
4794
4795         info->init_error = info->irq_occurred ? 0 : DiagStatus_IrqFailure;
4796         return info->irq_occurred ? 0 : -ENODEV;
4797 }
4798
4799 static int loopback_test_rx(struct slgt_info *info)
4800 {
4801         unsigned char *src, *dest;
4802         int count;
4803
4804         if (desc_complete(info->rbufs[0])) {
4805                 count = desc_count(info->rbufs[0]);
4806                 src   = info->rbufs[0].buf;
4807                 dest  = info->tmp_rbuf;
4808
4809                 for( ; count ; count-=2, src+=2) {
4810                         /* src=data byte (src+1)=status byte */
4811                         if (!(*(src+1) & (BIT9 + BIT8))) {
4812                                 *dest = *src;
4813                                 dest++;
4814                                 info->tmp_rbuf_count++;
4815                         }
4816                 }
4817                 DBGDATA(info, info->tmp_rbuf, info->tmp_rbuf_count, "rx");
4818                 return 1;
4819         }
4820         return 0;
4821 }
4822
4823 static int loopback_test(struct slgt_info *info)
4824 {
4825 #define TESTFRAMESIZE 20
4826
4827         unsigned long timeout;
4828         u16 count = TESTFRAMESIZE;
4829         unsigned char buf[TESTFRAMESIZE];
4830         int rc = -ENODEV;
4831         unsigned long flags;
4832
4833         struct tty_struct *oldtty = info->port.tty;
4834         MGSL_PARAMS params;
4835
4836         memcpy(&params, &info->params, sizeof(params));
4837
4838         info->params.mode = MGSL_MODE_ASYNC;
4839         info->params.data_rate = 921600;
4840         info->params.loopback = 1;
4841         info->port.tty = NULL;
4842
4843         /* build and send transmit frame */
4844         for (count = 0; count < TESTFRAMESIZE; ++count)
4845                 buf[count] = (unsigned char)count;
4846
4847         info->tmp_rbuf_count = 0;
4848         memset(info->tmp_rbuf, 0, TESTFRAMESIZE);
4849
4850         /* program hardware for HDLC and enabled receiver */
4851         spin_lock_irqsave(&info->lock,flags);
4852         async_mode(info);
4853         rx_start(info);
4854         info->tx_count = count;
4855         tx_load(info, buf, count);
4856         tx_start(info);
4857         spin_unlock_irqrestore(&info->lock, flags);
4858
4859         /* wait for receive complete */
4860         for (timeout = 100; timeout; --timeout) {
4861                 msleep_interruptible(10);
4862                 if (loopback_test_rx(info)) {
4863                         rc = 0;
4864                         break;
4865                 }
4866         }
4867
4868         /* verify received frame length and contents */
4869         if (!rc && (info->tmp_rbuf_count != count ||
4870                   memcmp(buf, info->tmp_rbuf, count))) {
4871                 rc = -ENODEV;
4872         }
4873
4874         spin_lock_irqsave(&info->lock,flags);
4875         reset_adapter(info);
4876         spin_unlock_irqrestore(&info->lock,flags);
4877
4878         memcpy(&info->params, &params, sizeof(info->params));
4879         info->port.tty = oldtty;
4880
4881         info->init_error = rc ? DiagStatus_DmaFailure : 0;
4882         return rc;
4883 }
4884
4885 static int adapter_test(struct slgt_info *info)
4886 {
4887         DBGINFO(("testing %s\n", info->device_name));
4888         if (register_test(info) < 0) {
4889                 printk("register test failure %s addr=%08X\n",
4890                         info->device_name, info->phys_reg_addr);
4891         } else if (irq_test(info) < 0) {
4892                 printk("IRQ test failure %s IRQ=%d\n",
4893                         info->device_name, info->irq_level);
4894         } else if (loopback_test(info) < 0) {
4895                 printk("loopback test failure %s\n", info->device_name);
4896         }
4897         return info->init_error;
4898 }
4899
4900 /*
4901  * transmit timeout handler
4902  */
4903 static void tx_timeout(unsigned long context)
4904 {
4905         struct slgt_info *info = (struct slgt_info*)context;
4906         unsigned long flags;
4907
4908         DBGINFO(("%s tx_timeout\n", info->device_name));
4909         if(info->tx_active && info->params.mode == MGSL_MODE_HDLC) {
4910                 info->icount.txtimeout++;
4911         }
4912         spin_lock_irqsave(&info->lock,flags);
4913         info->tx_active = false;
4914         info->tx_count = 0;
4915         spin_unlock_irqrestore(&info->lock,flags);
4916
4917 #if SYNCLINK_GENERIC_HDLC
4918         if (info->netcount)
4919                 hdlcdev_tx_done(info);
4920         else
4921 #endif
4922                 bh_transmit(info);
4923 }
4924
4925 /*
4926  * receive buffer polling timer
4927  */
4928 static void rx_timeout(unsigned long context)
4929 {
4930         struct slgt_info *info = (struct slgt_info*)context;
4931         unsigned long flags;
4932
4933         DBGINFO(("%s rx_timeout\n", info->device_name));
4934         spin_lock_irqsave(&info->lock, flags);
4935         info->pending_bh |= BH_RECEIVE;
4936         spin_unlock_irqrestore(&info->lock, flags);
4937         bh_handler(&info->task);
4938 }
4939