1 /* radeon_irq.c -- IRQ handling for radeon -*- linux-c -*-
3 * Copyright (C) The Weather Channel, Inc. 2002. All Rights Reserved.
5 * The Weather Channel (TM) funded Tungsten Graphics to develop the
6 * initial release of the Radeon 8500 driver under the XFree86 license.
7 * This notice must be preserved.
9 * Permission is hereby granted, free of charge, to any person obtaining a
10 * copy of this software and associated documentation files (the "Software"),
11 * to deal in the Software without restriction, including without limitation
12 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
13 * and/or sell copies of the Software, and to permit persons to whom the
14 * Software is furnished to do so, subject to the following conditions:
16 * The above copyright notice and this permission notice (including the next
17 * paragraph) shall be included in all copies or substantial portions of the
20 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
21 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
22 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
23 * PRECISION INSIGHT AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR
24 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
25 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
26 * DEALINGS IN THE SOFTWARE.
29 * Keith Whitwell <keith@tungstengraphics.com>
30 * Michel D�zer <michel@daenzer.net>
35 #include "radeon_drm.h"
36 #include "radeon_drv.h"
38 /* Interrupts - Used for device synchronization and flushing in the
39 * following circumstances:
41 * - Exclusive FB access with hw idle:
42 * - Wait for GUI Idle (?) interrupt, then do normal flush.
44 * - Frame throttling, NV_fence:
45 * - Drop marker irq's into command stream ahead of time.
46 * - Wait on irq's with lock *not held*
47 * - Check each for termination condition
49 * - Internally in cp_getbuffer, etc:
50 * - as above, but wait with lock held???
52 * NOTE: These functions are misleadingly named -- the irq's aren't
53 * tied to dma at all, this is just a hangover from dri prehistory.
56 irqreturn_t radeon_driver_irq_handler( DRM_IRQ_ARGS )
58 drm_device_t *dev = (drm_device_t *) arg;
59 drm_radeon_private_t *dev_priv =
60 (drm_radeon_private_t *)dev->dev_private;
63 /* Only consider the bits we're interested in - others could be used
66 stat = RADEON_READ(RADEON_GEN_INT_STATUS)
67 & (RADEON_SW_INT_TEST | RADEON_CRTC_VBLANK_STAT);
72 if (stat & RADEON_SW_INT_TEST) {
73 DRM_WAKEUP( &dev_priv->swi_queue );
76 /* VBLANK interrupt */
77 if (stat & RADEON_CRTC_VBLANK_STAT) {
78 atomic_inc(&dev->vbl_received);
79 DRM_WAKEUP(&dev->vbl_queue);
80 drm_vbl_send_signals( dev );
83 /* Acknowledge interrupts we handle */
84 RADEON_WRITE(RADEON_GEN_INT_STATUS, stat);
88 static __inline__ void radeon_acknowledge_irqs(drm_radeon_private_t *dev_priv)
90 u32 tmp = RADEON_READ( RADEON_GEN_INT_STATUS )
91 & (RADEON_SW_INT_TEST_ACK | RADEON_CRTC_VBLANK_STAT);
93 RADEON_WRITE( RADEON_GEN_INT_STATUS, tmp );
96 static int radeon_emit_irq(drm_device_t *dev)
98 drm_radeon_private_t *dev_priv = dev->dev_private;
102 atomic_inc(&dev_priv->swi_emitted);
103 ret = atomic_read(&dev_priv->swi_emitted);
106 OUT_RING_REG( RADEON_LAST_SWI_REG, ret );
107 OUT_RING_REG( RADEON_GEN_INT_STATUS, RADEON_SW_INT_FIRE );
115 static int radeon_wait_irq(drm_device_t *dev, int swi_nr)
117 drm_radeon_private_t *dev_priv =
118 (drm_radeon_private_t *)dev->dev_private;
121 if (RADEON_READ( RADEON_LAST_SWI_REG ) >= swi_nr)
124 dev_priv->stats.boxes |= RADEON_BOX_WAIT_IDLE;
126 DRM_WAIT_ON( ret, dev_priv->swi_queue, 3 * DRM_HZ,
127 RADEON_READ( RADEON_LAST_SWI_REG ) >= swi_nr );
132 int radeon_driver_vblank_wait(drm_device_t *dev, unsigned int *sequence)
134 drm_radeon_private_t *dev_priv =
135 (drm_radeon_private_t *)dev->dev_private;
136 unsigned int cur_vblank;
140 DRM_ERROR( "%s called with no initialization\n", __FUNCTION__ );
141 return DRM_ERR(EINVAL);
144 radeon_acknowledge_irqs( dev_priv );
146 dev_priv->stats.boxes |= RADEON_BOX_WAIT_IDLE;
148 /* Assume that the user has missed the current sequence number
149 * by about a day rather than she wants to wait for years
150 * using vertical blanks...
152 DRM_WAIT_ON( ret, dev->vbl_queue, 3*DRM_HZ,
153 ( ( ( cur_vblank = atomic_read(&dev->vbl_received ) )
154 - *sequence ) <= (1<<23) ) );
156 *sequence = cur_vblank;
162 /* Needs the lock as it touches the ring.
164 int radeon_irq_emit( DRM_IOCTL_ARGS )
167 drm_radeon_private_t *dev_priv = dev->dev_private;
168 drm_radeon_irq_emit_t emit;
171 LOCK_TEST_WITH_RETURN( dev, filp );
174 DRM_ERROR( "%s called with no initialization\n", __FUNCTION__ );
175 return DRM_ERR(EINVAL);
178 DRM_COPY_FROM_USER_IOCTL( emit, (drm_radeon_irq_emit_t __user *)data,
181 result = radeon_emit_irq( dev );
183 if ( DRM_COPY_TO_USER( emit.irq_seq, &result, sizeof(int) ) ) {
184 DRM_ERROR( "copy_to_user\n" );
185 return DRM_ERR(EFAULT);
192 /* Doesn't need the hardware lock.
194 int radeon_irq_wait( DRM_IOCTL_ARGS )
197 drm_radeon_private_t *dev_priv = dev->dev_private;
198 drm_radeon_irq_wait_t irqwait;
201 DRM_ERROR( "%s called with no initialization\n", __FUNCTION__ );
202 return DRM_ERR(EINVAL);
205 DRM_COPY_FROM_USER_IOCTL( irqwait, (drm_radeon_irq_wait_t __user*)data,
208 return radeon_wait_irq( dev, irqwait.irq_seq );
214 void radeon_driver_irq_preinstall( drm_device_t *dev ) {
215 drm_radeon_private_t *dev_priv =
216 (drm_radeon_private_t *)dev->dev_private;
218 /* Disable *all* interrupts */
219 RADEON_WRITE( RADEON_GEN_INT_CNTL, 0 );
221 /* Clear bits if they're already high */
222 radeon_acknowledge_irqs( dev_priv );
225 void radeon_driver_irq_postinstall( drm_device_t *dev ) {
226 drm_radeon_private_t *dev_priv =
227 (drm_radeon_private_t *)dev->dev_private;
229 atomic_set(&dev_priv->swi_emitted, 0);
230 DRM_INIT_WAITQUEUE( &dev_priv->swi_queue );
232 /* Turn on SW and VBL ints */
233 RADEON_WRITE( RADEON_GEN_INT_CNTL,
234 RADEON_CRTC_VBLANK_MASK |
235 RADEON_SW_INT_ENABLE );
238 void radeon_driver_irq_uninstall( drm_device_t *dev ) {
239 drm_radeon_private_t *dev_priv =
240 (drm_radeon_private_t *)dev->dev_private;
244 /* Disable *all* interrupts */
245 RADEON_WRITE( RADEON_GEN_INT_CNTL, 0 );