err.no Git - linux-2.6/blob - drivers/char/drm/radeon_cp.c

   1 /* radeon_cp.c -- CP support for Radeon -*- linux-c -*- */
   2 /*
   3  * Copyright 2000 Precision Insight, Inc., Cedar Park, Texas.
   4  * Copyright 2000 VA Linux Systems, Inc., Fremont, California.
   5  * Copyright 2007 Advanced Micro Devices, Inc.
   6  * All Rights Reserved.
   7  *
   8  * Permission is hereby granted, free of charge, to any person obtaining a
   9  * copy of this software and associated documentation files (the "Software"),
  10  * to deal in the Software without restriction, including without limitation
  11  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
  12  * and/or sell copies of the Software, and to permit persons to whom the
  13  * Software is furnished to do so, subject to the following conditions:
  14  *
  15  * The above copyright notice and this permission notice (including the next
  16  * paragraph) shall be included in all copies or substantial portions of the
  17  * Software.
  18  *
  19  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  20  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  21  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  22  * PRECISION INSIGHT AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR
  23  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  24  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
  25  * DEALINGS IN THE SOFTWARE.
  26  *
  27  * Authors:
  28  *    Kevin E. Martin <martin@valinux.com>
  29  *    Gareth Hughes <gareth@valinux.com>
  30  */
  31
  32 #include "drmP.h"
  33 #include "drm.h"
  34 #include "radeon_drm.h"
  35 #include "radeon_drv.h"
  36 #include "r300_reg.h"
  37
  38 #include "radeon_microcode.h"
  39
  40 #define RADEON_FIFO_DEBUG       0
  41
  42 static int radeon_do_cleanup_cp(struct drm_device * dev);
  43
  44 static u32 R500_READ_MCIND(drm_radeon_private_t *dev_priv, int addr)
  45 {
  46         u32 ret;
  47         RADEON_WRITE(R520_MC_IND_INDEX, 0x7f0000 | (addr & 0xff));
  48         ret = RADEON_READ(R520_MC_IND_DATA);
  49         RADEON_WRITE(R520_MC_IND_INDEX, 0);
  50         return ret;
  51 }
  52
  53 static u32 RS480_READ_MCIND(drm_radeon_private_t *dev_priv, int addr)
  54 {
  55         u32 ret;
  56         RADEON_WRITE(RS480_NB_MC_INDEX, addr & 0xff);
  57         ret = RADEON_READ(RS480_NB_MC_DATA);
  58         RADEON_WRITE(RS480_NB_MC_INDEX, 0xff);
  59         return ret;
  60 }
  61
  62 static u32 RS690_READ_MCIND(drm_radeon_private_t *dev_priv, int addr)
  63 {
  64         u32 ret;
  65         RADEON_WRITE(RS690_MC_INDEX, (addr & RS690_MC_INDEX_MASK));
  66         ret = RADEON_READ(RS690_MC_DATA);
  67         RADEON_WRITE(RS690_MC_INDEX, RS690_MC_INDEX_MASK);
  68         return ret;
  69 }
  70
  71 static u32 IGP_READ_MCIND(drm_radeon_private_t *dev_priv, int addr)
  72 {
  73         if ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS690)
  74                 return RS690_READ_MCIND(dev_priv, addr);
  75         else
  76                 return RS480_READ_MCIND(dev_priv, addr);
  77 }
  78
  79 u32 radeon_read_fb_location(drm_radeon_private_t *dev_priv)
  80 {
  81
  82         if ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RV515)
  83                 return R500_READ_MCIND(dev_priv, RV515_MC_FB_LOCATION);
  84         else if ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS690)
  85                 return RS690_READ_MCIND(dev_priv, RS690_MC_FB_LOCATION);
  86         else if ((dev_priv->flags & RADEON_FAMILY_MASK) > CHIP_RV515)
  87                 return R500_READ_MCIND(dev_priv, R520_MC_FB_LOCATION);
  88         else
  89                 return RADEON_READ(RADEON_MC_FB_LOCATION);
  90 }
  91
  92 static void radeon_write_fb_location(drm_radeon_private_t *dev_priv, u32 fb_loc)
  93 {
  94         if ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RV515)
  95                 R500_WRITE_MCIND(RV515_MC_FB_LOCATION, fb_loc);
  96         else if ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS690)
  97                 RS690_WRITE_MCIND(RS690_MC_FB_LOCATION, fb_loc);
  98         else if ((dev_priv->flags & RADEON_FAMILY_MASK) > CHIP_RV515)
  99                 R500_WRITE_MCIND(R520_MC_FB_LOCATION, fb_loc);
 100         else
 101                 RADEON_WRITE(RADEON_MC_FB_LOCATION, fb_loc);
 102 }
 103
 104 static void radeon_write_agp_location(drm_radeon_private_t *dev_priv, u32 agp_loc)
 105 {
 106         if ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RV515)
 107                 R500_WRITE_MCIND(RV515_MC_AGP_LOCATION, agp_loc);
 108         else if ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS690)
 109                 RS690_WRITE_MCIND(RS690_MC_AGP_LOCATION, agp_loc);
 110         else if ((dev_priv->flags & RADEON_FAMILY_MASK) > CHIP_RV515)
 111                 R500_WRITE_MCIND(R520_MC_AGP_LOCATION, agp_loc);
 112         else
 113                 RADEON_WRITE(RADEON_MC_AGP_LOCATION, agp_loc);
 114 }
 115
 116 static int RADEON_READ_PLL(struct drm_device * dev, int addr)
 117 {
 118         drm_radeon_private_t *dev_priv = dev->dev_private;
 119
 120         RADEON_WRITE8(RADEON_CLOCK_CNTL_INDEX, addr & 0x1f);
 121         return RADEON_READ(RADEON_CLOCK_CNTL_DATA);
 122 }
 123
 124 static u32 RADEON_READ_PCIE(drm_radeon_private_t *dev_priv, int addr)
 125 {
 126         RADEON_WRITE8(RADEON_PCIE_INDEX, addr & 0xff);
 127         return RADEON_READ(RADEON_PCIE_DATA);
 128 }
 129
 130 #if RADEON_FIFO_DEBUG
 131 static void radeon_status(drm_radeon_private_t * dev_priv)
 132 {
 133         printk("%s:\n", __func__);
 134         printk("RBBM_STATUS = 0x%08x\n",
 135                (unsigned int)RADEON_READ(RADEON_RBBM_STATUS));
 136         printk("CP_RB_RTPR = 0x%08x\n",
 137                (unsigned int)RADEON_READ(RADEON_CP_RB_RPTR));
 138         printk("CP_RB_WTPR = 0x%08x\n",
 139                (unsigned int)RADEON_READ(RADEON_CP_RB_WPTR));
 140         printk("AIC_CNTL = 0x%08x\n",
 141                (unsigned int)RADEON_READ(RADEON_AIC_CNTL));
 142         printk("AIC_STAT = 0x%08x\n",
 143                (unsigned int)RADEON_READ(RADEON_AIC_STAT));
 144         printk("AIC_PT_BASE = 0x%08x\n",
 145                (unsigned int)RADEON_READ(RADEON_AIC_PT_BASE));
 146         printk("TLB_ADDR = 0x%08x\n",
 147                (unsigned int)RADEON_READ(RADEON_AIC_TLB_ADDR));
 148         printk("TLB_DATA = 0x%08x\n",
 149                (unsigned int)RADEON_READ(RADEON_AIC_TLB_DATA));
 150 }
 151 #endif
 152
 153 /* ================================================================
 154  * Engine, FIFO control
 155  */
 156
 157 static int radeon_do_pixcache_flush(drm_radeon_private_t * dev_priv)
 158 {
 159         u32 tmp;
 160         int i;
 161
 162         dev_priv->stats.boxes |= RADEON_BOX_WAIT_IDLE;
 163
 164         tmp = RADEON_READ(RADEON_RB3D_DSTCACHE_CTLSTAT);
 165         tmp |= RADEON_RB3D_DC_FLUSH_ALL;
 166         RADEON_WRITE(RADEON_RB3D_DSTCACHE_CTLSTAT, tmp);
 167
 168         for (i = 0; i < dev_priv->usec_timeout; i++) {
 169                 if (!(RADEON_READ(RADEON_RB3D_DSTCACHE_CTLSTAT)
 170                       & RADEON_RB3D_DC_BUSY)) {
 171                         return 0;
 172                 }
 173                 DRM_UDELAY(1);
 174         }
 175
 176 #if RADEON_FIFO_DEBUG
 177         DRM_ERROR("failed!\n");
 178         radeon_status(dev_priv);
 179 #endif
 180         return -EBUSY;
 181 }
 182
 183 static int radeon_do_wait_for_fifo(drm_radeon_private_t * dev_priv, int entries)
 184 {
 185         int i;
 186
 187         dev_priv->stats.boxes |= RADEON_BOX_WAIT_IDLE;
 188
 189         for (i = 0; i < dev_priv->usec_timeout; i++) {
 190                 int slots = (RADEON_READ(RADEON_RBBM_STATUS)
 191                              & RADEON_RBBM_FIFOCNT_MASK);
 192                 if (slots >= entries)
 193                         return 0;
 194                 DRM_UDELAY(1);
 195         }
 196
 197 #if RADEON_FIFO_DEBUG
 198         DRM_ERROR("failed!\n");
 199         radeon_status(dev_priv);
 200 #endif
 201         return -EBUSY;
 202 }
 203
 204 static int radeon_do_wait_for_idle(drm_radeon_private_t * dev_priv)
 205 {
 206         int i, ret;
 207
 208         dev_priv->stats.boxes |= RADEON_BOX_WAIT_IDLE;
 209
 210         ret = radeon_do_wait_for_fifo(dev_priv, 64);
 211         if (ret)
 212                 return ret;
 213
 214         for (i = 0; i < dev_priv->usec_timeout; i++) {
 215                 if (!(RADEON_READ(RADEON_RBBM_STATUS)
 216                       & RADEON_RBBM_ACTIVE)) {
 217                         radeon_do_pixcache_flush(dev_priv);
 218                         return 0;
 219                 }
 220                 DRM_UDELAY(1);
 221         }
 222
 223 #if RADEON_FIFO_DEBUG
 224         DRM_ERROR("failed!\n");
 225         radeon_status(dev_priv);
 226 #endif
 227         return -EBUSY;
 228 }
 229
 230 /* ================================================================
 231  * CP control, initialization
 232  */
 233
 234 /* Load the microcode for the CP */
 235 static void radeon_cp_load_microcode(drm_radeon_private_t * dev_priv)
 236 {
 237         int i;
 238         DRM_DEBUG("\n");
 239
 240         radeon_do_wait_for_idle(dev_priv);
 241
 242         RADEON_WRITE(RADEON_CP_ME_RAM_ADDR, 0);
 243         if (((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_R100) ||
 244             ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RV100) ||
 245             ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RV200) ||
 246             ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS100) ||
 247             ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS200)) {
 248                 DRM_INFO("Loading R100 Microcode\n");
 249                 for (i = 0; i < 256; i++) {
 250                         RADEON_WRITE(RADEON_CP_ME_RAM_DATAH,
 251                                      R100_cp_microcode[i][1]);
 252                         RADEON_WRITE(RADEON_CP_ME_RAM_DATAL,
 253                                      R100_cp_microcode[i][0]);
 254                 }
 255         } else if (((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_R200) ||
 256                    ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RV250) ||
 257                    ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RV280) ||
 258                    ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS300)) {
 259                 DRM_INFO("Loading R200 Microcode\n");
 260                 for (i = 0; i < 256; i++) {
 261                         RADEON_WRITE(RADEON_CP_ME_RAM_DATAH,
 262                                      R200_cp_microcode[i][1]);
 263                         RADEON_WRITE(RADEON_CP_ME_RAM_DATAL,
 264                                      R200_cp_microcode[i][0]);
 265                 }
 266         } else if (((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_R300) ||
 267                    ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_R350) ||
 268                    ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RV350) ||
 269                    ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RV380) ||
 270                    ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS480)) {
 271                 DRM_INFO("Loading R300 Microcode\n");
 272                 for (i = 0; i < 256; i++) {
 273                         RADEON_WRITE(RADEON_CP_ME_RAM_DATAH,
 274                                      R300_cp_microcode[i][1]);
 275                         RADEON_WRITE(RADEON_CP_ME_RAM_DATAL,
 276                                      R300_cp_microcode[i][0]);
 277                 }
 278         } else if (((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_R420) ||
 279                    ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RV410)) {
 280                 DRM_INFO("Loading R400 Microcode\n");
 281                 for (i = 0; i < 256; i++) {
 282                         RADEON_WRITE(RADEON_CP_ME_RAM_DATAH,
 283                                      R420_cp_microcode[i][1]);
 284                         RADEON_WRITE(RADEON_CP_ME_RAM_DATAL,
 285                                      R420_cp_microcode[i][0]);
 286                 }
 287         } else if ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS690) {
 288                 DRM_INFO("Loading RS690 Microcode\n");
 289                 for (i = 0; i < 256; i++) {
 290                         RADEON_WRITE(RADEON_CP_ME_RAM_DATAH,
 291                                      RS690_cp_microcode[i][1]);
 292                         RADEON_WRITE(RADEON_CP_ME_RAM_DATAL,
 293                                      RS690_cp_microcode[i][0]);
 294                 }
 295         } else if (((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RV515) ||
 296                    ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_R520) ||
 297                    ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RV530) ||
 298                    ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_R580) ||
 299                    ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RV560) ||
 300                    ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RV570)) {
 301                 DRM_INFO("Loading R500 Microcode\n");
 302                 for (i = 0; i < 256; i++) {
 303                         RADEON_WRITE(RADEON_CP_ME_RAM_DATAH,
 304                                      R520_cp_microcode[i][1]);
 305                         RADEON_WRITE(RADEON_CP_ME_RAM_DATAL,
 306                                      R520_cp_microcode[i][0]);
 307                 }
 308         }
 309 }
 310
 311 /* Flush any pending commands to the CP.  This should only be used just
 312  * prior to a wait for idle, as it informs the engine that the command
 313  * stream is ending.
 314  */
 315 static void radeon_do_cp_flush(drm_radeon_private_t * dev_priv)
 316 {
 317         DRM_DEBUG("\n");
 318 #if 0
 319         u32 tmp;
 320
 321         tmp = RADEON_READ(RADEON_CP_RB_WPTR) | (1 << 31);
 322         RADEON_WRITE(RADEON_CP_RB_WPTR, tmp);
 323 #endif
 324 }
 325
 326 /* Wait for the CP to go idle.
 327  */
 328 int radeon_do_cp_idle(drm_radeon_private_t * dev_priv)
 329 {
 330         RING_LOCALS;
 331         DRM_DEBUG("\n");
 332
 333         BEGIN_RING(6);
 334
 335         RADEON_PURGE_CACHE();
 336         RADEON_PURGE_ZCACHE();
 337         RADEON_WAIT_UNTIL_IDLE();
 338
 339         ADVANCE_RING();
 340         COMMIT_RING();
 341
 342         return radeon_do_wait_for_idle(dev_priv);
 343 }
 344
 345 /* Start the Command Processor.
 346  */
 347 static void radeon_do_cp_start(drm_radeon_private_t * dev_priv)
 348 {
 349         RING_LOCALS;
 350         DRM_DEBUG("\n");
 351
 352         radeon_do_wait_for_idle(dev_priv);
 353
 354         RADEON_WRITE(RADEON_CP_CSQ_CNTL, dev_priv->cp_mode);
 355
 356         dev_priv->cp_running = 1;
 357
 358         BEGIN_RING(6);
 359
 360         RADEON_PURGE_CACHE();
 361         RADEON_PURGE_ZCACHE();
 362         RADEON_WAIT_UNTIL_IDLE();
 363
 364         ADVANCE_RING();
 365         COMMIT_RING();
 366 }
 367
 368 /* Reset the Command Processor.  This will not flush any pending
 369  * commands, so you must wait for the CP command stream to complete
 370  * before calling this routine.
 371  */
 372 static void radeon_do_cp_reset(drm_radeon_private_t * dev_priv)
 373 {
 374         u32 cur_read_ptr;
 375         DRM_DEBUG("\n");
 376
 377         cur_read_ptr = RADEON_READ(RADEON_CP_RB_RPTR);
 378         RADEON_WRITE(RADEON_CP_RB_WPTR, cur_read_ptr);
 379         SET_RING_HEAD(dev_priv, cur_read_ptr);
 380         dev_priv->ring.tail = cur_read_ptr;
 381 }
 382
 383 /* Stop the Command Processor.  This will not flush any pending
 384  * commands, so you must flush the command stream and wait for the CP
 385  * to go idle before calling this routine.
 386  */
 387 static void radeon_do_cp_stop(drm_radeon_private_t * dev_priv)
 388 {
 389         DRM_DEBUG("\n");
 390
 391         RADEON_WRITE(RADEON_CP_CSQ_CNTL, RADEON_CSQ_PRIDIS_INDDIS);
 392
 393         dev_priv->cp_running = 0;
 394 }
 395
 396 /* Reset the engine.  This will stop the CP if it is running.
 397  */
 398 static int radeon_do_engine_reset(struct drm_device * dev)
 399 {
 400         drm_radeon_private_t *dev_priv = dev->dev_private;
 401         u32 clock_cntl_index, mclk_cntl, rbbm_soft_reset;
 402         DRM_DEBUG("\n");
 403
 404         radeon_do_pixcache_flush(dev_priv);
 405
 406         if ((dev_priv->flags & RADEON_FAMILY_MASK) < CHIP_RV515) {
 407                 clock_cntl_index = RADEON_READ(RADEON_CLOCK_CNTL_INDEX);
 408                 mclk_cntl = RADEON_READ_PLL(dev, RADEON_MCLK_CNTL);
 409
 410                 RADEON_WRITE_PLL(RADEON_MCLK_CNTL, (mclk_cntl |
 411                                                     RADEON_FORCEON_MCLKA |
 412                                                     RADEON_FORCEON_MCLKB |
 413                                                     RADEON_FORCEON_YCLKA |
 414                                                     RADEON_FORCEON_YCLKB |
 415                                                     RADEON_FORCEON_MC |
 416                                                     RADEON_FORCEON_AIC));
 417
 418                 rbbm_soft_reset = RADEON_READ(RADEON_RBBM_SOFT_RESET);
 419
 420                 RADEON_WRITE(RADEON_RBBM_SOFT_RESET, (rbbm_soft_reset |
 421                                                       RADEON_SOFT_RESET_CP |
 422                                                       RADEON_SOFT_RESET_HI |
 423                                                       RADEON_SOFT_RESET_SE |
 424                                                       RADEON_SOFT_RESET_RE |
 425                                                       RADEON_SOFT_RESET_PP |
 426                                                       RADEON_SOFT_RESET_E2 |
 427                                                       RADEON_SOFT_RESET_RB));
 428                 RADEON_READ(RADEON_RBBM_SOFT_RESET);
 429                 RADEON_WRITE(RADEON_RBBM_SOFT_RESET, (rbbm_soft_reset &
 430                                                       ~(RADEON_SOFT_RESET_CP |
 431                                                         RADEON_SOFT_RESET_HI |
 432                                                         RADEON_SOFT_RESET_SE |
 433                                                         RADEON_SOFT_RESET_RE |
 434                                                         RADEON_SOFT_RESET_PP |
 435                                                         RADEON_SOFT_RESET_E2 |
 436                                                         RADEON_SOFT_RESET_RB)));
 437                 RADEON_READ(RADEON_RBBM_SOFT_RESET);
 438
 439                 RADEON_WRITE_PLL(RADEON_MCLK_CNTL, mclk_cntl);
 440                 RADEON_WRITE(RADEON_CLOCK_CNTL_INDEX, clock_cntl_index);
 441                 RADEON_WRITE(RADEON_RBBM_SOFT_RESET, rbbm_soft_reset);
 442         }
 443
 444         /* Reset the CP ring */
 445         radeon_do_cp_reset(dev_priv);
 446
 447         /* The CP is no longer running after an engine reset */
 448         dev_priv->cp_running = 0;
 449
 450         /* Reset any pending vertex, indirect buffers */
 451         radeon_freelist_reset(dev);
 452
 453         return 0;
 454 }
 455
 456 static void radeon_cp_init_ring_buffer(struct drm_device * dev,
 457                                        drm_radeon_private_t * dev_priv)
 458 {
 459         u32 ring_start, cur_read_ptr;
 460         u32 tmp;
 461
 462         /* Initialize the memory controller. With new memory map, the fb location
 463          * is not changed, it should have been properly initialized already. Part
 464          * of the problem is that the code below is bogus, assuming the GART is
 465          * always appended to the fb which is not necessarily the case
 466          */
 467         if (!dev_priv->new_memmap)
 468                 radeon_write_fb_location(dev_priv,
 469                              ((dev_priv->gart_vm_start - 1) & 0xffff0000)
 470                              | (dev_priv->fb_location >> 16));
 471
 472 #if __OS_HAS_AGP
 473         if (dev_priv->flags & RADEON_IS_AGP) {
 474                 RADEON_WRITE(RADEON_AGP_BASE, (unsigned int)dev->agp->base);
 475                 if ((dev_priv->flags & RADEON_FAMILY_MASK) >= CHIP_R200)
 476                         RADEON_WRITE(RADEON_AGP_BASE_2, 0);
 477                 radeon_write_agp_location(dev_priv,
 478                              (((dev_priv->gart_vm_start - 1 +
 479                                 dev_priv->gart_size) & 0xffff0000) |
 480                               (dev_priv->gart_vm_start >> 16)));
 481
 482                 ring_start = (dev_priv->cp_ring->offset
 483                               - dev->agp->base
 484                               + dev_priv->gart_vm_start);
 485         } else
 486 #endif
 487                 ring_start = (dev_priv->cp_ring->offset
 488                               - (unsigned long)dev->sg->virtual
 489                               + dev_priv->gart_vm_start);
 490
 491         RADEON_WRITE(RADEON_CP_RB_BASE, ring_start);
 492
 493         /* Set the write pointer delay */
 494         RADEON_WRITE(RADEON_CP_RB_WPTR_DELAY, 0);
 495
 496         /* Initialize the ring buffer's read and write pointers */
 497         cur_read_ptr = RADEON_READ(RADEON_CP_RB_RPTR);
 498         RADEON_WRITE(RADEON_CP_RB_WPTR, cur_read_ptr);
 499         SET_RING_HEAD(dev_priv, cur_read_ptr);
 500         dev_priv->ring.tail = cur_read_ptr;
 501
 502 #if __OS_HAS_AGP
 503         if (dev_priv->flags & RADEON_IS_AGP) {
 504                 RADEON_WRITE(RADEON_CP_RB_RPTR_ADDR,
 505                              dev_priv->ring_rptr->offset
 506                              - dev->agp->base + dev_priv->gart_vm_start);
 507         } else
 508 #endif
 509         {
 510                 struct drm_sg_mem *entry = dev->sg;
 511                 unsigned long tmp_ofs, page_ofs;
 512
 513                 tmp_ofs = dev_priv->ring_rptr->offset -
 514                                 (unsigned long)dev->sg->virtual;
 515                 page_ofs = tmp_ofs >> PAGE_SHIFT;
 516
 517                 RADEON_WRITE(RADEON_CP_RB_RPTR_ADDR, entry->busaddr[page_ofs]);
 518                 DRM_DEBUG("ring rptr: offset=0x%08lx handle=0x%08lx\n",
 519                           (unsigned long)entry->busaddr[page_ofs],
 520                           entry->handle + tmp_ofs);
 521         }
 522
 523         /* Set ring buffer size */
 524 #ifdef __BIG_ENDIAN
 525         RADEON_WRITE(RADEON_CP_RB_CNTL,
 526                      RADEON_BUF_SWAP_32BIT |
 527                      (dev_priv->ring.fetch_size_l2ow << 18) |
 528                      (dev_priv->ring.rptr_update_l2qw << 8) |
 529                      dev_priv->ring.size_l2qw);
 530 #else
 531         RADEON_WRITE(RADEON_CP_RB_CNTL,
 532                      (dev_priv->ring.fetch_size_l2ow << 18) |
 533                      (dev_priv->ring.rptr_update_l2qw << 8) |
 534                      dev_priv->ring.size_l2qw);
 535 #endif
 536
 537         /* Start with assuming that writeback doesn't work */
 538         dev_priv->writeback_works = 0;
 539
 540         /* Initialize the scratch register pointer.  This will cause
 541          * the scratch register values to be written out to memory
 542          * whenever they are updated.
 543          *
 544          * We simply put this behind the ring read pointer, this works
 545          * with PCI GART as well as (whatever kind of) AGP GART
 546          */
 547         RADEON_WRITE(RADEON_SCRATCH_ADDR, RADEON_READ(RADEON_CP_RB_RPTR_ADDR)
 548                      + RADEON_SCRATCH_REG_OFFSET);
 549
 550         dev_priv->scratch = ((__volatile__ u32 *)
 551                              dev_priv->ring_rptr->handle +
 552                              (RADEON_SCRATCH_REG_OFFSET / sizeof(u32)));
 553
 554         RADEON_WRITE(RADEON_SCRATCH_UMSK, 0x7);
 555
 556         /* Turn on bus mastering */
 557         tmp = RADEON_READ(RADEON_BUS_CNTL) & ~RADEON_BUS_MASTER_DIS;
 558         RADEON_WRITE(RADEON_BUS_CNTL, tmp);
 559
 560         dev_priv->sarea_priv->last_frame = dev_priv->scratch[0] = 0;
 561         RADEON_WRITE(RADEON_LAST_FRAME_REG, dev_priv->sarea_priv->last_frame);
 562
 563         dev_priv->sarea_priv->last_dispatch = dev_priv->scratch[1] = 0;
 564         RADEON_WRITE(RADEON_LAST_DISPATCH_REG,
 565                      dev_priv->sarea_priv->last_dispatch);
 566
 567         dev_priv->sarea_priv->last_clear = dev_priv->scratch[2] = 0;
 568         RADEON_WRITE(RADEON_LAST_CLEAR_REG, dev_priv->sarea_priv->last_clear);
 569
 570         radeon_do_wait_for_idle(dev_priv);
 571
 572         /* Sync everything up */
 573         RADEON_WRITE(RADEON_ISYNC_CNTL,
 574                      (RADEON_ISYNC_ANY2D_IDLE3D |
 575                       RADEON_ISYNC_ANY3D_IDLE2D |
 576                       RADEON_ISYNC_WAIT_IDLEGUI |
 577                       RADEON_ISYNC_CPSCRATCH_IDLEGUI));
 578
 579 }
 580
 581 static void radeon_test_writeback(drm_radeon_private_t * dev_priv)
 582 {
 583         u32 tmp;
 584
 585         /* Writeback doesn't seem to work everywhere, test it here and possibly
 586          * enable it if it appears to work
 587          */
 588         DRM_WRITE32(dev_priv->ring_rptr, RADEON_SCRATCHOFF(1), 0);
 589         RADEON_WRITE(RADEON_SCRATCH_REG1, 0xdeadbeef);
 590
 591         for (tmp = 0; tmp < dev_priv->usec_timeout; tmp++) {
 592                 if (DRM_READ32(dev_priv->ring_rptr, RADEON_SCRATCHOFF(1)) ==
 593                     0xdeadbeef)
 594                         break;
 595                 DRM_UDELAY(1);
 596         }
 597
 598         if (tmp < dev_priv->usec_timeout) {
 599                 dev_priv->writeback_works = 1;
 600                 DRM_INFO("writeback test succeeded in %d usecs\n", tmp);
 601         } else {
 602                 dev_priv->writeback_works = 0;
 603                 DRM_INFO("writeback test failed\n");
 604         }
 605         if (radeon_no_wb == 1) {
 606                 dev_priv->writeback_works = 0;
 607                 DRM_INFO("writeback forced off\n");
 608         }
 609
 610         if (!dev_priv->writeback_works) {
 611                 /* Disable writeback to avoid unnecessary bus master transfer */
 612                 RADEON_WRITE(RADEON_CP_RB_CNTL, RADEON_READ(RADEON_CP_RB_CNTL) |
 613                              RADEON_RB_NO_UPDATE);
 614                 RADEON_WRITE(RADEON_SCRATCH_UMSK, 0);
 615         }
 616 }
 617
 618 /* Enable or disable IGP GART on the chip */
 619 static void radeon_set_igpgart(drm_radeon_private_t * dev_priv, int on)
 620 {
 621         u32 temp;
 622
 623         if (on) {
 624                 DRM_DEBUG("programming igp gart %08X %08lX %08X\n",
 625                           dev_priv->gart_vm_start,
 626                           (long)dev_priv->gart_info.bus_addr,
 627                           dev_priv->gart_size);
 628
 629                 temp = IGP_READ_MCIND(dev_priv, RS480_MC_MISC_CNTL);
 630                 if ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS690)
 631                         IGP_WRITE_MCIND(RS480_MC_MISC_CNTL, (RS480_GART_INDEX_REG_EN |
 632                                                              RS690_BLOCK_GFX_D3_EN));
 633                 else
 634                         IGP_WRITE_MCIND(RS480_MC_MISC_CNTL, RS480_GART_INDEX_REG_EN);
 635
 636                 IGP_WRITE_MCIND(RS480_AGP_ADDRESS_SPACE_SIZE, (RS480_GART_EN |
 637                                                                RS480_VA_SIZE_32MB));
 638
 639                 temp = IGP_READ_MCIND(dev_priv, RS480_GART_FEATURE_ID);
 640                 IGP_WRITE_MCIND(RS480_GART_FEATURE_ID, (RS480_HANG_EN |
 641                                                         RS480_TLB_ENABLE |
 642                                                         RS480_GTW_LAC_EN |
 643                                                         RS480_1LEVEL_GART));
 644
 645                 temp = dev_priv->gart_info.bus_addr & 0xfffff000;
 646                 temp |= (upper_32_bits(dev_priv->gart_info.bus_addr) & 0xff) << 4;
 647                 IGP_WRITE_MCIND(RS480_GART_BASE, temp);
 648
 649                 temp = IGP_READ_MCIND(dev_priv, RS480_AGP_MODE_CNTL);
 650                 IGP_WRITE_MCIND(RS480_AGP_MODE_CNTL, ((1 << RS480_REQ_TYPE_SNOOP_SHIFT) |
 651                                                       RS480_REQ_TYPE_SNOOP_DIS));
 652
 653                 if ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS690) {
 654                         IGP_WRITE_MCIND(RS690_MC_AGP_BASE,
 655                                         (unsigned int)dev_priv->gart_vm_start);
 656                         IGP_WRITE_MCIND(RS690_MC_AGP_BASE_2, 0);
 657                 } else {
 658                         RADEON_WRITE(RADEON_AGP_BASE, (unsigned int)dev_priv->gart_vm_start);
 659                         RADEON_WRITE(RS480_AGP_BASE_2, 0);
 660                 }
 661
 662                 dev_priv->gart_size = 32*1024*1024;
 663                 temp = (((dev_priv->gart_vm_start - 1 + dev_priv->gart_size) &
 664                          0xffff0000) | (dev_priv->gart_vm_start >> 16));
 665
 666                 radeon_write_agp_location(dev_priv, temp);
 667
 668                 temp = IGP_READ_MCIND(dev_priv, RS480_AGP_ADDRESS_SPACE_SIZE);
 669                 IGP_WRITE_MCIND(RS480_AGP_ADDRESS_SPACE_SIZE, (RS480_GART_EN |
 670                                                                RS480_VA_SIZE_32MB));
 671
 672                 do {
 673                         temp = IGP_READ_MCIND(dev_priv, RS480_GART_CACHE_CNTRL);
 674                         if ((temp & RS480_GART_CACHE_INVALIDATE) == 0)
 675                                 break;
 676                         DRM_UDELAY(1);
 677                 } while (1);
 678
 679                 IGP_WRITE_MCIND(RS480_GART_CACHE_CNTRL,
 680                                 RS480_GART_CACHE_INVALIDATE);
 681
 682                 do {
 683                         temp = IGP_READ_MCIND(dev_priv, RS480_GART_CACHE_CNTRL);
 684                         if ((temp & RS480_GART_CACHE_INVALIDATE) == 0)
 685                                 break;
 686                         DRM_UDELAY(1);
 687                 } while (1);
 688
 689                 IGP_WRITE_MCIND(RS480_GART_CACHE_CNTRL, 0);
 690         } else {
 691                 IGP_WRITE_MCIND(RS480_AGP_ADDRESS_SPACE_SIZE, 0);
 692         }
 693 }
 694
 695 static void radeon_set_pciegart(drm_radeon_private_t * dev_priv, int on)
 696 {
 697         u32 tmp = RADEON_READ_PCIE(dev_priv, RADEON_PCIE_TX_GART_CNTL);
 698         if (on) {
 699
 700                 DRM_DEBUG("programming pcie %08X %08lX %08X\n",
 701                           dev_priv->gart_vm_start,
 702                           (long)dev_priv->gart_info.bus_addr,
 703                           dev_priv->gart_size);
 704                 RADEON_WRITE_PCIE(RADEON_PCIE_TX_DISCARD_RD_ADDR_LO,
 705                                   dev_priv->gart_vm_start);
 706                 RADEON_WRITE_PCIE(RADEON_PCIE_TX_GART_BASE,
 707                                   dev_priv->gart_info.bus_addr);
 708                 RADEON_WRITE_PCIE(RADEON_PCIE_TX_GART_START_LO,
 709                                   dev_priv->gart_vm_start);
 710                 RADEON_WRITE_PCIE(RADEON_PCIE_TX_GART_END_LO,
 711                                   dev_priv->gart_vm_start +
 712                                   dev_priv->gart_size - 1);
 713
 714                 radeon_write_agp_location(dev_priv, 0xffffffc0); /* ?? */
 715
 716                 RADEON_WRITE_PCIE(RADEON_PCIE_TX_GART_CNTL,
 717                                   RADEON_PCIE_TX_GART_EN);
 718         } else {
 719                 RADEON_WRITE_PCIE(RADEON_PCIE_TX_GART_CNTL,
 720                                   tmp & ~RADEON_PCIE_TX_GART_EN);
 721         }
 722 }
 723
 724 /* Enable or disable PCI GART on the chip */
 725 static void radeon_set_pcigart(drm_radeon_private_t * dev_priv, int on)
 726 {
 727         u32 tmp;
 728
 729         if (((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS690) ||
 730             (dev_priv->flags & RADEON_IS_IGPGART)) {
 731                 radeon_set_igpgart(dev_priv, on);
 732                 return;
 733         }
 734
 735         if (dev_priv->flags & RADEON_IS_PCIE) {
 736                 radeon_set_pciegart(dev_priv, on);
 737                 return;
 738         }
 739
 740         tmp = RADEON_READ(RADEON_AIC_CNTL);
 741
 742         if (on) {
 743                 RADEON_WRITE(RADEON_AIC_CNTL,
 744                              tmp | RADEON_PCIGART_TRANSLATE_EN);
 745
 746                 /* set PCI GART page-table base address
 747                  */
 748                 RADEON_WRITE(RADEON_AIC_PT_BASE, dev_priv->gart_info.bus_addr);
 749
 750                 /* set address range for PCI address translate
 751                  */
 752                 RADEON_WRITE(RADEON_AIC_LO_ADDR, dev_priv->gart_vm_start);
 753                 RADEON_WRITE(RADEON_AIC_HI_ADDR, dev_priv->gart_vm_start
 754                              + dev_priv->gart_size - 1);
 755
 756                 /* Turn off AGP aperture -- is this required for PCI GART?
 757                  */
 758                 radeon_write_agp_location(dev_priv, 0xffffffc0);
 759                 RADEON_WRITE(RADEON_AGP_COMMAND, 0);    /* clear AGP_COMMAND */
 760         } else {
 761                 RADEON_WRITE(RADEON_AIC_CNTL,
 762                              tmp & ~RADEON_PCIGART_TRANSLATE_EN);
 763         }
 764 }
 765
 766 static int radeon_do_init_cp(struct drm_device * dev, drm_radeon_init_t * init)
 767 {
 768         drm_radeon_private_t *dev_priv = dev->dev_private;
 769
 770         DRM_DEBUG("\n");
 771
 772         /* if we require new memory map but we don't have it fail */
 773         if ((dev_priv->flags & RADEON_NEW_MEMMAP) && !dev_priv->new_memmap) {
 774                 DRM_ERROR("Cannot initialise DRM on this card\nThis card requires a new X.org DDX for 3D\n");
 775                 radeon_do_cleanup_cp(dev);
 776                 return -EINVAL;
 777         }
 778
 779         if (init->is_pci && (dev_priv->flags & RADEON_IS_AGP)) {
 780                 DRM_DEBUG("Forcing AGP card to PCI mode\n");
 781                 dev_priv->flags &= ~RADEON_IS_AGP;
 782         } else if (!(dev_priv->flags & (RADEON_IS_AGP | RADEON_IS_PCI | RADEON_IS_PCIE))
 783                    && !init->is_pci) {
 784                 DRM_DEBUG("Restoring AGP flag\n");
 785                 dev_priv->flags |= RADEON_IS_AGP;
 786         }
 787
 788         if ((!(dev_priv->flags & RADEON_IS_AGP)) && !dev->sg) {
 789                 DRM_ERROR("PCI GART memory not allocated!\n");
 790                 radeon_do_cleanup_cp(dev);
 791                 return -EINVAL;
 792         }
 793
 794         dev_priv->usec_timeout = init->usec_timeout;
 795         if (dev_priv->usec_timeout < 1 ||
 796             dev_priv->usec_timeout > RADEON_MAX_USEC_TIMEOUT) {
 797                 DRM_DEBUG("TIMEOUT problem!\n");
 798                 radeon_do_cleanup_cp(dev);
 799                 return -EINVAL;
 800         }
 801
 802         /* Enable vblank on CRTC1 for older X servers
 803          */
 804         dev_priv->vblank_crtc = DRM_RADEON_VBLANK_CRTC1;
 805
 806         switch(init->func) {
 807         case RADEON_INIT_R200_CP:
 808                 dev_priv->microcode_version = UCODE_R200;
 809                 break;
 810         case RADEON_INIT_R300_CP:
 811                 dev_priv->microcode_version = UCODE_R300;
 812                 break;
 813         default:
 814                 dev_priv->microcode_version = UCODE_R100;
 815         }
 816
 817         dev_priv->do_boxes = 0;
 818         dev_priv->cp_mode = init->cp_mode;
 819
 820         /* We don't support anything other than bus-mastering ring mode,
 821          * but the ring can be in either AGP or PCI space for the ring
 822          * read pointer.
 823          */
 824         if ((init->cp_mode != RADEON_CSQ_PRIBM_INDDIS) &&
 825             (init->cp_mode != RADEON_CSQ_PRIBM_INDBM)) {
 826                 DRM_DEBUG("BAD cp_mode (%x)!\n", init->cp_mode);
 827                 radeon_do_cleanup_cp(dev);
 828                 return -EINVAL;
 829         }
 830
 831         switch (init->fb_bpp) {
 832         case 16:
 833                 dev_priv->color_fmt = RADEON_COLOR_FORMAT_RGB565;
 834                 break;
 835         case 32:
 836         default:
 837                 dev_priv->color_fmt = RADEON_COLOR_FORMAT_ARGB8888;
 838                 break;
 839         }
 840         dev_priv->front_offset = init->front_offset;
 841         dev_priv->front_pitch = init->front_pitch;
 842         dev_priv->back_offset = init->back_offset;
 843         dev_priv->back_pitch = init->back_pitch;
 844
 845         switch (init->depth_bpp) {
 846         case 16:
 847                 dev_priv->depth_fmt = RADEON_DEPTH_FORMAT_16BIT_INT_Z;
 848                 break;
 849         case 32:
 850         default:
 851                 dev_priv->depth_fmt = RADEON_DEPTH_FORMAT_24BIT_INT_Z;
 852                 break;
 853         }
 854         dev_priv->depth_offset = init->depth_offset;
 855         dev_priv->depth_pitch = init->depth_pitch;
 856
 857         /* Hardware state for depth clears.  Remove this if/when we no
 858          * longer clear the depth buffer with a 3D rectangle.  Hard-code
 859          * all values to prevent unwanted 3D state from slipping through
 860          * and screwing with the clear operation.
 861          */
 862         dev_priv->depth_clear.rb3d_cntl = (RADEON_PLANE_MASK_ENABLE |
 863                                            (dev_priv->color_fmt << 10) |
 864                                            (dev_priv->microcode_version ==
 865                                             UCODE_R100 ? RADEON_ZBLOCK16 : 0));
 866
 867         dev_priv->depth_clear.rb3d_zstencilcntl =
 868             (dev_priv->depth_fmt |
 869              RADEON_Z_TEST_ALWAYS |
 870              RADEON_STENCIL_TEST_ALWAYS |
 871              RADEON_STENCIL_S_FAIL_REPLACE |
 872              RADEON_STENCIL_ZPASS_REPLACE |
 873              RADEON_STENCIL_ZFAIL_REPLACE | RADEON_Z_WRITE_ENABLE);
 874
 875         dev_priv->depth_clear.se_cntl = (RADEON_FFACE_CULL_CW |
 876                                          RADEON_BFACE_SOLID |
 877                                          RADEON_FFACE_SOLID |
 878                                          RADEON_FLAT_SHADE_VTX_LAST |
 879                                          RADEON_DIFFUSE_SHADE_FLAT |
 880                                          RADEON_ALPHA_SHADE_FLAT |
 881                                          RADEON_SPECULAR_SHADE_FLAT |
 882                                          RADEON_FOG_SHADE_FLAT |
 883                                          RADEON_VTX_PIX_CENTER_OGL |
 884                                          RADEON_ROUND_MODE_TRUNC |
 885                                          RADEON_ROUND_PREC_8TH_PIX);
 886
 887
 888         dev_priv->ring_offset = init->ring_offset;
 889         dev_priv->ring_rptr_offset = init->ring_rptr_offset;
 890         dev_priv->buffers_offset = init->buffers_offset;
 891         dev_priv->gart_textures_offset = init->gart_textures_offset;
 892
 893         dev_priv->sarea = drm_getsarea(dev);
 894         if (!dev_priv->sarea) {
 895                 DRM_ERROR("could not find sarea!\n");
 896                 radeon_do_cleanup_cp(dev);
 897                 return -EINVAL;
 898         }
 899
 900         dev_priv->cp_ring = drm_core_findmap(dev, init->ring_offset);
 901         if (!dev_priv->cp_ring) {
 902                 DRM_ERROR("could not find cp ring region!\n");
 903                 radeon_do_cleanup_cp(dev);
 904                 return -EINVAL;
 905         }
 906         dev_priv->ring_rptr = drm_core_findmap(dev, init->ring_rptr_offset);
 907         if (!dev_priv->ring_rptr) {
 908                 DRM_ERROR("could not find ring read pointer!\n");
 909                 radeon_do_cleanup_cp(dev);
 910                 return -EINVAL;
 911         }
 912         dev->agp_buffer_token = init->buffers_offset;
 913         dev->agp_buffer_map = drm_core_findmap(dev, init->buffers_offset);
 914         if (!dev->agp_buffer_map) {
 915                 DRM_ERROR("could not find dma buffer region!\n");
 916                 radeon_do_cleanup_cp(dev);
 917                 return -EINVAL;
 918         }
 919
 920         if (init->gart_textures_offset) {
 921                 dev_priv->gart_textures =
 922                     drm_core_findmap(dev, init->gart_textures_offset);
 923                 if (!dev_priv->gart_textures) {
 924                         DRM_ERROR("could not find GART texture region!\n");
 925                         radeon_do_cleanup_cp(dev);
 926                         return -EINVAL;
 927                 }
 928         }
 929
 930         dev_priv->sarea_priv =
 931             (drm_radeon_sarea_t *) ((u8 *) dev_priv->sarea->handle +
 932                                     init->sarea_priv_offset);
 933
 934 #if __OS_HAS_AGP
 935         if (dev_priv->flags & RADEON_IS_AGP) {
 936                 drm_core_ioremap(dev_priv->cp_ring, dev);
 937                 drm_core_ioremap(dev_priv->ring_rptr, dev);
 938                 drm_core_ioremap(dev->agp_buffer_map, dev);
 939                 if (!dev_priv->cp_ring->handle ||
 940                     !dev_priv->ring_rptr->handle ||
 941                     !dev->agp_buffer_map->handle) {
 942                         DRM_ERROR("could not find ioremap agp regions!\n");
 943                         radeon_do_cleanup_cp(dev);
 944                         return -EINVAL;
 945                 }
 946         } else
 947 #endif
 948         {
 949                 dev_priv->cp_ring->handle = (void *)dev_priv->cp_ring->offset;
 950                 dev_priv->ring_rptr->handle =
 951                     (void *)dev_priv->ring_rptr->offset;
 952                 dev->agp_buffer_map->handle =
 953                     (void *)dev->agp_buffer_map->offset;
 954
 955                 DRM_DEBUG("dev_priv->cp_ring->handle %p\n",
 956                           dev_priv->cp_ring->handle);
 957                 DRM_DEBUG("dev_priv->ring_rptr->handle %p\n",
 958                           dev_priv->ring_rptr->handle);
 959                 DRM_DEBUG("dev->agp_buffer_map->handle %p\n",
 960                           dev->agp_buffer_map->handle);
 961         }
 962
 963         dev_priv->fb_location = (radeon_read_fb_location(dev_priv) & 0xffff) << 16;
 964         dev_priv->fb_size =
 965                 ((radeon_read_fb_location(dev_priv) & 0xffff0000u) + 0x10000)
 966                 - dev_priv->fb_location;
 967
 968         dev_priv->front_pitch_offset = (((dev_priv->front_pitch / 64) << 22) |
 969                                         ((dev_priv->front_offset
 970                                           + dev_priv->fb_location) >> 10));
 971
 972         dev_priv->back_pitch_offset = (((dev_priv->back_pitch / 64) << 22) |
 973                                        ((dev_priv->back_offset
 974                                          + dev_priv->fb_location) >> 10));
 975
 976         dev_priv->depth_pitch_offset = (((dev_priv->depth_pitch / 64) << 22) |
 977                                         ((dev_priv->depth_offset
 978                                           + dev_priv->fb_location) >> 10));
 979
 980         dev_priv->gart_size = init->gart_size;
 981
 982         /* New let's set the memory map ... */
 983         if (dev_priv->new_memmap) {
 984                 u32 base = 0;
 985
 986                 DRM_INFO("Setting GART location based on new memory map\n");
 987
 988                 /* If using AGP, try to locate the AGP aperture at the same
 989                  * location in the card and on the bus, though we have to
 990                  * align it down.
 991                  */
 992 #if __OS_HAS_AGP
 993                 if (dev_priv->flags & RADEON_IS_AGP) {
 994                         base = dev->agp->base;
 995                         /* Check if valid */
 996                         if ((base + dev_priv->gart_size - 1) >= dev_priv->fb_location &&
 997                             base < (dev_priv->fb_location + dev_priv->fb_size - 1)) {
 998                                 DRM_INFO("Can't use AGP base @0x%08lx, won't fit\n",
 999                                          dev->agp->base);
1000                                 base = 0;
1001                         }
1002                 }
1003 #endif
1004                 /* If not or if AGP is at 0 (Macs), try to put it elsewhere */
1005                 if (base == 0) {
1006                         base = dev_priv->fb_location + dev_priv->fb_size;
1007                         if (base < dev_priv->fb_location ||
1008                             ((base + dev_priv->gart_size) & 0xfffffffful) < base)
1009                                 base = dev_priv->fb_location
1010                                         - dev_priv->gart_size;
1011                 }
1012                 dev_priv->gart_vm_start = base & 0xffc00000u;
1013                 if (dev_priv->gart_vm_start != base)
1014                         DRM_INFO("GART aligned down from 0x%08x to 0x%08x\n",
1015                                  base, dev_priv->gart_vm_start);
1016         } else {
1017                 DRM_INFO("Setting GART location based on old memory map\n");
1018                 dev_priv->gart_vm_start = dev_priv->fb_location +
1019                         RADEON_READ(RADEON_CONFIG_APER_SIZE);
1020         }
1021
1022 #if __OS_HAS_AGP
1023         if (dev_priv->flags & RADEON_IS_AGP)
1024                 dev_priv->gart_buffers_offset = (dev->agp_buffer_map->offset
1025                                                  - dev->agp->base
1026                                                  + dev_priv->gart_vm_start);
1027         else
1028 #endif
1029                 dev_priv->gart_buffers_offset = (dev->agp_buffer_map->offset
1030                                         - (unsigned long)dev->sg->virtual
1031                                         + dev_priv->gart_vm_start);
1032
1033         DRM_DEBUG("dev_priv->gart_size %d\n", dev_priv->gart_size);
1034         DRM_DEBUG("dev_priv->gart_vm_start 0x%x\n", dev_priv->gart_vm_start);
1035         DRM_DEBUG("dev_priv->gart_buffers_offset 0x%lx\n",
1036                   dev_priv->gart_buffers_offset);
1037
1038         dev_priv->ring.start = (u32 *) dev_priv->cp_ring->handle;
1039         dev_priv->ring.end = ((u32 *) dev_priv->cp_ring->handle
1040                               + init->ring_size / sizeof(u32));
1041         dev_priv->ring.size = init->ring_size;
1042         dev_priv->ring.size_l2qw = drm_order(init->ring_size / 8);
1043
1044         dev_priv->ring.rptr_update = /* init->rptr_update */ 4096;
1045         dev_priv->ring.rptr_update_l2qw = drm_order( /* init->rptr_update */ 4096 / 8);
1046
1047         dev_priv->ring.fetch_size = /* init->fetch_size */ 32;
1048         dev_priv->ring.fetch_size_l2ow = drm_order( /* init->fetch_size */ 32 / 16);
1049         dev_priv->ring.tail_mask = (dev_priv->ring.size / sizeof(u32)) - 1;
1050
1051         dev_priv->ring.high_mark = RADEON_RING_HIGH_MARK;
1052
1053 #if __OS_HAS_AGP
1054         if (dev_priv->flags & RADEON_IS_AGP) {
1055                 /* Turn off PCI GART */
1056                 radeon_set_pcigart(dev_priv, 0);
1057         } else
1058 #endif
1059         {
1060                 dev_priv->gart_info.table_mask = DMA_BIT_MASK(32);
1061                 /* if we have an offset set from userspace */
1062                 if (dev_priv->pcigart_offset_set) {
1063                         dev_priv->gart_info.bus_addr =
1064                             dev_priv->pcigart_offset + dev_priv->fb_location;
1065                         dev_priv->gart_info.mapping.offset =
1066                             dev_priv->pcigart_offset + dev_priv->fb_aper_offset;
1067                         dev_priv->gart_info.mapping.size =
1068                             dev_priv->gart_info.table_size;
1069
1070                         drm_core_ioremap(&dev_priv->gart_info.mapping, dev);
1071                         dev_priv->gart_info.addr =
1072                             dev_priv->gart_info.mapping.handle;
1073
1074                         if (dev_priv->flags & RADEON_IS_PCIE)
1075                                 dev_priv->gart_info.gart_reg_if = DRM_ATI_GART_PCIE;
1076                         else
1077                                 dev_priv->gart_info.gart_reg_if = DRM_ATI_GART_PCI;
1078                         dev_priv->gart_info.gart_table_location =
1079                             DRM_ATI_GART_FB;
1080
1081                         DRM_DEBUG("Setting phys_pci_gart to %p %08lX\n",
1082                                   dev_priv->gart_info.addr,
1083                                   dev_priv->pcigart_offset);
1084                 } else {
1085                         if (dev_priv->flags & RADEON_IS_IGPGART)
1086                                 dev_priv->gart_info.gart_reg_if = DRM_ATI_GART_IGP;
1087                         else
1088                                 dev_priv->gart_info.gart_reg_if = DRM_ATI_GART_PCI;
1089                         dev_priv->gart_info.gart_table_location =
1090                             DRM_ATI_GART_MAIN;
1091                         dev_priv->gart_info.addr = NULL;
1092                         dev_priv->gart_info.bus_addr = 0;
1093                         if (dev_priv->flags & RADEON_IS_PCIE) {
1094                                 DRM_ERROR
1095                                     ("Cannot use PCI Express without GART in FB memory\n");
1096                                 radeon_do_cleanup_cp(dev);
1097                                 return -EINVAL;
1098                         }
1099                 }
1100
1101                 if (!drm_ati_pcigart_init(dev, &dev_priv->gart_info)) {
1102                         DRM_ERROR("failed to init PCI GART!\n");
1103                         radeon_do_cleanup_cp(dev);
1104                         return -ENOMEM;
1105                 }
1106
1107                 /* Turn on PCI GART */
1108                 radeon_set_pcigart(dev_priv, 1);
1109         }
1110
1111         radeon_cp_load_microcode(dev_priv);
1112         radeon_cp_init_ring_buffer(dev, dev_priv);
1113
1114         dev_priv->last_buf = 0;
1115
1116         radeon_do_engine_reset(dev);
1117         radeon_test_writeback(dev_priv);
1118
1119         return 0;
1120 }
1121
1122 static int radeon_do_cleanup_cp(struct drm_device * dev)
1123 {
1124         drm_radeon_private_t *dev_priv = dev->dev_private;
1125         DRM_DEBUG("\n");
1126
1127         /* Make sure interrupts are disabled here because the uninstall ioctl
1128          * may not have been called from userspace and after dev_private
1129          * is freed, it's too late.
1130          */
1131         if (dev->irq_enabled)
1132                 drm_irq_uninstall(dev);
1133
1134 #if __OS_HAS_AGP
1135         if (dev_priv->flags & RADEON_IS_AGP) {
1136                 if (dev_priv->cp_ring != NULL) {
1137                         drm_core_ioremapfree(dev_priv->cp_ring, dev);
1138                         dev_priv->cp_ring = NULL;
1139                 }
1140                 if (dev_priv->ring_rptr != NULL) {
1141                         drm_core_ioremapfree(dev_priv->ring_rptr, dev);
1142                         dev_priv->ring_rptr = NULL;
1143                 }
1144                 if (dev->agp_buffer_map != NULL) {
1145                         drm_core_ioremapfree(dev->agp_buffer_map, dev);
1146                         dev->agp_buffer_map = NULL;
1147                 }
1148         } else
1149 #endif
1150         {
1151
1152                 if (dev_priv->gart_info.bus_addr) {
1153                         /* Turn off PCI GART */
1154                         radeon_set_pcigart(dev_priv, 0);
1155                         if (!drm_ati_pcigart_cleanup(dev, &dev_priv->gart_info))
1156                                 DRM_ERROR("failed to cleanup PCI GART!\n");
1157                 }
1158
1159                 if (dev_priv->gart_info.gart_table_location == DRM_ATI_GART_FB)
1160                 {
1161                         drm_core_ioremapfree(&dev_priv->gart_info.mapping, dev);
1162                         dev_priv->gart_info.addr = 0;
1163                 }
1164         }
1165         /* only clear to the start of flags */
1166         memset(dev_priv, 0, offsetof(drm_radeon_private_t, flags));
1167
1168         return 0;
1169 }
1170
1171 /* This code will reinit the Radeon CP hardware after a resume from disc.
1172  * AFAIK, it would be very difficult to pickle the state at suspend time, so
1173  * here we make sure that all Radeon hardware initialisation is re-done without
1174  * affecting running applications.
1175  *
1176  * Charl P. Botha <http://cpbotha.net>
1177  */
1178 static int radeon_do_resume_cp(struct drm_device * dev)
1179 {
1180         drm_radeon_private_t *dev_priv = dev->dev_private;
1181
1182         if (!dev_priv) {
1183                 DRM_ERROR("Called with no initialization\n");
1184                 return -EINVAL;
1185         }
1186
1187         DRM_DEBUG("Starting radeon_do_resume_cp()\n");
1188
1189 #if __OS_HAS_AGP
1190         if (dev_priv->flags & RADEON_IS_AGP) {
1191                 /* Turn off PCI GART */
1192                 radeon_set_pcigart(dev_priv, 0);
1193         } else
1194 #endif
1195         {
1196                 /* Turn on PCI GART */
1197                 radeon_set_pcigart(dev_priv, 1);
1198         }
1199
1200         radeon_cp_load_microcode(dev_priv);
1201         radeon_cp_init_ring_buffer(dev, dev_priv);
1202
1203         radeon_do_engine_reset(dev);
1204
1205         DRM_DEBUG("radeon_do_resume_cp() complete\n");
1206
1207         return 0;
1208 }
1209
1210 int radeon_cp_init(struct drm_device *dev, void *data, struct drm_file *file_priv)
1211 {
1212         drm_radeon_init_t *init = data;
1213
1214         LOCK_TEST_WITH_RETURN(dev, file_priv);
1215
1216         if (init->func == RADEON_INIT_R300_CP)
1217                 r300_init_reg_flags(dev);
1218
1219         switch (init->func) {
1220         case RADEON_INIT_CP:
1221         case RADEON_INIT_R200_CP:
1222         case RADEON_INIT_R300_CP:
1223                 return radeon_do_init_cp(dev, init);
1224         case RADEON_CLEANUP_CP:
1225                 return radeon_do_cleanup_cp(dev);
1226         }
1227
1228         return -EINVAL;
1229 }
1230
1231 int radeon_cp_start(struct drm_device *dev, void *data, struct drm_file *file_priv)
1232 {
1233         drm_radeon_private_t *dev_priv = dev->dev_private;
1234         DRM_DEBUG("\n");
1235
1236         LOCK_TEST_WITH_RETURN(dev, file_priv);
1237
1238         if (dev_priv->cp_running) {
1239                 DRM_DEBUG("while CP running\n");
1240                 return 0;
1241         }
1242         if (dev_priv->cp_mode == RADEON_CSQ_PRIDIS_INDDIS) {
1243                 DRM_DEBUG("called with bogus CP mode (%d)\n",
1244                           dev_priv->cp_mode);
1245                 return 0;
1246         }
1247
1248         radeon_do_cp_start(dev_priv);
1249
1250         return 0;
1251 }
1252
1253 /* Stop the CP.  The engine must have been idled before calling this
1254  * routine.
1255  */
1256 int radeon_cp_stop(struct drm_device *dev, void *data, struct drm_file *file_priv)
1257 {
1258         drm_radeon_private_t *dev_priv = dev->dev_private;
1259         drm_radeon_cp_stop_t *stop = data;
1260         int ret;
1261         DRM_DEBUG("\n");
1262
1263         LOCK_TEST_WITH_RETURN(dev, file_priv);
1264
1265         if (!dev_priv->cp_running)
1266                 return 0;
1267
1268         /* Flush any pending CP commands.  This ensures any outstanding
1269          * commands are exectuted by the engine before we turn it off.
1270          */
1271         if (stop->flush) {
1272                 radeon_do_cp_flush(dev_priv);
1273         }
1274
1275         /* If we fail to make the engine go idle, we return an error
1276          * code so that the DRM ioctl wrapper can try again.
1277          */
1278         if (stop->idle) {
1279                 ret = radeon_do_cp_idle(dev_priv);
1280                 if (ret)
1281                         return ret;
1282         }
1283
1284         /* Finally, we can turn off the CP.  If the engine isn't idle,
1285          * we will get some dropped triangles as they won't be fully
1286          * rendered before the CP is shut down.
1287          */
1288         radeon_do_cp_stop(dev_priv);
1289
1290         /* Reset the engine */
1291         radeon_do_engine_reset(dev);
1292
1293         return 0;
1294 }
1295
1296 void radeon_do_release(struct drm_device * dev)
1297 {
1298         drm_radeon_private_t *dev_priv = dev->dev_private;
1299         int i, ret;
1300
1301         if (dev_priv) {
1302                 if (dev_priv->cp_running) {
1303                         /* Stop the cp */
1304                         while ((ret = radeon_do_cp_idle(dev_priv)) != 0) {
1305                                 DRM_DEBUG("radeon_do_cp_idle %d\n", ret);
1306 #ifdef __linux__
1307                                 schedule();
1308 #else
1309                                 tsleep(&ret, PZERO, "rdnrel", 1);
1310 #endif
1311                         }
1312                         radeon_do_cp_stop(dev_priv);
1313                         radeon_do_engine_reset(dev);
1314                 }
1315
1316                 /* Disable *all* interrupts */
1317                 if (dev_priv->mmio)     /* remove this after permanent addmaps */
1318                         RADEON_WRITE(RADEON_GEN_INT_CNTL, 0);
1319
1320                 if (dev_priv->mmio) {   /* remove all surfaces */
1321                         for (i = 0; i < RADEON_MAX_SURFACES; i++) {
1322                                 RADEON_WRITE(RADEON_SURFACE0_INFO + 16 * i, 0);
1323                                 RADEON_WRITE(RADEON_SURFACE0_LOWER_BOUND +
1324                                              16 * i, 0);
1325                                 RADEON_WRITE(RADEON_SURFACE0_UPPER_BOUND +
1326                                              16 * i, 0);
1327                         }
1328                 }
1329
1330                 /* Free memory heap structures */
1331                 radeon_mem_takedown(&(dev_priv->gart_heap));
1332                 radeon_mem_takedown(&(dev_priv->fb_heap));
1333
1334                 /* deallocate kernel resources */
1335                 radeon_do_cleanup_cp(dev);
1336         }
1337 }
1338
1339 /* Just reset the CP ring.  Called as part of an X Server engine reset.
1340  */
1341 int radeon_cp_reset(struct drm_device *dev, void *data, struct drm_file *file_priv)
1342 {
1343         drm_radeon_private_t *dev_priv = dev->dev_private;
1344         DRM_DEBUG("\n");
1345
1346         LOCK_TEST_WITH_RETURN(dev, file_priv);
1347
1348         if (!dev_priv) {
1349                 DRM_DEBUG("called before init done\n");
1350                 return -EINVAL;
1351         }
1352
1353         radeon_do_cp_reset(dev_priv);
1354
1355         /* The CP is no longer running after an engine reset */
1356         dev_priv->cp_running = 0;
1357
1358         return 0;
1359 }
1360
1361 int radeon_cp_idle(struct drm_device *dev, void *data, struct drm_file *file_priv)
1362 {
1363         drm_radeon_private_t *dev_priv = dev->dev_private;
1364         DRM_DEBUG("\n");
1365
1366         LOCK_TEST_WITH_RETURN(dev, file_priv);
1367
1368         return radeon_do_cp_idle(dev_priv);
1369 }
1370
1371 /* Added by Charl P. Botha to call radeon_do_resume_cp().
1372  */
1373 int radeon_cp_resume(struct drm_device *dev, void *data, struct drm_file *file_priv)
1374 {
1375
1376         return radeon_do_resume_cp(dev);
1377 }
1378
1379 int radeon_engine_reset(struct drm_device *dev, void *data, struct drm_file *file_priv)
1380 {
1381         DRM_DEBUG("\n");
1382
1383         LOCK_TEST_WITH_RETURN(dev, file_priv);
1384
1385         return radeon_do_engine_reset(dev);
1386 }
1387
1388 /* ================================================================
1389  * Fullscreen mode
1390  */
1391
1392 /* KW: Deprecated to say the least:
1393  */
1394 int radeon_fullscreen(struct drm_device *dev, void *data, struct drm_file *file_priv)
1395 {
1396         return 0;
1397 }
1398
1399 /* ================================================================
1400  * Freelist management
1401  */
1402
1403 /* Original comment: FIXME: ROTATE_BUFS is a hack to cycle through
1404  *   bufs until freelist code is used.  Note this hides a problem with
1405  *   the scratch register * (used to keep track of last buffer
1406  *   completed) being written to before * the last buffer has actually
1407  *   completed rendering.
1408  *
1409  * KW:  It's also a good way to find free buffers quickly.
1410  *
1411  * KW: Ideally this loop wouldn't exist, and freelist_get wouldn't
1412  * sleep.  However, bugs in older versions of radeon_accel.c mean that
1413  * we essentially have to do this, else old clients will break.
1414  *
1415  * However, it does leave open a potential deadlock where all the
1416  * buffers are held by other clients, which can't release them because
1417  * they can't get the lock.
1418  */
1419
1420 struct drm_buf *radeon_freelist_get(struct drm_device * dev)
1421 {
1422         struct drm_device_dma *dma = dev->dma;
1423         drm_radeon_private_t *dev_priv = dev->dev_private;
1424         drm_radeon_buf_priv_t *buf_priv;
1425         struct drm_buf *buf;
1426         int i, t;
1427         int start;
1428
1429         if (++dev_priv->last_buf >= dma->buf_count)
1430                 dev_priv->last_buf = 0;
1431
1432         start = dev_priv->last_buf;
1433
1434         for (t = 0; t < dev_priv->usec_timeout; t++) {
1435                 u32 done_age = GET_SCRATCH(1);
1436                 DRM_DEBUG("done_age = %d\n", done_age);
1437                 for (i = start; i < dma->buf_count; i++) {
1438                         buf = dma->buflist[i];
1439                         buf_priv = buf->dev_private;
1440                         if (buf->file_priv == NULL || (buf->pending &&
1441                                                        buf_priv->age <=
1442                                                        done_age)) {
1443                                 dev_priv->stats.requested_bufs++;
1444                                 buf->pending = 0;
1445                                 return buf;
1446                         }
1447                         start = 0;
1448                 }
1449
1450                 if (t) {
1451                         DRM_UDELAY(1);
1452                         dev_priv->stats.freelist_loops++;
1453                 }
1454         }
1455
1456         DRM_DEBUG("returning NULL!\n");
1457         return NULL;
1458 }
1459
1460 #if 0
1461 struct drm_buf *radeon_freelist_get(struct drm_device * dev)
1462 {
1463         struct drm_device_dma *dma = dev->dma;
1464         drm_radeon_private_t *dev_priv = dev->dev_private;
1465         drm_radeon_buf_priv_t *buf_priv;
1466         struct drm_buf *buf;
1467         int i, t;
1468         int start;
1469         u32 done_age = DRM_READ32(dev_priv->ring_rptr, RADEON_SCRATCHOFF(1));
1470
1471         if (++dev_priv->last_buf >= dma->buf_count)
1472                 dev_priv->last_buf = 0;
1473
1474         start = dev_priv->last_buf;
1475         dev_priv->stats.freelist_loops++;
1476
1477         for (t = 0; t < 2; t++) {
1478                 for (i = start; i < dma->buf_count; i++) {
1479                         buf = dma->buflist[i];
1480                         buf_priv = buf->dev_private;
1481                         if (buf->file_priv == 0 || (buf->pending &&
1482                                                     buf_priv->age <=
1483                                                     done_age)) {
1484                                 dev_priv->stats.requested_bufs++;
1485                                 buf->pending = 0;
1486                                 return buf;
1487                         }
1488                 }
1489                 start = 0;
1490         }
1491
1492         return NULL;
1493 }
1494 #endif
1495
1496 void radeon_freelist_reset(struct drm_device * dev)
1497 {
1498         struct drm_device_dma *dma = dev->dma;
1499         drm_radeon_private_t *dev_priv = dev->dev_private;
1500         int i;
1501
1502         dev_priv->last_buf = 0;
1503         for (i = 0; i < dma->buf_count; i++) {
1504                 struct drm_buf *buf = dma->buflist[i];
1505                 drm_radeon_buf_priv_t *buf_priv = buf->dev_private;
1506                 buf_priv->age = 0;
1507         }
1508 }
1509
1510 /* ================================================================
1511  * CP command submission
1512  */
1513
1514 int radeon_wait_ring(drm_radeon_private_t * dev_priv, int n)
1515 {
1516         drm_radeon_ring_buffer_t *ring = &dev_priv->ring;
1517         int i;
1518         u32 last_head = GET_RING_HEAD(dev_priv);
1519
1520         for (i = 0; i < dev_priv->usec_timeout; i++) {
1521                 u32 head = GET_RING_HEAD(dev_priv);
1522
1523                 ring->space = (head - ring->tail) * sizeof(u32);
1524                 if (ring->space <= 0)
1525                         ring->space += ring->size;
1526                 if (ring->space > n)
1527                         return 0;
1528
1529                 dev_priv->stats.boxes |= RADEON_BOX_WAIT_IDLE;
1530
1531                 if (head != last_head)
1532                         i = 0;
1533                 last_head = head;
1534
1535                 DRM_UDELAY(1);
1536         }
1537
1538         /* FIXME: This return value is ignored in the BEGIN_RING macro! */
1539 #if RADEON_FIFO_DEBUG
1540         radeon_status(dev_priv);
1541         DRM_ERROR("failed!\n");
1542 #endif
1543         return -EBUSY;
1544 }
1545
1546 static int radeon_cp_get_buffers(struct drm_device *dev,
1547                                  struct drm_file *file_priv,
1548                                  struct drm_dma * d)
1549 {
1550         int i;
1551         struct drm_buf *buf;
1552
1553         for (i = d->granted_count; i < d->request_count; i++) {
1554                 buf = radeon_freelist_get(dev);
1555                 if (!buf)
1556                         return -EBUSY;  /* NOTE: broken client */
1557
1558                 buf->file_priv = file_priv;
1559
1560                 if (DRM_COPY_TO_USER(&d->request_indices[i], &buf->idx,
1561                                      sizeof(buf->idx)))
1562                         return -EFAULT;
1563                 if (DRM_COPY_TO_USER(&d->request_sizes[i], &buf->total,
1564                                      sizeof(buf->total)))
1565                         return -EFAULT;
1566
1567                 d->granted_count++;
1568         }
1569         return 0;
1570 }
1571
1572 int radeon_cp_buffers(struct drm_device *dev, void *data, struct drm_file *file_priv)
1573 {
1574         struct drm_device_dma *dma = dev->dma;
1575         int ret = 0;
1576         struct drm_dma *d = data;
1577
1578         LOCK_TEST_WITH_RETURN(dev, file_priv);
1579
1580         /* Please don't send us buffers.
1581          */
1582         if (d->send_count != 0) {
1583                 DRM_ERROR("Process %d trying to send %d buffers via drmDMA\n",
1584                           DRM_CURRENTPID, d->send_count);
1585                 return -EINVAL;
1586         }
1587
1588         /* We'll send you buffers.
1589          */
1590         if (d->request_count < 0 || d->request_count > dma->buf_count) {
1591                 DRM_ERROR("Process %d trying to get %d buffers (of %d max)\n",
1592                           DRM_CURRENTPID, d->request_count, dma->buf_count);
1593                 return -EINVAL;
1594         }
1595
1596         d->granted_count = 0;
1597
1598         if (d->request_count) {
1599                 ret = radeon_cp_get_buffers(dev, file_priv, d);
1600         }
1601
1602         return ret;
1603 }
1604
1605 int radeon_driver_load(struct drm_device *dev, unsigned long flags)
1606 {
1607         drm_radeon_private_t *dev_priv;
1608         int ret = 0;
1609
1610         dev_priv = drm_alloc(sizeof(drm_radeon_private_t), DRM_MEM_DRIVER);
1611         if (dev_priv == NULL)
1612                 return -ENOMEM;
1613
1614         memset(dev_priv, 0, sizeof(drm_radeon_private_t));
1615         dev->dev_private = (void *)dev_priv;
1616         dev_priv->flags = flags;
1617
1618         switch (flags & RADEON_FAMILY_MASK) {
1619         case CHIP_R100:
1620         case CHIP_RV200:
1621         case CHIP_R200:
1622         case CHIP_R300:
1623         case CHIP_R350:
1624         case CHIP_R420:
1625         case CHIP_RV410:
1626         case CHIP_RV515:
1627         case CHIP_R520:
1628         case CHIP_RV570:
1629         case CHIP_R580:
1630                 dev_priv->flags |= RADEON_HAS_HIERZ;
1631                 break;
1632         default:
1633                 /* all other chips have no hierarchical z buffer */
1634                 break;
1635         }
1636
1637         if (drm_device_is_agp(dev))
1638                 dev_priv->flags |= RADEON_IS_AGP;
1639         else if (drm_device_is_pcie(dev))
1640                 dev_priv->flags |= RADEON_IS_PCIE;
1641         else
1642                 dev_priv->flags |= RADEON_IS_PCI;
1643
1644         DRM_DEBUG("%s card detected\n",
1645                   ((dev_priv->flags & RADEON_IS_AGP) ? "AGP" : (((dev_priv->flags & RADEON_IS_PCIE) ? "PCIE" : "PCI"))));
1646         return ret;
1647 }
1648
1649 /* Create mappings for registers and framebuffer so userland doesn't necessarily
1650  * have to find them.
1651  */
1652 int radeon_driver_firstopen(struct drm_device *dev)
1653 {
1654         int ret;
1655         drm_local_map_t *map;
1656         drm_radeon_private_t *dev_priv = dev->dev_private;
1657
1658         dev_priv->gart_info.table_size = RADEON_PCIGART_TABLE_SIZE;
1659
1660         ret = drm_addmap(dev, drm_get_resource_start(dev, 2),
1661                          drm_get_resource_len(dev, 2), _DRM_REGISTERS,
1662                          _DRM_READ_ONLY, &dev_priv->mmio);
1663         if (ret != 0)
1664                 return ret;
1665
1666         dev_priv->fb_aper_offset = drm_get_resource_start(dev, 0);
1667         ret = drm_addmap(dev, dev_priv->fb_aper_offset,
1668                          drm_get_resource_len(dev, 0), _DRM_FRAME_BUFFER,
1669                          _DRM_WRITE_COMBINING, &map);
1670         if (ret != 0)
1671                 return ret;
1672
1673         return 0;
1674 }
1675
1676 int radeon_driver_unload(struct drm_device *dev)
1677 {
1678         drm_radeon_private_t *dev_priv = dev->dev_private;
1679
1680         DRM_DEBUG("\n");
1681         drm_free(dev_priv, sizeof(*dev_priv), DRM_MEM_DRIVER);
1682
1683         dev->dev_private = NULL;
1684         return 0;
1685 }