1 /* radeon_cp.c -- CP support for Radeon -*- linux-c -*- */
3 * Copyright 2000 Precision Insight, Inc., Cedar Park, Texas.
4 * Copyright 2000 VA Linux Systems, Inc., Fremont, California.
7 * Permission is hereby granted, free of charge, to any person obtaining a
8 * copy of this software and associated documentation files (the "Software"),
9 * to deal in the Software without restriction, including without limitation
10 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
11 * and/or sell copies of the Software, and to permit persons to whom the
12 * Software is furnished to do so, subject to the following conditions:
14 * The above copyright notice and this permission notice (including the next
15 * paragraph) shall be included in all copies or substantial portions of the
18 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
19 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
20 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
21 * PRECISION INSIGHT AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR
22 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
23 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
24 * DEALINGS IN THE SOFTWARE.
27 * Kevin E. Martin <martin@valinux.com>
28 * Gareth Hughes <gareth@valinux.com>
33 #include "radeon_drm.h"
34 #include "radeon_drv.h"
37 #include "radeon_microcode.h"
39 #define RADEON_FIFO_DEBUG 0
41 static int radeon_do_cleanup_cp(struct drm_device * dev);
43 static u32 RADEON_READ_MCIND(drm_radeon_private_t *dev_priv, int addr)
46 RADEON_WRITE(R520_MC_IND_INDEX, 0x7f0000 | (addr & 0xff));
47 ret = RADEON_READ(R520_MC_IND_DATA);
48 RADEON_WRITE(R520_MC_IND_INDEX, 0);
52 static u32 RS690_READ_MCIND(drm_radeon_private_t *dev_priv, int addr)
54 RADEON_WRITE(RS690_MC_INDEX, (addr & RS690_MC_INDEX_MASK));
55 return RADEON_READ(RS690_MC_DATA);
58 u32 radeon_read_fb_location(drm_radeon_private_t *dev_priv)
61 if ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RV515)
62 return RADEON_READ_MCIND(dev_priv, RV515_MC_FB_LOCATION);
63 else if ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS690)
64 return RS690_READ_MCIND(dev_priv, RS690_MC_FB_LOCATION);
65 else if ((dev_priv->flags & RADEON_FAMILY_MASK) > CHIP_RV515)
66 return RADEON_READ_MCIND(dev_priv, R520_MC_FB_LOCATION);
68 return RADEON_READ(RADEON_MC_FB_LOCATION);
71 static void radeon_write_fb_location(drm_radeon_private_t *dev_priv, u32 fb_loc)
73 if ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RV515)
74 RADEON_WRITE_MCIND(RV515_MC_FB_LOCATION, fb_loc);
75 else if ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS690)
76 RS690_WRITE_MCIND(RS690_MC_FB_LOCATION, fb_loc);
77 else if ((dev_priv->flags & RADEON_FAMILY_MASK) > CHIP_RV515)
78 RADEON_WRITE_MCIND(R520_MC_FB_LOCATION, fb_loc);
80 RADEON_WRITE(RADEON_MC_FB_LOCATION, fb_loc);
83 static void radeon_write_agp_location(drm_radeon_private_t *dev_priv, u32 agp_loc)
85 if ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RV515)
86 RADEON_WRITE_MCIND(RV515_MC_AGP_LOCATION, agp_loc);
87 else if ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS690)
88 RS690_WRITE_MCIND(RS690_MC_AGP_LOCATION, agp_loc);
89 else if ((dev_priv->flags & RADEON_FAMILY_MASK) > CHIP_RV515)
90 RADEON_WRITE_MCIND(R520_MC_AGP_LOCATION, agp_loc);
92 RADEON_WRITE(RADEON_MC_AGP_LOCATION, agp_loc);
95 static int RADEON_READ_PLL(struct drm_device * dev, int addr)
97 drm_radeon_private_t *dev_priv = dev->dev_private;
99 RADEON_WRITE8(RADEON_CLOCK_CNTL_INDEX, addr & 0x1f);
100 return RADEON_READ(RADEON_CLOCK_CNTL_DATA);
103 static u32 RADEON_READ_PCIE(drm_radeon_private_t *dev_priv, int addr)
105 RADEON_WRITE8(RADEON_PCIE_INDEX, addr & 0xff);
106 return RADEON_READ(RADEON_PCIE_DATA);
109 static u32 RADEON_READ_IGPGART(drm_radeon_private_t *dev_priv, int addr)
112 RADEON_WRITE(RS400_NB_MC_INDEX, addr & 0x7f);
113 ret = RADEON_READ(RS400_NB_MC_DATA);
114 RADEON_WRITE(RS400_NB_MC_INDEX, 0x7f);
118 #if RADEON_FIFO_DEBUG
119 static void radeon_status(drm_radeon_private_t * dev_priv)
121 printk("%s:\n", __func__);
122 printk("RBBM_STATUS = 0x%08x\n",
123 (unsigned int)RADEON_READ(RADEON_RBBM_STATUS));
124 printk("CP_RB_RTPR = 0x%08x\n",
125 (unsigned int)RADEON_READ(RADEON_CP_RB_RPTR));
126 printk("CP_RB_WTPR = 0x%08x\n",
127 (unsigned int)RADEON_READ(RADEON_CP_RB_WPTR));
128 printk("AIC_CNTL = 0x%08x\n",
129 (unsigned int)RADEON_READ(RADEON_AIC_CNTL));
130 printk("AIC_STAT = 0x%08x\n",
131 (unsigned int)RADEON_READ(RADEON_AIC_STAT));
132 printk("AIC_PT_BASE = 0x%08x\n",
133 (unsigned int)RADEON_READ(RADEON_AIC_PT_BASE));
134 printk("TLB_ADDR = 0x%08x\n",
135 (unsigned int)RADEON_READ(RADEON_AIC_TLB_ADDR));
136 printk("TLB_DATA = 0x%08x\n",
137 (unsigned int)RADEON_READ(RADEON_AIC_TLB_DATA));
141 /* ================================================================
142 * Engine, FIFO control
145 static int radeon_do_pixcache_flush(drm_radeon_private_t * dev_priv)
150 dev_priv->stats.boxes |= RADEON_BOX_WAIT_IDLE;
152 tmp = RADEON_READ(RADEON_RB3D_DSTCACHE_CTLSTAT);
153 tmp |= RADEON_RB3D_DC_FLUSH_ALL;
154 RADEON_WRITE(RADEON_RB3D_DSTCACHE_CTLSTAT, tmp);
156 for (i = 0; i < dev_priv->usec_timeout; i++) {
157 if (!(RADEON_READ(RADEON_RB3D_DSTCACHE_CTLSTAT)
158 & RADEON_RB3D_DC_BUSY)) {
164 #if RADEON_FIFO_DEBUG
165 DRM_ERROR("failed!\n");
166 radeon_status(dev_priv);
171 static int radeon_do_wait_for_fifo(drm_radeon_private_t * dev_priv, int entries)
175 dev_priv->stats.boxes |= RADEON_BOX_WAIT_IDLE;
177 for (i = 0; i < dev_priv->usec_timeout; i++) {
178 int slots = (RADEON_READ(RADEON_RBBM_STATUS)
179 & RADEON_RBBM_FIFOCNT_MASK);
180 if (slots >= entries)
185 #if RADEON_FIFO_DEBUG
186 DRM_ERROR("failed!\n");
187 radeon_status(dev_priv);
192 static int radeon_do_wait_for_idle(drm_radeon_private_t * dev_priv)
196 dev_priv->stats.boxes |= RADEON_BOX_WAIT_IDLE;
198 ret = radeon_do_wait_for_fifo(dev_priv, 64);
202 for (i = 0; i < dev_priv->usec_timeout; i++) {
203 if (!(RADEON_READ(RADEON_RBBM_STATUS)
204 & RADEON_RBBM_ACTIVE)) {
205 radeon_do_pixcache_flush(dev_priv);
211 #if RADEON_FIFO_DEBUG
212 DRM_ERROR("failed!\n");
213 radeon_status(dev_priv);
218 /* ================================================================
219 * CP control, initialization
222 /* Load the microcode for the CP */
223 static void radeon_cp_load_microcode(drm_radeon_private_t * dev_priv)
228 radeon_do_wait_for_idle(dev_priv);
230 RADEON_WRITE(RADEON_CP_ME_RAM_ADDR, 0);
231 if (((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_R100) ||
232 ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RV100) ||
233 ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RV200) ||
234 ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS100) ||
235 ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS200)) {
236 DRM_INFO("Loading R100 Microcode\n");
237 for (i = 0; i < 256; i++) {
238 RADEON_WRITE(RADEON_CP_ME_RAM_DATAH,
239 R100_cp_microcode[i][1]);
240 RADEON_WRITE(RADEON_CP_ME_RAM_DATAL,
241 R100_cp_microcode[i][0]);
243 } else if (((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_R200) ||
244 ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RV250) ||
245 ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RV280) ||
246 ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS300)) {
247 DRM_INFO("Loading R200 Microcode\n");
248 for (i = 0; i < 256; i++) {
249 RADEON_WRITE(RADEON_CP_ME_RAM_DATAH,
250 R200_cp_microcode[i][1]);
251 RADEON_WRITE(RADEON_CP_ME_RAM_DATAL,
252 R200_cp_microcode[i][0]);
254 } else if (((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_R300) ||
255 ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_R350) ||
256 ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RV350) ||
257 ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RV380) ||
258 ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS400)) {
259 DRM_INFO("Loading R300 Microcode\n");
260 for (i = 0; i < 256; i++) {
261 RADEON_WRITE(RADEON_CP_ME_RAM_DATAH,
262 R300_cp_microcode[i][1]);
263 RADEON_WRITE(RADEON_CP_ME_RAM_DATAL,
264 R300_cp_microcode[i][0]);
266 } else if (((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_R420) ||
267 ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RV410)) {
268 DRM_INFO("Loading R400 Microcode\n");
269 for (i = 0; i < 256; i++) {
270 RADEON_WRITE(RADEON_CP_ME_RAM_DATAH,
271 R420_cp_microcode[i][1]);
272 RADEON_WRITE(RADEON_CP_ME_RAM_DATAL,
273 R420_cp_microcode[i][0]);
275 } else if ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS690) {
276 DRM_INFO("Loading RS690 Microcode\n");
277 for (i = 0; i < 256; i++) {
278 RADEON_WRITE(RADEON_CP_ME_RAM_DATAH,
279 RS690_cp_microcode[i][1]);
280 RADEON_WRITE(RADEON_CP_ME_RAM_DATAL,
281 RS690_cp_microcode[i][0]);
283 } else if (((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RV515) ||
284 ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_R520) ||
285 ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RV530) ||
286 ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_R580) ||
287 ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RV560) ||
288 ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RV570)) {
289 DRM_INFO("Loading R500 Microcode\n");
290 for (i = 0; i < 256; i++) {
291 RADEON_WRITE(RADEON_CP_ME_RAM_DATAH,
292 R520_cp_microcode[i][1]);
293 RADEON_WRITE(RADEON_CP_ME_RAM_DATAL,
294 R520_cp_microcode[i][0]);
299 /* Flush any pending commands to the CP. This should only be used just
300 * prior to a wait for idle, as it informs the engine that the command
303 static void radeon_do_cp_flush(drm_radeon_private_t * dev_priv)
309 tmp = RADEON_READ(RADEON_CP_RB_WPTR) | (1 << 31);
310 RADEON_WRITE(RADEON_CP_RB_WPTR, tmp);
314 /* Wait for the CP to go idle.
316 int radeon_do_cp_idle(drm_radeon_private_t * dev_priv)
323 RADEON_PURGE_CACHE();
324 RADEON_PURGE_ZCACHE();
325 RADEON_WAIT_UNTIL_IDLE();
330 return radeon_do_wait_for_idle(dev_priv);
333 /* Start the Command Processor.
335 static void radeon_do_cp_start(drm_radeon_private_t * dev_priv)
340 radeon_do_wait_for_idle(dev_priv);
342 RADEON_WRITE(RADEON_CP_CSQ_CNTL, dev_priv->cp_mode);
344 dev_priv->cp_running = 1;
348 RADEON_PURGE_CACHE();
349 RADEON_PURGE_ZCACHE();
350 RADEON_WAIT_UNTIL_IDLE();
356 /* Reset the Command Processor. This will not flush any pending
357 * commands, so you must wait for the CP command stream to complete
358 * before calling this routine.
360 static void radeon_do_cp_reset(drm_radeon_private_t * dev_priv)
365 cur_read_ptr = RADEON_READ(RADEON_CP_RB_RPTR);
366 RADEON_WRITE(RADEON_CP_RB_WPTR, cur_read_ptr);
367 SET_RING_HEAD(dev_priv, cur_read_ptr);
368 dev_priv->ring.tail = cur_read_ptr;
371 /* Stop the Command Processor. This will not flush any pending
372 * commands, so you must flush the command stream and wait for the CP
373 * to go idle before calling this routine.
375 static void radeon_do_cp_stop(drm_radeon_private_t * dev_priv)
379 RADEON_WRITE(RADEON_CP_CSQ_CNTL, RADEON_CSQ_PRIDIS_INDDIS);
381 dev_priv->cp_running = 0;
384 /* Reset the engine. This will stop the CP if it is running.
386 static int radeon_do_engine_reset(struct drm_device * dev)
388 drm_radeon_private_t *dev_priv = dev->dev_private;
389 u32 clock_cntl_index, mclk_cntl, rbbm_soft_reset;
392 radeon_do_pixcache_flush(dev_priv);
394 if ((dev_priv->flags & RADEON_FAMILY_MASK) < CHIP_RV515) {
395 clock_cntl_index = RADEON_READ(RADEON_CLOCK_CNTL_INDEX);
396 mclk_cntl = RADEON_READ_PLL(dev, RADEON_MCLK_CNTL);
398 RADEON_WRITE_PLL(RADEON_MCLK_CNTL, (mclk_cntl |
399 RADEON_FORCEON_MCLKA |
400 RADEON_FORCEON_MCLKB |
401 RADEON_FORCEON_YCLKA |
402 RADEON_FORCEON_YCLKB |
404 RADEON_FORCEON_AIC));
406 rbbm_soft_reset = RADEON_READ(RADEON_RBBM_SOFT_RESET);
408 RADEON_WRITE(RADEON_RBBM_SOFT_RESET, (rbbm_soft_reset |
409 RADEON_SOFT_RESET_CP |
410 RADEON_SOFT_RESET_HI |
411 RADEON_SOFT_RESET_SE |
412 RADEON_SOFT_RESET_RE |
413 RADEON_SOFT_RESET_PP |
414 RADEON_SOFT_RESET_E2 |
415 RADEON_SOFT_RESET_RB));
416 RADEON_READ(RADEON_RBBM_SOFT_RESET);
417 RADEON_WRITE(RADEON_RBBM_SOFT_RESET, (rbbm_soft_reset &
418 ~(RADEON_SOFT_RESET_CP |
419 RADEON_SOFT_RESET_HI |
420 RADEON_SOFT_RESET_SE |
421 RADEON_SOFT_RESET_RE |
422 RADEON_SOFT_RESET_PP |
423 RADEON_SOFT_RESET_E2 |
424 RADEON_SOFT_RESET_RB)));
425 RADEON_READ(RADEON_RBBM_SOFT_RESET);
427 RADEON_WRITE_PLL(RADEON_MCLK_CNTL, mclk_cntl);
428 RADEON_WRITE(RADEON_CLOCK_CNTL_INDEX, clock_cntl_index);
429 RADEON_WRITE(RADEON_RBBM_SOFT_RESET, rbbm_soft_reset);
432 /* Reset the CP ring */
433 radeon_do_cp_reset(dev_priv);
435 /* The CP is no longer running after an engine reset */
436 dev_priv->cp_running = 0;
438 /* Reset any pending vertex, indirect buffers */
439 radeon_freelist_reset(dev);
444 static void radeon_cp_init_ring_buffer(struct drm_device * dev,
445 drm_radeon_private_t * dev_priv)
447 u32 ring_start, cur_read_ptr;
450 /* Initialize the memory controller. With new memory map, the fb location
451 * is not changed, it should have been properly initialized already. Part
452 * of the problem is that the code below is bogus, assuming the GART is
453 * always appended to the fb which is not necessarily the case
455 if (!dev_priv->new_memmap)
456 radeon_write_fb_location(dev_priv,
457 ((dev_priv->gart_vm_start - 1) & 0xffff0000)
458 | (dev_priv->fb_location >> 16));
461 if (dev_priv->flags & RADEON_IS_AGP) {
462 RADEON_WRITE(RADEON_AGP_BASE, (unsigned int)dev->agp->base);
463 radeon_write_agp_location(dev_priv,
464 (((dev_priv->gart_vm_start - 1 +
465 dev_priv->gart_size) & 0xffff0000) |
466 (dev_priv->gart_vm_start >> 16)));
468 ring_start = (dev_priv->cp_ring->offset
470 + dev_priv->gart_vm_start);
473 ring_start = (dev_priv->cp_ring->offset
474 - (unsigned long)dev->sg->virtual
475 + dev_priv->gart_vm_start);
477 RADEON_WRITE(RADEON_CP_RB_BASE, ring_start);
479 /* Set the write pointer delay */
480 RADEON_WRITE(RADEON_CP_RB_WPTR_DELAY, 0);
482 /* Initialize the ring buffer's read and write pointers */
483 cur_read_ptr = RADEON_READ(RADEON_CP_RB_RPTR);
484 RADEON_WRITE(RADEON_CP_RB_WPTR, cur_read_ptr);
485 SET_RING_HEAD(dev_priv, cur_read_ptr);
486 dev_priv->ring.tail = cur_read_ptr;
489 if (dev_priv->flags & RADEON_IS_AGP) {
490 RADEON_WRITE(RADEON_CP_RB_RPTR_ADDR,
491 dev_priv->ring_rptr->offset
492 - dev->agp->base + dev_priv->gart_vm_start);
496 struct drm_sg_mem *entry = dev->sg;
497 unsigned long tmp_ofs, page_ofs;
499 tmp_ofs = dev_priv->ring_rptr->offset -
500 (unsigned long)dev->sg->virtual;
501 page_ofs = tmp_ofs >> PAGE_SHIFT;
503 RADEON_WRITE(RADEON_CP_RB_RPTR_ADDR, entry->busaddr[page_ofs]);
504 DRM_DEBUG("ring rptr: offset=0x%08lx handle=0x%08lx\n",
505 (unsigned long)entry->busaddr[page_ofs],
506 entry->handle + tmp_ofs);
509 /* Set ring buffer size */
511 RADEON_WRITE(RADEON_CP_RB_CNTL,
512 RADEON_BUF_SWAP_32BIT |
513 (dev_priv->ring.fetch_size_l2ow << 18) |
514 (dev_priv->ring.rptr_update_l2qw << 8) |
515 dev_priv->ring.size_l2qw);
517 RADEON_WRITE(RADEON_CP_RB_CNTL,
518 (dev_priv->ring.fetch_size_l2ow << 18) |
519 (dev_priv->ring.rptr_update_l2qw << 8) |
520 dev_priv->ring.size_l2qw);
523 /* Start with assuming that writeback doesn't work */
524 dev_priv->writeback_works = 0;
526 /* Initialize the scratch register pointer. This will cause
527 * the scratch register values to be written out to memory
528 * whenever they are updated.
530 * We simply put this behind the ring read pointer, this works
531 * with PCI GART as well as (whatever kind of) AGP GART
533 RADEON_WRITE(RADEON_SCRATCH_ADDR, RADEON_READ(RADEON_CP_RB_RPTR_ADDR)
534 + RADEON_SCRATCH_REG_OFFSET);
536 dev_priv->scratch = ((__volatile__ u32 *)
537 dev_priv->ring_rptr->handle +
538 (RADEON_SCRATCH_REG_OFFSET / sizeof(u32)));
540 RADEON_WRITE(RADEON_SCRATCH_UMSK, 0x7);
542 /* Turn on bus mastering */
543 tmp = RADEON_READ(RADEON_BUS_CNTL) & ~RADEON_BUS_MASTER_DIS;
544 RADEON_WRITE(RADEON_BUS_CNTL, tmp);
546 dev_priv->sarea_priv->last_frame = dev_priv->scratch[0] = 0;
547 RADEON_WRITE(RADEON_LAST_FRAME_REG, dev_priv->sarea_priv->last_frame);
549 dev_priv->sarea_priv->last_dispatch = dev_priv->scratch[1] = 0;
550 RADEON_WRITE(RADEON_LAST_DISPATCH_REG,
551 dev_priv->sarea_priv->last_dispatch);
553 dev_priv->sarea_priv->last_clear = dev_priv->scratch[2] = 0;
554 RADEON_WRITE(RADEON_LAST_CLEAR_REG, dev_priv->sarea_priv->last_clear);
556 radeon_do_wait_for_idle(dev_priv);
558 /* Sync everything up */
559 RADEON_WRITE(RADEON_ISYNC_CNTL,
560 (RADEON_ISYNC_ANY2D_IDLE3D |
561 RADEON_ISYNC_ANY3D_IDLE2D |
562 RADEON_ISYNC_WAIT_IDLEGUI |
563 RADEON_ISYNC_CPSCRATCH_IDLEGUI));
567 static void radeon_test_writeback(drm_radeon_private_t * dev_priv)
571 /* Writeback doesn't seem to work everywhere, test it here and possibly
572 * enable it if it appears to work
574 DRM_WRITE32(dev_priv->ring_rptr, RADEON_SCRATCHOFF(1), 0);
575 RADEON_WRITE(RADEON_SCRATCH_REG1, 0xdeadbeef);
577 for (tmp = 0; tmp < dev_priv->usec_timeout; tmp++) {
578 if (DRM_READ32(dev_priv->ring_rptr, RADEON_SCRATCHOFF(1)) ==
584 if (tmp < dev_priv->usec_timeout) {
585 dev_priv->writeback_works = 1;
586 DRM_INFO("writeback test succeeded in %d usecs\n", tmp);
588 dev_priv->writeback_works = 0;
589 DRM_INFO("writeback test failed\n");
591 if (radeon_no_wb == 1) {
592 dev_priv->writeback_works = 0;
593 DRM_INFO("writeback forced off\n");
596 if (!dev_priv->writeback_works) {
597 /* Disable writeback to avoid unnecessary bus master transfer */
598 RADEON_WRITE(RADEON_CP_RB_CNTL, RADEON_READ(RADEON_CP_RB_CNTL) |
599 RADEON_RB_NO_UPDATE);
600 RADEON_WRITE(RADEON_SCRATCH_UMSK, 0);
604 /* Enable or disable IGP GART on the chip */
605 static void radeon_set_igpgart(drm_radeon_private_t * dev_priv, int on)
609 tmp = RADEON_READ(RADEON_AIC_CNTL);
611 DRM_DEBUG("programming igpgart %08X %08lX %08X\n",
612 dev_priv->gart_vm_start,
613 (long)dev_priv->gart_info.bus_addr,
614 dev_priv->gart_size);
616 RADEON_WRITE_IGPGART(RS400_MC_MISC_CNTL, RS400_GART_INDEX_REG_EN);
617 RADEON_WRITE_IGPGART(RS400_AGP_ADDRESS_SPACE_SIZE, (RS400_GART_EN |
618 RS400_VA_SIZE_32MB));
619 RADEON_WRITE_IGPGART(RS400_GART_FEATURE_ID, (RS400_HANG_EN |
623 RADEON_WRITE_IGPGART(RS400_GART_BASE,
624 dev_priv->gart_info.bus_addr);
626 temp = RADEON_READ_IGPGART(dev_priv, RS400_AGP_MODE_CNTL);
627 RADEON_WRITE_IGPGART(RS400_AGP_MODE_CNTL, temp);
629 RADEON_WRITE(RADEON_AGP_BASE, (unsigned int)dev_priv->gart_vm_start);
630 dev_priv->gart_size = 32*1024*1024;
631 radeon_write_agp_location(dev_priv,
632 (((dev_priv->gart_vm_start - 1 +
633 dev_priv->gart_size) & 0xffff0000) |
634 (dev_priv->gart_vm_start >> 16)));
636 temp = RADEON_READ_IGPGART(dev_priv, RS400_AGP_ADDRESS_SPACE_SIZE);
637 RADEON_WRITE_IGPGART(RS400_AGP_ADDRESS_SPACE_SIZE, temp);
639 RADEON_READ_IGPGART(dev_priv, RS400_GART_CACHE_CNTRL);
640 RADEON_WRITE_IGPGART(RS400_GART_CACHE_CNTRL, RS400_GART_CACHE_INVALIDATE);
641 RADEON_READ_IGPGART(dev_priv, RS400_GART_CACHE_CNTRL);
642 RADEON_WRITE_IGPGART(RS400_GART_CACHE_CNTRL, 0);
646 /* Enable or disable RS690 GART on the chip */
647 static void radeon_set_rs690gart(drm_radeon_private_t *dev_priv, int on)
652 DRM_DEBUG("programming rs690 gart %08X %08lX %08X\n",
653 dev_priv->gart_vm_start,
654 (long)dev_priv->gart_info.bus_addr,
655 dev_priv->gart_size);
657 temp = RS690_READ_MCIND(dev_priv, RS400_MC_MISC_CNTL);
658 RS690_WRITE_MCIND(RS400_MC_MISC_CNTL, (RS400_GART_INDEX_REG_EN |
659 RS690_BLOCK_GFX_D3_EN));
661 RS690_WRITE_MCIND(RS400_AGP_ADDRESS_SPACE_SIZE, (RS400_GART_EN |
662 RS400_VA_SIZE_32MB));
664 temp = RS690_READ_MCIND(dev_priv, RS400_GART_FEATURE_ID);
665 RS690_WRITE_MCIND(RS400_GART_FEATURE_ID, (RS400_HANG_EN |
670 temp = dev_priv->gart_info.bus_addr & 0xfffff000;
671 temp |= (upper_32_bits(dev_priv->gart_info.bus_addr) & 0xff) << 4;
672 RS690_WRITE_MCIND(RS400_GART_BASE, temp);
674 temp = RS690_READ_MCIND(dev_priv, RS400_AGP_MODE_CNTL);
675 RS690_WRITE_MCIND(RS400_AGP_MODE_CNTL, ((1 << RS400_REQ_TYPE_SNOOP_SHIFT) |
676 RS400_REQ_TYPE_SNOOP_DIS));
678 RS690_WRITE_MCIND(RS690_MC_AGP_BASE,
679 (unsigned int)dev_priv->gart_vm_start);
681 RS690_WRITE_MCIND(RS690_MC_AGP_BASE_2, 0);
683 dev_priv->gart_size = 32*1024*1024;
684 temp = (((dev_priv->gart_vm_start - 1 + dev_priv->gart_size) &
685 0xffff0000) | (dev_priv->gart_vm_start >> 16));
687 RS690_WRITE_MCIND(RS690_MC_AGP_LOCATION, temp);
689 temp = RS690_READ_MCIND(dev_priv, RS400_AGP_ADDRESS_SPACE_SIZE);
690 RS690_WRITE_MCIND(RS400_AGP_ADDRESS_SPACE_SIZE, (RS400_GART_EN |
691 RS400_VA_SIZE_32MB));
694 temp = RS690_READ_MCIND(dev_priv, RS400_GART_CACHE_CNTRL);
695 if ((temp & RS690_MC_GART_CLEAR_STATUS) ==
696 RS690_MC_GART_CLEAR_DONE)
701 RS690_WRITE_MCIND(RS400_GART_CACHE_CNTRL,
702 RS400_GART_CACHE_INVALIDATE);
705 temp = RS690_READ_MCIND(dev_priv, RS400_GART_CACHE_CNTRL);
706 if ((temp & RS690_MC_GART_CLEAR_STATUS) ==
707 RS690_MC_GART_CLEAR_DONE)
712 RS690_WRITE_MCIND(RS400_GART_CACHE_CNTRL, 0);
714 RS690_WRITE_MCIND(RS400_AGP_ADDRESS_SPACE_SIZE, 0);
718 static void radeon_set_pciegart(drm_radeon_private_t * dev_priv, int on)
720 u32 tmp = RADEON_READ_PCIE(dev_priv, RADEON_PCIE_TX_GART_CNTL);
723 DRM_DEBUG("programming pcie %08X %08lX %08X\n",
724 dev_priv->gart_vm_start,
725 (long)dev_priv->gart_info.bus_addr,
726 dev_priv->gart_size);
727 RADEON_WRITE_PCIE(RADEON_PCIE_TX_DISCARD_RD_ADDR_LO,
728 dev_priv->gart_vm_start);
729 RADEON_WRITE_PCIE(RADEON_PCIE_TX_GART_BASE,
730 dev_priv->gart_info.bus_addr);
731 RADEON_WRITE_PCIE(RADEON_PCIE_TX_GART_START_LO,
732 dev_priv->gart_vm_start);
733 RADEON_WRITE_PCIE(RADEON_PCIE_TX_GART_END_LO,
734 dev_priv->gart_vm_start +
735 dev_priv->gart_size - 1);
737 radeon_write_agp_location(dev_priv, 0xffffffc0); /* ?? */
739 RADEON_WRITE_PCIE(RADEON_PCIE_TX_GART_CNTL,
740 RADEON_PCIE_TX_GART_EN);
742 RADEON_WRITE_PCIE(RADEON_PCIE_TX_GART_CNTL,
743 tmp & ~RADEON_PCIE_TX_GART_EN);
747 /* Enable or disable PCI GART on the chip */
748 static void radeon_set_pcigart(drm_radeon_private_t * dev_priv, int on)
752 if ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS690) {
753 radeon_set_rs690gart(dev_priv, on);
757 if (dev_priv->flags & RADEON_IS_IGPGART) {
758 radeon_set_igpgart(dev_priv, on);
762 if (dev_priv->flags & RADEON_IS_PCIE) {
763 radeon_set_pciegart(dev_priv, on);
767 tmp = RADEON_READ(RADEON_AIC_CNTL);
770 RADEON_WRITE(RADEON_AIC_CNTL,
771 tmp | RADEON_PCIGART_TRANSLATE_EN);
773 /* set PCI GART page-table base address
775 RADEON_WRITE(RADEON_AIC_PT_BASE, dev_priv->gart_info.bus_addr);
777 /* set address range for PCI address translate
779 RADEON_WRITE(RADEON_AIC_LO_ADDR, dev_priv->gart_vm_start);
780 RADEON_WRITE(RADEON_AIC_HI_ADDR, dev_priv->gart_vm_start
781 + dev_priv->gart_size - 1);
783 /* Turn off AGP aperture -- is this required for PCI GART?
785 radeon_write_agp_location(dev_priv, 0xffffffc0);
786 RADEON_WRITE(RADEON_AGP_COMMAND, 0); /* clear AGP_COMMAND */
788 RADEON_WRITE(RADEON_AIC_CNTL,
789 tmp & ~RADEON_PCIGART_TRANSLATE_EN);
793 static int radeon_do_init_cp(struct drm_device * dev, drm_radeon_init_t * init)
795 drm_radeon_private_t *dev_priv = dev->dev_private;
799 /* if we require new memory map but we don't have it fail */
800 if ((dev_priv->flags & RADEON_NEW_MEMMAP) && !dev_priv->new_memmap) {
801 DRM_ERROR("Cannot initialise DRM on this card\nThis card requires a new X.org DDX for 3D\n");
802 radeon_do_cleanup_cp(dev);
806 if (init->is_pci && (dev_priv->flags & RADEON_IS_AGP)) {
807 DRM_DEBUG("Forcing AGP card to PCI mode\n");
808 dev_priv->flags &= ~RADEON_IS_AGP;
809 } else if (!(dev_priv->flags & (RADEON_IS_AGP | RADEON_IS_PCI | RADEON_IS_PCIE))
811 DRM_DEBUG("Restoring AGP flag\n");
812 dev_priv->flags |= RADEON_IS_AGP;
815 if ((!(dev_priv->flags & RADEON_IS_AGP)) && !dev->sg) {
816 DRM_ERROR("PCI GART memory not allocated!\n");
817 radeon_do_cleanup_cp(dev);
821 dev_priv->usec_timeout = init->usec_timeout;
822 if (dev_priv->usec_timeout < 1 ||
823 dev_priv->usec_timeout > RADEON_MAX_USEC_TIMEOUT) {
824 DRM_DEBUG("TIMEOUT problem!\n");
825 radeon_do_cleanup_cp(dev);
829 /* Enable vblank on CRTC1 for older X servers
831 dev_priv->vblank_crtc = DRM_RADEON_VBLANK_CRTC1;
834 case RADEON_INIT_R200_CP:
835 dev_priv->microcode_version = UCODE_R200;
837 case RADEON_INIT_R300_CP:
838 dev_priv->microcode_version = UCODE_R300;
841 dev_priv->microcode_version = UCODE_R100;
844 dev_priv->do_boxes = 0;
845 dev_priv->cp_mode = init->cp_mode;
847 /* We don't support anything other than bus-mastering ring mode,
848 * but the ring can be in either AGP or PCI space for the ring
851 if ((init->cp_mode != RADEON_CSQ_PRIBM_INDDIS) &&
852 (init->cp_mode != RADEON_CSQ_PRIBM_INDBM)) {
853 DRM_DEBUG("BAD cp_mode (%x)!\n", init->cp_mode);
854 radeon_do_cleanup_cp(dev);
858 switch (init->fb_bpp) {
860 dev_priv->color_fmt = RADEON_COLOR_FORMAT_RGB565;
864 dev_priv->color_fmt = RADEON_COLOR_FORMAT_ARGB8888;
867 dev_priv->front_offset = init->front_offset;
868 dev_priv->front_pitch = init->front_pitch;
869 dev_priv->back_offset = init->back_offset;
870 dev_priv->back_pitch = init->back_pitch;
872 switch (init->depth_bpp) {
874 dev_priv->depth_fmt = RADEON_DEPTH_FORMAT_16BIT_INT_Z;
878 dev_priv->depth_fmt = RADEON_DEPTH_FORMAT_24BIT_INT_Z;
881 dev_priv->depth_offset = init->depth_offset;
882 dev_priv->depth_pitch = init->depth_pitch;
884 /* Hardware state for depth clears. Remove this if/when we no
885 * longer clear the depth buffer with a 3D rectangle. Hard-code
886 * all values to prevent unwanted 3D state from slipping through
887 * and screwing with the clear operation.
889 dev_priv->depth_clear.rb3d_cntl = (RADEON_PLANE_MASK_ENABLE |
890 (dev_priv->color_fmt << 10) |
891 (dev_priv->microcode_version ==
892 UCODE_R100 ? RADEON_ZBLOCK16 : 0));
894 dev_priv->depth_clear.rb3d_zstencilcntl =
895 (dev_priv->depth_fmt |
896 RADEON_Z_TEST_ALWAYS |
897 RADEON_STENCIL_TEST_ALWAYS |
898 RADEON_STENCIL_S_FAIL_REPLACE |
899 RADEON_STENCIL_ZPASS_REPLACE |
900 RADEON_STENCIL_ZFAIL_REPLACE | RADEON_Z_WRITE_ENABLE);
902 dev_priv->depth_clear.se_cntl = (RADEON_FFACE_CULL_CW |
905 RADEON_FLAT_SHADE_VTX_LAST |
906 RADEON_DIFFUSE_SHADE_FLAT |
907 RADEON_ALPHA_SHADE_FLAT |
908 RADEON_SPECULAR_SHADE_FLAT |
909 RADEON_FOG_SHADE_FLAT |
910 RADEON_VTX_PIX_CENTER_OGL |
911 RADEON_ROUND_MODE_TRUNC |
912 RADEON_ROUND_PREC_8TH_PIX);
915 dev_priv->ring_offset = init->ring_offset;
916 dev_priv->ring_rptr_offset = init->ring_rptr_offset;
917 dev_priv->buffers_offset = init->buffers_offset;
918 dev_priv->gart_textures_offset = init->gart_textures_offset;
920 dev_priv->sarea = drm_getsarea(dev);
921 if (!dev_priv->sarea) {
922 DRM_ERROR("could not find sarea!\n");
923 radeon_do_cleanup_cp(dev);
927 dev_priv->cp_ring = drm_core_findmap(dev, init->ring_offset);
928 if (!dev_priv->cp_ring) {
929 DRM_ERROR("could not find cp ring region!\n");
930 radeon_do_cleanup_cp(dev);
933 dev_priv->ring_rptr = drm_core_findmap(dev, init->ring_rptr_offset);
934 if (!dev_priv->ring_rptr) {
935 DRM_ERROR("could not find ring read pointer!\n");
936 radeon_do_cleanup_cp(dev);
939 dev->agp_buffer_token = init->buffers_offset;
940 dev->agp_buffer_map = drm_core_findmap(dev, init->buffers_offset);
941 if (!dev->agp_buffer_map) {
942 DRM_ERROR("could not find dma buffer region!\n");
943 radeon_do_cleanup_cp(dev);
947 if (init->gart_textures_offset) {
948 dev_priv->gart_textures =
949 drm_core_findmap(dev, init->gart_textures_offset);
950 if (!dev_priv->gart_textures) {
951 DRM_ERROR("could not find GART texture region!\n");
952 radeon_do_cleanup_cp(dev);
957 dev_priv->sarea_priv =
958 (drm_radeon_sarea_t *) ((u8 *) dev_priv->sarea->handle +
959 init->sarea_priv_offset);
962 if (dev_priv->flags & RADEON_IS_AGP) {
963 drm_core_ioremap(dev_priv->cp_ring, dev);
964 drm_core_ioremap(dev_priv->ring_rptr, dev);
965 drm_core_ioremap(dev->agp_buffer_map, dev);
966 if (!dev_priv->cp_ring->handle ||
967 !dev_priv->ring_rptr->handle ||
968 !dev->agp_buffer_map->handle) {
969 DRM_ERROR("could not find ioremap agp regions!\n");
970 radeon_do_cleanup_cp(dev);
976 dev_priv->cp_ring->handle = (void *)dev_priv->cp_ring->offset;
977 dev_priv->ring_rptr->handle =
978 (void *)dev_priv->ring_rptr->offset;
979 dev->agp_buffer_map->handle =
980 (void *)dev->agp_buffer_map->offset;
982 DRM_DEBUG("dev_priv->cp_ring->handle %p\n",
983 dev_priv->cp_ring->handle);
984 DRM_DEBUG("dev_priv->ring_rptr->handle %p\n",
985 dev_priv->ring_rptr->handle);
986 DRM_DEBUG("dev->agp_buffer_map->handle %p\n",
987 dev->agp_buffer_map->handle);
990 dev_priv->fb_location = (radeon_read_fb_location(dev_priv) & 0xffff) << 16;
992 ((radeon_read_fb_location(dev_priv) & 0xffff0000u) + 0x10000)
993 - dev_priv->fb_location;
995 dev_priv->front_pitch_offset = (((dev_priv->front_pitch / 64) << 22) |
996 ((dev_priv->front_offset
997 + dev_priv->fb_location) >> 10));
999 dev_priv->back_pitch_offset = (((dev_priv->back_pitch / 64) << 22) |
1000 ((dev_priv->back_offset
1001 + dev_priv->fb_location) >> 10));
1003 dev_priv->depth_pitch_offset = (((dev_priv->depth_pitch / 64) << 22) |
1004 ((dev_priv->depth_offset
1005 + dev_priv->fb_location) >> 10));
1007 dev_priv->gart_size = init->gart_size;
1009 /* New let's set the memory map ... */
1010 if (dev_priv->new_memmap) {
1013 DRM_INFO("Setting GART location based on new memory map\n");
1015 /* If using AGP, try to locate the AGP aperture at the same
1016 * location in the card and on the bus, though we have to
1020 if (dev_priv->flags & RADEON_IS_AGP) {
1021 base = dev->agp->base;
1022 /* Check if valid */
1023 if ((base + dev_priv->gart_size - 1) >= dev_priv->fb_location &&
1024 base < (dev_priv->fb_location + dev_priv->fb_size - 1)) {
1025 DRM_INFO("Can't use AGP base @0x%08lx, won't fit\n",
1031 /* If not or if AGP is at 0 (Macs), try to put it elsewhere */
1033 base = dev_priv->fb_location + dev_priv->fb_size;
1034 if (base < dev_priv->fb_location ||
1035 ((base + dev_priv->gart_size) & 0xfffffffful) < base)
1036 base = dev_priv->fb_location
1037 - dev_priv->gart_size;
1039 dev_priv->gart_vm_start = base & 0xffc00000u;
1040 if (dev_priv->gart_vm_start != base)
1041 DRM_INFO("GART aligned down from 0x%08x to 0x%08x\n",
1042 base, dev_priv->gart_vm_start);
1044 DRM_INFO("Setting GART location based on old memory map\n");
1045 dev_priv->gart_vm_start = dev_priv->fb_location +
1046 RADEON_READ(RADEON_CONFIG_APER_SIZE);
1050 if (dev_priv->flags & RADEON_IS_AGP)
1051 dev_priv->gart_buffers_offset = (dev->agp_buffer_map->offset
1053 + dev_priv->gart_vm_start);
1056 dev_priv->gart_buffers_offset = (dev->agp_buffer_map->offset
1057 - (unsigned long)dev->sg->virtual
1058 + dev_priv->gart_vm_start);
1060 DRM_DEBUG("dev_priv->gart_size %d\n", dev_priv->gart_size);
1061 DRM_DEBUG("dev_priv->gart_vm_start 0x%x\n", dev_priv->gart_vm_start);
1062 DRM_DEBUG("dev_priv->gart_buffers_offset 0x%lx\n",
1063 dev_priv->gart_buffers_offset);
1065 dev_priv->ring.start = (u32 *) dev_priv->cp_ring->handle;
1066 dev_priv->ring.end = ((u32 *) dev_priv->cp_ring->handle
1067 + init->ring_size / sizeof(u32));
1068 dev_priv->ring.size = init->ring_size;
1069 dev_priv->ring.size_l2qw = drm_order(init->ring_size / 8);
1071 dev_priv->ring.rptr_update = /* init->rptr_update */ 4096;
1072 dev_priv->ring.rptr_update_l2qw = drm_order( /* init->rptr_update */ 4096 / 8);
1074 dev_priv->ring.fetch_size = /* init->fetch_size */ 32;
1075 dev_priv->ring.fetch_size_l2ow = drm_order( /* init->fetch_size */ 32 / 16);
1076 dev_priv->ring.tail_mask = (dev_priv->ring.size / sizeof(u32)) - 1;
1078 dev_priv->ring.high_mark = RADEON_RING_HIGH_MARK;
1081 if (dev_priv->flags & RADEON_IS_AGP) {
1082 /* Turn off PCI GART */
1083 radeon_set_pcigart(dev_priv, 0);
1087 dev_priv->gart_info.table_mask = DMA_BIT_MASK(32);
1088 /* if we have an offset set from userspace */
1089 if (dev_priv->pcigart_offset_set) {
1090 dev_priv->gart_info.bus_addr =
1091 dev_priv->pcigart_offset + dev_priv->fb_location;
1092 dev_priv->gart_info.mapping.offset =
1093 dev_priv->pcigart_offset + dev_priv->fb_aper_offset;
1094 dev_priv->gart_info.mapping.size =
1095 dev_priv->gart_info.table_size;
1097 drm_core_ioremap(&dev_priv->gart_info.mapping, dev);
1098 dev_priv->gart_info.addr =
1099 dev_priv->gart_info.mapping.handle;
1101 if (dev_priv->flags & RADEON_IS_PCIE)
1102 dev_priv->gart_info.gart_reg_if = DRM_ATI_GART_PCIE;
1104 dev_priv->gart_info.gart_reg_if = DRM_ATI_GART_PCI;
1105 dev_priv->gart_info.gart_table_location =
1108 DRM_DEBUG("Setting phys_pci_gart to %p %08lX\n",
1109 dev_priv->gart_info.addr,
1110 dev_priv->pcigart_offset);
1112 if (dev_priv->flags & RADEON_IS_IGPGART)
1113 dev_priv->gart_info.gart_reg_if = DRM_ATI_GART_IGP;
1115 dev_priv->gart_info.gart_reg_if = DRM_ATI_GART_PCI;
1116 dev_priv->gart_info.gart_table_location =
1118 dev_priv->gart_info.addr = NULL;
1119 dev_priv->gart_info.bus_addr = 0;
1120 if (dev_priv->flags & RADEON_IS_PCIE) {
1122 ("Cannot use PCI Express without GART in FB memory\n");
1123 radeon_do_cleanup_cp(dev);
1128 if (!drm_ati_pcigart_init(dev, &dev_priv->gart_info)) {
1129 DRM_ERROR("failed to init PCI GART!\n");
1130 radeon_do_cleanup_cp(dev);
1134 /* Turn on PCI GART */
1135 radeon_set_pcigart(dev_priv, 1);
1138 radeon_cp_load_microcode(dev_priv);
1139 radeon_cp_init_ring_buffer(dev, dev_priv);
1141 dev_priv->last_buf = 0;
1143 radeon_do_engine_reset(dev);
1144 radeon_test_writeback(dev_priv);
1149 static int radeon_do_cleanup_cp(struct drm_device * dev)
1151 drm_radeon_private_t *dev_priv = dev->dev_private;
1154 /* Make sure interrupts are disabled here because the uninstall ioctl
1155 * may not have been called from userspace and after dev_private
1156 * is freed, it's too late.
1158 if (dev->irq_enabled)
1159 drm_irq_uninstall(dev);
1162 if (dev_priv->flags & RADEON_IS_AGP) {
1163 if (dev_priv->cp_ring != NULL) {
1164 drm_core_ioremapfree(dev_priv->cp_ring, dev);
1165 dev_priv->cp_ring = NULL;
1167 if (dev_priv->ring_rptr != NULL) {
1168 drm_core_ioremapfree(dev_priv->ring_rptr, dev);
1169 dev_priv->ring_rptr = NULL;
1171 if (dev->agp_buffer_map != NULL) {
1172 drm_core_ioremapfree(dev->agp_buffer_map, dev);
1173 dev->agp_buffer_map = NULL;
1179 if (dev_priv->gart_info.bus_addr) {
1180 /* Turn off PCI GART */
1181 radeon_set_pcigart(dev_priv, 0);
1182 if (!drm_ati_pcigart_cleanup(dev, &dev_priv->gart_info))
1183 DRM_ERROR("failed to cleanup PCI GART!\n");
1186 if (dev_priv->gart_info.gart_table_location == DRM_ATI_GART_FB)
1188 drm_core_ioremapfree(&dev_priv->gart_info.mapping, dev);
1189 dev_priv->gart_info.addr = 0;
1192 /* only clear to the start of flags */
1193 memset(dev_priv, 0, offsetof(drm_radeon_private_t, flags));
1198 /* This code will reinit the Radeon CP hardware after a resume from disc.
1199 * AFAIK, it would be very difficult to pickle the state at suspend time, so
1200 * here we make sure that all Radeon hardware initialisation is re-done without
1201 * affecting running applications.
1203 * Charl P. Botha <http://cpbotha.net>
1205 static int radeon_do_resume_cp(struct drm_device * dev)
1207 drm_radeon_private_t *dev_priv = dev->dev_private;
1210 DRM_ERROR("Called with no initialization\n");
1214 DRM_DEBUG("Starting radeon_do_resume_cp()\n");
1217 if (dev_priv->flags & RADEON_IS_AGP) {
1218 /* Turn off PCI GART */
1219 radeon_set_pcigart(dev_priv, 0);
1223 /* Turn on PCI GART */
1224 radeon_set_pcigart(dev_priv, 1);
1227 radeon_cp_load_microcode(dev_priv);
1228 radeon_cp_init_ring_buffer(dev, dev_priv);
1230 radeon_do_engine_reset(dev);
1232 DRM_DEBUG("radeon_do_resume_cp() complete\n");
1237 int radeon_cp_init(struct drm_device *dev, void *data, struct drm_file *file_priv)
1239 drm_radeon_init_t *init = data;
1241 LOCK_TEST_WITH_RETURN(dev, file_priv);
1243 if (init->func == RADEON_INIT_R300_CP)
1244 r300_init_reg_flags(dev);
1246 switch (init->func) {
1247 case RADEON_INIT_CP:
1248 case RADEON_INIT_R200_CP:
1249 case RADEON_INIT_R300_CP:
1250 return radeon_do_init_cp(dev, init);
1251 case RADEON_CLEANUP_CP:
1252 return radeon_do_cleanup_cp(dev);
1258 int radeon_cp_start(struct drm_device *dev, void *data, struct drm_file *file_priv)
1260 drm_radeon_private_t *dev_priv = dev->dev_private;
1263 LOCK_TEST_WITH_RETURN(dev, file_priv);
1265 if (dev_priv->cp_running) {
1266 DRM_DEBUG("while CP running\n");
1269 if (dev_priv->cp_mode == RADEON_CSQ_PRIDIS_INDDIS) {
1270 DRM_DEBUG("called with bogus CP mode (%d)\n",
1275 radeon_do_cp_start(dev_priv);
1280 /* Stop the CP. The engine must have been idled before calling this
1283 int radeon_cp_stop(struct drm_device *dev, void *data, struct drm_file *file_priv)
1285 drm_radeon_private_t *dev_priv = dev->dev_private;
1286 drm_radeon_cp_stop_t *stop = data;
1290 LOCK_TEST_WITH_RETURN(dev, file_priv);
1292 if (!dev_priv->cp_running)
1295 /* Flush any pending CP commands. This ensures any outstanding
1296 * commands are exectuted by the engine before we turn it off.
1299 radeon_do_cp_flush(dev_priv);
1302 /* If we fail to make the engine go idle, we return an error
1303 * code so that the DRM ioctl wrapper can try again.
1306 ret = radeon_do_cp_idle(dev_priv);
1311 /* Finally, we can turn off the CP. If the engine isn't idle,
1312 * we will get some dropped triangles as they won't be fully
1313 * rendered before the CP is shut down.
1315 radeon_do_cp_stop(dev_priv);
1317 /* Reset the engine */
1318 radeon_do_engine_reset(dev);
1323 void radeon_do_release(struct drm_device * dev)
1325 drm_radeon_private_t *dev_priv = dev->dev_private;
1329 if (dev_priv->cp_running) {
1331 while ((ret = radeon_do_cp_idle(dev_priv)) != 0) {
1332 DRM_DEBUG("radeon_do_cp_idle %d\n", ret);
1336 tsleep(&ret, PZERO, "rdnrel", 1);
1339 radeon_do_cp_stop(dev_priv);
1340 radeon_do_engine_reset(dev);
1343 /* Disable *all* interrupts */
1344 if (dev_priv->mmio) /* remove this after permanent addmaps */
1345 RADEON_WRITE(RADEON_GEN_INT_CNTL, 0);
1347 if (dev_priv->mmio) { /* remove all surfaces */
1348 for (i = 0; i < RADEON_MAX_SURFACES; i++) {
1349 RADEON_WRITE(RADEON_SURFACE0_INFO + 16 * i, 0);
1350 RADEON_WRITE(RADEON_SURFACE0_LOWER_BOUND +
1352 RADEON_WRITE(RADEON_SURFACE0_UPPER_BOUND +
1357 /* Free memory heap structures */
1358 radeon_mem_takedown(&(dev_priv->gart_heap));
1359 radeon_mem_takedown(&(dev_priv->fb_heap));
1361 /* deallocate kernel resources */
1362 radeon_do_cleanup_cp(dev);
1366 /* Just reset the CP ring. Called as part of an X Server engine reset.
1368 int radeon_cp_reset(struct drm_device *dev, void *data, struct drm_file *file_priv)
1370 drm_radeon_private_t *dev_priv = dev->dev_private;
1373 LOCK_TEST_WITH_RETURN(dev, file_priv);
1376 DRM_DEBUG("called before init done\n");
1380 radeon_do_cp_reset(dev_priv);
1382 /* The CP is no longer running after an engine reset */
1383 dev_priv->cp_running = 0;
1388 int radeon_cp_idle(struct drm_device *dev, void *data, struct drm_file *file_priv)
1390 drm_radeon_private_t *dev_priv = dev->dev_private;
1393 LOCK_TEST_WITH_RETURN(dev, file_priv);
1395 return radeon_do_cp_idle(dev_priv);
1398 /* Added by Charl P. Botha to call radeon_do_resume_cp().
1400 int radeon_cp_resume(struct drm_device *dev, void *data, struct drm_file *file_priv)
1403 return radeon_do_resume_cp(dev);
1406 int radeon_engine_reset(struct drm_device *dev, void *data, struct drm_file *file_priv)
1410 LOCK_TEST_WITH_RETURN(dev, file_priv);
1412 return radeon_do_engine_reset(dev);
1415 /* ================================================================
1419 /* KW: Deprecated to say the least:
1421 int radeon_fullscreen(struct drm_device *dev, void *data, struct drm_file *file_priv)
1426 /* ================================================================
1427 * Freelist management
1430 /* Original comment: FIXME: ROTATE_BUFS is a hack to cycle through
1431 * bufs until freelist code is used. Note this hides a problem with
1432 * the scratch register * (used to keep track of last buffer
1433 * completed) being written to before * the last buffer has actually
1434 * completed rendering.
1436 * KW: It's also a good way to find free buffers quickly.
1438 * KW: Ideally this loop wouldn't exist, and freelist_get wouldn't
1439 * sleep. However, bugs in older versions of radeon_accel.c mean that
1440 * we essentially have to do this, else old clients will break.
1442 * However, it does leave open a potential deadlock where all the
1443 * buffers are held by other clients, which can't release them because
1444 * they can't get the lock.
1447 struct drm_buf *radeon_freelist_get(struct drm_device * dev)
1449 struct drm_device_dma *dma = dev->dma;
1450 drm_radeon_private_t *dev_priv = dev->dev_private;
1451 drm_radeon_buf_priv_t *buf_priv;
1452 struct drm_buf *buf;
1456 if (++dev_priv->last_buf >= dma->buf_count)
1457 dev_priv->last_buf = 0;
1459 start = dev_priv->last_buf;
1461 for (t = 0; t < dev_priv->usec_timeout; t++) {
1462 u32 done_age = GET_SCRATCH(1);
1463 DRM_DEBUG("done_age = %d\n", done_age);
1464 for (i = start; i < dma->buf_count; i++) {
1465 buf = dma->buflist[i];
1466 buf_priv = buf->dev_private;
1467 if (buf->file_priv == NULL || (buf->pending &&
1470 dev_priv->stats.requested_bufs++;
1479 dev_priv->stats.freelist_loops++;
1483 DRM_DEBUG("returning NULL!\n");
1488 struct drm_buf *radeon_freelist_get(struct drm_device * dev)
1490 struct drm_device_dma *dma = dev->dma;
1491 drm_radeon_private_t *dev_priv = dev->dev_private;
1492 drm_radeon_buf_priv_t *buf_priv;
1493 struct drm_buf *buf;
1496 u32 done_age = DRM_READ32(dev_priv->ring_rptr, RADEON_SCRATCHOFF(1));
1498 if (++dev_priv->last_buf >= dma->buf_count)
1499 dev_priv->last_buf = 0;
1501 start = dev_priv->last_buf;
1502 dev_priv->stats.freelist_loops++;
1504 for (t = 0; t < 2; t++) {
1505 for (i = start; i < dma->buf_count; i++) {
1506 buf = dma->buflist[i];
1507 buf_priv = buf->dev_private;
1508 if (buf->file_priv == 0 || (buf->pending &&
1511 dev_priv->stats.requested_bufs++;
1523 void radeon_freelist_reset(struct drm_device * dev)
1525 struct drm_device_dma *dma = dev->dma;
1526 drm_radeon_private_t *dev_priv = dev->dev_private;
1529 dev_priv->last_buf = 0;
1530 for (i = 0; i < dma->buf_count; i++) {
1531 struct drm_buf *buf = dma->buflist[i];
1532 drm_radeon_buf_priv_t *buf_priv = buf->dev_private;
1537 /* ================================================================
1538 * CP command submission
1541 int radeon_wait_ring(drm_radeon_private_t * dev_priv, int n)
1543 drm_radeon_ring_buffer_t *ring = &dev_priv->ring;
1545 u32 last_head = GET_RING_HEAD(dev_priv);
1547 for (i = 0; i < dev_priv->usec_timeout; i++) {
1548 u32 head = GET_RING_HEAD(dev_priv);
1550 ring->space = (head - ring->tail) * sizeof(u32);
1551 if (ring->space <= 0)
1552 ring->space += ring->size;
1553 if (ring->space > n)
1556 dev_priv->stats.boxes |= RADEON_BOX_WAIT_IDLE;
1558 if (head != last_head)
1565 /* FIXME: This return value is ignored in the BEGIN_RING macro! */
1566 #if RADEON_FIFO_DEBUG
1567 radeon_status(dev_priv);
1568 DRM_ERROR("failed!\n");
1573 static int radeon_cp_get_buffers(struct drm_device *dev,
1574 struct drm_file *file_priv,
1578 struct drm_buf *buf;
1580 for (i = d->granted_count; i < d->request_count; i++) {
1581 buf = radeon_freelist_get(dev);
1583 return -EBUSY; /* NOTE: broken client */
1585 buf->file_priv = file_priv;
1587 if (DRM_COPY_TO_USER(&d->request_indices[i], &buf->idx,
1590 if (DRM_COPY_TO_USER(&d->request_sizes[i], &buf->total,
1591 sizeof(buf->total)))
1599 int radeon_cp_buffers(struct drm_device *dev, void *data, struct drm_file *file_priv)
1601 struct drm_device_dma *dma = dev->dma;
1603 struct drm_dma *d = data;
1605 LOCK_TEST_WITH_RETURN(dev, file_priv);
1607 /* Please don't send us buffers.
1609 if (d->send_count != 0) {
1610 DRM_ERROR("Process %d trying to send %d buffers via drmDMA\n",
1611 DRM_CURRENTPID, d->send_count);
1615 /* We'll send you buffers.
1617 if (d->request_count < 0 || d->request_count > dma->buf_count) {
1618 DRM_ERROR("Process %d trying to get %d buffers (of %d max)\n",
1619 DRM_CURRENTPID, d->request_count, dma->buf_count);
1623 d->granted_count = 0;
1625 if (d->request_count) {
1626 ret = radeon_cp_get_buffers(dev, file_priv, d);
1632 int radeon_driver_load(struct drm_device *dev, unsigned long flags)
1634 drm_radeon_private_t *dev_priv;
1637 dev_priv = drm_alloc(sizeof(drm_radeon_private_t), DRM_MEM_DRIVER);
1638 if (dev_priv == NULL)
1641 memset(dev_priv, 0, sizeof(drm_radeon_private_t));
1642 dev->dev_private = (void *)dev_priv;
1643 dev_priv->flags = flags;
1645 switch (flags & RADEON_FAMILY_MASK) {
1657 dev_priv->flags |= RADEON_HAS_HIERZ;
1660 /* all other chips have no hierarchical z buffer */
1664 if (drm_device_is_agp(dev))
1665 dev_priv->flags |= RADEON_IS_AGP;
1666 else if (drm_device_is_pcie(dev))
1667 dev_priv->flags |= RADEON_IS_PCIE;
1669 dev_priv->flags |= RADEON_IS_PCI;
1671 DRM_DEBUG("%s card detected\n",
1672 ((dev_priv->flags & RADEON_IS_AGP) ? "AGP" : (((dev_priv->flags & RADEON_IS_PCIE) ? "PCIE" : "PCI"))));
1676 /* Create mappings for registers and framebuffer so userland doesn't necessarily
1677 * have to find them.
1679 int radeon_driver_firstopen(struct drm_device *dev)
1682 drm_local_map_t *map;
1683 drm_radeon_private_t *dev_priv = dev->dev_private;
1685 dev_priv->gart_info.table_size = RADEON_PCIGART_TABLE_SIZE;
1687 ret = drm_addmap(dev, drm_get_resource_start(dev, 2),
1688 drm_get_resource_len(dev, 2), _DRM_REGISTERS,
1689 _DRM_READ_ONLY, &dev_priv->mmio);
1693 dev_priv->fb_aper_offset = drm_get_resource_start(dev, 0);
1694 ret = drm_addmap(dev, dev_priv->fb_aper_offset,
1695 drm_get_resource_len(dev, 0), _DRM_FRAME_BUFFER,
1696 _DRM_WRITE_COMBINING, &map);
1703 int radeon_driver_unload(struct drm_device *dev)
1705 drm_radeon_private_t *dev_priv = dev->dev_private;
1708 drm_free(dev_priv, sizeof(*dev_priv), DRM_MEM_DRIVER);
1710 dev->dev_private = NULL;