err.no Git - linux-2.6/blob - drivers/char/drm/mga_dma.c

   1 /* mga_dma.c -- DMA support for mga g200/g400 -*- linux-c -*-
   2  * Created: Mon Dec 13 01:50:01 1999 by jhartmann@precisioninsight.com
   3  *
   4  * Copyright 1999 Precision Insight, Inc., Cedar Park, Texas.
   5  * Copyright 2000 VA Linux Systems, Inc., Sunnyvale, California.
   6  * All Rights Reserved.
   7  *
   8  * Permission is hereby granted, free of charge, to any person obtaining a
   9  * copy of this software and associated documentation files (the "Software"),
  10  * to deal in the Software without restriction, including without limitation
  11  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
  12  * and/or sell copies of the Software, and to permit persons to whom the
  13  * Software is furnished to do so, subject to the following conditions:
  14  *
  15  * The above copyright notice and this permission notice (including the next
  16  * paragraph) shall be included in all copies or substantial portions of the
  17  * Software.
  18  *
  19  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  20  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  21  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  22  * PRECISION INSIGHT AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR
  23  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  24  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
  25  * DEALINGS IN THE SOFTWARE.
  26  */
  27
  28 /**
  29  * \file mga_dma.c
  30  * DMA support for MGA G200 / G400.
  31  *
  32  * \author Rickard E. (Rik) Faith <faith@valinux.com>
  33  * \author Jeff Hartmann <jhartmann@valinux.com>
  34  * \author Keith Whitwell <keith@tungstengraphics.com>
  35  * \author Gareth Hughes <gareth@valinux.com>
  36  */
  37
  38 #include "drmP.h"
  39 #include "drm.h"
  40 #include "drm_sarea.h"
  41 #include "mga_drm.h"
  42 #include "mga_drv.h"
  43
  44 #define MGA_DEFAULT_USEC_TIMEOUT        10000
  45 #define MGA_FREELIST_DEBUG              0
  46
  47 static int mga_do_cleanup_dma(drm_device_t * dev);
  48
  49 /* ================================================================
  50  * Engine control
  51  */
  52
  53 int mga_do_wait_for_idle(drm_mga_private_t * dev_priv)
  54 {
  55         u32 status = 0;
  56         int i;
  57         DRM_DEBUG("\n");
  58
  59         for (i = 0; i < dev_priv->usec_timeout; i++) {
  60                 status = MGA_READ(MGA_STATUS) & MGA_ENGINE_IDLE_MASK;
  61                 if (status == MGA_ENDPRDMASTS) {
  62                         MGA_WRITE8(MGA_CRTC_INDEX, 0);
  63                         return 0;
  64                 }
  65                 DRM_UDELAY(1);
  66         }
  67
  68 #if MGA_DMA_DEBUG
  69         DRM_ERROR("failed!\n");
  70         DRM_INFO("   status=0x%08x\n", status);
  71 #endif
  72         return DRM_ERR(EBUSY);
  73 }
  74
  75 static int mga_do_dma_reset(drm_mga_private_t * dev_priv)
  76 {
  77         drm_mga_sarea_t *sarea_priv = dev_priv->sarea_priv;
  78         drm_mga_primary_buffer_t *primary = &dev_priv->prim;
  79
  80         DRM_DEBUG("\n");
  81
  82         /* The primary DMA stream should look like new right about now.
  83          */
  84         primary->tail = 0;
  85         primary->space = primary->size;
  86         primary->last_flush = 0;
  87
  88         sarea_priv->last_wrap = 0;
  89
  90         /* FIXME: Reset counters, buffer ages etc...
  91          */
  92
  93         /* FIXME: What else do we need to reinitialize?  WARP stuff?
  94          */
  95
  96         return 0;
  97 }
  98
  99 /* ================================================================
 100  * Primary DMA stream
 101  */
 102
 103 void mga_do_dma_flush(drm_mga_private_t * dev_priv)
 104 {
 105         drm_mga_primary_buffer_t *primary = &dev_priv->prim;
 106         u32 head, tail;
 107         u32 status = 0;
 108         int i;
 109         DMA_LOCALS;
 110         DRM_DEBUG("\n");
 111
 112         /* We need to wait so that we can do an safe flush */
 113         for (i = 0; i < dev_priv->usec_timeout; i++) {
 114                 status = MGA_READ(MGA_STATUS) & MGA_ENGINE_IDLE_MASK;
 115                 if (status == MGA_ENDPRDMASTS)
 116                         break;
 117                 DRM_UDELAY(1);
 118         }
 119
 120         if (primary->tail == primary->last_flush) {
 121                 DRM_DEBUG("   bailing out...\n");
 122                 return;
 123         }
 124
 125         tail = primary->tail + dev_priv->primary->offset;
 126
 127         /* We need to pad the stream between flushes, as the card
 128          * actually (partially?) reads the first of these commands.
 129          * See page 4-16 in the G400 manual, middle of the page or so.
 130          */
 131         BEGIN_DMA(1);
 132
 133         DMA_BLOCK(MGA_DMAPAD, 0x00000000,
 134                   MGA_DMAPAD, 0x00000000,
 135                   MGA_DMAPAD, 0x00000000, MGA_DMAPAD, 0x00000000);
 136
 137         ADVANCE_DMA();
 138
 139         primary->last_flush = primary->tail;
 140
 141         head = MGA_READ(MGA_PRIMADDRESS);
 142
 143         if (head <= tail) {
 144                 primary->space = primary->size - primary->tail;
 145         } else {
 146                 primary->space = head - tail;
 147         }
 148
 149         DRM_DEBUG("   head = 0x%06lx\n", head - dev_priv->primary->offset);
 150         DRM_DEBUG("   tail = 0x%06lx\n", tail - dev_priv->primary->offset);
 151         DRM_DEBUG("  space = 0x%06x\n", primary->space);
 152
 153         mga_flush_write_combine();
 154         MGA_WRITE(MGA_PRIMEND, tail | dev_priv->dma_access);
 155
 156         DRM_DEBUG("done.\n");
 157 }
 158
 159 void mga_do_dma_wrap_start(drm_mga_private_t * dev_priv)
 160 {
 161         drm_mga_primary_buffer_t *primary = &dev_priv->prim;
 162         u32 head, tail;
 163         DMA_LOCALS;
 164         DRM_DEBUG("\n");
 165
 166         BEGIN_DMA_WRAP();
 167
 168         DMA_BLOCK(MGA_DMAPAD, 0x00000000,
 169                   MGA_DMAPAD, 0x00000000,
 170                   MGA_DMAPAD, 0x00000000, MGA_DMAPAD, 0x00000000);
 171
 172         ADVANCE_DMA();
 173
 174         tail = primary->tail + dev_priv->primary->offset;
 175
 176         primary->tail = 0;
 177         primary->last_flush = 0;
 178         primary->last_wrap++;
 179
 180         head = MGA_READ(MGA_PRIMADDRESS);
 181
 182         if (head == dev_priv->primary->offset) {
 183                 primary->space = primary->size;
 184         } else {
 185                 primary->space = head - dev_priv->primary->offset;
 186         }
 187
 188         DRM_DEBUG("   head = 0x%06lx\n", head - dev_priv->primary->offset);
 189         DRM_DEBUG("   tail = 0x%06x\n", primary->tail);
 190         DRM_DEBUG("   wrap = %d\n", primary->last_wrap);
 191         DRM_DEBUG("  space = 0x%06x\n", primary->space);
 192
 193         mga_flush_write_combine();
 194         MGA_WRITE(MGA_PRIMEND, tail | dev_priv->dma_access);
 195
 196         set_bit(0, &primary->wrapped);
 197         DRM_DEBUG("done.\n");
 198 }
 199
 200 void mga_do_dma_wrap_end(drm_mga_private_t * dev_priv)
 201 {
 202         drm_mga_primary_buffer_t *primary = &dev_priv->prim;
 203         drm_mga_sarea_t *sarea_priv = dev_priv->sarea_priv;
 204         u32 head = dev_priv->primary->offset;
 205         DRM_DEBUG("\n");
 206
 207         sarea_priv->last_wrap++;
 208         DRM_DEBUG("   wrap = %d\n", sarea_priv->last_wrap);
 209
 210         mga_flush_write_combine();
 211         MGA_WRITE(MGA_PRIMADDRESS, head | MGA_DMA_GENERAL);
 212
 213         clear_bit(0, &primary->wrapped);
 214         DRM_DEBUG("done.\n");
 215 }
 216
 217 /* ================================================================
 218  * Freelist management
 219  */
 220
 221 #define MGA_BUFFER_USED         ~0
 222 #define MGA_BUFFER_FREE         0
 223
 224 #if MGA_FREELIST_DEBUG
 225 static void mga_freelist_print(drm_device_t * dev)
 226 {
 227         drm_mga_private_t *dev_priv = dev->dev_private;
 228         drm_mga_freelist_t *entry;
 229
 230         DRM_INFO("\n");
 231         DRM_INFO("current dispatch: last=0x%x done=0x%x\n",
 232                  dev_priv->sarea_priv->last_dispatch,
 233                  (unsigned int)(MGA_READ(MGA_PRIMADDRESS) -
 234                                 dev_priv->primary->offset));
 235         DRM_INFO("current freelist:\n");
 236
 237         for (entry = dev_priv->head->next; entry; entry = entry->next) {
 238                 DRM_INFO("   %p   idx=%2d  age=0x%x 0x%06lx\n",
 239                          entry, entry->buf->idx, entry->age.head,
 240                          entry->age.head - dev_priv->primary->offset);
 241         }
 242         DRM_INFO("\n");
 243 }
 244 #endif
 245
 246 static int mga_freelist_init(drm_device_t * dev, drm_mga_private_t * dev_priv)
 247 {
 248         drm_device_dma_t *dma = dev->dma;
 249         drm_buf_t *buf;
 250         drm_mga_buf_priv_t *buf_priv;
 251         drm_mga_freelist_t *entry;
 252         int i;
 253         DRM_DEBUG("count=%d\n", dma->buf_count);
 254
 255         dev_priv->head = drm_alloc(sizeof(drm_mga_freelist_t), DRM_MEM_DRIVER);
 256         if (dev_priv->head == NULL)
 257                 return DRM_ERR(ENOMEM);
 258
 259         memset(dev_priv->head, 0, sizeof(drm_mga_freelist_t));
 260         SET_AGE(&dev_priv->head->age, MGA_BUFFER_USED, 0);
 261
 262         for (i = 0; i < dma->buf_count; i++) {
 263                 buf = dma->buflist[i];
 264                 buf_priv = buf->dev_private;
 265
 266                 entry = drm_alloc(sizeof(drm_mga_freelist_t), DRM_MEM_DRIVER);
 267                 if (entry == NULL)
 268                         return DRM_ERR(ENOMEM);
 269
 270                 memset(entry, 0, sizeof(drm_mga_freelist_t));
 271
 272                 entry->next = dev_priv->head->next;
 273                 entry->prev = dev_priv->head;
 274                 SET_AGE(&entry->age, MGA_BUFFER_FREE, 0);
 275                 entry->buf = buf;
 276
 277                 if (dev_priv->head->next != NULL)
 278                         dev_priv->head->next->prev = entry;
 279                 if (entry->next == NULL)
 280                         dev_priv->tail = entry;
 281
 282                 buf_priv->list_entry = entry;
 283                 buf_priv->discard = 0;
 284                 buf_priv->dispatched = 0;
 285
 286                 dev_priv->head->next = entry;
 287         }
 288
 289         return 0;
 290 }
 291
 292 static void mga_freelist_cleanup(drm_device_t * dev)
 293 {
 294         drm_mga_private_t *dev_priv = dev->dev_private;
 295         drm_mga_freelist_t *entry;
 296         drm_mga_freelist_t *next;
 297         DRM_DEBUG("\n");
 298
 299         entry = dev_priv->head;
 300         while (entry) {
 301                 next = entry->next;
 302                 drm_free(entry, sizeof(drm_mga_freelist_t), DRM_MEM_DRIVER);
 303                 entry = next;
 304         }
 305
 306         dev_priv->head = dev_priv->tail = NULL;
 307 }
 308
 309 #if 0
 310 /* FIXME: Still needed?
 311  */
 312 static void mga_freelist_reset(drm_device_t * dev)
 313 {
 314         drm_device_dma_t *dma = dev->dma;
 315         drm_buf_t *buf;
 316         drm_mga_buf_priv_t *buf_priv;
 317         int i;
 318
 319         for (i = 0; i < dma->buf_count; i++) {
 320                 buf = dma->buflist[i];
 321                 buf_priv = buf->dev_private;
 322                 SET_AGE(&buf_priv->list_entry->age, MGA_BUFFER_FREE, 0);
 323         }
 324 }
 325 #endif
 326
 327 static drm_buf_t *mga_freelist_get(drm_device_t * dev)
 328 {
 329         drm_mga_private_t *dev_priv = dev->dev_private;
 330         drm_mga_freelist_t *next;
 331         drm_mga_freelist_t *prev;
 332         drm_mga_freelist_t *tail = dev_priv->tail;
 333         u32 head, wrap;
 334         DRM_DEBUG("\n");
 335
 336         head = MGA_READ(MGA_PRIMADDRESS);
 337         wrap = dev_priv->sarea_priv->last_wrap;
 338
 339         DRM_DEBUG("   tail=0x%06lx %d\n",
 340                   tail->age.head ?
 341                   tail->age.head - dev_priv->primary->offset : 0,
 342                   tail->age.wrap);
 343         DRM_DEBUG("   head=0x%06lx %d\n",
 344                   head - dev_priv->primary->offset, wrap);
 345
 346         if (TEST_AGE(&tail->age, head, wrap)) {
 347                 prev = dev_priv->tail->prev;
 348                 next = dev_priv->tail;
 349                 prev->next = NULL;
 350                 next->prev = next->next = NULL;
 351                 dev_priv->tail = prev;
 352                 SET_AGE(&next->age, MGA_BUFFER_USED, 0);
 353                 return next->buf;
 354         }
 355
 356         DRM_DEBUG("returning NULL!\n");
 357         return NULL;
 358 }
 359
 360 int mga_freelist_put(drm_device_t * dev, drm_buf_t * buf)
 361 {
 362         drm_mga_private_t *dev_priv = dev->dev_private;
 363         drm_mga_buf_priv_t *buf_priv = buf->dev_private;
 364         drm_mga_freelist_t *head, *entry, *prev;
 365
 366         DRM_DEBUG("age=0x%06lx wrap=%d\n",
 367                   buf_priv->list_entry->age.head -
 368                   dev_priv->primary->offset, buf_priv->list_entry->age.wrap);
 369
 370         entry = buf_priv->list_entry;
 371         head = dev_priv->head;
 372
 373         if (buf_priv->list_entry->age.head == MGA_BUFFER_USED) {
 374                 SET_AGE(&entry->age, MGA_BUFFER_FREE, 0);
 375                 prev = dev_priv->tail;
 376                 prev->next = entry;
 377                 entry->prev = prev;
 378                 entry->next = NULL;
 379         } else {
 380                 prev = head->next;
 381                 head->next = entry;
 382                 prev->prev = entry;
 383                 entry->prev = head;
 384                 entry->next = prev;
 385         }
 386
 387         return 0;
 388 }
 389
 390 /* ================================================================
 391  * DMA initialization, cleanup
 392  */
 393
 394 int mga_driver_load(drm_device_t * dev, unsigned long flags)
 395 {
 396         drm_mga_private_t *dev_priv;
 397
 398         dev_priv = drm_alloc(sizeof(drm_mga_private_t), DRM_MEM_DRIVER);
 399         if (!dev_priv)
 400                 return DRM_ERR(ENOMEM);
 401
 402         dev->dev_private = (void *)dev_priv;
 403         memset(dev_priv, 0, sizeof(drm_mga_private_t));
 404
 405         dev_priv->usec_timeout = MGA_DEFAULT_USEC_TIMEOUT;
 406         dev_priv->chipset = flags;
 407
 408         dev_priv->mmio_base = drm_get_resource_start(dev, 1);
 409         dev_priv->mmio_size = drm_get_resource_len(dev, 1);
 410
 411         dev->counters += 3;
 412         dev->types[6] = _DRM_STAT_IRQ;
 413         dev->types[7] = _DRM_STAT_PRIMARY;
 414         dev->types[8] = _DRM_STAT_SECONDARY;
 415
 416         return 0;
 417 }
 418
 419 #if __OS_HAS_AGP
 420 /**
 421  * Bootstrap the driver for AGP DMA.
 422  *
 423  * \todo
 424  * Investigate whether there is any benifit to storing the WARP microcode in
 425  * AGP memory.  If not, the microcode may as well always be put in PCI
 426  * memory.
 427  *
 428  * \todo
 429  * This routine needs to set dma_bs->agp_mode to the mode actually configured
 430  * in the hardware.  Looking just at the Linux AGP driver code, I don't see
 431  * an easy way to determine this.
 432  *
 433  * \sa mga_do_dma_bootstrap, mga_do_pci_dma_bootstrap
 434  */
 435 static int mga_do_agp_dma_bootstrap(drm_device_t * dev,
 436                                     drm_mga_dma_bootstrap_t * dma_bs)
 437 {
 438         drm_mga_private_t *const dev_priv =
 439             (drm_mga_private_t *) dev->dev_private;
 440         unsigned int warp_size = mga_warp_microcode_size(dev_priv);
 441         int err;
 442         unsigned offset;
 443         const unsigned secondary_size = dma_bs->secondary_bin_count
 444             * dma_bs->secondary_bin_size;
 445         const unsigned agp_size = (dma_bs->agp_size << 20);
 446         drm_buf_desc_t req;
 447         drm_agp_mode_t mode;
 448         drm_agp_info_t info;
 449
 450         /* Acquire AGP. */
 451         err = drm_agp_acquire(dev);
 452         if (err) {
 453                 DRM_ERROR("Unable to acquire AGP\n");
 454                 return err;
 455         }
 456
 457         err = drm_agp_info(dev, &info);
 458         if (err) {
 459                 DRM_ERROR("Unable to get AGP info\n");
 460                 return err;
 461         }
 462
 463         mode.mode = (info.mode & ~0x07) | dma_bs->agp_mode;
 464         err = drm_agp_enable(dev, mode);
 465         if (err) {
 466                 DRM_ERROR("Unable to enable AGP (mode = 0x%lx)\n", mode.mode);
 467                 return err;
 468         }
 469
 470         /* In addition to the usual AGP mode configuration, the G200 AGP cards
 471          * need to have the AGP mode "manually" set.
 472          */
 473
 474         if (dev_priv->chipset == MGA_CARD_TYPE_G200) {
 475                 if (mode.mode & 0x02) {
 476                         MGA_WRITE(MGA_AGP_PLL, MGA_AGP2XPLL_ENABLE);
 477                 } else {
 478                         MGA_WRITE(MGA_AGP_PLL, MGA_AGP2XPLL_DISABLE);
 479                 }
 480         }
 481
 482         /* Allocate and bind AGP memory. */
 483         dev_priv->agp_pages = agp_size / PAGE_SIZE;
 484         dev_priv->agp_mem = drm_alloc_agp(dev, dev_priv->agp_pages, 0);
 485         if (dev_priv->agp_mem == NULL) {
 486                 dev_priv->agp_pages = 0;
 487                 DRM_ERROR("Unable to allocate %uMB AGP memory\n",
 488                           dma_bs->agp_size);
 489                 return DRM_ERR(ENOMEM);
 490         }
 491
 492         err = drm_bind_agp(dev_priv->agp_mem, 0);
 493         if (err) {
 494                 DRM_ERROR("Unable to bind AGP memory\n");
 495                 return err;
 496         }
 497
 498         /* Make drm_addbufs happy by not trying to create a mapping for less
 499          * than a page.
 500          */
 501         if (warp_size < PAGE_SIZE)
 502                 warp_size = PAGE_SIZE;
 503
 504         offset = 0;
 505         err = drm_addmap(dev, offset, warp_size,
 506                          _DRM_AGP, _DRM_READ_ONLY, &dev_priv->warp);
 507         if (err) {
 508                 DRM_ERROR("Unable to map WARP microcode\n");
 509                 return err;
 510         }
 511
 512         offset += warp_size;
 513         err = drm_addmap(dev, offset, dma_bs->primary_size,
 514                          _DRM_AGP, _DRM_READ_ONLY, &dev_priv->primary);
 515         if (err) {
 516                 DRM_ERROR("Unable to map primary DMA region\n");
 517                 return err;
 518         }
 519
 520         offset += dma_bs->primary_size;
 521         err = drm_addmap(dev, offset, secondary_size,
 522                          _DRM_AGP, 0, &dev->agp_buffer_map);
 523         if (err) {
 524                 DRM_ERROR("Unable to map secondary DMA region\n");
 525                 return err;
 526         }
 527
 528         (void)memset(&req, 0, sizeof(req));
 529         req.count = dma_bs->secondary_bin_count;
 530         req.size = dma_bs->secondary_bin_size;
 531         req.flags = _DRM_AGP_BUFFER;
 532         req.agp_start = offset;
 533
 534         err = drm_addbufs_agp(dev, &req);
 535         if (err) {
 536                 DRM_ERROR("Unable to add secondary DMA buffers\n");
 537                 return err;
 538         }
 539
 540         offset += secondary_size;
 541         err = drm_addmap(dev, offset, agp_size - offset,
 542                          _DRM_AGP, 0, &dev_priv->agp_textures);
 543         if (err) {
 544                 DRM_ERROR("Unable to map AGP texture region\n");
 545                 return err;
 546         }
 547
 548         drm_core_ioremap(dev_priv->warp, dev);
 549         drm_core_ioremap(dev_priv->primary, dev);
 550         drm_core_ioremap(dev->agp_buffer_map, dev);
 551
 552         if (!dev_priv->warp->handle ||
 553             !dev_priv->primary->handle || !dev->agp_buffer_map->handle) {
 554                 DRM_ERROR("failed to ioremap agp regions! (%p, %p, %p)\n",
 555                           dev_priv->warp->handle, dev_priv->primary->handle,
 556                           dev->agp_buffer_map->handle);
 557                 return DRM_ERR(ENOMEM);
 558         }
 559
 560         dev_priv->dma_access = MGA_PAGPXFER;
 561         dev_priv->wagp_enable = MGA_WAGP_ENABLE;
 562
 563         DRM_INFO("Initialized card for AGP DMA.\n");
 564         return 0;
 565 }
 566 #else
 567 static int mga_do_agp_dma_bootstrap(drm_device_t * dev,
 568                                     drm_mga_dma_bootstrap_t * dma_bs)
 569 {
 570         return -EINVAL;
 571 }
 572 #endif
 573
 574 /**
 575  * Bootstrap the driver for PCI DMA.
 576  *
 577  * \todo
 578  * The algorithm for decreasing the size of the primary DMA buffer could be
 579  * better.  The size should be rounded up to the nearest page size, then
 580  * decrease the request size by a single page each pass through the loop.
 581  *
 582  * \todo
 583  * Determine whether the maximum address passed to drm_pci_alloc is correct.
 584  * The same goes for drm_addbufs_pci.
 585  *
 586  * \sa mga_do_dma_bootstrap, mga_do_agp_dma_bootstrap
 587  */
 588 static int mga_do_pci_dma_bootstrap(drm_device_t * dev,
 589                                     drm_mga_dma_bootstrap_t * dma_bs)
 590 {
 591         drm_mga_private_t *const dev_priv =
 592             (drm_mga_private_t *) dev->dev_private;
 593         unsigned int warp_size = mga_warp_microcode_size(dev_priv);
 594         unsigned int primary_size;
 595         unsigned int bin_count;
 596         int err;
 597         drm_buf_desc_t req;
 598
 599         if (dev->dma == NULL) {
 600                 DRM_ERROR("dev->dma is NULL\n");
 601                 return DRM_ERR(EFAULT);
 602         }
 603
 604         /* Make drm_addbufs happy by not trying to create a mapping for less
 605          * than a page.
 606          */
 607         if (warp_size < PAGE_SIZE)
 608                 warp_size = PAGE_SIZE;
 609
 610         /* The proper alignment is 0x100 for this mapping */
 611         err = drm_addmap(dev, 0, warp_size, _DRM_CONSISTENT,
 612                          _DRM_READ_ONLY, &dev_priv->warp);
 613         if (err != 0) {
 614                 DRM_ERROR("Unable to create mapping for WARP microcode\n");
 615                 return err;
 616         }
 617
 618         /* Other than the bottom two bits being used to encode other
 619          * information, there don't appear to be any restrictions on the
 620          * alignment of the primary or secondary DMA buffers.
 621          */
 622
 623         for (primary_size = dma_bs->primary_size; primary_size != 0;
 624              primary_size >>= 1) {
 625                 /* The proper alignment for this mapping is 0x04 */
 626                 err = drm_addmap(dev, 0, primary_size, _DRM_CONSISTENT,
 627                                  _DRM_READ_ONLY, &dev_priv->primary);
 628                 if (!err)
 629                         break;
 630         }
 631
 632         if (err != 0) {
 633                 DRM_ERROR("Unable to allocate primary DMA region\n");
 634                 return DRM_ERR(ENOMEM);
 635         }
 636
 637         if (dev_priv->primary->size != dma_bs->primary_size) {
 638                 DRM_INFO("Primary DMA buffer size reduced from %u to %u.\n",
 639                          dma_bs->primary_size,
 640                          (unsigned)dev_priv->primary->size);
 641                 dma_bs->primary_size = dev_priv->primary->size;
 642         }
 643
 644         for (bin_count = dma_bs->secondary_bin_count; bin_count > 0;
 645              bin_count--) {
 646                 (void)memset(&req, 0, sizeof(req));
 647                 req.count = bin_count;
 648                 req.size = dma_bs->secondary_bin_size;
 649
 650                 err = drm_addbufs_pci(dev, &req);
 651                 if (!err) {
 652                         break;
 653                 }
 654         }
 655
 656         if (bin_count == 0) {
 657                 DRM_ERROR("Unable to add secondary DMA buffers\n");
 658                 return err;
 659         }
 660
 661         if (bin_count != dma_bs->secondary_bin_count) {
 662                 DRM_INFO("Secondary PCI DMA buffer bin count reduced from %u "
 663                          "to %u.\n", dma_bs->secondary_bin_count, bin_count);
 664
 665                 dma_bs->secondary_bin_count = bin_count;
 666         }
 667
 668         dev_priv->dma_access = 0;
 669         dev_priv->wagp_enable = 0;
 670
 671         dma_bs->agp_mode = 0;
 672
 673         DRM_INFO("Initialized card for PCI DMA.\n");
 674         return 0;
 675 }
 676
 677 static int mga_do_dma_bootstrap(drm_device_t * dev,
 678                                 drm_mga_dma_bootstrap_t * dma_bs)
 679 {
 680         const int is_agp = (dma_bs->agp_mode != 0) && drm_device_is_agp(dev);
 681         int err;
 682         drm_mga_private_t *const dev_priv =
 683             (drm_mga_private_t *) dev->dev_private;
 684
 685         dev_priv->used_new_dma_init = 1;
 686
 687         /* The first steps are the same for both PCI and AGP based DMA.  Map
 688          * the cards MMIO registers and map a status page.
 689          */
 690         err = drm_addmap(dev, dev_priv->mmio_base, dev_priv->mmio_size,
 691                          _DRM_REGISTERS, _DRM_READ_ONLY, &dev_priv->mmio);
 692         if (err) {
 693                 DRM_ERROR("Unable to map MMIO region\n");
 694                 return err;
 695         }
 696
 697         err = drm_addmap(dev, 0, SAREA_MAX, _DRM_SHM,
 698                          _DRM_READ_ONLY | _DRM_LOCKED | _DRM_KERNEL,
 699                          &dev_priv->status);
 700         if (err) {
 701                 DRM_ERROR("Unable to map status region\n");
 702                 return err;
 703         }
 704
 705         /* The DMA initialization procedure is slightly different for PCI and
 706          * AGP cards.  AGP cards just allocate a large block of AGP memory and
 707          * carve off portions of it for internal uses.  The remaining memory
 708          * is returned to user-mode to be used for AGP textures.
 709          */
 710         if (is_agp) {
 711                 err = mga_do_agp_dma_bootstrap(dev, dma_bs);
 712         }
 713
 714         /* If we attempted to initialize the card for AGP DMA but failed,
 715          * clean-up any mess that may have been created.
 716          */
 717
 718         if (err) {
 719                 mga_do_cleanup_dma(dev);
 720         }
 721
 722         /* Not only do we want to try and initialized PCI cards for PCI DMA,
 723          * but we also try to initialized AGP cards that could not be
 724          * initialized for AGP DMA.  This covers the case where we have an AGP
 725          * card in a system with an unsupported AGP chipset.  In that case the
 726          * card will be detected as AGP, but we won't be able to allocate any
 727          * AGP memory, etc.
 728          */
 729
 730         if (!is_agp || err) {
 731                 err = mga_do_pci_dma_bootstrap(dev, dma_bs);
 732         }
 733
 734         return err;
 735 }
 736
 737 int mga_dma_bootstrap(DRM_IOCTL_ARGS)
 738 {
 739         DRM_DEVICE;
 740         drm_mga_dma_bootstrap_t bootstrap;
 741         int err;
 742
 743         DRM_COPY_FROM_USER_IOCTL(bootstrap,
 744                                  (drm_mga_dma_bootstrap_t __user *) data,
 745                                  sizeof(bootstrap));
 746
 747         err = mga_do_dma_bootstrap(dev, &bootstrap);
 748         if (!err) {
 749                 static const int modes[] = { 0, 1, 2, 2, 4, 4, 4, 4 };
 750                 const drm_mga_private_t *const dev_priv =
 751                     (drm_mga_private_t *) dev->dev_private;
 752
 753                 if (dev_priv->agp_textures != NULL) {
 754                         bootstrap.texture_handle =
 755                             dev_priv->agp_textures->offset;
 756                         bootstrap.texture_size = dev_priv->agp_textures->size;
 757                 } else {
 758                         bootstrap.texture_handle = 0;
 759                         bootstrap.texture_size = 0;
 760                 }
 761
 762                 bootstrap.agp_mode = modes[bootstrap.agp_mode & 0x07];
 763                 if (DRM_COPY_TO_USER((void __user *)data, &bootstrap,
 764                                      sizeof(bootstrap))) {
 765                         err = DRM_ERR(EFAULT);
 766                 }
 767         } else {
 768                 mga_do_cleanup_dma(dev);
 769         }
 770
 771         return err;
 772 }
 773
 774 static int mga_do_init_dma(drm_device_t * dev, drm_mga_init_t * init)
 775 {
 776         drm_mga_private_t *dev_priv;
 777         int ret;
 778         DRM_DEBUG("\n");
 779
 780         dev_priv = dev->dev_private;
 781
 782         if (init->sgram) {
 783                 dev_priv->clear_cmd = MGA_DWGCTL_CLEAR | MGA_ATYPE_BLK;
 784         } else {
 785                 dev_priv->clear_cmd = MGA_DWGCTL_CLEAR | MGA_ATYPE_RSTR;
 786         }
 787         dev_priv->maccess = init->maccess;
 788
 789         dev_priv->fb_cpp = init->fb_cpp;
 790         dev_priv->front_offset = init->front_offset;
 791         dev_priv->front_pitch = init->front_pitch;
 792         dev_priv->back_offset = init->back_offset;
 793         dev_priv->back_pitch = init->back_pitch;
 794
 795         dev_priv->depth_cpp = init->depth_cpp;
 796         dev_priv->depth_offset = init->depth_offset;
 797         dev_priv->depth_pitch = init->depth_pitch;
 798
 799         /* FIXME: Need to support AGP textures...
 800          */
 801         dev_priv->texture_offset = init->texture_offset[0];
 802         dev_priv->texture_size = init->texture_size[0];
 803
 804         DRM_GETSAREA();
 805
 806         if (!dev_priv->sarea) {
 807                 DRM_ERROR("failed to find sarea!\n");
 808                 return DRM_ERR(EINVAL);
 809         }
 810
 811         if (!dev_priv->used_new_dma_init) {
 812
 813                 dev_priv->dma_access = MGA_PAGPXFER;
 814                 dev_priv->wagp_enable = MGA_WAGP_ENABLE;
 815
 816                 dev_priv->status = drm_core_findmap(dev, init->status_offset);
 817                 if (!dev_priv->status) {
 818                         DRM_ERROR("failed to find status page!\n");
 819                         return DRM_ERR(EINVAL);
 820                 }
 821                 dev_priv->mmio = drm_core_findmap(dev, init->mmio_offset);
 822                 if (!dev_priv->mmio) {
 823                         DRM_ERROR("failed to find mmio region!\n");
 824                         return DRM_ERR(EINVAL);
 825                 }
 826                 dev_priv->warp = drm_core_findmap(dev, init->warp_offset);
 827                 if (!dev_priv->warp) {
 828                         DRM_ERROR("failed to find warp microcode region!\n");
 829                         return DRM_ERR(EINVAL);
 830                 }
 831                 dev_priv->primary = drm_core_findmap(dev, init->primary_offset);
 832                 if (!dev_priv->primary) {
 833                         DRM_ERROR("failed to find primary dma region!\n");
 834                         return DRM_ERR(EINVAL);
 835                 }
 836                 dev->agp_buffer_token = init->buffers_offset;
 837                 dev->agp_buffer_map =
 838                     drm_core_findmap(dev, init->buffers_offset);
 839                 if (!dev->agp_buffer_map) {
 840                         DRM_ERROR("failed to find dma buffer region!\n");
 841                         return DRM_ERR(EINVAL);
 842                 }
 843
 844                 drm_core_ioremap(dev_priv->warp, dev);
 845                 drm_core_ioremap(dev_priv->primary, dev);
 846                 drm_core_ioremap(dev->agp_buffer_map, dev);
 847         }
 848
 849         dev_priv->sarea_priv =
 850             (drm_mga_sarea_t *) ((u8 *) dev_priv->sarea->handle +
 851                                  init->sarea_priv_offset);
 852
 853         if (!dev_priv->warp->handle ||
 854             !dev_priv->primary->handle ||
 855             ((dev_priv->dma_access != 0) &&
 856              ((dev->agp_buffer_map == NULL) ||
 857               (dev->agp_buffer_map->handle == NULL)))) {
 858                 DRM_ERROR("failed to ioremap agp regions!\n");
 859                 return DRM_ERR(ENOMEM);
 860         }
 861
 862         ret = mga_warp_install_microcode(dev_priv);
 863         if (ret < 0) {
 864                 DRM_ERROR("failed to install WARP ucode!\n");
 865                 return ret;
 866         }
 867
 868         ret = mga_warp_init(dev_priv);
 869         if (ret < 0) {
 870                 DRM_ERROR("failed to init WARP engine!\n");
 871                 return ret;
 872         }
 873
 874         dev_priv->prim.status = (u32 *) dev_priv->status->handle;
 875
 876         mga_do_wait_for_idle(dev_priv);
 877
 878         /* Init the primary DMA registers.
 879          */
 880         MGA_WRITE(MGA_PRIMADDRESS, dev_priv->primary->offset | MGA_DMA_GENERAL);
 881 #if 0
 882         MGA_WRITE(MGA_PRIMPTR, virt_to_bus((void *)dev_priv->prim.status) | MGA_PRIMPTREN0 |    /* Soft trap, SECEND, SETUPEND */
 883                   MGA_PRIMPTREN1);      /* DWGSYNC */
 884 #endif
 885
 886         dev_priv->prim.start = (u8 *) dev_priv->primary->handle;
 887         dev_priv->prim.end = ((u8 *) dev_priv->primary->handle
 888                               + dev_priv->primary->size);
 889         dev_priv->prim.size = dev_priv->primary->size;
 890
 891         dev_priv->prim.tail = 0;
 892         dev_priv->prim.space = dev_priv->prim.size;
 893         dev_priv->prim.wrapped = 0;
 894
 895         dev_priv->prim.last_flush = 0;
 896         dev_priv->prim.last_wrap = 0;
 897
 898         dev_priv->prim.high_mark = 256 * DMA_BLOCK_SIZE;
 899
 900         dev_priv->prim.status[0] = dev_priv->primary->offset;
 901         dev_priv->prim.status[1] = 0;
 902
 903         dev_priv->sarea_priv->last_wrap = 0;
 904         dev_priv->sarea_priv->last_frame.head = 0;
 905         dev_priv->sarea_priv->last_frame.wrap = 0;
 906
 907         if (mga_freelist_init(dev, dev_priv) < 0) {
 908                 DRM_ERROR("could not initialize freelist\n");
 909                 return DRM_ERR(ENOMEM);
 910         }
 911
 912         return 0;
 913 }
 914
 915 static int mga_do_cleanup_dma(drm_device_t * dev)
 916 {
 917         int err = 0;
 918         DRM_DEBUG("\n");
 919
 920         /* Make sure interrupts are disabled here because the uninstall ioctl
 921          * may not have been called from userspace and after dev_private
 922          * is freed, it's too late.
 923          */
 924         if (dev->irq_enabled)
 925                 drm_irq_uninstall(dev);
 926
 927         if (dev->dev_private) {
 928                 drm_mga_private_t *dev_priv = dev->dev_private;
 929
 930                 if ((dev_priv->warp != NULL)
 931                     && (dev_priv->warp->type != _DRM_CONSISTENT))
 932                         drm_core_ioremapfree(dev_priv->warp, dev);
 933
 934                 if ((dev_priv->primary != NULL)
 935                     && (dev_priv->primary->type != _DRM_CONSISTENT))
 936                         drm_core_ioremapfree(dev_priv->primary, dev);
 937
 938                 if (dev->agp_buffer_map != NULL)
 939                         drm_core_ioremapfree(dev->agp_buffer_map, dev);
 940
 941                 if (dev_priv->used_new_dma_init) {
 942 #if __OS_HAS_AGP
 943                         if (dev_priv->agp_mem != NULL) {
 944                                 dev_priv->agp_textures = NULL;
 945                                 drm_unbind_agp(dev_priv->agp_mem);
 946
 947                                 drm_free_agp(dev_priv->agp_mem,
 948                                              dev_priv->agp_pages);
 949                                 dev_priv->agp_pages = 0;
 950                                 dev_priv->agp_mem = NULL;
 951                         }
 952
 953                         if ((dev->agp != NULL) && dev->agp->acquired) {
 954                                 err = drm_agp_release(dev);
 955                         }
 956 #endif
 957                         dev_priv->used_new_dma_init = 0;
 958                 }
 959
 960                 dev_priv->warp = NULL;
 961                 dev_priv->primary = NULL;
 962                 dev_priv->mmio = NULL;
 963                 dev_priv->status = NULL;
 964                 dev_priv->sarea = NULL;
 965                 dev_priv->sarea_priv = NULL;
 966                 dev->agp_buffer_map = NULL;
 967
 968                 memset(&dev_priv->prim, 0, sizeof(dev_priv->prim));
 969                 dev_priv->warp_pipe = 0;
 970                 memset(dev_priv->warp_pipe_phys, 0,
 971                        sizeof(dev_priv->warp_pipe_phys));
 972
 973                 if (dev_priv->head != NULL) {
 974                         mga_freelist_cleanup(dev);
 975                 }
 976         }
 977
 978         return err;
 979 }
 980
 981 int mga_dma_init(DRM_IOCTL_ARGS)
 982 {
 983         DRM_DEVICE;
 984         drm_mga_init_t init;
 985         int err;
 986
 987         LOCK_TEST_WITH_RETURN(dev, filp);
 988
 989         DRM_COPY_FROM_USER_IOCTL(init, (drm_mga_init_t __user *) data,
 990                                  sizeof(init));
 991
 992         switch (init.func) {
 993         case MGA_INIT_DMA:
 994                 err = mga_do_init_dma(dev, &init);
 995                 if (err) {
 996                         (void)mga_do_cleanup_dma(dev);
 997                 }
 998                 return err;
 999         case MGA_CLEANUP_DMA:
1000                 return mga_do_cleanup_dma(dev);
1001         }
1002
1003         return DRM_ERR(EINVAL);
1004 }
1005
1006 /* ================================================================
1007  * Primary DMA stream management
1008  */
1009
1010 int mga_dma_flush(DRM_IOCTL_ARGS)
1011 {
1012         DRM_DEVICE;
1013         drm_mga_private_t *dev_priv = (drm_mga_private_t *) dev->dev_private;
1014         drm_lock_t lock;
1015
1016         LOCK_TEST_WITH_RETURN(dev, filp);
1017
1018         DRM_COPY_FROM_USER_IOCTL(lock, (drm_lock_t __user *) data,
1019                                  sizeof(lock));
1020
1021         DRM_DEBUG("%s%s%s\n",
1022                   (lock.flags & _DRM_LOCK_FLUSH) ? "flush, " : "",
1023                   (lock.flags & _DRM_LOCK_FLUSH_ALL) ? "flush all, " : "",
1024                   (lock.flags & _DRM_LOCK_QUIESCENT) ? "idle, " : "");
1025
1026         WRAP_WAIT_WITH_RETURN(dev_priv);
1027
1028         if (lock.flags & (_DRM_LOCK_FLUSH | _DRM_LOCK_FLUSH_ALL)) {
1029                 mga_do_dma_flush(dev_priv);
1030         }
1031
1032         if (lock.flags & _DRM_LOCK_QUIESCENT) {
1033 #if MGA_DMA_DEBUG
1034                 int ret = mga_do_wait_for_idle(dev_priv);
1035                 if (ret < 0)
1036                         DRM_INFO("%s: -EBUSY\n", __FUNCTION__);
1037                 return ret;
1038 #else
1039                 return mga_do_wait_for_idle(dev_priv);
1040 #endif
1041         } else {
1042                 return 0;
1043         }
1044 }
1045
1046 int mga_dma_reset(DRM_IOCTL_ARGS)
1047 {
1048         DRM_DEVICE;
1049         drm_mga_private_t *dev_priv = (drm_mga_private_t *) dev->dev_private;
1050
1051         LOCK_TEST_WITH_RETURN(dev, filp);
1052
1053         return mga_do_dma_reset(dev_priv);
1054 }
1055
1056 /* ================================================================
1057  * DMA buffer management
1058  */
1059
1060 static int mga_dma_get_buffers(DRMFILE filp, drm_device_t * dev, drm_dma_t * d)
1061 {
1062         drm_buf_t *buf;
1063         int i;
1064
1065         for (i = d->granted_count; i < d->request_count; i++) {
1066                 buf = mga_freelist_get(dev);
1067                 if (!buf)
1068                         return DRM_ERR(EAGAIN);
1069
1070                 buf->filp = filp;
1071
1072                 if (DRM_COPY_TO_USER(&d->request_indices[i],
1073                                      &buf->idx, sizeof(buf->idx)))
1074                         return DRM_ERR(EFAULT);
1075                 if (DRM_COPY_TO_USER(&d->request_sizes[i],
1076                                      &buf->total, sizeof(buf->total)))
1077                         return DRM_ERR(EFAULT);
1078
1079                 d->granted_count++;
1080         }
1081         return 0;
1082 }
1083
1084 int mga_dma_buffers(DRM_IOCTL_ARGS)
1085 {
1086         DRM_DEVICE;
1087         drm_device_dma_t *dma = dev->dma;
1088         drm_mga_private_t *dev_priv = (drm_mga_private_t *) dev->dev_private;
1089         drm_dma_t __user *argp = (void __user *)data;
1090         drm_dma_t d;
1091         int ret = 0;
1092
1093         LOCK_TEST_WITH_RETURN(dev, filp);
1094
1095         DRM_COPY_FROM_USER_IOCTL(d, argp, sizeof(d));
1096
1097         /* Please don't send us buffers.
1098          */
1099         if (d.send_count != 0) {
1100                 DRM_ERROR("Process %d trying to send %d buffers via drmDMA\n",
1101                           DRM_CURRENTPID, d.send_count);
1102                 return DRM_ERR(EINVAL);
1103         }
1104
1105         /* We'll send you buffers.
1106          */
1107         if (d.request_count < 0 || d.request_count > dma->buf_count) {
1108                 DRM_ERROR("Process %d trying to get %d buffers (of %d max)\n",
1109                           DRM_CURRENTPID, d.request_count, dma->buf_count);
1110                 return DRM_ERR(EINVAL);
1111         }
1112
1113         WRAP_TEST_WITH_RETURN(dev_priv);
1114
1115         d.granted_count = 0;
1116
1117         if (d.request_count) {
1118                 ret = mga_dma_get_buffers(filp, dev, &d);
1119         }
1120
1121         DRM_COPY_TO_USER_IOCTL(argp, d, sizeof(d));
1122
1123         return ret;
1124 }
1125
1126 /**
1127  * Called just before the module is unloaded.
1128  */
1129 int mga_driver_unload(drm_device_t * dev)
1130 {
1131         drm_free(dev->dev_private, sizeof(drm_mga_private_t), DRM_MEM_DRIVER);
1132         dev->dev_private = NULL;
1133
1134         return 0;
1135 }
1136
1137 /**
1138  * Called when the last opener of the device is closed.
1139  */
1140 void mga_driver_lastclose(drm_device_t * dev)
1141 {
1142         mga_do_cleanup_dma(dev);
1143 }
1144
1145 int mga_driver_dma_quiescent(drm_device_t * dev)
1146 {
1147         drm_mga_private_t *dev_priv = dev->dev_private;
1148         return mga_do_wait_for_idle(dev_priv);
1149 }