err.no Git - linux-2.6/blob - drivers/char/drm/i915_drv.c

   1 /* i915_drv.c -- i830,i845,i855,i865,i915 driver -*- linux-c -*-
   2  */
   3 /*
   4  *
   5  * Copyright 2003 Tungsten Graphics, Inc., Cedar Park, Texas.
   6  * All Rights Reserved.
   7  *
   8  * Permission is hereby granted, free of charge, to any person obtaining a
   9  * copy of this software and associated documentation files (the
  10  * "Software"), to deal in the Software without restriction, including
  11  * without limitation the rights to use, copy, modify, merge, publish,
  12  * distribute, sub license, and/or sell copies of the Software, and to
  13  * permit persons to whom the Software is furnished to do so, subject to
  14  * the following conditions:
  15  *
  16  * The above copyright notice and this permission notice (including the
  17  * next paragraph) shall be included in all copies or substantial portions
  18  * of the Software.
  19  *
  20  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
  21  * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
  22  * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT.
  23  * IN NO EVENT SHALL TUNGSTEN GRAPHICS AND/OR ITS SUPPLIERS BE LIABLE FOR
  24  * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
  25  * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
  26  * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
  27  *
  28  */
  29
  30 #include "drmP.h"
  31 #include "drm.h"
  32 #include "i915_drm.h"
  33 #include "i915_drv.h"
  34
  35 #include "drm_pciids.h"
  36
  37 static struct pci_device_id pciidlist[] = {
  38         i915_PCI_IDS
  39 };
  40
  41 enum pipe {
  42     PIPE_A = 0,
  43     PIPE_B,
  44 };
  45
  46 static bool i915_pipe_enabled(struct drm_device *dev, enum pipe pipe)
  47 {
  48         struct drm_i915_private *dev_priv = dev->dev_private;
  49
  50         if (pipe == PIPE_A)
  51                 return (I915_READ(DPLL_A) & DPLL_VCO_ENABLE);
  52         else
  53                 return (I915_READ(DPLL_B) & DPLL_VCO_ENABLE);
  54 }
  55
  56 static void i915_save_palette(struct drm_device *dev, enum pipe pipe)
  57 {
  58         struct drm_i915_private *dev_priv = dev->dev_private;
  59         unsigned long reg = (pipe == PIPE_A ? PALETTE_A : PALETTE_B);
  60         u32 *array;
  61         int i;
  62
  63         if (!i915_pipe_enabled(dev, pipe))
  64                 return;
  65
  66         if (pipe == PIPE_A)
  67                 array = dev_priv->save_palette_a;
  68         else
  69                 array = dev_priv->save_palette_b;
  70
  71         for(i = 0; i < 256; i++)
  72                 array[i] = I915_READ(reg + (i << 2));
  73 }
  74
  75 static void i915_restore_palette(struct drm_device *dev, enum pipe pipe)
  76 {
  77         struct drm_i915_private *dev_priv = dev->dev_private;
  78         unsigned long reg = (pipe == PIPE_A ? PALETTE_A : PALETTE_B);
  79         u32 *array;
  80         int i;
  81
  82         if (!i915_pipe_enabled(dev, pipe))
  83                 return;
  84
  85         if (pipe == PIPE_A)
  86                 array = dev_priv->save_palette_a;
  87         else
  88                 array = dev_priv->save_palette_b;
  89
  90         for(i = 0; i < 256; i++)
  91                 I915_WRITE(reg + (i << 2), array[i]);
  92 }
  93
  94 static u8 i915_read_indexed(u16 index_port, u16 data_port, u8 reg)
  95 {
  96         outb(reg, index_port);
  97         return inb(data_port);
  98 }
  99
 100 static u8 i915_read_ar(u16 st01, u8 reg, u16 palette_enable)
 101 {
 102         inb(st01);
 103         outb(palette_enable | reg, VGA_AR_INDEX);
 104         return inb(VGA_AR_DATA_READ);
 105 }
 106
 107 static void i915_write_ar(u8 st01, u8 reg, u8 val, u16 palette_enable)
 108 {
 109         inb(st01);
 110         outb(palette_enable | reg, VGA_AR_INDEX);
 111         outb(val, VGA_AR_DATA_WRITE);
 112 }
 113
 114 static void i915_write_indexed(u16 index_port, u16 data_port, u8 reg, u8 val)
 115 {
 116         outb(reg, index_port);
 117         outb(val, data_port);
 118 }
 119
 120 static void i915_save_vga(struct drm_device *dev)
 121 {
 122         struct drm_i915_private *dev_priv = dev->dev_private;
 123         int i;
 124         u16 cr_index, cr_data, st01;
 125
 126         /* VGA color palette registers */
 127         dev_priv->saveDACMASK = inb(VGA_DACMASK);
 128         /* DACCRX automatically increments during read */
 129         outb(0, VGA_DACRX);
 130         /* Read 3 bytes of color data from each index */
 131         for (i = 0; i < 256 * 3; i++)
 132                 dev_priv->saveDACDATA[i] = inb(VGA_DACDATA);
 133
 134         /* MSR bits */
 135         dev_priv->saveMSR = inb(VGA_MSR_READ);
 136         if (dev_priv->saveMSR & VGA_MSR_CGA_MODE) {
 137                 cr_index = VGA_CR_INDEX_CGA;
 138                 cr_data = VGA_CR_DATA_CGA;
 139                 st01 = VGA_ST01_CGA;
 140         } else {
 141                 cr_index = VGA_CR_INDEX_MDA;
 142                 cr_data = VGA_CR_DATA_MDA;
 143                 st01 = VGA_ST01_MDA;
 144         }
 145
 146         /* CRT controller regs */
 147         i915_write_indexed(cr_index, cr_data, 0x11,
 148                            i915_read_indexed(cr_index, cr_data, 0x11) &
 149                            (~0x80));
 150         for (i = 0; i < 0x24; i++)
 151                 dev_priv->saveCR[i] =
 152                         i915_read_indexed(cr_index, cr_data, i);
 153         /* Make sure we don't turn off CR group 0 writes */
 154         dev_priv->saveCR[0x11] &= ~0x80;
 155
 156         /* Attribute controller registers */
 157         inb(st01);
 158         dev_priv->saveAR_INDEX = inb(VGA_AR_INDEX);
 159         for (i = 0; i < 20; i++)
 160                 dev_priv->saveAR[i] = i915_read_ar(st01, i, 0);
 161         inb(st01);
 162         outb(dev_priv->saveAR_INDEX, VGA_AR_INDEX);
 163
 164         /* Graphics controller registers */
 165         for (i = 0; i < 9; i++)
 166                 dev_priv->saveGR[i] =
 167                         i915_read_indexed(VGA_GR_INDEX, VGA_GR_DATA, i);
 168
 169         dev_priv->saveGR[0x10] =
 170                 i915_read_indexed(VGA_GR_INDEX, VGA_GR_DATA, 0x10);
 171         dev_priv->saveGR[0x11] =
 172                 i915_read_indexed(VGA_GR_INDEX, VGA_GR_DATA, 0x11);
 173         dev_priv->saveGR[0x18] =
 174                 i915_read_indexed(VGA_GR_INDEX, VGA_GR_DATA, 0x18);
 175
 176         /* Sequencer registers */
 177         for (i = 0; i < 8; i++)
 178                 dev_priv->saveSR[i] =
 179                         i915_read_indexed(VGA_SR_INDEX, VGA_SR_DATA, i);
 180 }
 181
 182 static void i915_restore_vga(struct drm_device *dev)
 183 {
 184         struct drm_i915_private *dev_priv = dev->dev_private;
 185         int i;
 186         u16 cr_index, cr_data, st01;
 187
 188         /* MSR bits */
 189         outb(dev_priv->saveMSR, VGA_MSR_WRITE);
 190         if (dev_priv->saveMSR & VGA_MSR_CGA_MODE) {
 191                 cr_index = VGA_CR_INDEX_CGA;
 192                 cr_data = VGA_CR_DATA_CGA;
 193                 st01 = VGA_ST01_CGA;
 194         } else {
 195                 cr_index = VGA_CR_INDEX_MDA;
 196                 cr_data = VGA_CR_DATA_MDA;
 197                 st01 = VGA_ST01_MDA;
 198         }
 199
 200         /* Sequencer registers, don't write SR07 */
 201         for (i = 0; i < 7; i++)
 202                 i915_write_indexed(VGA_SR_INDEX, VGA_SR_DATA, i,
 203                                    dev_priv->saveSR[i]);
 204
 205         /* CRT controller regs */
 206         /* Enable CR group 0 writes */
 207         i915_write_indexed(cr_index, cr_data, 0x11, dev_priv->saveCR[0x11]);
 208         for (i = 0; i < 0x24; i++)
 209                 i915_write_indexed(cr_index, cr_data, i, dev_priv->saveCR[i]);
 210
 211         /* Graphics controller regs */
 212         for (i = 0; i < 9; i++)
 213                 i915_write_indexed(VGA_GR_INDEX, VGA_GR_DATA, i,
 214                                    dev_priv->saveGR[i]);
 215
 216         i915_write_indexed(VGA_GR_INDEX, VGA_GR_DATA, 0x10,
 217                            dev_priv->saveGR[0x10]);
 218         i915_write_indexed(VGA_GR_INDEX, VGA_GR_DATA, 0x11,
 219                            dev_priv->saveGR[0x11]);
 220         i915_write_indexed(VGA_GR_INDEX, VGA_GR_DATA, 0x18,
 221                            dev_priv->saveGR[0x18]);
 222
 223         /* Attribute controller registers */
 224         for (i = 0; i < 20; i++)
 225                 i915_write_ar(st01, i, dev_priv->saveAR[i], 0);
 226         inb(st01); /* switch back to index mode */
 227         outb(dev_priv->saveAR_INDEX | 0x20, VGA_AR_INDEX);
 228
 229         /* VGA color palette registers */
 230         outb(dev_priv->saveDACMASK, VGA_DACMASK);
 231         /* DACCRX automatically increments during read */
 232         outb(0, VGA_DACWX);
 233         /* Read 3 bytes of color data from each index */
 234         for (i = 0; i < 256 * 3; i++)
 235                 outb(dev_priv->saveDACDATA[i], VGA_DACDATA);
 236
 237 }
 238
 239 static int i915_suspend(struct drm_device *dev)
 240 {
 241         struct drm_i915_private *dev_priv = dev->dev_private;
 242         int i;
 243
 244         if (!dev || !dev_priv) {
 245                 printk(KERN_ERR "dev: %p, dev_priv: %p\n", dev, dev_priv);
 246                 printk(KERN_ERR "DRM not initialized, aborting suspend.\n");
 247                 return -ENODEV;
 248         }
 249
 250         pci_save_state(dev->pdev);
 251         pci_read_config_byte(dev->pdev, LBB, &dev_priv->saveLBB);
 252
 253         /* Pipe & plane A info */
 254         dev_priv->savePIPEACONF = I915_READ(PIPEACONF);
 255         dev_priv->savePIPEASRC = I915_READ(PIPEASRC);
 256         dev_priv->saveFPA0 = I915_READ(FPA0);
 257         dev_priv->saveFPA1 = I915_READ(FPA1);
 258         dev_priv->saveDPLL_A = I915_READ(DPLL_A);
 259         if (IS_I965G(dev))
 260                 dev_priv->saveDPLL_A_MD = I915_READ(DPLL_A_MD);
 261         dev_priv->saveHTOTAL_A = I915_READ(HTOTAL_A);
 262         dev_priv->saveHBLANK_A = I915_READ(HBLANK_A);
 263         dev_priv->saveHSYNC_A = I915_READ(HSYNC_A);
 264         dev_priv->saveVTOTAL_A = I915_READ(VTOTAL_A);
 265         dev_priv->saveVBLANK_A = I915_READ(VBLANK_A);
 266         dev_priv->saveVSYNC_A = I915_READ(VSYNC_A);
 267         dev_priv->saveBCLRPAT_A = I915_READ(BCLRPAT_A);
 268
 269         dev_priv->saveDSPACNTR = I915_READ(DSPACNTR);
 270         dev_priv->saveDSPASTRIDE = I915_READ(DSPASTRIDE);
 271         dev_priv->saveDSPASIZE = I915_READ(DSPASIZE);
 272         dev_priv->saveDSPAPOS = I915_READ(DSPAPOS);
 273         dev_priv->saveDSPABASE = I915_READ(DSPABASE);
 274         if (IS_I965G(dev)) {
 275                 dev_priv->saveDSPASURF = I915_READ(DSPASURF);
 276                 dev_priv->saveDSPATILEOFF = I915_READ(DSPATILEOFF);
 277         }
 278         i915_save_palette(dev, PIPE_A);
 279
 280         /* Pipe & plane B info */
 281         dev_priv->savePIPEBCONF = I915_READ(PIPEBCONF);
 282         dev_priv->savePIPEBSRC = I915_READ(PIPEBSRC);
 283         dev_priv->saveFPB0 = I915_READ(FPB0);
 284         dev_priv->saveFPB1 = I915_READ(FPB1);
 285         dev_priv->saveDPLL_B = I915_READ(DPLL_B);
 286         if (IS_I965G(dev))
 287                 dev_priv->saveDPLL_B_MD = I915_READ(DPLL_B_MD);
 288         dev_priv->saveHTOTAL_B = I915_READ(HTOTAL_B);
 289         dev_priv->saveHBLANK_B = I915_READ(HBLANK_B);
 290         dev_priv->saveHSYNC_B = I915_READ(HSYNC_B);
 291         dev_priv->saveVTOTAL_B = I915_READ(VTOTAL_B);
 292         dev_priv->saveVBLANK_B = I915_READ(VBLANK_B);
 293         dev_priv->saveVSYNC_B = I915_READ(VSYNC_B);
 294         dev_priv->saveBCLRPAT_A = I915_READ(BCLRPAT_A);
 295
 296         dev_priv->saveDSPBCNTR = I915_READ(DSPBCNTR);
 297         dev_priv->saveDSPBSTRIDE = I915_READ(DSPBSTRIDE);
 298         dev_priv->saveDSPBSIZE = I915_READ(DSPBSIZE);
 299         dev_priv->saveDSPBPOS = I915_READ(DSPBPOS);
 300         dev_priv->saveDSPBBASE = I915_READ(DSPBBASE);
 301         if (IS_I965GM(dev) || IS_IGD_GM(dev)) {
 302                 dev_priv->saveDSPBSURF = I915_READ(DSPBSURF);
 303                 dev_priv->saveDSPBTILEOFF = I915_READ(DSPBTILEOFF);
 304         }
 305         i915_save_palette(dev, PIPE_B);
 306
 307         /* CRT state */
 308         dev_priv->saveADPA = I915_READ(ADPA);
 309
 310         /* LVDS state */
 311         dev_priv->savePP_CONTROL = I915_READ(PP_CONTROL);
 312         dev_priv->savePFIT_PGM_RATIOS = I915_READ(PFIT_PGM_RATIOS);
 313         dev_priv->saveBLC_PWM_CTL = I915_READ(BLC_PWM_CTL);
 314         if (IS_I965G(dev))
 315                 dev_priv->saveBLC_PWM_CTL2 = I915_READ(BLC_PWM_CTL2);
 316         if (IS_MOBILE(dev) && !IS_I830(dev))
 317                 dev_priv->saveLVDS = I915_READ(LVDS);
 318         if (!IS_I830(dev) && !IS_845G(dev))
 319                 dev_priv->savePFIT_CONTROL = I915_READ(PFIT_CONTROL);
 320         dev_priv->saveLVDSPP_ON = I915_READ(LVDSPP_ON);
 321         dev_priv->saveLVDSPP_OFF = I915_READ(LVDSPP_OFF);
 322         dev_priv->savePP_CYCLE = I915_READ(PP_CYCLE);
 323
 324         /* FIXME: save TV & SDVO state */
 325
 326         /* FBC state */
 327         dev_priv->saveFBC_CFB_BASE = I915_READ(FBC_CFB_BASE);
 328         dev_priv->saveFBC_LL_BASE = I915_READ(FBC_LL_BASE);
 329         dev_priv->saveFBC_CONTROL2 = I915_READ(FBC_CONTROL2);
 330         dev_priv->saveFBC_CONTROL = I915_READ(FBC_CONTROL);
 331
 332         /* VGA state */
 333         dev_priv->saveVCLK_DIVISOR_VGA0 = I915_READ(VCLK_DIVISOR_VGA0);
 334         dev_priv->saveVCLK_DIVISOR_VGA1 = I915_READ(VCLK_DIVISOR_VGA1);
 335         dev_priv->saveVCLK_POST_DIV = I915_READ(VCLK_POST_DIV);
 336         dev_priv->saveVGACNTRL = I915_READ(VGACNTRL);
 337
 338         /* Scratch space */
 339         for (i = 0; i < 16; i++) {
 340                 dev_priv->saveSWF0[i] = I915_READ(SWF0 + (i << 2));
 341                 dev_priv->saveSWF1[i] = I915_READ(SWF10 + (i << 2));
 342         }
 343         for (i = 0; i < 3; i++)
 344                 dev_priv->saveSWF2[i] = I915_READ(SWF30 + (i << 2));
 345
 346         i915_save_vga(dev);
 347
 348         /* Shut down the device */
 349         pci_disable_device(dev->pdev);
 350         pci_set_power_state(dev->pdev, PCI_D3hot);
 351
 352         return 0;
 353 }
 354
 355 static int i915_resume(struct drm_device *dev)
 356 {
 357         struct drm_i915_private *dev_priv = dev->dev_private;
 358         int i;
 359
 360         pci_set_power_state(dev->pdev, PCI_D0);
 361         pci_restore_state(dev->pdev);
 362         if (pci_enable_device(dev->pdev))
 363                 return -1;
 364
 365         pci_write_config_byte(dev->pdev, LBB, dev_priv->saveLBB);
 366
 367         /* Pipe & plane A info */
 368         /* Prime the clock */
 369         if (dev_priv->saveDPLL_A & DPLL_VCO_ENABLE) {
 370                 I915_WRITE(DPLL_A, dev_priv->saveDPLL_A &
 371                            ~DPLL_VCO_ENABLE);
 372                 udelay(150);
 373         }
 374         I915_WRITE(FPA0, dev_priv->saveFPA0);
 375         I915_WRITE(FPA1, dev_priv->saveFPA1);
 376         /* Actually enable it */
 377         I915_WRITE(DPLL_A, dev_priv->saveDPLL_A);
 378         udelay(150);
 379         if (IS_I965G(dev))
 380                 I915_WRITE(DPLL_A_MD, dev_priv->saveDPLL_A_MD);
 381         udelay(150);
 382
 383         /* Restore mode */
 384         I915_WRITE(HTOTAL_A, dev_priv->saveHTOTAL_A);
 385         I915_WRITE(HBLANK_A, dev_priv->saveHBLANK_A);
 386         I915_WRITE(HSYNC_A, dev_priv->saveHSYNC_A);
 387         I915_WRITE(VTOTAL_A, dev_priv->saveVTOTAL_A);
 388         I915_WRITE(VBLANK_A, dev_priv->saveVBLANK_A);
 389         I915_WRITE(VSYNC_A, dev_priv->saveVSYNC_A);
 390         I915_WRITE(BCLRPAT_A, dev_priv->saveBCLRPAT_A);
 391
 392         /* Restore plane info */
 393         I915_WRITE(DSPASIZE, dev_priv->saveDSPASIZE);
 394         I915_WRITE(DSPAPOS, dev_priv->saveDSPAPOS);
 395         I915_WRITE(PIPEASRC, dev_priv->savePIPEASRC);
 396         I915_WRITE(DSPABASE, dev_priv->saveDSPABASE);
 397         I915_WRITE(DSPASTRIDE, dev_priv->saveDSPASTRIDE);
 398         if (IS_I965G(dev)) {
 399                 I915_WRITE(DSPASURF, dev_priv->saveDSPASURF);
 400                 I915_WRITE(DSPATILEOFF, dev_priv->saveDSPATILEOFF);
 401         }
 402
 403         if ((dev_priv->saveDPLL_A & DPLL_VCO_ENABLE) &&
 404             (dev_priv->saveDPLL_A & DPLL_VGA_MODE_DIS))
 405                 I915_WRITE(PIPEACONF, dev_priv->savePIPEACONF);
 406
 407         i915_restore_palette(dev, PIPE_A);
 408         /* Enable the plane */
 409         I915_WRITE(DSPACNTR, dev_priv->saveDSPACNTR);
 410         I915_WRITE(DSPABASE, I915_READ(DSPABASE));
 411
 412         /* Pipe & plane B info */
 413         if (dev_priv->saveDPLL_B & DPLL_VCO_ENABLE) {
 414                 I915_WRITE(DPLL_B, dev_priv->saveDPLL_B &
 415                            ~DPLL_VCO_ENABLE);
 416                 udelay(150);
 417         }
 418         I915_WRITE(FPB0, dev_priv->saveFPB0);
 419         I915_WRITE(FPB1, dev_priv->saveFPB1);
 420         /* Actually enable it */
 421         I915_WRITE(DPLL_B, dev_priv->saveDPLL_B);
 422         udelay(150);
 423         if (IS_I965G(dev))
 424                 I915_WRITE(DPLL_B_MD, dev_priv->saveDPLL_B_MD);
 425         udelay(150);
 426
 427         /* Restore mode */
 428         I915_WRITE(HTOTAL_B, dev_priv->saveHTOTAL_B);
 429         I915_WRITE(HBLANK_B, dev_priv->saveHBLANK_B);
 430         I915_WRITE(HSYNC_B, dev_priv->saveHSYNC_B);
 431         I915_WRITE(VTOTAL_B, dev_priv->saveVTOTAL_B);
 432         I915_WRITE(VBLANK_B, dev_priv->saveVBLANK_B);
 433         I915_WRITE(VSYNC_B, dev_priv->saveVSYNC_B);
 434         I915_WRITE(BCLRPAT_B, dev_priv->saveBCLRPAT_B);
 435
 436         /* Restore plane info */
 437         I915_WRITE(DSPBSIZE, dev_priv->saveDSPBSIZE);
 438         I915_WRITE(DSPBPOS, dev_priv->saveDSPBPOS);
 439         I915_WRITE(PIPEBSRC, dev_priv->savePIPEBSRC);
 440         I915_WRITE(DSPBBASE, dev_priv->saveDSPBBASE);
 441         I915_WRITE(DSPBSTRIDE, dev_priv->saveDSPBSTRIDE);
 442         if (IS_I965G(dev)) {
 443                 I915_WRITE(DSPBSURF, dev_priv->saveDSPBSURF);
 444                 I915_WRITE(DSPBTILEOFF, dev_priv->saveDSPBTILEOFF);
 445         }
 446
 447         if ((dev_priv->saveDPLL_B & DPLL_VCO_ENABLE) &&
 448             (dev_priv->saveDPLL_B & DPLL_VGA_MODE_DIS))
 449                 I915_WRITE(PIPEBCONF, dev_priv->savePIPEBCONF);
 450         i915_restore_palette(dev, PIPE_A);
 451         /* Enable the plane */
 452         I915_WRITE(DSPBCNTR, dev_priv->saveDSPBCNTR);
 453         I915_WRITE(DSPBBASE, I915_READ(DSPBBASE));
 454
 455         /* CRT state */
 456         I915_WRITE(ADPA, dev_priv->saveADPA);
 457
 458         /* LVDS state */
 459         if (IS_I965G(dev))
 460                 I915_WRITE(BLC_PWM_CTL2, dev_priv->saveBLC_PWM_CTL2);
 461         if (IS_MOBILE(dev) && !IS_I830(dev))
 462                 I915_WRITE(LVDS, dev_priv->saveLVDS);
 463         if (!IS_I830(dev) && !IS_845G(dev))
 464                 I915_WRITE(PFIT_CONTROL, dev_priv->savePFIT_CONTROL);
 465
 466         I915_WRITE(PFIT_PGM_RATIOS, dev_priv->savePFIT_PGM_RATIOS);
 467         I915_WRITE(BLC_PWM_CTL, dev_priv->saveBLC_PWM_CTL);
 468         I915_WRITE(LVDSPP_ON, dev_priv->saveLVDSPP_ON);
 469         I915_WRITE(LVDSPP_OFF, dev_priv->saveLVDSPP_OFF);
 470         I915_WRITE(PP_CYCLE, dev_priv->savePP_CYCLE);
 471         I915_WRITE(PP_CONTROL, dev_priv->savePP_CONTROL);
 472
 473         /* FIXME: restore TV & SDVO state */
 474
 475         /* FBC info */
 476         I915_WRITE(FBC_CFB_BASE, dev_priv->saveFBC_CFB_BASE);
 477         I915_WRITE(FBC_LL_BASE, dev_priv->saveFBC_LL_BASE);
 478         I915_WRITE(FBC_CONTROL2, dev_priv->saveFBC_CONTROL2);
 479         I915_WRITE(FBC_CONTROL, dev_priv->saveFBC_CONTROL);
 480
 481         /* VGA state */
 482         I915_WRITE(VGACNTRL, dev_priv->saveVGACNTRL);
 483         I915_WRITE(VCLK_DIVISOR_VGA0, dev_priv->saveVCLK_DIVISOR_VGA0);
 484         I915_WRITE(VCLK_DIVISOR_VGA1, dev_priv->saveVCLK_DIVISOR_VGA1);
 485         I915_WRITE(VCLK_POST_DIV, dev_priv->saveVCLK_POST_DIV);
 486         udelay(150);
 487
 488         for (i = 0; i < 16; i++) {
 489                 I915_WRITE(SWF0 + (i << 2), dev_priv->saveSWF0[i]);
 490                 I915_WRITE(SWF10 + (i << 2), dev_priv->saveSWF1[i+7]);
 491         }
 492         for (i = 0; i < 3; i++)
 493                 I915_WRITE(SWF30 + (i << 2), dev_priv->saveSWF2[i]);
 494
 495         i915_restore_vga(dev);
 496
 497         return 0;
 498 }
 499
 500 static struct drm_driver driver = {
 501         /* don't use mtrr's here, the Xserver or user space app should
 502          * deal with them for intel hardware.
 503          */
 504         .driver_features =
 505             DRIVER_USE_AGP | DRIVER_REQUIRE_AGP | /* DRIVER_USE_MTRR |*/
 506             DRIVER_HAVE_IRQ | DRIVER_IRQ_SHARED | DRIVER_IRQ_VBL |
 507             DRIVER_IRQ_VBL2,
 508         .load = i915_driver_load,
 509         .unload = i915_driver_unload,
 510         .lastclose = i915_driver_lastclose,
 511         .preclose = i915_driver_preclose,
 512         .suspend = i915_suspend,
 513         .resume = i915_resume,
 514         .device_is_agp = i915_driver_device_is_agp,
 515         .vblank_wait = i915_driver_vblank_wait,
 516         .vblank_wait2 = i915_driver_vblank_wait2,
 517         .irq_preinstall = i915_driver_irq_preinstall,
 518         .irq_postinstall = i915_driver_irq_postinstall,
 519         .irq_uninstall = i915_driver_irq_uninstall,
 520         .irq_handler = i915_driver_irq_handler,
 521         .reclaim_buffers = drm_core_reclaim_buffers,
 522         .get_map_ofs = drm_core_get_map_ofs,
 523         .get_reg_ofs = drm_core_get_reg_ofs,
 524         .ioctls = i915_ioctls,
 525         .fops = {
 526                  .owner = THIS_MODULE,
 527                  .open = drm_open,
 528                  .release = drm_release,
 529                  .ioctl = drm_ioctl,
 530                  .mmap = drm_mmap,
 531                  .poll = drm_poll,
 532                  .fasync = drm_fasync,
 533 #ifdef CONFIG_COMPAT
 534                  .compat_ioctl = i915_compat_ioctl,
 535 #endif
 536         },
 537
 538         .pci_driver = {
 539                  .name = DRIVER_NAME,
 540                  .id_table = pciidlist,
 541         },
 542
 543         .name = DRIVER_NAME,
 544         .desc = DRIVER_DESC,
 545         .date = DRIVER_DATE,
 546         .major = DRIVER_MAJOR,
 547         .minor = DRIVER_MINOR,
 548         .patchlevel = DRIVER_PATCHLEVEL,
 549 };
 550
 551 static int __init i915_init(void)
 552 {
 553         driver.num_ioctls = i915_max_ioctl;
 554         return drm_init(&driver);
 555 }
 556
 557 static void __exit i915_exit(void)
 558 {
 559         drm_exit(&driver);
 560 }
 561
 562 module_init(i915_init);
 563 module_exit(i915_exit);
 564
 565 MODULE_AUTHOR(DRIVER_AUTHOR);
 566 MODULE_DESCRIPTION(DRIVER_DESC);
 567 MODULE_LICENSE("GPL and additional rights");