2 * Copyright 2003 Tungsten Graphics, Inc., Cedar Park, Texas.
5 * Permission is hereby granted, free of charge, to any person obtaining a
6 * copy of this software and associated documentation files (the
7 * "Software"), to deal in the Software without restriction, including
8 * without limitation the rights to use, copy, modify, merge, publish,
9 * distribute, sub license, and/or sell copies of the Software, and to
10 * permit persons to whom the Software is furnished to do so, subject to
11 * the following conditions:
13 * The above copyright notice and this permission notice (including the
14 * next paragraph) shall be included in all copies or substantial portions
17 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
18 * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
19 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT.
20 * IN NO EVENT SHALL TUNGSTEN GRAPHICS AND/OR ITS SUPPLIERS BE LIABLE FOR
21 * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
22 * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
23 * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
30 /* Please note that modifications to all structs defined here are
31 * subject to backwards-compatibility constraints.
36 /* Each region is a minimum of 16k, and there are at most 255 of them.
38 #define I915_NR_TEX_REGIONS 255 /* table size 2k - maximum due to use
39 * of chars for next/prev indices */
40 #define I915_LOG_MIN_TEX_REGION_SIZE 14
42 typedef struct _drm_i915_init {
45 I915_CLEANUP_DMA = 0x02,
46 I915_RESUME_DMA = 0x03
48 unsigned int mmio_offset;
49 int sarea_priv_offset;
50 unsigned int ring_start;
51 unsigned int ring_end;
52 unsigned int ring_size;
53 unsigned int front_offset;
54 unsigned int back_offset;
55 unsigned int depth_offset;
59 unsigned int pitch_bits;
60 unsigned int back_pitch;
61 unsigned int depth_pitch;
66 typedef struct _drm_i915_sarea {
67 drm_tex_region_t texList[I915_NR_TEX_REGIONS + 1];
68 int last_upload; /* last time texture was uploaded */
69 int last_enqueue; /* last time a buffer was enqueued */
70 int last_dispatch; /* age of the most recently dispatched buffer */
71 int ctxOwner; /* last context to upload state */
73 int pf_enabled; /* is pageflipping allowed? */
75 int pf_current_page; /* which buffer is being displayed? */
76 int perf_boxes; /* performance boxes to be displayed */
79 /* Flags for perf_boxes
81 #define I915_BOX_RING_EMPTY 0x1
82 #define I915_BOX_FLIP 0x2
83 #define I915_BOX_WAIT 0x4
84 #define I915_BOX_TEXTURE_LOAD 0x8
85 #define I915_BOX_LOST_CONTEXT 0x10
87 /* I915 specific ioctls
88 * The device specific ioctl range is 0x40 to 0x79.
90 #define DRM_I915_INIT 0x00
91 #define DRM_I915_FLUSH 0x01
92 #define DRM_I915_FLIP 0x02
93 #define DRM_I915_BATCHBUFFER 0x03
94 #define DRM_I915_IRQ_EMIT 0x04
95 #define DRM_I915_IRQ_WAIT 0x05
96 #define DRM_I915_GETPARAM 0x06
97 #define DRM_I915_SETPARAM 0x07
98 #define DRM_I915_ALLOC 0x08
99 #define DRM_I915_FREE 0x09
100 #define DRM_I915_INIT_HEAP 0x0a
101 #define DRM_I915_CMDBUFFER 0x0b
103 #define DRM_IOCTL_I915_INIT DRM_IOW( DRM_COMMAND_BASE + DRM_I915_INIT, drm_i915_init_t)
104 #define DRM_IOCTL_I915_FLUSH DRM_IO ( DRM_COMMAND_BASE + DRM_I915_FLUSH)
105 #define DRM_IOCTL_I915_FLIP DRM_IO ( DRM_COMMAND_BASE + DRM_I915_FLIP)
106 #define DRM_IOCTL_I915_BATCHBUFFER DRM_IOW( DRM_COMMAND_BASE + DRM_I915_BATCHBUFFER, drm_i915_batchbuffer_t)
107 #define DRM_IOCTL_I915_IRQ_EMIT DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_IRQ_EMIT, drm_i915_irq_emit_t)
108 #define DRM_IOCTL_I915_IRQ_WAIT DRM_IOW( DRM_COMMAND_BASE + DRM_I915_IRQ_WAIT, drm_i915_irq_wait_t)
109 #define DRM_IOCTL_I915_GETPARAM DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_GETPARAM, drm_i915_getparam_t)
110 #define DRM_IOCTL_I915_SETPARAM DRM_IOW( DRM_COMMAND_BASE + DRM_I915_SETPARAM, drm_i915_setparam_t)
111 #define DRM_IOCTL_I915_ALLOC DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_ALLOC, drm_i915_mem_alloc_t)
112 #define DRM_IOCTL_I915_FREE DRM_IOW( DRM_COMMAND_BASE + DRM_I915_FREE, drm_i915_mem_free_t)
113 #define DRM_IOCTL_I915_INIT_HEAP DRM_IOW( DRM_COMMAND_BASE + DRM_I915_INIT_HEAP, drm_i915_mem_init_heap_t)
114 #define DRM_IOCTL_I915_CMDBUFFER DRM_IOW( DRM_COMMAND_BASE + DRM_I915_CMDBUFFER, drm_i915_cmdbuffer_t)
116 /* Allow drivers to submit batchbuffers directly to hardware, relying
117 * on the security mechanisms provided by hardware.
119 typedef struct _drm_i915_batchbuffer {
120 int start; /* agp offset */
121 int used; /* nr bytes in use */
122 int DR1; /* hw flags for GFX_OP_DRAWRECT_INFO */
123 int DR4; /* window origin for GFX_OP_DRAWRECT_INFO */
124 int num_cliprects; /* mulitpass with multiple cliprects? */
125 drm_clip_rect_t __user *cliprects; /* pointer to userspace cliprects */
126 } drm_i915_batchbuffer_t;
128 /* As above, but pass a pointer to userspace buffer which can be
129 * validated by the kernel prior to sending to hardware.
131 typedef struct _drm_i915_cmdbuffer {
132 char __user *buf; /* pointer to userspace command buffer */
133 int sz; /* nr bytes in buf */
134 int DR1; /* hw flags for GFX_OP_DRAWRECT_INFO */
135 int DR4; /* window origin for GFX_OP_DRAWRECT_INFO */
136 int num_cliprects; /* mulitpass with multiple cliprects? */
137 drm_clip_rect_t __user *cliprects; /* pointer to userspace cliprects */
138 } drm_i915_cmdbuffer_t;
140 /* Userspace can request & wait on irq's:
142 typedef struct drm_i915_irq_emit {
144 } drm_i915_irq_emit_t;
146 typedef struct drm_i915_irq_wait {
148 } drm_i915_irq_wait_t;
150 /* Ioctl to query kernel params:
152 #define I915_PARAM_IRQ_ACTIVE 1
153 #define I915_PARAM_ALLOW_BATCHBUFFER 2
154 #define I915_PARAM_LAST_DISPATCH 3
156 typedef struct drm_i915_getparam {
159 } drm_i915_getparam_t;
161 /* Ioctl to set kernel params:
163 #define I915_SETPARAM_USE_MI_BATCHBUFFER_START 1
164 #define I915_SETPARAM_TEX_LRU_LOG_GRANULARITY 2
165 #define I915_SETPARAM_ALLOW_BATCHBUFFER 3
167 typedef struct drm_i915_setparam {
170 } drm_i915_setparam_t;
172 /* A memory manager for regions of shared memory:
174 #define I915_MEM_REGION_AGP 1
176 typedef struct drm_i915_mem_alloc {
180 int __user *region_offset; /* offset from start of fb or agp */
181 } drm_i915_mem_alloc_t;
183 typedef struct drm_i915_mem_free {
186 } drm_i915_mem_free_t;
188 typedef struct drm_i915_mem_init_heap {
192 } drm_i915_mem_init_heap_t;
194 #endif /* _I915_DRM_H_ */