2 * Copyright 2003 Tungsten Graphics, Inc., Cedar Park, Texas.
5 * Permission is hereby granted, free of charge, to any person obtaining a
6 * copy of this software and associated documentation files (the
7 * "Software"), to deal in the Software without restriction, including
8 * without limitation the rights to use, copy, modify, merge, publish,
9 * distribute, sub license, and/or sell copies of the Software, and to
10 * permit persons to whom the Software is furnished to do so, subject to
11 * the following conditions:
13 * The above copyright notice and this permission notice (including the
14 * next paragraph) shall be included in all copies or substantial portions
17 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
18 * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
19 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT.
20 * IN NO EVENT SHALL TUNGSTEN GRAPHICS AND/OR ITS SUPPLIERS BE LIABLE FOR
21 * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
22 * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
23 * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
30 /* Please note that modifications to all structs defined here are
31 * subject to backwards-compatibility constraints.
36 /* Each region is a minimum of 16k, and there are at most 255 of them.
38 #define I915_NR_TEX_REGIONS 255 /* table size 2k - maximum due to use
39 * of chars for next/prev indices */
40 #define I915_LOG_MIN_TEX_REGION_SIZE 14
42 typedef struct _drm_i915_init {
45 I915_CLEANUP_DMA = 0x02,
46 I915_RESUME_DMA = 0x03
48 unsigned int mmio_offset;
49 int sarea_priv_offset;
50 unsigned int ring_start;
51 unsigned int ring_end;
52 unsigned int ring_size;
53 unsigned int front_offset;
54 unsigned int back_offset;
55 unsigned int depth_offset;
59 unsigned int pitch_bits;
60 unsigned int back_pitch;
61 unsigned int depth_pitch;
66 typedef struct _drm_i915_sarea {
67 drm_tex_region_t texList[I915_NR_TEX_REGIONS + 1];
68 int last_upload; /* last time texture was uploaded */
69 int last_enqueue; /* last time a buffer was enqueued */
70 int last_dispatch; /* age of the most recently dispatched buffer */
71 int ctxOwner; /* last context to upload state */
73 int pf_enabled; /* is pageflipping allowed? */
75 int pf_current_page; /* which buffer is being displayed? */
76 int perf_boxes; /* performance boxes to be displayed */
77 int width, height; /* screen size in pixels */
79 drm_handle_t front_handle;
83 drm_handle_t back_handle;
87 drm_handle_t depth_handle;
91 drm_handle_t tex_handle;
94 int log_tex_granularity;
96 int rotation; /* 0, 90, 180 or 270 */
100 int virtualX, virtualY;
103 /* Flags for perf_boxes
105 #define I915_BOX_RING_EMPTY 0x1
106 #define I915_BOX_FLIP 0x2
107 #define I915_BOX_WAIT 0x4
108 #define I915_BOX_TEXTURE_LOAD 0x8
109 #define I915_BOX_LOST_CONTEXT 0x10
111 /* I915 specific ioctls
112 * The device specific ioctl range is 0x40 to 0x79.
114 #define DRM_I915_INIT 0x00
115 #define DRM_I915_FLUSH 0x01
116 #define DRM_I915_FLIP 0x02
117 #define DRM_I915_BATCHBUFFER 0x03
118 #define DRM_I915_IRQ_EMIT 0x04
119 #define DRM_I915_IRQ_WAIT 0x05
120 #define DRM_I915_GETPARAM 0x06
121 #define DRM_I915_SETPARAM 0x07
122 #define DRM_I915_ALLOC 0x08
123 #define DRM_I915_FREE 0x09
124 #define DRM_I915_INIT_HEAP 0x0a
125 #define DRM_I915_CMDBUFFER 0x0b
126 #define DRM_I915_DESTROY_HEAP 0x0c
127 #define DRM_I915_SET_VBLANK_PIPE 0x0d
128 #define DRM_I915_GET_VBLANK_PIPE 0x0e
130 #define DRM_IOCTL_I915_INIT DRM_IOW( DRM_COMMAND_BASE + DRM_I915_INIT, drm_i915_init_t)
131 #define DRM_IOCTL_I915_FLUSH DRM_IO ( DRM_COMMAND_BASE + DRM_I915_FLUSH)
132 #define DRM_IOCTL_I915_FLIP DRM_IO ( DRM_COMMAND_BASE + DRM_I915_FLIP)
133 #define DRM_IOCTL_I915_BATCHBUFFER DRM_IOW( DRM_COMMAND_BASE + DRM_I915_BATCHBUFFER, drm_i915_batchbuffer_t)
134 #define DRM_IOCTL_I915_IRQ_EMIT DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_IRQ_EMIT, drm_i915_irq_emit_t)
135 #define DRM_IOCTL_I915_IRQ_WAIT DRM_IOW( DRM_COMMAND_BASE + DRM_I915_IRQ_WAIT, drm_i915_irq_wait_t)
136 #define DRM_IOCTL_I915_GETPARAM DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_GETPARAM, drm_i915_getparam_t)
137 #define DRM_IOCTL_I915_SETPARAM DRM_IOW( DRM_COMMAND_BASE + DRM_I915_SETPARAM, drm_i915_setparam_t)
138 #define DRM_IOCTL_I915_ALLOC DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_ALLOC, drm_i915_mem_alloc_t)
139 #define DRM_IOCTL_I915_FREE DRM_IOW( DRM_COMMAND_BASE + DRM_I915_FREE, drm_i915_mem_free_t)
140 #define DRM_IOCTL_I915_INIT_HEAP DRM_IOW( DRM_COMMAND_BASE + DRM_I915_INIT_HEAP, drm_i915_mem_init_heap_t)
141 #define DRM_IOCTL_I915_CMDBUFFER DRM_IOW( DRM_COMMAND_BASE + DRM_I915_CMDBUFFER, drm_i915_cmdbuffer_t)
142 #define DRM_IOCTL_I915_DESTROY_HEAP DRM_IOW( DRM_COMMAND_BASE + DRM_I915_DESTROY_HEAP, drm_i915_mem_destroy_heap_t)
143 #define DRM_IOCTL_I915_SET_VBLANK_PIPE DRM_IOW( DRM_COMMAND_BASE + DRM_I915_SET_VBLANK_PIPE, drm_i915_vblank_pipe_t)
144 #define DRM_IOCTL_I915_GET_VBLANK_PIPE DRM_IOR( DRM_COMMAND_BASE + DRM_I915_GET_VBLANK_PIPE, drm_i915_vblank_pipe_t)
146 /* Allow drivers to submit batchbuffers directly to hardware, relying
147 * on the security mechanisms provided by hardware.
149 typedef struct _drm_i915_batchbuffer {
150 int start; /* agp offset */
151 int used; /* nr bytes in use */
152 int DR1; /* hw flags for GFX_OP_DRAWRECT_INFO */
153 int DR4; /* window origin for GFX_OP_DRAWRECT_INFO */
154 int num_cliprects; /* mulitpass with multiple cliprects? */
155 drm_clip_rect_t __user *cliprects; /* pointer to userspace cliprects */
156 } drm_i915_batchbuffer_t;
158 /* As above, but pass a pointer to userspace buffer which can be
159 * validated by the kernel prior to sending to hardware.
161 typedef struct _drm_i915_cmdbuffer {
162 char __user *buf; /* pointer to userspace command buffer */
163 int sz; /* nr bytes in buf */
164 int DR1; /* hw flags for GFX_OP_DRAWRECT_INFO */
165 int DR4; /* window origin for GFX_OP_DRAWRECT_INFO */
166 int num_cliprects; /* mulitpass with multiple cliprects? */
167 drm_clip_rect_t __user *cliprects; /* pointer to userspace cliprects */
168 } drm_i915_cmdbuffer_t;
170 /* Userspace can request & wait on irq's:
172 typedef struct drm_i915_irq_emit {
174 } drm_i915_irq_emit_t;
176 typedef struct drm_i915_irq_wait {
178 } drm_i915_irq_wait_t;
180 /* Ioctl to query kernel params:
182 #define I915_PARAM_IRQ_ACTIVE 1
183 #define I915_PARAM_ALLOW_BATCHBUFFER 2
184 #define I915_PARAM_LAST_DISPATCH 3
186 typedef struct drm_i915_getparam {
189 } drm_i915_getparam_t;
191 /* Ioctl to set kernel params:
193 #define I915_SETPARAM_USE_MI_BATCHBUFFER_START 1
194 #define I915_SETPARAM_TEX_LRU_LOG_GRANULARITY 2
195 #define I915_SETPARAM_ALLOW_BATCHBUFFER 3
197 typedef struct drm_i915_setparam {
200 } drm_i915_setparam_t;
202 /* A memory manager for regions of shared memory:
204 #define I915_MEM_REGION_AGP 1
206 typedef struct drm_i915_mem_alloc {
210 int __user *region_offset; /* offset from start of fb or agp */
211 } drm_i915_mem_alloc_t;
213 typedef struct drm_i915_mem_free {
216 } drm_i915_mem_free_t;
218 typedef struct drm_i915_mem_init_heap {
222 } drm_i915_mem_init_heap_t;
224 /* Allow memory manager to be torn down and re-initialized (eg on
227 typedef struct drm_i915_mem_destroy_heap {
229 } drm_i915_mem_destroy_heap_t;
231 /* Allow X server to configure which pipes to monitor for vblank signals
233 #define DRM_I915_VBLANK_PIPE_A 1
234 #define DRM_I915_VBLANK_PIPE_B 2
236 typedef struct drm_i915_vblank_pipe {
238 } drm_i915_vblank_pipe_t;
240 #endif /* _I915_DRM_H_ */