2 * Intel AGPGART routines.
5 #include <linux/module.h>
7 #include <linux/init.h>
8 #include <linux/kernel.h>
9 #include <linux/pagemap.h>
10 #include <linux/agp_backend.h>
13 #define PCI_DEVICE_ID_INTEL_E7221_HB 0x2588
14 #define PCI_DEVICE_ID_INTEL_E7221_IG 0x258a
15 #define PCI_DEVICE_ID_INTEL_82946GZ_HB 0x2970
16 #define PCI_DEVICE_ID_INTEL_82946GZ_IG 0x2972
17 #define PCI_DEVICE_ID_INTEL_82965G_1_HB 0x2980
18 #define PCI_DEVICE_ID_INTEL_82965G_1_IG 0x2982
19 #define PCI_DEVICE_ID_INTEL_82965Q_HB 0x2990
20 #define PCI_DEVICE_ID_INTEL_82965Q_IG 0x2992
21 #define PCI_DEVICE_ID_INTEL_82965G_HB 0x29A0
22 #define PCI_DEVICE_ID_INTEL_82965G_IG 0x29A2
23 #define PCI_DEVICE_ID_INTEL_82965GM_HB 0x2A00
24 #define PCI_DEVICE_ID_INTEL_82965GM_IG 0x2A02
25 #define PCI_DEVICE_ID_INTEL_82965GME_HB 0x2A10
26 #define PCI_DEVICE_ID_INTEL_82965GME_IG 0x2A12
27 #define PCI_DEVICE_ID_INTEL_82945GME_HB 0x27AC
28 #define PCI_DEVICE_ID_INTEL_82945GME_IG 0x27AE
29 #define PCI_DEVICE_ID_INTEL_G33_HB 0x29C0
30 #define PCI_DEVICE_ID_INTEL_G33_IG 0x29C2
31 #define PCI_DEVICE_ID_INTEL_Q35_HB 0x29B0
32 #define PCI_DEVICE_ID_INTEL_Q35_IG 0x29B2
33 #define PCI_DEVICE_ID_INTEL_Q33_HB 0x29D0
34 #define PCI_DEVICE_ID_INTEL_Q33_IG 0x29D2
35 #define PCI_DEVICE_ID_INTEL_IGD_HB 0x2A40
36 #define PCI_DEVICE_ID_INTEL_IGD_IG 0x2A42
38 #define IS_I965 (agp_bridge->dev->device == PCI_DEVICE_ID_INTEL_82946GZ_HB || \
39 agp_bridge->dev->device == PCI_DEVICE_ID_INTEL_82965G_1_HB || \
40 agp_bridge->dev->device == PCI_DEVICE_ID_INTEL_82965Q_HB || \
41 agp_bridge->dev->device == PCI_DEVICE_ID_INTEL_82965G_HB || \
42 agp_bridge->dev->device == PCI_DEVICE_ID_INTEL_82965GM_HB || \
43 agp_bridge->dev->device == PCI_DEVICE_ID_INTEL_82965GME_HB || \
44 agp_bridge->dev->device == PCI_DEVICE_ID_INTEL_IGD_HB)
46 #define IS_G33 (agp_bridge->dev->device == PCI_DEVICE_ID_INTEL_G33_HB || \
47 agp_bridge->dev->device == PCI_DEVICE_ID_INTEL_Q35_HB || \
48 agp_bridge->dev->device == PCI_DEVICE_ID_INTEL_Q33_HB)
50 extern int agp_memory_reserved;
53 /* Intel 815 register */
54 #define INTEL_815_APCONT 0x51
55 #define INTEL_815_ATTBASE_MASK ~0x1FFFFFFF
57 /* Intel i820 registers */
58 #define INTEL_I820_RDCR 0x51
59 #define INTEL_I820_ERRSTS 0xc8
61 /* Intel i840 registers */
62 #define INTEL_I840_MCHCFG 0x50
63 #define INTEL_I840_ERRSTS 0xc8
65 /* Intel i850 registers */
66 #define INTEL_I850_MCHCFG 0x50
67 #define INTEL_I850_ERRSTS 0xc8
69 /* intel 915G registers */
70 #define I915_GMADDR 0x18
71 #define I915_MMADDR 0x10
72 #define I915_PTEADDR 0x1C
73 #define I915_GMCH_GMS_STOLEN_48M (0x6 << 4)
74 #define I915_GMCH_GMS_STOLEN_64M (0x7 << 4)
75 #define G33_GMCH_GMS_STOLEN_128M (0x8 << 4)
76 #define G33_GMCH_GMS_STOLEN_256M (0x9 << 4)
77 #define I915_IFPADDR 0x60
79 /* Intel 965G registers */
80 #define I965_MSAC 0x62
81 #define I965_IFPADDR 0x70
83 /* Intel 7505 registers */
84 #define INTEL_I7505_APSIZE 0x74
85 #define INTEL_I7505_NCAPID 0x60
86 #define INTEL_I7505_NISTAT 0x6c
87 #define INTEL_I7505_ATTBASE 0x78
88 #define INTEL_I7505_ERRSTS 0x42
89 #define INTEL_I7505_AGPCTRL 0x70
90 #define INTEL_I7505_MCHCFG 0x50
92 static const struct aper_size_info_fixed intel_i810_sizes[] =
95 /* The 32M mode still requires a 64k gatt */
99 #define AGP_DCACHE_MEMORY 1
100 #define AGP_PHYS_MEMORY 2
101 #define INTEL_AGP_CACHED_MEMORY 3
103 static struct gatt_mask intel_i810_masks[] =
105 {.mask = I810_PTE_VALID, .type = 0},
106 {.mask = (I810_PTE_VALID | I810_PTE_LOCAL), .type = AGP_DCACHE_MEMORY},
107 {.mask = I810_PTE_VALID, .type = 0},
108 {.mask = I810_PTE_VALID | I830_PTE_SYSTEM_CACHED,
109 .type = INTEL_AGP_CACHED_MEMORY}
112 static struct _intel_private {
113 struct pci_dev *pcidev; /* device one */
114 u8 __iomem *registers;
115 u32 __iomem *gtt; /* I915G */
116 int num_dcache_entries;
117 /* gtt_entries is the number of gtt entries that are already mapped
118 * to stolen memory. Stolen memory is larger than the memory mapped
119 * through gtt_entries, as it includes some reserved space for the BIOS
120 * popup and for the GTT.
122 int gtt_entries; /* i830+ */
124 void __iomem *i9xx_flush_page;
125 void *i8xx_flush_page;
127 struct page *i8xx_page;
128 struct resource ifp_resource;
132 static int intel_i810_fetch_size(void)
135 struct aper_size_info_fixed *values;
137 pci_read_config_dword(agp_bridge->dev, I810_SMRAM_MISCC, &smram_miscc);
138 values = A_SIZE_FIX(agp_bridge->driver->aperture_sizes);
140 if ((smram_miscc & I810_GMS) == I810_GMS_DISABLE) {
141 printk(KERN_WARNING PFX "i810 is disabled\n");
144 if ((smram_miscc & I810_GFX_MEM_WIN_SIZE) == I810_GFX_MEM_WIN_32M) {
145 agp_bridge->previous_size =
146 agp_bridge->current_size = (void *) (values + 1);
147 agp_bridge->aperture_size_idx = 1;
148 return values[1].size;
150 agp_bridge->previous_size =
151 agp_bridge->current_size = (void *) (values);
152 agp_bridge->aperture_size_idx = 0;
153 return values[0].size;
159 static int intel_i810_configure(void)
161 struct aper_size_info_fixed *current_size;
165 current_size = A_SIZE_FIX(agp_bridge->current_size);
167 if (!intel_private.registers) {
168 pci_read_config_dword(intel_private.pcidev, I810_MMADDR, &temp);
171 intel_private.registers = ioremap(temp, 128 * 4096);
172 if (!intel_private.registers) {
173 printk(KERN_ERR PFX "Unable to remap memory.\n");
178 if ((readl(intel_private.registers+I810_DRAM_CTL)
179 & I810_DRAM_ROW_0) == I810_DRAM_ROW_0_SDRAM) {
180 /* This will need to be dynamically assigned */
181 printk(KERN_INFO PFX "detected 4MB dedicated video ram.\n");
182 intel_private.num_dcache_entries = 1024;
184 pci_read_config_dword(intel_private.pcidev, I810_GMADDR, &temp);
185 agp_bridge->gart_bus_addr = (temp & PCI_BASE_ADDRESS_MEM_MASK);
186 writel(agp_bridge->gatt_bus_addr | I810_PGETBL_ENABLED, intel_private.registers+I810_PGETBL_CTL);
187 readl(intel_private.registers+I810_PGETBL_CTL); /* PCI Posting. */
189 if (agp_bridge->driver->needs_scratch_page) {
190 for (i = 0; i < current_size->num_entries; i++) {
191 writel(agp_bridge->scratch_page, intel_private.registers+I810_PTE_BASE+(i*4));
192 readl(intel_private.registers+I810_PTE_BASE+(i*4)); /* PCI posting. */
195 global_cache_flush();
199 static void intel_i810_cleanup(void)
201 writel(0, intel_private.registers+I810_PGETBL_CTL);
202 readl(intel_private.registers); /* PCI Posting. */
203 iounmap(intel_private.registers);
206 static void intel_i810_tlbflush(struct agp_memory *mem)
211 static void intel_i810_agp_enable(struct agp_bridge_data *bridge, u32 mode)
216 /* Exists to support ARGB cursors */
217 static void *i8xx_alloc_pages(void)
221 page = alloc_pages(GFP_KERNEL | GFP_DMA32, 2);
225 if (set_pages_uc(page, 4) < 0) {
226 set_pages_wb(page, 4);
227 __free_pages(page, 2);
231 atomic_inc(&agp_bridge->current_memory_agp);
232 return page_address(page);
235 static void i8xx_destroy_pages(void *addr)
242 page = virt_to_page(addr);
243 set_pages_wb(page, 4);
245 __free_pages(page, 2);
246 atomic_dec(&agp_bridge->current_memory_agp);
249 static int intel_i830_type_to_mask_type(struct agp_bridge_data *bridge,
252 if (type < AGP_USER_TYPES)
254 else if (type == AGP_USER_CACHED_MEMORY)
255 return INTEL_AGP_CACHED_MEMORY;
260 static int intel_i810_insert_entries(struct agp_memory *mem, off_t pg_start,
263 int i, j, num_entries;
268 if (mem->page_count == 0)
271 temp = agp_bridge->current_size;
272 num_entries = A_SIZE_FIX(temp)->num_entries;
274 if ((pg_start + mem->page_count) > num_entries)
278 for (j = pg_start; j < (pg_start + mem->page_count); j++) {
279 if (!PGE_EMPTY(agp_bridge, readl(agp_bridge->gatt_table+j))) {
285 if (type != mem->type)
288 mask_type = agp_bridge->driver->agp_type_to_mask_type(agp_bridge, type);
291 case AGP_DCACHE_MEMORY:
292 if (!mem->is_flushed)
293 global_cache_flush();
294 for (i = pg_start; i < (pg_start + mem->page_count); i++) {
295 writel((i*4096)|I810_PTE_LOCAL|I810_PTE_VALID,
296 intel_private.registers+I810_PTE_BASE+(i*4));
298 readl(intel_private.registers+I810_PTE_BASE+((i-1)*4));
300 case AGP_PHYS_MEMORY:
301 case AGP_NORMAL_MEMORY:
302 if (!mem->is_flushed)
303 global_cache_flush();
304 for (i = 0, j = pg_start; i < mem->page_count; i++, j++) {
305 writel(agp_bridge->driver->mask_memory(agp_bridge,
308 intel_private.registers+I810_PTE_BASE+(j*4));
310 readl(intel_private.registers+I810_PTE_BASE+((j-1)*4));
316 agp_bridge->driver->tlb_flush(mem);
324 static int intel_i810_remove_entries(struct agp_memory *mem, off_t pg_start,
329 if (mem->page_count == 0)
332 for (i = pg_start; i < (mem->page_count + pg_start); i++) {
333 writel(agp_bridge->scratch_page, intel_private.registers+I810_PTE_BASE+(i*4));
335 readl(intel_private.registers+I810_PTE_BASE+((i-1)*4));
337 agp_bridge->driver->tlb_flush(mem);
342 * The i810/i830 requires a physical address to program its mouse
343 * pointer into hardware.
344 * However the Xserver still writes to it through the agp aperture.
346 static struct agp_memory *alloc_agpphysmem_i8xx(size_t pg_count, int type)
348 struct agp_memory *new;
352 case 1: addr = agp_bridge->driver->agp_alloc_page(agp_bridge);
355 /* kludge to get 4 physical pages for ARGB cursor */
356 addr = i8xx_alloc_pages();
365 new = agp_create_memory(pg_count);
369 new->memory[0] = virt_to_gart(addr);
371 /* kludge to get 4 physical pages for ARGB cursor */
372 new->memory[1] = new->memory[0] + PAGE_SIZE;
373 new->memory[2] = new->memory[1] + PAGE_SIZE;
374 new->memory[3] = new->memory[2] + PAGE_SIZE;
376 new->page_count = pg_count;
377 new->num_scratch_pages = pg_count;
378 new->type = AGP_PHYS_MEMORY;
379 new->physical = new->memory[0];
383 static struct agp_memory *intel_i810_alloc_by_type(size_t pg_count, int type)
385 struct agp_memory *new;
387 if (type == AGP_DCACHE_MEMORY) {
388 if (pg_count != intel_private.num_dcache_entries)
391 new = agp_create_memory(1);
395 new->type = AGP_DCACHE_MEMORY;
396 new->page_count = pg_count;
397 new->num_scratch_pages = 0;
398 agp_free_page_array(new);
401 if (type == AGP_PHYS_MEMORY)
402 return alloc_agpphysmem_i8xx(pg_count, type);
406 static void intel_i810_free_by_type(struct agp_memory *curr)
408 agp_free_key(curr->key);
409 if (curr->type == AGP_PHYS_MEMORY) {
410 if (curr->page_count == 4)
411 i8xx_destroy_pages(gart_to_virt(curr->memory[0]));
413 agp_bridge->driver->agp_destroy_page(gart_to_virt(curr->memory[0]),
414 AGP_PAGE_DESTROY_UNMAP);
415 agp_bridge->driver->agp_destroy_page(gart_to_virt(curr->memory[0]),
416 AGP_PAGE_DESTROY_FREE);
418 agp_free_page_array(curr);
423 static unsigned long intel_i810_mask_memory(struct agp_bridge_data *bridge,
424 unsigned long addr, int type)
426 /* Type checking must be done elsewhere */
427 return addr | bridge->driver->masks[type].mask;
430 static struct aper_size_info_fixed intel_i830_sizes[] =
433 /* The 64M mode still requires a 128k gatt */
439 static void intel_i830_init_gtt_entries(void)
445 static const int ddt[4] = { 0, 16, 32, 64 };
446 int size; /* reserved space (in kb) at the top of stolen memory */
448 pci_read_config_word(agp_bridge->dev,I830_GMCH_CTRL,&gmch_ctrl);
452 pgetbl_ctl = readl(intel_private.registers+I810_PGETBL_CTL);
454 /* The 965 has a field telling us the size of the GTT,
455 * which may be larger than what is necessary to map the
458 switch (pgetbl_ctl & I965_PGETBL_SIZE_MASK) {
459 case I965_PGETBL_SIZE_128KB:
462 case I965_PGETBL_SIZE_256KB:
465 case I965_PGETBL_SIZE_512KB:
468 case I965_PGETBL_SIZE_1MB:
471 case I965_PGETBL_SIZE_2MB:
474 case I965_PGETBL_SIZE_1_5MB:
478 printk(KERN_INFO PFX "Unknown page table size, "
482 size += 4; /* add in BIOS popup space */
484 /* G33's GTT size defined in gmch_ctrl */
485 switch (gmch_ctrl & G33_PGETBL_SIZE_MASK) {
486 case G33_PGETBL_SIZE_1M:
489 case G33_PGETBL_SIZE_2M:
493 printk(KERN_INFO PFX "Unknown page table size 0x%x, "
495 (gmch_ctrl & G33_PGETBL_SIZE_MASK));
500 /* On previous hardware, the GTT size was just what was
501 * required to map the aperture.
503 size = agp_bridge->driver->fetch_size() + 4;
506 if (agp_bridge->dev->device == PCI_DEVICE_ID_INTEL_82830_HB ||
507 agp_bridge->dev->device == PCI_DEVICE_ID_INTEL_82845G_HB) {
508 switch (gmch_ctrl & I830_GMCH_GMS_MASK) {
509 case I830_GMCH_GMS_STOLEN_512:
510 gtt_entries = KB(512) - KB(size);
512 case I830_GMCH_GMS_STOLEN_1024:
513 gtt_entries = MB(1) - KB(size);
515 case I830_GMCH_GMS_STOLEN_8192:
516 gtt_entries = MB(8) - KB(size);
518 case I830_GMCH_GMS_LOCAL:
519 rdct = readb(intel_private.registers+I830_RDRAM_CHANNEL_TYPE);
520 gtt_entries = (I830_RDRAM_ND(rdct) + 1) *
521 MB(ddt[I830_RDRAM_DDT(rdct)]);
529 switch (gmch_ctrl & I855_GMCH_GMS_MASK) {
530 case I855_GMCH_GMS_STOLEN_1M:
531 gtt_entries = MB(1) - KB(size);
533 case I855_GMCH_GMS_STOLEN_4M:
534 gtt_entries = MB(4) - KB(size);
536 case I855_GMCH_GMS_STOLEN_8M:
537 gtt_entries = MB(8) - KB(size);
539 case I855_GMCH_GMS_STOLEN_16M:
540 gtt_entries = MB(16) - KB(size);
542 case I855_GMCH_GMS_STOLEN_32M:
543 gtt_entries = MB(32) - KB(size);
545 case I915_GMCH_GMS_STOLEN_48M:
546 /* Check it's really I915G */
547 if (agp_bridge->dev->device == PCI_DEVICE_ID_INTEL_E7221_HB ||
548 agp_bridge->dev->device == PCI_DEVICE_ID_INTEL_82915G_HB ||
549 agp_bridge->dev->device == PCI_DEVICE_ID_INTEL_82915GM_HB ||
550 agp_bridge->dev->device == PCI_DEVICE_ID_INTEL_82945G_HB ||
551 agp_bridge->dev->device == PCI_DEVICE_ID_INTEL_82945GM_HB ||
552 agp_bridge->dev->device == PCI_DEVICE_ID_INTEL_82945GME_HB ||
554 gtt_entries = MB(48) - KB(size);
558 case I915_GMCH_GMS_STOLEN_64M:
559 /* Check it's really I915G */
560 if (agp_bridge->dev->device == PCI_DEVICE_ID_INTEL_E7221_HB ||
561 agp_bridge->dev->device == PCI_DEVICE_ID_INTEL_82915G_HB ||
562 agp_bridge->dev->device == PCI_DEVICE_ID_INTEL_82915GM_HB ||
563 agp_bridge->dev->device == PCI_DEVICE_ID_INTEL_82945G_HB ||
564 agp_bridge->dev->device == PCI_DEVICE_ID_INTEL_82945GM_HB ||
565 agp_bridge->dev->device == PCI_DEVICE_ID_INTEL_82945GME_HB ||
567 gtt_entries = MB(64) - KB(size);
571 case G33_GMCH_GMS_STOLEN_128M:
573 gtt_entries = MB(128) - KB(size);
577 case G33_GMCH_GMS_STOLEN_256M:
579 gtt_entries = MB(256) - KB(size);
589 printk(KERN_INFO PFX "Detected %dK %s memory.\n",
590 gtt_entries / KB(1), local ? "local" : "stolen");
593 "No pre-allocated video memory detected.\n");
594 gtt_entries /= KB(4);
596 intel_private.gtt_entries = gtt_entries;
599 static void intel_i830_fini_flush(void)
601 kunmap(intel_private.i8xx_page);
602 intel_private.i8xx_flush_page = NULL;
603 unmap_page_from_agp(intel_private.i8xx_page);
604 flush_agp_mappings();
606 __free_page(intel_private.i8xx_page);
607 intel_private.i8xx_page = NULL;
610 static void intel_i830_setup_flush(void)
612 /* return if we've already set the flush mechanism up */
613 if (intel_private.i8xx_page)
616 intel_private.i8xx_page = alloc_page(GFP_KERNEL | __GFP_ZERO | GFP_DMA32);
617 if (!intel_private.i8xx_page) {
621 /* make page uncached */
622 map_page_into_agp(intel_private.i8xx_page);
623 flush_agp_mappings();
625 intel_private.i8xx_flush_page = kmap(intel_private.i8xx_page);
626 if (!intel_private.i8xx_flush_page)
627 intel_i830_fini_flush();
630 static void intel_i830_chipset_flush(struct agp_bridge_data *bridge)
632 unsigned int *pg = intel_private.i8xx_flush_page;
635 for (i = 0; i < 256; i+=2)
641 /* The intel i830 automatically initializes the agp aperture during POST.
642 * Use the memory already set aside for in the GTT.
644 static int intel_i830_create_gatt_table(struct agp_bridge_data *bridge)
647 struct aper_size_info_fixed *size;
651 size = agp_bridge->current_size;
652 page_order = size->page_order;
653 num_entries = size->num_entries;
654 agp_bridge->gatt_table_real = NULL;
656 pci_read_config_dword(intel_private.pcidev,I810_MMADDR,&temp);
659 intel_private.registers = ioremap(temp,128 * 4096);
660 if (!intel_private.registers)
663 temp = readl(intel_private.registers+I810_PGETBL_CTL) & 0xfffff000;
664 global_cache_flush(); /* FIXME: ?? */
666 /* we have to call this as early as possible after the MMIO base address is known */
667 intel_i830_init_gtt_entries();
669 agp_bridge->gatt_table = NULL;
671 agp_bridge->gatt_bus_addr = temp;
676 /* Return the gatt table to a sane state. Use the top of stolen
677 * memory for the GTT.
679 static int intel_i830_free_gatt_table(struct agp_bridge_data *bridge)
684 static int intel_i830_fetch_size(void)
687 struct aper_size_info_fixed *values;
689 values = A_SIZE_FIX(agp_bridge->driver->aperture_sizes);
691 if (agp_bridge->dev->device != PCI_DEVICE_ID_INTEL_82830_HB &&
692 agp_bridge->dev->device != PCI_DEVICE_ID_INTEL_82845G_HB) {
693 /* 855GM/852GM/865G has 128MB aperture size */
694 agp_bridge->previous_size = agp_bridge->current_size = (void *) values;
695 agp_bridge->aperture_size_idx = 0;
696 return values[0].size;
699 pci_read_config_word(agp_bridge->dev,I830_GMCH_CTRL,&gmch_ctrl);
701 if ((gmch_ctrl & I830_GMCH_MEM_MASK) == I830_GMCH_MEM_128M) {
702 agp_bridge->previous_size = agp_bridge->current_size = (void *) values;
703 agp_bridge->aperture_size_idx = 0;
704 return values[0].size;
706 agp_bridge->previous_size = agp_bridge->current_size = (void *) (values + 1);
707 agp_bridge->aperture_size_idx = 1;
708 return values[1].size;
714 static int intel_i830_configure(void)
716 struct aper_size_info_fixed *current_size;
721 current_size = A_SIZE_FIX(agp_bridge->current_size);
723 pci_read_config_dword(intel_private.pcidev,I810_GMADDR,&temp);
724 agp_bridge->gart_bus_addr = (temp & PCI_BASE_ADDRESS_MEM_MASK);
726 pci_read_config_word(agp_bridge->dev,I830_GMCH_CTRL,&gmch_ctrl);
727 gmch_ctrl |= I830_GMCH_ENABLED;
728 pci_write_config_word(agp_bridge->dev,I830_GMCH_CTRL,gmch_ctrl);
730 writel(agp_bridge->gatt_bus_addr|I810_PGETBL_ENABLED, intel_private.registers+I810_PGETBL_CTL);
731 readl(intel_private.registers+I810_PGETBL_CTL); /* PCI Posting. */
733 if (agp_bridge->driver->needs_scratch_page) {
734 for (i = intel_private.gtt_entries; i < current_size->num_entries; i++) {
735 writel(agp_bridge->scratch_page, intel_private.registers+I810_PTE_BASE+(i*4));
736 readl(intel_private.registers+I810_PTE_BASE+(i*4)); /* PCI Posting. */
740 global_cache_flush();
742 intel_i830_setup_flush();
746 static void intel_i830_cleanup(void)
748 iounmap(intel_private.registers);
751 static int intel_i830_insert_entries(struct agp_memory *mem,off_t pg_start, int type)
758 if (mem->page_count == 0)
761 temp = agp_bridge->current_size;
762 num_entries = A_SIZE_FIX(temp)->num_entries;
764 if (pg_start < intel_private.gtt_entries) {
765 printk (KERN_DEBUG PFX "pg_start == 0x%.8lx,intel_private.gtt_entries == 0x%.8x\n",
766 pg_start,intel_private.gtt_entries);
768 printk (KERN_INFO PFX "Trying to insert into local/stolen memory\n");
772 if ((pg_start + mem->page_count) > num_entries)
775 /* The i830 can't check the GTT for entries since its read only,
776 * depend on the caller to make the correct offset decisions.
779 if (type != mem->type)
782 mask_type = agp_bridge->driver->agp_type_to_mask_type(agp_bridge, type);
784 if (mask_type != 0 && mask_type != AGP_PHYS_MEMORY &&
785 mask_type != INTEL_AGP_CACHED_MEMORY)
788 if (!mem->is_flushed)
789 global_cache_flush();
791 for (i = 0, j = pg_start; i < mem->page_count; i++, j++) {
792 writel(agp_bridge->driver->mask_memory(agp_bridge,
793 mem->memory[i], mask_type),
794 intel_private.registers+I810_PTE_BASE+(j*4));
796 readl(intel_private.registers+I810_PTE_BASE+((j-1)*4));
797 agp_bridge->driver->tlb_flush(mem);
806 static int intel_i830_remove_entries(struct agp_memory *mem,off_t pg_start,
811 if (mem->page_count == 0)
814 if (pg_start < intel_private.gtt_entries) {
815 printk (KERN_INFO PFX "Trying to disable local/stolen memory\n");
819 for (i = pg_start; i < (mem->page_count + pg_start); i++) {
820 writel(agp_bridge->scratch_page, intel_private.registers+I810_PTE_BASE+(i*4));
822 readl(intel_private.registers+I810_PTE_BASE+((i-1)*4));
824 agp_bridge->driver->tlb_flush(mem);
828 static struct agp_memory *intel_i830_alloc_by_type(size_t pg_count,int type)
830 if (type == AGP_PHYS_MEMORY)
831 return alloc_agpphysmem_i8xx(pg_count, type);
832 /* always return NULL for other allocation types for now */
836 static int intel_alloc_chipset_flush_resource(void)
839 ret = pci_bus_alloc_resource(agp_bridge->dev->bus, &intel_private.ifp_resource, PAGE_SIZE,
840 PAGE_SIZE, PCIBIOS_MIN_MEM, 0,
841 pcibios_align_resource, agp_bridge->dev);
846 static void intel_i915_setup_chipset_flush(void)
851 pci_read_config_dword(agp_bridge->dev, I915_IFPADDR, &temp);
853 intel_alloc_chipset_flush_resource();
854 intel_private.resource_valid = 1;
855 pci_write_config_dword(agp_bridge->dev, I915_IFPADDR, (intel_private.ifp_resource.start & 0xffffffff) | 0x1);
859 intel_private.resource_valid = 1;
860 intel_private.ifp_resource.start = temp;
861 intel_private.ifp_resource.end = temp + PAGE_SIZE;
862 ret = request_resource(&iomem_resource, &intel_private.ifp_resource);
863 /* some BIOSes reserve this area in a pnp some don't */
865 intel_private.resource_valid = 0;
869 static void intel_i965_g33_setup_chipset_flush(void)
871 u32 temp_hi, temp_lo;
874 pci_read_config_dword(agp_bridge->dev, I965_IFPADDR + 4, &temp_hi);
875 pci_read_config_dword(agp_bridge->dev, I965_IFPADDR, &temp_lo);
877 if (!(temp_lo & 0x1)) {
879 intel_alloc_chipset_flush_resource();
881 intel_private.resource_valid = 1;
882 pci_write_config_dword(agp_bridge->dev, I965_IFPADDR + 4,
883 upper_32_bits(intel_private.ifp_resource.start));
884 pci_write_config_dword(agp_bridge->dev, I965_IFPADDR, (intel_private.ifp_resource.start & 0xffffffff) | 0x1);
889 l64 = ((u64)temp_hi << 32) | temp_lo;
891 intel_private.resource_valid = 1;
892 intel_private.ifp_resource.start = l64;
893 intel_private.ifp_resource.end = l64 + PAGE_SIZE;
894 ret = request_resource(&iomem_resource, &intel_private.ifp_resource);
895 /* some BIOSes reserve this area in a pnp some don't */
897 intel_private.resource_valid = 0;
901 static void intel_i9xx_setup_flush(void)
903 /* return if already configured */
904 if (intel_private.ifp_resource.start)
907 /* setup a resource for this object */
908 intel_private.ifp_resource.name = "Intel Flush Page";
909 intel_private.ifp_resource.flags = IORESOURCE_MEM;
911 /* Setup chipset flush for 915 */
912 if (IS_I965 || IS_G33) {
913 intel_i965_g33_setup_chipset_flush();
915 intel_i915_setup_chipset_flush();
918 if (intel_private.ifp_resource.start) {
919 intel_private.i9xx_flush_page = ioremap_nocache(intel_private.ifp_resource.start, PAGE_SIZE);
920 if (!intel_private.i9xx_flush_page)
921 printk("unable to ioremap flush page - no chipset flushing");
925 static int intel_i915_configure(void)
927 struct aper_size_info_fixed *current_size;
932 current_size = A_SIZE_FIX(agp_bridge->current_size);
934 pci_read_config_dword(intel_private.pcidev, I915_GMADDR, &temp);
936 agp_bridge->gart_bus_addr = (temp & PCI_BASE_ADDRESS_MEM_MASK);
938 pci_read_config_word(agp_bridge->dev,I830_GMCH_CTRL,&gmch_ctrl);
939 gmch_ctrl |= I830_GMCH_ENABLED;
940 pci_write_config_word(agp_bridge->dev,I830_GMCH_CTRL,gmch_ctrl);
942 writel(agp_bridge->gatt_bus_addr|I810_PGETBL_ENABLED, intel_private.registers+I810_PGETBL_CTL);
943 readl(intel_private.registers+I810_PGETBL_CTL); /* PCI Posting. */
945 if (agp_bridge->driver->needs_scratch_page) {
946 for (i = intel_private.gtt_entries; i < current_size->num_entries; i++) {
947 writel(agp_bridge->scratch_page, intel_private.gtt+i);
948 readl(intel_private.gtt+i); /* PCI Posting. */
952 global_cache_flush();
954 intel_i9xx_setup_flush();
959 static void intel_i915_cleanup(void)
961 if (intel_private.i9xx_flush_page)
962 iounmap(intel_private.i9xx_flush_page);
963 if (intel_private.resource_valid)
964 release_resource(&intel_private.ifp_resource);
965 intel_private.ifp_resource.start = 0;
966 intel_private.resource_valid = 0;
967 iounmap(intel_private.gtt);
968 iounmap(intel_private.registers);
971 static void intel_i915_chipset_flush(struct agp_bridge_data *bridge)
973 if (intel_private.i9xx_flush_page)
974 writel(1, intel_private.i9xx_flush_page);
977 static int intel_i915_insert_entries(struct agp_memory *mem,off_t pg_start,
985 if (mem->page_count == 0)
988 temp = agp_bridge->current_size;
989 num_entries = A_SIZE_FIX(temp)->num_entries;
991 if (pg_start < intel_private.gtt_entries) {
992 printk (KERN_DEBUG PFX "pg_start == 0x%.8lx,intel_private.gtt_entries == 0x%.8x\n",
993 pg_start,intel_private.gtt_entries);
995 printk (KERN_INFO PFX "Trying to insert into local/stolen memory\n");
999 if ((pg_start + mem->page_count) > num_entries)
1002 /* The i915 can't check the GTT for entries since its read only,
1003 * depend on the caller to make the correct offset decisions.
1006 if (type != mem->type)
1009 mask_type = agp_bridge->driver->agp_type_to_mask_type(agp_bridge, type);
1011 if (mask_type != 0 && mask_type != AGP_PHYS_MEMORY &&
1012 mask_type != INTEL_AGP_CACHED_MEMORY)
1015 if (!mem->is_flushed)
1016 global_cache_flush();
1018 for (i = 0, j = pg_start; i < mem->page_count; i++, j++) {
1019 writel(agp_bridge->driver->mask_memory(agp_bridge,
1020 mem->memory[i], mask_type), intel_private.gtt+j);
1023 readl(intel_private.gtt+j-1);
1024 agp_bridge->driver->tlb_flush(mem);
1029 mem->is_flushed = 1;
1033 static int intel_i915_remove_entries(struct agp_memory *mem,off_t pg_start,
1038 if (mem->page_count == 0)
1041 if (pg_start < intel_private.gtt_entries) {
1042 printk (KERN_INFO PFX "Trying to disable local/stolen memory\n");
1046 for (i = pg_start; i < (mem->page_count + pg_start); i++) {
1047 writel(agp_bridge->scratch_page, intel_private.gtt+i);
1049 readl(intel_private.gtt+i-1);
1051 agp_bridge->driver->tlb_flush(mem);
1055 /* Return the aperture size by just checking the resource length. The effect
1056 * described in the spec of the MSAC registers is just changing of the
1059 static int intel_i9xx_fetch_size(void)
1061 int num_sizes = ARRAY_SIZE(intel_i830_sizes);
1062 int aper_size; /* size in megabytes */
1065 aper_size = pci_resource_len(intel_private.pcidev, 2) / MB(1);
1067 for (i = 0; i < num_sizes; i++) {
1068 if (aper_size == intel_i830_sizes[i].size) {
1069 agp_bridge->current_size = intel_i830_sizes + i;
1070 agp_bridge->previous_size = agp_bridge->current_size;
1078 /* The intel i915 automatically initializes the agp aperture during POST.
1079 * Use the memory already set aside for in the GTT.
1081 static int intel_i915_create_gatt_table(struct agp_bridge_data *bridge)
1084 struct aper_size_info_fixed *size;
1087 int gtt_map_size = 256 * 1024;
1089 size = agp_bridge->current_size;
1090 page_order = size->page_order;
1091 num_entries = size->num_entries;
1092 agp_bridge->gatt_table_real = NULL;
1094 pci_read_config_dword(intel_private.pcidev, I915_MMADDR, &temp);
1095 pci_read_config_dword(intel_private.pcidev, I915_PTEADDR,&temp2);
1098 gtt_map_size = 1024 * 1024; /* 1M on G33 */
1099 intel_private.gtt = ioremap(temp2, gtt_map_size);
1100 if (!intel_private.gtt)
1105 intel_private.registers = ioremap(temp,128 * 4096);
1106 if (!intel_private.registers) {
1107 iounmap(intel_private.gtt);
1111 temp = readl(intel_private.registers+I810_PGETBL_CTL) & 0xfffff000;
1112 global_cache_flush(); /* FIXME: ? */
1114 /* we have to call this as early as possible after the MMIO base address is known */
1115 intel_i830_init_gtt_entries();
1117 agp_bridge->gatt_table = NULL;
1119 agp_bridge->gatt_bus_addr = temp;
1125 * The i965 supports 36-bit physical addresses, but to keep
1126 * the format of the GTT the same, the bits that don't fit
1127 * in a 32-bit word are shifted down to bits 4..7.
1129 * Gcc is smart enough to notice that "(addr >> 28) & 0xf0"
1130 * is always zero on 32-bit architectures, so no need to make
1133 static unsigned long intel_i965_mask_memory(struct agp_bridge_data *bridge,
1134 unsigned long addr, int type)
1136 /* Shift high bits down */
1137 addr |= (addr >> 28) & 0xf0;
1139 /* Type checking must be done elsewhere */
1140 return addr | bridge->driver->masks[type].mask;
1143 /* The intel i965 automatically initializes the agp aperture during POST.
1144 * Use the memory already set aside for in the GTT.
1146 static int intel_i965_create_gatt_table(struct agp_bridge_data *bridge)
1149 struct aper_size_info_fixed *size;
1152 int gtt_offset, gtt_size;
1154 size = agp_bridge->current_size;
1155 page_order = size->page_order;
1156 num_entries = size->num_entries;
1157 agp_bridge->gatt_table_real = NULL;
1159 pci_read_config_dword(intel_private.pcidev, I915_MMADDR, &temp);
1163 if (agp_bridge->dev->device == PCI_DEVICE_ID_INTEL_IGD_HB)
1164 gtt_offset = gtt_size = MB(2);
1166 gtt_offset = gtt_size = KB(512);
1168 intel_private.gtt = ioremap((temp + gtt_offset) , gtt_size);
1170 if (!intel_private.gtt)
1173 intel_private.registers = ioremap(temp, 128 * 4096);
1174 if (!intel_private.registers) {
1175 iounmap(intel_private.gtt);
1179 temp = readl(intel_private.registers+I810_PGETBL_CTL) & 0xfffff000;
1180 global_cache_flush(); /* FIXME: ? */
1182 /* we have to call this as early as possible after the MMIO base address is known */
1183 intel_i830_init_gtt_entries();
1185 agp_bridge->gatt_table = NULL;
1187 agp_bridge->gatt_bus_addr = temp;
1193 static int intel_fetch_size(void)
1197 struct aper_size_info_16 *values;
1199 pci_read_config_word(agp_bridge->dev, INTEL_APSIZE, &temp);
1200 values = A_SIZE_16(agp_bridge->driver->aperture_sizes);
1202 for (i = 0; i < agp_bridge->driver->num_aperture_sizes; i++) {
1203 if (temp == values[i].size_value) {
1204 agp_bridge->previous_size = agp_bridge->current_size = (void *) (values + i);
1205 agp_bridge->aperture_size_idx = i;
1206 return values[i].size;
1213 static int __intel_8xx_fetch_size(u8 temp)
1216 struct aper_size_info_8 *values;
1218 values = A_SIZE_8(agp_bridge->driver->aperture_sizes);
1220 for (i = 0; i < agp_bridge->driver->num_aperture_sizes; i++) {
1221 if (temp == values[i].size_value) {
1222 agp_bridge->previous_size =
1223 agp_bridge->current_size = (void *) (values + i);
1224 agp_bridge->aperture_size_idx = i;
1225 return values[i].size;
1231 static int intel_8xx_fetch_size(void)
1235 pci_read_config_byte(agp_bridge->dev, INTEL_APSIZE, &temp);
1236 return __intel_8xx_fetch_size(temp);
1239 static int intel_815_fetch_size(void)
1243 /* Intel 815 chipsets have a _weird_ APSIZE register with only
1244 * one non-reserved bit, so mask the others out ... */
1245 pci_read_config_byte(agp_bridge->dev, INTEL_APSIZE, &temp);
1248 return __intel_8xx_fetch_size(temp);
1251 static void intel_tlbflush(struct agp_memory *mem)
1253 pci_write_config_dword(agp_bridge->dev, INTEL_AGPCTRL, 0x2200);
1254 pci_write_config_dword(agp_bridge->dev, INTEL_AGPCTRL, 0x2280);
1258 static void intel_8xx_tlbflush(struct agp_memory *mem)
1261 pci_read_config_dword(agp_bridge->dev, INTEL_AGPCTRL, &temp);
1262 pci_write_config_dword(agp_bridge->dev, INTEL_AGPCTRL, temp & ~(1 << 7));
1263 pci_read_config_dword(agp_bridge->dev, INTEL_AGPCTRL, &temp);
1264 pci_write_config_dword(agp_bridge->dev, INTEL_AGPCTRL, temp | (1 << 7));
1268 static void intel_cleanup(void)
1271 struct aper_size_info_16 *previous_size;
1273 previous_size = A_SIZE_16(agp_bridge->previous_size);
1274 pci_read_config_word(agp_bridge->dev, INTEL_NBXCFG, &temp);
1275 pci_write_config_word(agp_bridge->dev, INTEL_NBXCFG, temp & ~(1 << 9));
1276 pci_write_config_word(agp_bridge->dev, INTEL_APSIZE, previous_size->size_value);
1280 static void intel_8xx_cleanup(void)
1283 struct aper_size_info_8 *previous_size;
1285 previous_size = A_SIZE_8(agp_bridge->previous_size);
1286 pci_read_config_word(agp_bridge->dev, INTEL_NBXCFG, &temp);
1287 pci_write_config_word(agp_bridge->dev, INTEL_NBXCFG, temp & ~(1 << 9));
1288 pci_write_config_byte(agp_bridge->dev, INTEL_APSIZE, previous_size->size_value);
1292 static int intel_configure(void)
1296 struct aper_size_info_16 *current_size;
1298 current_size = A_SIZE_16(agp_bridge->current_size);
1301 pci_write_config_word(agp_bridge->dev, INTEL_APSIZE, current_size->size_value);
1303 /* address to map to */
1304 pci_read_config_dword(agp_bridge->dev, AGP_APBASE, &temp);
1305 agp_bridge->gart_bus_addr = (temp & PCI_BASE_ADDRESS_MEM_MASK);
1307 /* attbase - aperture base */
1308 pci_write_config_dword(agp_bridge->dev, INTEL_ATTBASE, agp_bridge->gatt_bus_addr);
1311 pci_write_config_dword(agp_bridge->dev, INTEL_AGPCTRL, 0x2280);
1314 pci_read_config_word(agp_bridge->dev, INTEL_NBXCFG, &temp2);
1315 pci_write_config_word(agp_bridge->dev, INTEL_NBXCFG,
1316 (temp2 & ~(1 << 10)) | (1 << 9));
1317 /* clear any possible error conditions */
1318 pci_write_config_byte(agp_bridge->dev, INTEL_ERRSTS + 1, 7);
1322 static int intel_815_configure(void)
1326 struct aper_size_info_8 *current_size;
1328 /* attbase - aperture base */
1329 /* the Intel 815 chipset spec. says that bits 29-31 in the
1330 * ATTBASE register are reserved -> try not to write them */
1331 if (agp_bridge->gatt_bus_addr & INTEL_815_ATTBASE_MASK) {
1332 printk (KERN_EMERG PFX "gatt bus addr too high");
1336 current_size = A_SIZE_8(agp_bridge->current_size);
1339 pci_write_config_byte(agp_bridge->dev, INTEL_APSIZE,
1340 current_size->size_value);
1342 /* address to map to */
1343 pci_read_config_dword(agp_bridge->dev, AGP_APBASE, &temp);
1344 agp_bridge->gart_bus_addr = (temp & PCI_BASE_ADDRESS_MEM_MASK);
1346 pci_read_config_dword(agp_bridge->dev, INTEL_ATTBASE, &addr);
1347 addr &= INTEL_815_ATTBASE_MASK;
1348 addr |= agp_bridge->gatt_bus_addr;
1349 pci_write_config_dword(agp_bridge->dev, INTEL_ATTBASE, addr);
1352 pci_write_config_dword(agp_bridge->dev, INTEL_AGPCTRL, 0x0000);
1355 pci_read_config_byte(agp_bridge->dev, INTEL_815_APCONT, &temp2);
1356 pci_write_config_byte(agp_bridge->dev, INTEL_815_APCONT, temp2 | (1 << 1));
1358 /* clear any possible error conditions */
1359 /* Oddness : this chipset seems to have no ERRSTS register ! */
1363 static void intel_820_tlbflush(struct agp_memory *mem)
1368 static void intel_820_cleanup(void)
1371 struct aper_size_info_8 *previous_size;
1373 previous_size = A_SIZE_8(agp_bridge->previous_size);
1374 pci_read_config_byte(agp_bridge->dev, INTEL_I820_RDCR, &temp);
1375 pci_write_config_byte(agp_bridge->dev, INTEL_I820_RDCR,
1377 pci_write_config_byte(agp_bridge->dev, INTEL_APSIZE,
1378 previous_size->size_value);
1382 static int intel_820_configure(void)
1386 struct aper_size_info_8 *current_size;
1388 current_size = A_SIZE_8(agp_bridge->current_size);
1391 pci_write_config_byte(agp_bridge->dev, INTEL_APSIZE, current_size->size_value);
1393 /* address to map to */
1394 pci_read_config_dword(agp_bridge->dev, AGP_APBASE, &temp);
1395 agp_bridge->gart_bus_addr = (temp & PCI_BASE_ADDRESS_MEM_MASK);
1397 /* attbase - aperture base */
1398 pci_write_config_dword(agp_bridge->dev, INTEL_ATTBASE, agp_bridge->gatt_bus_addr);
1401 pci_write_config_dword(agp_bridge->dev, INTEL_AGPCTRL, 0x0000);
1403 /* global enable aperture access */
1404 /* This flag is not accessed through MCHCFG register as in */
1406 pci_read_config_byte(agp_bridge->dev, INTEL_I820_RDCR, &temp2);
1407 pci_write_config_byte(agp_bridge->dev, INTEL_I820_RDCR, temp2 | (1 << 1));
1408 /* clear any possible AGP-related error conditions */
1409 pci_write_config_word(agp_bridge->dev, INTEL_I820_ERRSTS, 0x001c);
1413 static int intel_840_configure(void)
1417 struct aper_size_info_8 *current_size;
1419 current_size = A_SIZE_8(agp_bridge->current_size);
1422 pci_write_config_byte(agp_bridge->dev, INTEL_APSIZE, current_size->size_value);
1424 /* address to map to */
1425 pci_read_config_dword(agp_bridge->dev, AGP_APBASE, &temp);
1426 agp_bridge->gart_bus_addr = (temp & PCI_BASE_ADDRESS_MEM_MASK);
1428 /* attbase - aperture base */
1429 pci_write_config_dword(agp_bridge->dev, INTEL_ATTBASE, agp_bridge->gatt_bus_addr);
1432 pci_write_config_dword(agp_bridge->dev, INTEL_AGPCTRL, 0x0000);
1435 pci_read_config_word(agp_bridge->dev, INTEL_I840_MCHCFG, &temp2);
1436 pci_write_config_word(agp_bridge->dev, INTEL_I840_MCHCFG, temp2 | (1 << 9));
1437 /* clear any possible error conditions */
1438 pci_write_config_word(agp_bridge->dev, INTEL_I840_ERRSTS, 0xc000);
1442 static int intel_845_configure(void)
1446 struct aper_size_info_8 *current_size;
1448 current_size = A_SIZE_8(agp_bridge->current_size);
1451 pci_write_config_byte(agp_bridge->dev, INTEL_APSIZE, current_size->size_value);
1453 if (agp_bridge->apbase_config != 0) {
1454 pci_write_config_dword(agp_bridge->dev, AGP_APBASE,
1455 agp_bridge->apbase_config);
1457 /* address to map to */
1458 pci_read_config_dword(agp_bridge->dev, AGP_APBASE, &temp);
1459 agp_bridge->gart_bus_addr = (temp & PCI_BASE_ADDRESS_MEM_MASK);
1460 agp_bridge->apbase_config = temp;
1463 /* attbase - aperture base */
1464 pci_write_config_dword(agp_bridge->dev, INTEL_ATTBASE, agp_bridge->gatt_bus_addr);
1467 pci_write_config_dword(agp_bridge->dev, INTEL_AGPCTRL, 0x0000);
1470 pci_read_config_byte(agp_bridge->dev, INTEL_I845_AGPM, &temp2);
1471 pci_write_config_byte(agp_bridge->dev, INTEL_I845_AGPM, temp2 | (1 << 1));
1472 /* clear any possible error conditions */
1473 pci_write_config_word(agp_bridge->dev, INTEL_I845_ERRSTS, 0x001c);
1475 intel_i830_setup_flush();
1479 static int intel_850_configure(void)
1483 struct aper_size_info_8 *current_size;
1485 current_size = A_SIZE_8(agp_bridge->current_size);
1488 pci_write_config_byte(agp_bridge->dev, INTEL_APSIZE, current_size->size_value);
1490 /* address to map to */
1491 pci_read_config_dword(agp_bridge->dev, AGP_APBASE, &temp);
1492 agp_bridge->gart_bus_addr = (temp & PCI_BASE_ADDRESS_MEM_MASK);
1494 /* attbase - aperture base */
1495 pci_write_config_dword(agp_bridge->dev, INTEL_ATTBASE, agp_bridge->gatt_bus_addr);
1498 pci_write_config_dword(agp_bridge->dev, INTEL_AGPCTRL, 0x0000);
1501 pci_read_config_word(agp_bridge->dev, INTEL_I850_MCHCFG, &temp2);
1502 pci_write_config_word(agp_bridge->dev, INTEL_I850_MCHCFG, temp2 | (1 << 9));
1503 /* clear any possible AGP-related error conditions */
1504 pci_write_config_word(agp_bridge->dev, INTEL_I850_ERRSTS, 0x001c);
1508 static int intel_860_configure(void)
1512 struct aper_size_info_8 *current_size;
1514 current_size = A_SIZE_8(agp_bridge->current_size);
1517 pci_write_config_byte(agp_bridge->dev, INTEL_APSIZE, current_size->size_value);
1519 /* address to map to */
1520 pci_read_config_dword(agp_bridge->dev, AGP_APBASE, &temp);
1521 agp_bridge->gart_bus_addr = (temp & PCI_BASE_ADDRESS_MEM_MASK);
1523 /* attbase - aperture base */
1524 pci_write_config_dword(agp_bridge->dev, INTEL_ATTBASE, agp_bridge->gatt_bus_addr);
1527 pci_write_config_dword(agp_bridge->dev, INTEL_AGPCTRL, 0x0000);
1530 pci_read_config_word(agp_bridge->dev, INTEL_I860_MCHCFG, &temp2);
1531 pci_write_config_word(agp_bridge->dev, INTEL_I860_MCHCFG, temp2 | (1 << 9));
1532 /* clear any possible AGP-related error conditions */
1533 pci_write_config_word(agp_bridge->dev, INTEL_I860_ERRSTS, 0xf700);
1537 static int intel_830mp_configure(void)
1541 struct aper_size_info_8 *current_size;
1543 current_size = A_SIZE_8(agp_bridge->current_size);
1546 pci_write_config_byte(agp_bridge->dev, INTEL_APSIZE, current_size->size_value);
1548 /* address to map to */
1549 pci_read_config_dword(agp_bridge->dev, AGP_APBASE, &temp);
1550 agp_bridge->gart_bus_addr = (temp & PCI_BASE_ADDRESS_MEM_MASK);
1552 /* attbase - aperture base */
1553 pci_write_config_dword(agp_bridge->dev, INTEL_ATTBASE, agp_bridge->gatt_bus_addr);
1556 pci_write_config_dword(agp_bridge->dev, INTEL_AGPCTRL, 0x0000);
1559 pci_read_config_word(agp_bridge->dev, INTEL_NBXCFG, &temp2);
1560 pci_write_config_word(agp_bridge->dev, INTEL_NBXCFG, temp2 | (1 << 9));
1561 /* clear any possible AGP-related error conditions */
1562 pci_write_config_word(agp_bridge->dev, INTEL_I830_ERRSTS, 0x1c);
1566 static int intel_7505_configure(void)
1570 struct aper_size_info_8 *current_size;
1572 current_size = A_SIZE_8(agp_bridge->current_size);
1575 pci_write_config_byte(agp_bridge->dev, INTEL_APSIZE, current_size->size_value);
1577 /* address to map to */
1578 pci_read_config_dword(agp_bridge->dev, AGP_APBASE, &temp);
1579 agp_bridge->gart_bus_addr = (temp & PCI_BASE_ADDRESS_MEM_MASK);
1581 /* attbase - aperture base */
1582 pci_write_config_dword(agp_bridge->dev, INTEL_ATTBASE, agp_bridge->gatt_bus_addr);
1585 pci_write_config_dword(agp_bridge->dev, INTEL_AGPCTRL, 0x0000);
1588 pci_read_config_word(agp_bridge->dev, INTEL_I7505_MCHCFG, &temp2);
1589 pci_write_config_word(agp_bridge->dev, INTEL_I7505_MCHCFG, temp2 | (1 << 9));
1594 /* Setup function */
1595 static const struct gatt_mask intel_generic_masks[] =
1597 {.mask = 0x00000017, .type = 0}
1600 static const struct aper_size_info_8 intel_815_sizes[2] =
1606 static const struct aper_size_info_8 intel_8xx_sizes[7] =
1609 {128, 32768, 5, 32},
1617 static const struct aper_size_info_16 intel_generic_sizes[7] =
1620 {128, 32768, 5, 32},
1628 static const struct aper_size_info_8 intel_830mp_sizes[4] =
1631 {128, 32768, 5, 32},
1636 static const struct agp_bridge_driver intel_generic_driver = {
1637 .owner = THIS_MODULE,
1638 .aperture_sizes = intel_generic_sizes,
1639 .size_type = U16_APER_SIZE,
1640 .num_aperture_sizes = 7,
1641 .configure = intel_configure,
1642 .fetch_size = intel_fetch_size,
1643 .cleanup = intel_cleanup,
1644 .tlb_flush = intel_tlbflush,
1645 .mask_memory = agp_generic_mask_memory,
1646 .masks = intel_generic_masks,
1647 .agp_enable = agp_generic_enable,
1648 .cache_flush = global_cache_flush,
1649 .create_gatt_table = agp_generic_create_gatt_table,
1650 .free_gatt_table = agp_generic_free_gatt_table,
1651 .insert_memory = agp_generic_insert_memory,
1652 .remove_memory = agp_generic_remove_memory,
1653 .alloc_by_type = agp_generic_alloc_by_type,
1654 .free_by_type = agp_generic_free_by_type,
1655 .agp_alloc_page = agp_generic_alloc_page,
1656 .agp_destroy_page = agp_generic_destroy_page,
1657 .agp_type_to_mask_type = agp_generic_type_to_mask_type,
1660 static const struct agp_bridge_driver intel_810_driver = {
1661 .owner = THIS_MODULE,
1662 .aperture_sizes = intel_i810_sizes,
1663 .size_type = FIXED_APER_SIZE,
1664 .num_aperture_sizes = 2,
1665 .needs_scratch_page = TRUE,
1666 .configure = intel_i810_configure,
1667 .fetch_size = intel_i810_fetch_size,
1668 .cleanup = intel_i810_cleanup,
1669 .tlb_flush = intel_i810_tlbflush,
1670 .mask_memory = intel_i810_mask_memory,
1671 .masks = intel_i810_masks,
1672 .agp_enable = intel_i810_agp_enable,
1673 .cache_flush = global_cache_flush,
1674 .create_gatt_table = agp_generic_create_gatt_table,
1675 .free_gatt_table = agp_generic_free_gatt_table,
1676 .insert_memory = intel_i810_insert_entries,
1677 .remove_memory = intel_i810_remove_entries,
1678 .alloc_by_type = intel_i810_alloc_by_type,
1679 .free_by_type = intel_i810_free_by_type,
1680 .agp_alloc_page = agp_generic_alloc_page,
1681 .agp_destroy_page = agp_generic_destroy_page,
1682 .agp_type_to_mask_type = agp_generic_type_to_mask_type,
1685 static const struct agp_bridge_driver intel_815_driver = {
1686 .owner = THIS_MODULE,
1687 .aperture_sizes = intel_815_sizes,
1688 .size_type = U8_APER_SIZE,
1689 .num_aperture_sizes = 2,
1690 .configure = intel_815_configure,
1691 .fetch_size = intel_815_fetch_size,
1692 .cleanup = intel_8xx_cleanup,
1693 .tlb_flush = intel_8xx_tlbflush,
1694 .mask_memory = agp_generic_mask_memory,
1695 .masks = intel_generic_masks,
1696 .agp_enable = agp_generic_enable,
1697 .cache_flush = global_cache_flush,
1698 .create_gatt_table = agp_generic_create_gatt_table,
1699 .free_gatt_table = agp_generic_free_gatt_table,
1700 .insert_memory = agp_generic_insert_memory,
1701 .remove_memory = agp_generic_remove_memory,
1702 .alloc_by_type = agp_generic_alloc_by_type,
1703 .free_by_type = agp_generic_free_by_type,
1704 .agp_alloc_page = agp_generic_alloc_page,
1705 .agp_destroy_page = agp_generic_destroy_page,
1706 .agp_type_to_mask_type = agp_generic_type_to_mask_type,
1709 static const struct agp_bridge_driver intel_830_driver = {
1710 .owner = THIS_MODULE,
1711 .aperture_sizes = intel_i830_sizes,
1712 .size_type = FIXED_APER_SIZE,
1713 .num_aperture_sizes = 4,
1714 .needs_scratch_page = TRUE,
1715 .configure = intel_i830_configure,
1716 .fetch_size = intel_i830_fetch_size,
1717 .cleanup = intel_i830_cleanup,
1718 .tlb_flush = intel_i810_tlbflush,
1719 .mask_memory = intel_i810_mask_memory,
1720 .masks = intel_i810_masks,
1721 .agp_enable = intel_i810_agp_enable,
1722 .cache_flush = global_cache_flush,
1723 .create_gatt_table = intel_i830_create_gatt_table,
1724 .free_gatt_table = intel_i830_free_gatt_table,
1725 .insert_memory = intel_i830_insert_entries,
1726 .remove_memory = intel_i830_remove_entries,
1727 .alloc_by_type = intel_i830_alloc_by_type,
1728 .free_by_type = intel_i810_free_by_type,
1729 .agp_alloc_page = agp_generic_alloc_page,
1730 .agp_destroy_page = agp_generic_destroy_page,
1731 .agp_type_to_mask_type = intel_i830_type_to_mask_type,
1732 .chipset_flush = intel_i830_chipset_flush,
1735 static const struct agp_bridge_driver intel_820_driver = {
1736 .owner = THIS_MODULE,
1737 .aperture_sizes = intel_8xx_sizes,
1738 .size_type = U8_APER_SIZE,
1739 .num_aperture_sizes = 7,
1740 .configure = intel_820_configure,
1741 .fetch_size = intel_8xx_fetch_size,
1742 .cleanup = intel_820_cleanup,
1743 .tlb_flush = intel_820_tlbflush,
1744 .mask_memory = agp_generic_mask_memory,
1745 .masks = intel_generic_masks,
1746 .agp_enable = agp_generic_enable,
1747 .cache_flush = global_cache_flush,
1748 .create_gatt_table = agp_generic_create_gatt_table,
1749 .free_gatt_table = agp_generic_free_gatt_table,
1750 .insert_memory = agp_generic_insert_memory,
1751 .remove_memory = agp_generic_remove_memory,
1752 .alloc_by_type = agp_generic_alloc_by_type,
1753 .free_by_type = agp_generic_free_by_type,
1754 .agp_alloc_page = agp_generic_alloc_page,
1755 .agp_destroy_page = agp_generic_destroy_page,
1756 .agp_type_to_mask_type = agp_generic_type_to_mask_type,
1759 static const struct agp_bridge_driver intel_830mp_driver = {
1760 .owner = THIS_MODULE,
1761 .aperture_sizes = intel_830mp_sizes,
1762 .size_type = U8_APER_SIZE,
1763 .num_aperture_sizes = 4,
1764 .configure = intel_830mp_configure,
1765 .fetch_size = intel_8xx_fetch_size,
1766 .cleanup = intel_8xx_cleanup,
1767 .tlb_flush = intel_8xx_tlbflush,
1768 .mask_memory = agp_generic_mask_memory,
1769 .masks = intel_generic_masks,
1770 .agp_enable = agp_generic_enable,
1771 .cache_flush = global_cache_flush,
1772 .create_gatt_table = agp_generic_create_gatt_table,
1773 .free_gatt_table = agp_generic_free_gatt_table,
1774 .insert_memory = agp_generic_insert_memory,
1775 .remove_memory = agp_generic_remove_memory,
1776 .alloc_by_type = agp_generic_alloc_by_type,
1777 .free_by_type = agp_generic_free_by_type,
1778 .agp_alloc_page = agp_generic_alloc_page,
1779 .agp_destroy_page = agp_generic_destroy_page,
1780 .agp_type_to_mask_type = agp_generic_type_to_mask_type,
1783 static const struct agp_bridge_driver intel_840_driver = {
1784 .owner = THIS_MODULE,
1785 .aperture_sizes = intel_8xx_sizes,
1786 .size_type = U8_APER_SIZE,
1787 .num_aperture_sizes = 7,
1788 .configure = intel_840_configure,
1789 .fetch_size = intel_8xx_fetch_size,
1790 .cleanup = intel_8xx_cleanup,
1791 .tlb_flush = intel_8xx_tlbflush,
1792 .mask_memory = agp_generic_mask_memory,
1793 .masks = intel_generic_masks,
1794 .agp_enable = agp_generic_enable,
1795 .cache_flush = global_cache_flush,
1796 .create_gatt_table = agp_generic_create_gatt_table,
1797 .free_gatt_table = agp_generic_free_gatt_table,
1798 .insert_memory = agp_generic_insert_memory,
1799 .remove_memory = agp_generic_remove_memory,
1800 .alloc_by_type = agp_generic_alloc_by_type,
1801 .free_by_type = agp_generic_free_by_type,
1802 .agp_alloc_page = agp_generic_alloc_page,
1803 .agp_destroy_page = agp_generic_destroy_page,
1804 .agp_type_to_mask_type = agp_generic_type_to_mask_type,
1807 static const struct agp_bridge_driver intel_845_driver = {
1808 .owner = THIS_MODULE,
1809 .aperture_sizes = intel_8xx_sizes,
1810 .size_type = U8_APER_SIZE,
1811 .num_aperture_sizes = 7,
1812 .configure = intel_845_configure,
1813 .fetch_size = intel_8xx_fetch_size,
1814 .cleanup = intel_8xx_cleanup,
1815 .tlb_flush = intel_8xx_tlbflush,
1816 .mask_memory = agp_generic_mask_memory,
1817 .masks = intel_generic_masks,
1818 .agp_enable = agp_generic_enable,
1819 .cache_flush = global_cache_flush,
1820 .create_gatt_table = agp_generic_create_gatt_table,
1821 .free_gatt_table = agp_generic_free_gatt_table,
1822 .insert_memory = agp_generic_insert_memory,
1823 .remove_memory = agp_generic_remove_memory,
1824 .alloc_by_type = agp_generic_alloc_by_type,
1825 .free_by_type = agp_generic_free_by_type,
1826 .agp_alloc_page = agp_generic_alloc_page,
1827 .agp_destroy_page = agp_generic_destroy_page,
1828 .agp_type_to_mask_type = agp_generic_type_to_mask_type,
1829 .chipset_flush = intel_i830_chipset_flush,
1832 static const struct agp_bridge_driver intel_850_driver = {
1833 .owner = THIS_MODULE,
1834 .aperture_sizes = intel_8xx_sizes,
1835 .size_type = U8_APER_SIZE,
1836 .num_aperture_sizes = 7,
1837 .configure = intel_850_configure,
1838 .fetch_size = intel_8xx_fetch_size,
1839 .cleanup = intel_8xx_cleanup,
1840 .tlb_flush = intel_8xx_tlbflush,
1841 .mask_memory = agp_generic_mask_memory,
1842 .masks = intel_generic_masks,
1843 .agp_enable = agp_generic_enable,
1844 .cache_flush = global_cache_flush,
1845 .create_gatt_table = agp_generic_create_gatt_table,
1846 .free_gatt_table = agp_generic_free_gatt_table,
1847 .insert_memory = agp_generic_insert_memory,
1848 .remove_memory = agp_generic_remove_memory,
1849 .alloc_by_type = agp_generic_alloc_by_type,
1850 .free_by_type = agp_generic_free_by_type,
1851 .agp_alloc_page = agp_generic_alloc_page,
1852 .agp_destroy_page = agp_generic_destroy_page,
1853 .agp_type_to_mask_type = agp_generic_type_to_mask_type,
1856 static const struct agp_bridge_driver intel_860_driver = {
1857 .owner = THIS_MODULE,
1858 .aperture_sizes = intel_8xx_sizes,
1859 .size_type = U8_APER_SIZE,
1860 .num_aperture_sizes = 7,
1861 .configure = intel_860_configure,
1862 .fetch_size = intel_8xx_fetch_size,
1863 .cleanup = intel_8xx_cleanup,
1864 .tlb_flush = intel_8xx_tlbflush,
1865 .mask_memory = agp_generic_mask_memory,
1866 .masks = intel_generic_masks,
1867 .agp_enable = agp_generic_enable,
1868 .cache_flush = global_cache_flush,
1869 .create_gatt_table = agp_generic_create_gatt_table,
1870 .free_gatt_table = agp_generic_free_gatt_table,
1871 .insert_memory = agp_generic_insert_memory,
1872 .remove_memory = agp_generic_remove_memory,
1873 .alloc_by_type = agp_generic_alloc_by_type,
1874 .free_by_type = agp_generic_free_by_type,
1875 .agp_alloc_page = agp_generic_alloc_page,
1876 .agp_destroy_page = agp_generic_destroy_page,
1877 .agp_type_to_mask_type = agp_generic_type_to_mask_type,
1880 static const struct agp_bridge_driver intel_915_driver = {
1881 .owner = THIS_MODULE,
1882 .aperture_sizes = intel_i830_sizes,
1883 .size_type = FIXED_APER_SIZE,
1884 .num_aperture_sizes = 4,
1885 .needs_scratch_page = TRUE,
1886 .configure = intel_i915_configure,
1887 .fetch_size = intel_i9xx_fetch_size,
1888 .cleanup = intel_i915_cleanup,
1889 .tlb_flush = intel_i810_tlbflush,
1890 .mask_memory = intel_i810_mask_memory,
1891 .masks = intel_i810_masks,
1892 .agp_enable = intel_i810_agp_enable,
1893 .cache_flush = global_cache_flush,
1894 .create_gatt_table = intel_i915_create_gatt_table,
1895 .free_gatt_table = intel_i830_free_gatt_table,
1896 .insert_memory = intel_i915_insert_entries,
1897 .remove_memory = intel_i915_remove_entries,
1898 .alloc_by_type = intel_i830_alloc_by_type,
1899 .free_by_type = intel_i810_free_by_type,
1900 .agp_alloc_page = agp_generic_alloc_page,
1901 .agp_destroy_page = agp_generic_destroy_page,
1902 .agp_type_to_mask_type = intel_i830_type_to_mask_type,
1903 .chipset_flush = intel_i915_chipset_flush,
1906 static const struct agp_bridge_driver intel_i965_driver = {
1907 .owner = THIS_MODULE,
1908 .aperture_sizes = intel_i830_sizes,
1909 .size_type = FIXED_APER_SIZE,
1910 .num_aperture_sizes = 4,
1911 .needs_scratch_page = TRUE,
1912 .configure = intel_i915_configure,
1913 .fetch_size = intel_i9xx_fetch_size,
1914 .cleanup = intel_i915_cleanup,
1915 .tlb_flush = intel_i810_tlbflush,
1916 .mask_memory = intel_i965_mask_memory,
1917 .masks = intel_i810_masks,
1918 .agp_enable = intel_i810_agp_enable,
1919 .cache_flush = global_cache_flush,
1920 .create_gatt_table = intel_i965_create_gatt_table,
1921 .free_gatt_table = intel_i830_free_gatt_table,
1922 .insert_memory = intel_i915_insert_entries,
1923 .remove_memory = intel_i915_remove_entries,
1924 .alloc_by_type = intel_i830_alloc_by_type,
1925 .free_by_type = intel_i810_free_by_type,
1926 .agp_alloc_page = agp_generic_alloc_page,
1927 .agp_destroy_page = agp_generic_destroy_page,
1928 .agp_type_to_mask_type = intel_i830_type_to_mask_type,
1929 .chipset_flush = intel_i915_chipset_flush,
1932 static const struct agp_bridge_driver intel_7505_driver = {
1933 .owner = THIS_MODULE,
1934 .aperture_sizes = intel_8xx_sizes,
1935 .size_type = U8_APER_SIZE,
1936 .num_aperture_sizes = 7,
1937 .configure = intel_7505_configure,
1938 .fetch_size = intel_8xx_fetch_size,
1939 .cleanup = intel_8xx_cleanup,
1940 .tlb_flush = intel_8xx_tlbflush,
1941 .mask_memory = agp_generic_mask_memory,
1942 .masks = intel_generic_masks,
1943 .agp_enable = agp_generic_enable,
1944 .cache_flush = global_cache_flush,
1945 .create_gatt_table = agp_generic_create_gatt_table,
1946 .free_gatt_table = agp_generic_free_gatt_table,
1947 .insert_memory = agp_generic_insert_memory,
1948 .remove_memory = agp_generic_remove_memory,
1949 .alloc_by_type = agp_generic_alloc_by_type,
1950 .free_by_type = agp_generic_free_by_type,
1951 .agp_alloc_page = agp_generic_alloc_page,
1952 .agp_destroy_page = agp_generic_destroy_page,
1953 .agp_type_to_mask_type = agp_generic_type_to_mask_type,
1956 static const struct agp_bridge_driver intel_g33_driver = {
1957 .owner = THIS_MODULE,
1958 .aperture_sizes = intel_i830_sizes,
1959 .size_type = FIXED_APER_SIZE,
1960 .num_aperture_sizes = 4,
1961 .needs_scratch_page = TRUE,
1962 .configure = intel_i915_configure,
1963 .fetch_size = intel_i9xx_fetch_size,
1964 .cleanup = intel_i915_cleanup,
1965 .tlb_flush = intel_i810_tlbflush,
1966 .mask_memory = intel_i965_mask_memory,
1967 .masks = intel_i810_masks,
1968 .agp_enable = intel_i810_agp_enable,
1969 .cache_flush = global_cache_flush,
1970 .create_gatt_table = intel_i915_create_gatt_table,
1971 .free_gatt_table = intel_i830_free_gatt_table,
1972 .insert_memory = intel_i915_insert_entries,
1973 .remove_memory = intel_i915_remove_entries,
1974 .alloc_by_type = intel_i830_alloc_by_type,
1975 .free_by_type = intel_i810_free_by_type,
1976 .agp_alloc_page = agp_generic_alloc_page,
1977 .agp_destroy_page = agp_generic_destroy_page,
1978 .agp_type_to_mask_type = intel_i830_type_to_mask_type,
1979 .chipset_flush = intel_i915_chipset_flush,
1982 static int find_gmch(u16 device)
1984 struct pci_dev *gmch_device;
1986 gmch_device = pci_get_device(PCI_VENDOR_ID_INTEL, device, NULL);
1987 if (gmch_device && PCI_FUNC(gmch_device->devfn) != 0) {
1988 gmch_device = pci_get_device(PCI_VENDOR_ID_INTEL,
1989 device, gmch_device);
1995 intel_private.pcidev = gmch_device;
1999 /* Table to describe Intel GMCH and AGP/PCIE GART drivers. At least one of
2000 * driver and gmch_driver must be non-null, and find_gmch will determine
2001 * which one should be used if a gmch_chip_id is present.
2003 static const struct intel_driver_description {
2004 unsigned int chip_id;
2005 unsigned int gmch_chip_id;
2006 unsigned int multi_gmch_chip; /* if we have more gfx chip type on this HB. */
2008 const struct agp_bridge_driver *driver;
2009 const struct agp_bridge_driver *gmch_driver;
2010 } intel_agp_chipsets[] = {
2011 { PCI_DEVICE_ID_INTEL_82443LX_0, 0, 0, "440LX", &intel_generic_driver, NULL },
2012 { PCI_DEVICE_ID_INTEL_82443BX_0, 0, 0, "440BX", &intel_generic_driver, NULL },
2013 { PCI_DEVICE_ID_INTEL_82443GX_0, 0, 0, "440GX", &intel_generic_driver, NULL },
2014 { PCI_DEVICE_ID_INTEL_82810_MC1, PCI_DEVICE_ID_INTEL_82810_IG1, 0, "i810",
2015 NULL, &intel_810_driver },
2016 { PCI_DEVICE_ID_INTEL_82810_MC3, PCI_DEVICE_ID_INTEL_82810_IG3, 0, "i810",
2017 NULL, &intel_810_driver },
2018 { PCI_DEVICE_ID_INTEL_82810E_MC, PCI_DEVICE_ID_INTEL_82810E_IG, 0, "i810",
2019 NULL, &intel_810_driver },
2020 { PCI_DEVICE_ID_INTEL_82815_MC, PCI_DEVICE_ID_INTEL_82815_CGC, 0, "i815",
2021 &intel_815_driver, &intel_810_driver },
2022 { PCI_DEVICE_ID_INTEL_82820_HB, 0, 0, "i820", &intel_820_driver, NULL },
2023 { PCI_DEVICE_ID_INTEL_82820_UP_HB, 0, 0, "i820", &intel_820_driver, NULL },
2024 { PCI_DEVICE_ID_INTEL_82830_HB, PCI_DEVICE_ID_INTEL_82830_CGC, 0, "830M",
2025 &intel_830mp_driver, &intel_830_driver },
2026 { PCI_DEVICE_ID_INTEL_82840_HB, 0, 0, "i840", &intel_840_driver, NULL },
2027 { PCI_DEVICE_ID_INTEL_82845_HB, 0, 0, "845G", &intel_845_driver, NULL },
2028 { PCI_DEVICE_ID_INTEL_82845G_HB, PCI_DEVICE_ID_INTEL_82845G_IG, 0, "830M",
2029 &intel_845_driver, &intel_830_driver },
2030 { PCI_DEVICE_ID_INTEL_82850_HB, 0, 0, "i850", &intel_850_driver, NULL },
2031 { PCI_DEVICE_ID_INTEL_82855PM_HB, 0, 0, "855PM", &intel_845_driver, NULL },
2032 { PCI_DEVICE_ID_INTEL_82855GM_HB, PCI_DEVICE_ID_INTEL_82855GM_IG, 0, "855GM",
2033 &intel_845_driver, &intel_830_driver },
2034 { PCI_DEVICE_ID_INTEL_82860_HB, 0, 0, "i860", &intel_860_driver, NULL },
2035 { PCI_DEVICE_ID_INTEL_82865_HB, PCI_DEVICE_ID_INTEL_82865_IG, 0, "865",
2036 &intel_845_driver, &intel_830_driver },
2037 { PCI_DEVICE_ID_INTEL_82875_HB, 0, 0, "i875", &intel_845_driver, NULL },
2038 { PCI_DEVICE_ID_INTEL_E7221_HB, PCI_DEVICE_ID_INTEL_E7221_IG, 0, "E7221 (i915)",
2039 NULL, &intel_915_driver },
2040 { PCI_DEVICE_ID_INTEL_82915G_HB, PCI_DEVICE_ID_INTEL_82915G_IG, 0, "915G",
2041 NULL, &intel_915_driver },
2042 { PCI_DEVICE_ID_INTEL_82915GM_HB, PCI_DEVICE_ID_INTEL_82915GM_IG, 0, "915GM",
2043 NULL, &intel_915_driver },
2044 { PCI_DEVICE_ID_INTEL_82945G_HB, PCI_DEVICE_ID_INTEL_82945G_IG, 0, "945G",
2045 NULL, &intel_915_driver },
2046 { PCI_DEVICE_ID_INTEL_82945GM_HB, PCI_DEVICE_ID_INTEL_82945GM_IG, 0, "945GM",
2047 NULL, &intel_915_driver },
2048 { PCI_DEVICE_ID_INTEL_82945GME_HB, PCI_DEVICE_ID_INTEL_82945GME_IG, 0, "945GME",
2049 NULL, &intel_915_driver },
2050 { PCI_DEVICE_ID_INTEL_82946GZ_HB, PCI_DEVICE_ID_INTEL_82946GZ_IG, 0, "946GZ",
2051 NULL, &intel_i965_driver },
2052 { PCI_DEVICE_ID_INTEL_82965G_1_HB, PCI_DEVICE_ID_INTEL_82965G_1_IG, 0, "965G",
2053 NULL, &intel_i965_driver },
2054 { PCI_DEVICE_ID_INTEL_82965Q_HB, PCI_DEVICE_ID_INTEL_82965Q_IG, 0, "965Q",
2055 NULL, &intel_i965_driver },
2056 { PCI_DEVICE_ID_INTEL_82965G_HB, PCI_DEVICE_ID_INTEL_82965G_IG, 0, "965G",
2057 NULL, &intel_i965_driver },
2058 { PCI_DEVICE_ID_INTEL_82965GM_HB, PCI_DEVICE_ID_INTEL_82965GM_IG, 0, "965GM",
2059 NULL, &intel_i965_driver },
2060 { PCI_DEVICE_ID_INTEL_82965GME_HB, PCI_DEVICE_ID_INTEL_82965GME_IG, 0, "965GME/GLE",
2061 NULL, &intel_i965_driver },
2062 { PCI_DEVICE_ID_INTEL_7505_0, 0, 0, "E7505", &intel_7505_driver, NULL },
2063 { PCI_DEVICE_ID_INTEL_7205_0, 0, 0, "E7205", &intel_7505_driver, NULL },
2064 { PCI_DEVICE_ID_INTEL_G33_HB, PCI_DEVICE_ID_INTEL_G33_IG, 0, "G33",
2065 NULL, &intel_g33_driver },
2066 { PCI_DEVICE_ID_INTEL_Q35_HB, PCI_DEVICE_ID_INTEL_Q35_IG, 0, "Q35",
2067 NULL, &intel_g33_driver },
2068 { PCI_DEVICE_ID_INTEL_Q33_HB, PCI_DEVICE_ID_INTEL_Q33_IG, 0, "Q33",
2069 NULL, &intel_g33_driver },
2070 { PCI_DEVICE_ID_INTEL_IGD_HB, PCI_DEVICE_ID_INTEL_IGD_IG, 0,
2071 "Intel Integrated Graphics Device", NULL, &intel_i965_driver },
2072 { 0, 0, 0, NULL, NULL, NULL }
2075 static int __devinit agp_intel_probe(struct pci_dev *pdev,
2076 const struct pci_device_id *ent)
2078 struct agp_bridge_data *bridge;
2083 cap_ptr = pci_find_capability(pdev, PCI_CAP_ID_AGP);
2085 bridge = agp_alloc_bridge();
2089 for (i = 0; intel_agp_chipsets[i].name != NULL; i++) {
2090 /* In case that multiple models of gfx chip may
2091 stand on same host bridge type, this can be
2092 sure we detect the right IGD. */
2093 if (pdev->device == intel_agp_chipsets[i].chip_id) {
2094 if ((intel_agp_chipsets[i].gmch_chip_id != 0) &&
2095 find_gmch(intel_agp_chipsets[i].gmch_chip_id)) {
2097 intel_agp_chipsets[i].gmch_driver;
2099 } else if (intel_agp_chipsets[i].multi_gmch_chip) {
2102 bridge->driver = intel_agp_chipsets[i].driver;
2108 if (intel_agp_chipsets[i].name == NULL) {
2110 printk(KERN_WARNING PFX "Unsupported Intel chipset"
2111 "(device id: %04x)\n", pdev->device);
2112 agp_put_bridge(bridge);
2116 if (bridge->driver == NULL) {
2117 /* bridge has no AGP and no IGD detected */
2119 printk(KERN_WARNING PFX "Failed to find bridge device "
2120 "(chip_id: %04x)\n",
2121 intel_agp_chipsets[i].gmch_chip_id);
2122 agp_put_bridge(bridge);
2127 bridge->capndx = cap_ptr;
2128 bridge->dev_private_data = &intel_private;
2130 printk(KERN_INFO PFX "Detected an Intel %s Chipset.\n",
2131 intel_agp_chipsets[i].name);
2134 * The following fixes the case where the BIOS has "forgotten" to
2135 * provide an address range for the GART.
2136 * 20030610 - hamish@zot.org
2138 r = &pdev->resource[0];
2139 if (!r->start && r->end) {
2140 if (pci_assign_resource(pdev, 0)) {
2141 printk(KERN_ERR PFX "could not assign resource 0\n");
2142 agp_put_bridge(bridge);
2148 * If the device has not been properly setup, the following will catch
2149 * the problem and should stop the system from crashing.
2150 * 20030610 - hamish@zot.org
2152 if (pci_enable_device(pdev)) {
2153 printk(KERN_ERR PFX "Unable to Enable PCI device\n");
2154 agp_put_bridge(bridge);
2158 /* Fill in the mode register */
2160 pci_read_config_dword(pdev,
2161 bridge->capndx+PCI_AGP_STATUS,
2165 pci_set_drvdata(pdev, bridge);
2166 return agp_add_bridge(bridge);
2169 static void __devexit agp_intel_remove(struct pci_dev *pdev)
2171 struct agp_bridge_data *bridge = pci_get_drvdata(pdev);
2173 agp_remove_bridge(bridge);
2175 if (intel_private.pcidev)
2176 pci_dev_put(intel_private.pcidev);
2178 agp_put_bridge(bridge);
2182 static int agp_intel_resume(struct pci_dev *pdev)
2184 struct agp_bridge_data *bridge = pci_get_drvdata(pdev);
2186 pci_restore_state(pdev);
2188 /* We should restore our graphics device's config space,
2189 * as host bridge (00:00) resumes before graphics device (02:00),
2190 * then our access to its pci space can work right.
2192 if (intel_private.pcidev)
2193 pci_restore_state(intel_private.pcidev);
2195 if (bridge->driver == &intel_generic_driver)
2197 else if (bridge->driver == &intel_850_driver)
2198 intel_850_configure();
2199 else if (bridge->driver == &intel_845_driver)
2200 intel_845_configure();
2201 else if (bridge->driver == &intel_830mp_driver)
2202 intel_830mp_configure();
2203 else if (bridge->driver == &intel_915_driver)
2204 intel_i915_configure();
2205 else if (bridge->driver == &intel_830_driver)
2206 intel_i830_configure();
2207 else if (bridge->driver == &intel_810_driver)
2208 intel_i810_configure();
2209 else if (bridge->driver == &intel_i965_driver)
2210 intel_i915_configure();
2216 static struct pci_device_id agp_intel_pci_table[] = {
2219 .class = (PCI_CLASS_BRIDGE_HOST << 8), \
2221 .vendor = PCI_VENDOR_ID_INTEL, \
2223 .subvendor = PCI_ANY_ID, \
2224 .subdevice = PCI_ANY_ID, \
2226 ID(PCI_DEVICE_ID_INTEL_82443LX_0),
2227 ID(PCI_DEVICE_ID_INTEL_82443BX_0),
2228 ID(PCI_DEVICE_ID_INTEL_82443GX_0),
2229 ID(PCI_DEVICE_ID_INTEL_82810_MC1),
2230 ID(PCI_DEVICE_ID_INTEL_82810_MC3),
2231 ID(PCI_DEVICE_ID_INTEL_82810E_MC),
2232 ID(PCI_DEVICE_ID_INTEL_82815_MC),
2233 ID(PCI_DEVICE_ID_INTEL_82820_HB),
2234 ID(PCI_DEVICE_ID_INTEL_82820_UP_HB),
2235 ID(PCI_DEVICE_ID_INTEL_82830_HB),
2236 ID(PCI_DEVICE_ID_INTEL_82840_HB),
2237 ID(PCI_DEVICE_ID_INTEL_82845_HB),
2238 ID(PCI_DEVICE_ID_INTEL_82845G_HB),
2239 ID(PCI_DEVICE_ID_INTEL_82850_HB),
2240 ID(PCI_DEVICE_ID_INTEL_82855PM_HB),
2241 ID(PCI_DEVICE_ID_INTEL_82855GM_HB),
2242 ID(PCI_DEVICE_ID_INTEL_82860_HB),
2243 ID(PCI_DEVICE_ID_INTEL_82865_HB),
2244 ID(PCI_DEVICE_ID_INTEL_82875_HB),
2245 ID(PCI_DEVICE_ID_INTEL_7505_0),
2246 ID(PCI_DEVICE_ID_INTEL_7205_0),
2247 ID(PCI_DEVICE_ID_INTEL_E7221_HB),
2248 ID(PCI_DEVICE_ID_INTEL_82915G_HB),
2249 ID(PCI_DEVICE_ID_INTEL_82915GM_HB),
2250 ID(PCI_DEVICE_ID_INTEL_82945G_HB),
2251 ID(PCI_DEVICE_ID_INTEL_82945GM_HB),
2252 ID(PCI_DEVICE_ID_INTEL_82945GME_HB),
2253 ID(PCI_DEVICE_ID_INTEL_82946GZ_HB),
2254 ID(PCI_DEVICE_ID_INTEL_82965G_1_HB),
2255 ID(PCI_DEVICE_ID_INTEL_82965Q_HB),
2256 ID(PCI_DEVICE_ID_INTEL_82965G_HB),
2257 ID(PCI_DEVICE_ID_INTEL_82965GM_HB),
2258 ID(PCI_DEVICE_ID_INTEL_82965GME_HB),
2259 ID(PCI_DEVICE_ID_INTEL_G33_HB),
2260 ID(PCI_DEVICE_ID_INTEL_Q35_HB),
2261 ID(PCI_DEVICE_ID_INTEL_Q33_HB),
2262 ID(PCI_DEVICE_ID_INTEL_IGD_HB),
2266 MODULE_DEVICE_TABLE(pci, agp_intel_pci_table);
2268 static struct pci_driver agp_intel_pci_driver = {
2269 .name = "agpgart-intel",
2270 .id_table = agp_intel_pci_table,
2271 .probe = agp_intel_probe,
2272 .remove = __devexit_p(agp_intel_remove),
2274 .resume = agp_intel_resume,
2278 static int __init agp_intel_init(void)
2282 return pci_register_driver(&agp_intel_pci_driver);
2285 static void __exit agp_intel_cleanup(void)
2287 pci_unregister_driver(&agp_intel_pci_driver);
2290 module_init(agp_intel_init);
2291 module_exit(agp_intel_cleanup);
2293 MODULE_AUTHOR("Dave Jones <davej@codemonkey.org.uk>");
2294 MODULE_LICENSE("GPL and additional rights");