2 * Intel AGPGART routines.
5 #include <linux/module.h>
7 #include <linux/init.h>
8 #include <linux/kernel.h>
9 #include <linux/pagemap.h>
10 #include <linux/agp_backend.h>
13 #define PCI_DEVICE_ID_INTEL_E7221_HB 0x2588
14 #define PCI_DEVICE_ID_INTEL_E7221_IG 0x258a
15 #define PCI_DEVICE_ID_INTEL_82946GZ_HB 0x2970
16 #define PCI_DEVICE_ID_INTEL_82946GZ_IG 0x2972
17 #define PCI_DEVICE_ID_INTEL_82965G_1_HB 0x2980
18 #define PCI_DEVICE_ID_INTEL_82965G_1_IG 0x2982
19 #define PCI_DEVICE_ID_INTEL_82965Q_HB 0x2990
20 #define PCI_DEVICE_ID_INTEL_82965Q_IG 0x2992
21 #define PCI_DEVICE_ID_INTEL_82965G_HB 0x29A0
22 #define PCI_DEVICE_ID_INTEL_82965G_IG 0x29A2
23 #define PCI_DEVICE_ID_INTEL_82965GM_HB 0x2A00
24 #define PCI_DEVICE_ID_INTEL_82965GM_IG 0x2A02
25 #define PCI_DEVICE_ID_INTEL_82965GME_HB 0x2A10
26 #define PCI_DEVICE_ID_INTEL_82965GME_IG 0x2A12
27 #define PCI_DEVICE_ID_INTEL_82945GME_HB 0x27AC
28 #define PCI_DEVICE_ID_INTEL_82945GME_IG 0x27AE
29 #define PCI_DEVICE_ID_INTEL_G33_HB 0x29C0
30 #define PCI_DEVICE_ID_INTEL_G33_IG 0x29C2
31 #define PCI_DEVICE_ID_INTEL_Q35_HB 0x29B0
32 #define PCI_DEVICE_ID_INTEL_Q35_IG 0x29B2
33 #define PCI_DEVICE_ID_INTEL_Q33_HB 0x29D0
34 #define PCI_DEVICE_ID_INTEL_Q33_IG 0x29D2
35 #define PCI_DEVICE_ID_INTEL_IGD_HB 0x2A40
36 #define PCI_DEVICE_ID_INTEL_IGD_IG 0x2A42
38 #define IS_I965 (agp_bridge->dev->device == PCI_DEVICE_ID_INTEL_82946GZ_HB || \
39 agp_bridge->dev->device == PCI_DEVICE_ID_INTEL_82965G_1_HB || \
40 agp_bridge->dev->device == PCI_DEVICE_ID_INTEL_82965Q_HB || \
41 agp_bridge->dev->device == PCI_DEVICE_ID_INTEL_82965G_HB || \
42 agp_bridge->dev->device == PCI_DEVICE_ID_INTEL_82965GM_HB || \
43 agp_bridge->dev->device == PCI_DEVICE_ID_INTEL_82965GME_HB || \
44 agp_bridge->dev->device == PCI_DEVICE_ID_INTEL_IGD_HB)
46 #define IS_G33 (agp_bridge->dev->device == PCI_DEVICE_ID_INTEL_G33_HB || \
47 agp_bridge->dev->device == PCI_DEVICE_ID_INTEL_Q35_HB || \
48 agp_bridge->dev->device == PCI_DEVICE_ID_INTEL_Q33_HB)
50 extern int agp_memory_reserved;
53 /* Intel 815 register */
54 #define INTEL_815_APCONT 0x51
55 #define INTEL_815_ATTBASE_MASK ~0x1FFFFFFF
57 /* Intel i820 registers */
58 #define INTEL_I820_RDCR 0x51
59 #define INTEL_I820_ERRSTS 0xc8
61 /* Intel i840 registers */
62 #define INTEL_I840_MCHCFG 0x50
63 #define INTEL_I840_ERRSTS 0xc8
65 /* Intel i850 registers */
66 #define INTEL_I850_MCHCFG 0x50
67 #define INTEL_I850_ERRSTS 0xc8
69 /* intel 915G registers */
70 #define I915_GMADDR 0x18
71 #define I915_MMADDR 0x10
72 #define I915_PTEADDR 0x1C
73 #define I915_GMCH_GMS_STOLEN_48M (0x6 << 4)
74 #define I915_GMCH_GMS_STOLEN_64M (0x7 << 4)
75 #define G33_GMCH_GMS_STOLEN_128M (0x8 << 4)
76 #define G33_GMCH_GMS_STOLEN_256M (0x9 << 4)
77 #define I915_IFPADDR 0x60
79 /* Intel 965G registers */
80 #define I965_MSAC 0x62
81 #define I965_IFPADDR 0x70
83 /* Intel 7505 registers */
84 #define INTEL_I7505_APSIZE 0x74
85 #define INTEL_I7505_NCAPID 0x60
86 #define INTEL_I7505_NISTAT 0x6c
87 #define INTEL_I7505_ATTBASE 0x78
88 #define INTEL_I7505_ERRSTS 0x42
89 #define INTEL_I7505_AGPCTRL 0x70
90 #define INTEL_I7505_MCHCFG 0x50
92 static const struct aper_size_info_fixed intel_i810_sizes[] =
95 /* The 32M mode still requires a 64k gatt */
99 #define AGP_DCACHE_MEMORY 1
100 #define AGP_PHYS_MEMORY 2
101 #define INTEL_AGP_CACHED_MEMORY 3
103 static struct gatt_mask intel_i810_masks[] =
105 {.mask = I810_PTE_VALID, .type = 0},
106 {.mask = (I810_PTE_VALID | I810_PTE_LOCAL), .type = AGP_DCACHE_MEMORY},
107 {.mask = I810_PTE_VALID, .type = 0},
108 {.mask = I810_PTE_VALID | I830_PTE_SYSTEM_CACHED,
109 .type = INTEL_AGP_CACHED_MEMORY}
112 static struct _intel_private {
113 struct pci_dev *pcidev; /* device one */
114 u8 __iomem *registers;
115 u32 __iomem *gtt; /* I915G */
116 int num_dcache_entries;
117 /* gtt_entries is the number of gtt entries that are already mapped
118 * to stolen memory. Stolen memory is larger than the memory mapped
119 * through gtt_entries, as it includes some reserved space for the BIOS
120 * popup and for the GTT.
122 int gtt_entries; /* i830+ */
124 void __iomem *i9xx_flush_page;
125 void *i8xx_flush_page;
127 struct page *i8xx_page;
128 struct resource ifp_resource;
131 static int intel_i810_fetch_size(void)
134 struct aper_size_info_fixed *values;
136 pci_read_config_dword(agp_bridge->dev, I810_SMRAM_MISCC, &smram_miscc);
137 values = A_SIZE_FIX(agp_bridge->driver->aperture_sizes);
139 if ((smram_miscc & I810_GMS) == I810_GMS_DISABLE) {
140 printk(KERN_WARNING PFX "i810 is disabled\n");
143 if ((smram_miscc & I810_GFX_MEM_WIN_SIZE) == I810_GFX_MEM_WIN_32M) {
144 agp_bridge->previous_size =
145 agp_bridge->current_size = (void *) (values + 1);
146 agp_bridge->aperture_size_idx = 1;
147 return values[1].size;
149 agp_bridge->previous_size =
150 agp_bridge->current_size = (void *) (values);
151 agp_bridge->aperture_size_idx = 0;
152 return values[0].size;
158 static int intel_i810_configure(void)
160 struct aper_size_info_fixed *current_size;
164 current_size = A_SIZE_FIX(agp_bridge->current_size);
166 if (!intel_private.registers) {
167 pci_read_config_dword(intel_private.pcidev, I810_MMADDR, &temp);
170 intel_private.registers = ioremap(temp, 128 * 4096);
171 if (!intel_private.registers) {
172 printk(KERN_ERR PFX "Unable to remap memory.\n");
177 if ((readl(intel_private.registers+I810_DRAM_CTL)
178 & I810_DRAM_ROW_0) == I810_DRAM_ROW_0_SDRAM) {
179 /* This will need to be dynamically assigned */
180 printk(KERN_INFO PFX "detected 4MB dedicated video ram.\n");
181 intel_private.num_dcache_entries = 1024;
183 pci_read_config_dword(intel_private.pcidev, I810_GMADDR, &temp);
184 agp_bridge->gart_bus_addr = (temp & PCI_BASE_ADDRESS_MEM_MASK);
185 writel(agp_bridge->gatt_bus_addr | I810_PGETBL_ENABLED, intel_private.registers+I810_PGETBL_CTL);
186 readl(intel_private.registers+I810_PGETBL_CTL); /* PCI Posting. */
188 if (agp_bridge->driver->needs_scratch_page) {
189 for (i = 0; i < current_size->num_entries; i++) {
190 writel(agp_bridge->scratch_page, intel_private.registers+I810_PTE_BASE+(i*4));
191 readl(intel_private.registers+I810_PTE_BASE+(i*4)); /* PCI posting. */
194 global_cache_flush();
198 static void intel_i810_cleanup(void)
200 writel(0, intel_private.registers+I810_PGETBL_CTL);
201 readl(intel_private.registers); /* PCI Posting. */
202 iounmap(intel_private.registers);
205 static void intel_i810_tlbflush(struct agp_memory *mem)
210 static void intel_i810_agp_enable(struct agp_bridge_data *bridge, u32 mode)
215 /* Exists to support ARGB cursors */
216 static void *i8xx_alloc_pages(void)
220 page = alloc_pages(GFP_KERNEL | GFP_DMA32, 2);
224 if (set_pages_uc(page, 4) < 0) {
225 set_pages_wb(page, 4);
226 __free_pages(page, 2);
230 atomic_inc(&agp_bridge->current_memory_agp);
231 return page_address(page);
234 static void i8xx_destroy_pages(void *addr)
241 page = virt_to_page(addr);
242 set_pages_wb(page, 4);
244 __free_pages(page, 2);
245 atomic_dec(&agp_bridge->current_memory_agp);
248 static int intel_i830_type_to_mask_type(struct agp_bridge_data *bridge,
251 if (type < AGP_USER_TYPES)
253 else if (type == AGP_USER_CACHED_MEMORY)
254 return INTEL_AGP_CACHED_MEMORY;
259 static int intel_i810_insert_entries(struct agp_memory *mem, off_t pg_start,
262 int i, j, num_entries;
267 if (mem->page_count == 0)
270 temp = agp_bridge->current_size;
271 num_entries = A_SIZE_FIX(temp)->num_entries;
273 if ((pg_start + mem->page_count) > num_entries)
277 for (j = pg_start; j < (pg_start + mem->page_count); j++) {
278 if (!PGE_EMPTY(agp_bridge, readl(agp_bridge->gatt_table+j))) {
284 if (type != mem->type)
287 mask_type = agp_bridge->driver->agp_type_to_mask_type(agp_bridge, type);
290 case AGP_DCACHE_MEMORY:
291 if (!mem->is_flushed)
292 global_cache_flush();
293 for (i = pg_start; i < (pg_start + mem->page_count); i++) {
294 writel((i*4096)|I810_PTE_LOCAL|I810_PTE_VALID,
295 intel_private.registers+I810_PTE_BASE+(i*4));
297 readl(intel_private.registers+I810_PTE_BASE+((i-1)*4));
299 case AGP_PHYS_MEMORY:
300 case AGP_NORMAL_MEMORY:
301 if (!mem->is_flushed)
302 global_cache_flush();
303 for (i = 0, j = pg_start; i < mem->page_count; i++, j++) {
304 writel(agp_bridge->driver->mask_memory(agp_bridge,
307 intel_private.registers+I810_PTE_BASE+(j*4));
309 readl(intel_private.registers+I810_PTE_BASE+((j-1)*4));
315 agp_bridge->driver->tlb_flush(mem);
323 static int intel_i810_remove_entries(struct agp_memory *mem, off_t pg_start,
328 if (mem->page_count == 0)
331 for (i = pg_start; i < (mem->page_count + pg_start); i++) {
332 writel(agp_bridge->scratch_page, intel_private.registers+I810_PTE_BASE+(i*4));
334 readl(intel_private.registers+I810_PTE_BASE+((i-1)*4));
336 agp_bridge->driver->tlb_flush(mem);
341 * The i810/i830 requires a physical address to program its mouse
342 * pointer into hardware.
343 * However the Xserver still writes to it through the agp aperture.
345 static struct agp_memory *alloc_agpphysmem_i8xx(size_t pg_count, int type)
347 struct agp_memory *new;
351 case 1: addr = agp_bridge->driver->agp_alloc_page(agp_bridge);
354 /* kludge to get 4 physical pages for ARGB cursor */
355 addr = i8xx_alloc_pages();
364 new = agp_create_memory(pg_count);
368 new->memory[0] = virt_to_gart(addr);
370 /* kludge to get 4 physical pages for ARGB cursor */
371 new->memory[1] = new->memory[0] + PAGE_SIZE;
372 new->memory[2] = new->memory[1] + PAGE_SIZE;
373 new->memory[3] = new->memory[2] + PAGE_SIZE;
375 new->page_count = pg_count;
376 new->num_scratch_pages = pg_count;
377 new->type = AGP_PHYS_MEMORY;
378 new->physical = new->memory[0];
382 static struct agp_memory *intel_i810_alloc_by_type(size_t pg_count, int type)
384 struct agp_memory *new;
386 if (type == AGP_DCACHE_MEMORY) {
387 if (pg_count != intel_private.num_dcache_entries)
390 new = agp_create_memory(1);
394 new->type = AGP_DCACHE_MEMORY;
395 new->page_count = pg_count;
396 new->num_scratch_pages = 0;
397 agp_free_page_array(new);
400 if (type == AGP_PHYS_MEMORY)
401 return alloc_agpphysmem_i8xx(pg_count, type);
405 static void intel_i810_free_by_type(struct agp_memory *curr)
407 agp_free_key(curr->key);
408 if (curr->type == AGP_PHYS_MEMORY) {
409 if (curr->page_count == 4)
410 i8xx_destroy_pages(gart_to_virt(curr->memory[0]));
412 agp_bridge->driver->agp_destroy_page(gart_to_virt(curr->memory[0]),
413 AGP_PAGE_DESTROY_UNMAP);
414 agp_bridge->driver->agp_destroy_page(gart_to_virt(curr->memory[0]),
415 AGP_PAGE_DESTROY_FREE);
417 agp_free_page_array(curr);
422 static unsigned long intel_i810_mask_memory(struct agp_bridge_data *bridge,
423 unsigned long addr, int type)
425 /* Type checking must be done elsewhere */
426 return addr | bridge->driver->masks[type].mask;
429 static struct aper_size_info_fixed intel_i830_sizes[] =
432 /* The 64M mode still requires a 128k gatt */
438 static void intel_i830_init_gtt_entries(void)
444 static const int ddt[4] = { 0, 16, 32, 64 };
445 int size; /* reserved space (in kb) at the top of stolen memory */
447 pci_read_config_word(agp_bridge->dev,I830_GMCH_CTRL,&gmch_ctrl);
451 pgetbl_ctl = readl(intel_private.registers+I810_PGETBL_CTL);
453 /* The 965 has a field telling us the size of the GTT,
454 * which may be larger than what is necessary to map the
457 switch (pgetbl_ctl & I965_PGETBL_SIZE_MASK) {
458 case I965_PGETBL_SIZE_128KB:
461 case I965_PGETBL_SIZE_256KB:
464 case I965_PGETBL_SIZE_512KB:
467 case I965_PGETBL_SIZE_1MB:
470 case I965_PGETBL_SIZE_2MB:
473 case I965_PGETBL_SIZE_1_5MB:
477 printk(KERN_INFO PFX "Unknown page table size, "
481 size += 4; /* add in BIOS popup space */
483 /* G33's GTT size defined in gmch_ctrl */
484 switch (gmch_ctrl & G33_PGETBL_SIZE_MASK) {
485 case G33_PGETBL_SIZE_1M:
488 case G33_PGETBL_SIZE_2M:
492 printk(KERN_INFO PFX "Unknown page table size 0x%x, "
494 (gmch_ctrl & G33_PGETBL_SIZE_MASK));
499 /* On previous hardware, the GTT size was just what was
500 * required to map the aperture.
502 size = agp_bridge->driver->fetch_size() + 4;
505 if (agp_bridge->dev->device == PCI_DEVICE_ID_INTEL_82830_HB ||
506 agp_bridge->dev->device == PCI_DEVICE_ID_INTEL_82845G_HB) {
507 switch (gmch_ctrl & I830_GMCH_GMS_MASK) {
508 case I830_GMCH_GMS_STOLEN_512:
509 gtt_entries = KB(512) - KB(size);
511 case I830_GMCH_GMS_STOLEN_1024:
512 gtt_entries = MB(1) - KB(size);
514 case I830_GMCH_GMS_STOLEN_8192:
515 gtt_entries = MB(8) - KB(size);
517 case I830_GMCH_GMS_LOCAL:
518 rdct = readb(intel_private.registers+I830_RDRAM_CHANNEL_TYPE);
519 gtt_entries = (I830_RDRAM_ND(rdct) + 1) *
520 MB(ddt[I830_RDRAM_DDT(rdct)]);
528 switch (gmch_ctrl & I855_GMCH_GMS_MASK) {
529 case I855_GMCH_GMS_STOLEN_1M:
530 gtt_entries = MB(1) - KB(size);
532 case I855_GMCH_GMS_STOLEN_4M:
533 gtt_entries = MB(4) - KB(size);
535 case I855_GMCH_GMS_STOLEN_8M:
536 gtt_entries = MB(8) - KB(size);
538 case I855_GMCH_GMS_STOLEN_16M:
539 gtt_entries = MB(16) - KB(size);
541 case I855_GMCH_GMS_STOLEN_32M:
542 gtt_entries = MB(32) - KB(size);
544 case I915_GMCH_GMS_STOLEN_48M:
545 /* Check it's really I915G */
546 if (agp_bridge->dev->device == PCI_DEVICE_ID_INTEL_E7221_HB ||
547 agp_bridge->dev->device == PCI_DEVICE_ID_INTEL_82915G_HB ||
548 agp_bridge->dev->device == PCI_DEVICE_ID_INTEL_82915GM_HB ||
549 agp_bridge->dev->device == PCI_DEVICE_ID_INTEL_82945G_HB ||
550 agp_bridge->dev->device == PCI_DEVICE_ID_INTEL_82945GM_HB ||
551 agp_bridge->dev->device == PCI_DEVICE_ID_INTEL_82945GME_HB ||
553 gtt_entries = MB(48) - KB(size);
557 case I915_GMCH_GMS_STOLEN_64M:
558 /* Check it's really I915G */
559 if (agp_bridge->dev->device == PCI_DEVICE_ID_INTEL_E7221_HB ||
560 agp_bridge->dev->device == PCI_DEVICE_ID_INTEL_82915G_HB ||
561 agp_bridge->dev->device == PCI_DEVICE_ID_INTEL_82915GM_HB ||
562 agp_bridge->dev->device == PCI_DEVICE_ID_INTEL_82945G_HB ||
563 agp_bridge->dev->device == PCI_DEVICE_ID_INTEL_82945GM_HB ||
564 agp_bridge->dev->device == PCI_DEVICE_ID_INTEL_82945GME_HB ||
566 gtt_entries = MB(64) - KB(size);
570 case G33_GMCH_GMS_STOLEN_128M:
572 gtt_entries = MB(128) - KB(size);
576 case G33_GMCH_GMS_STOLEN_256M:
578 gtt_entries = MB(256) - KB(size);
588 printk(KERN_INFO PFX "Detected %dK %s memory.\n",
589 gtt_entries / KB(1), local ? "local" : "stolen");
592 "No pre-allocated video memory detected.\n");
593 gtt_entries /= KB(4);
595 intel_private.gtt_entries = gtt_entries;
598 static void intel_i830_fini_flush(void)
600 kunmap(intel_private.i8xx_page);
601 intel_private.i8xx_flush_page = NULL;
602 unmap_page_from_agp(intel_private.i8xx_page);
603 flush_agp_mappings();
605 __free_page(intel_private.i8xx_page);
608 static void intel_i830_setup_flush(void)
611 intel_private.i8xx_page = alloc_page(GFP_KERNEL | __GFP_ZERO | GFP_DMA32);
612 if (!intel_private.i8xx_page) {
616 /* make page uncached */
617 map_page_into_agp(intel_private.i8xx_page);
618 flush_agp_mappings();
620 intel_private.i8xx_flush_page = kmap(intel_private.i8xx_page);
621 if (!intel_private.i8xx_flush_page)
622 intel_i830_fini_flush();
625 static void intel_i830_chipset_flush(struct agp_bridge_data *bridge)
627 unsigned int *pg = intel_private.i8xx_flush_page;
630 for (i = 0; i < 256; i+=2)
636 /* The intel i830 automatically initializes the agp aperture during POST.
637 * Use the memory already set aside for in the GTT.
639 static int intel_i830_create_gatt_table(struct agp_bridge_data *bridge)
642 struct aper_size_info_fixed *size;
646 size = agp_bridge->current_size;
647 page_order = size->page_order;
648 num_entries = size->num_entries;
649 agp_bridge->gatt_table_real = NULL;
651 pci_read_config_dword(intel_private.pcidev,I810_MMADDR,&temp);
654 intel_private.registers = ioremap(temp,128 * 4096);
655 if (!intel_private.registers)
658 temp = readl(intel_private.registers+I810_PGETBL_CTL) & 0xfffff000;
659 global_cache_flush(); /* FIXME: ?? */
661 /* we have to call this as early as possible after the MMIO base address is known */
662 intel_i830_init_gtt_entries();
664 agp_bridge->gatt_table = NULL;
666 agp_bridge->gatt_bus_addr = temp;
671 /* Return the gatt table to a sane state. Use the top of stolen
672 * memory for the GTT.
674 static int intel_i830_free_gatt_table(struct agp_bridge_data *bridge)
679 static int intel_i830_fetch_size(void)
682 struct aper_size_info_fixed *values;
684 values = A_SIZE_FIX(agp_bridge->driver->aperture_sizes);
686 if (agp_bridge->dev->device != PCI_DEVICE_ID_INTEL_82830_HB &&
687 agp_bridge->dev->device != PCI_DEVICE_ID_INTEL_82845G_HB) {
688 /* 855GM/852GM/865G has 128MB aperture size */
689 agp_bridge->previous_size = agp_bridge->current_size = (void *) values;
690 agp_bridge->aperture_size_idx = 0;
691 return values[0].size;
694 pci_read_config_word(agp_bridge->dev,I830_GMCH_CTRL,&gmch_ctrl);
696 if ((gmch_ctrl & I830_GMCH_MEM_MASK) == I830_GMCH_MEM_128M) {
697 agp_bridge->previous_size = agp_bridge->current_size = (void *) values;
698 agp_bridge->aperture_size_idx = 0;
699 return values[0].size;
701 agp_bridge->previous_size = agp_bridge->current_size = (void *) (values + 1);
702 agp_bridge->aperture_size_idx = 1;
703 return values[1].size;
709 static int intel_i830_configure(void)
711 struct aper_size_info_fixed *current_size;
716 current_size = A_SIZE_FIX(agp_bridge->current_size);
718 pci_read_config_dword(intel_private.pcidev,I810_GMADDR,&temp);
719 agp_bridge->gart_bus_addr = (temp & PCI_BASE_ADDRESS_MEM_MASK);
721 pci_read_config_word(agp_bridge->dev,I830_GMCH_CTRL,&gmch_ctrl);
722 gmch_ctrl |= I830_GMCH_ENABLED;
723 pci_write_config_word(agp_bridge->dev,I830_GMCH_CTRL,gmch_ctrl);
725 writel(agp_bridge->gatt_bus_addr|I810_PGETBL_ENABLED, intel_private.registers+I810_PGETBL_CTL);
726 readl(intel_private.registers+I810_PGETBL_CTL); /* PCI Posting. */
728 if (agp_bridge->driver->needs_scratch_page) {
729 for (i = intel_private.gtt_entries; i < current_size->num_entries; i++) {
730 writel(agp_bridge->scratch_page, intel_private.registers+I810_PTE_BASE+(i*4));
731 readl(intel_private.registers+I810_PTE_BASE+(i*4)); /* PCI Posting. */
735 global_cache_flush();
737 intel_i830_setup_flush();
741 static void intel_i830_cleanup(void)
743 iounmap(intel_private.registers);
746 static int intel_i830_insert_entries(struct agp_memory *mem,off_t pg_start, int type)
753 if (mem->page_count == 0)
756 temp = agp_bridge->current_size;
757 num_entries = A_SIZE_FIX(temp)->num_entries;
759 if (pg_start < intel_private.gtt_entries) {
760 printk (KERN_DEBUG PFX "pg_start == 0x%.8lx,intel_private.gtt_entries == 0x%.8x\n",
761 pg_start,intel_private.gtt_entries);
763 printk (KERN_INFO PFX "Trying to insert into local/stolen memory\n");
767 if ((pg_start + mem->page_count) > num_entries)
770 /* The i830 can't check the GTT for entries since its read only,
771 * depend on the caller to make the correct offset decisions.
774 if (type != mem->type)
777 mask_type = agp_bridge->driver->agp_type_to_mask_type(agp_bridge, type);
779 if (mask_type != 0 && mask_type != AGP_PHYS_MEMORY &&
780 mask_type != INTEL_AGP_CACHED_MEMORY)
783 if (!mem->is_flushed)
784 global_cache_flush();
786 for (i = 0, j = pg_start; i < mem->page_count; i++, j++) {
787 writel(agp_bridge->driver->mask_memory(agp_bridge,
788 mem->memory[i], mask_type),
789 intel_private.registers+I810_PTE_BASE+(j*4));
791 readl(intel_private.registers+I810_PTE_BASE+((j-1)*4));
792 agp_bridge->driver->tlb_flush(mem);
801 static int intel_i830_remove_entries(struct agp_memory *mem,off_t pg_start,
806 if (mem->page_count == 0)
809 if (pg_start < intel_private.gtt_entries) {
810 printk (KERN_INFO PFX "Trying to disable local/stolen memory\n");
814 for (i = pg_start; i < (mem->page_count + pg_start); i++) {
815 writel(agp_bridge->scratch_page, intel_private.registers+I810_PTE_BASE+(i*4));
817 readl(intel_private.registers+I810_PTE_BASE+((i-1)*4));
819 agp_bridge->driver->tlb_flush(mem);
823 static struct agp_memory *intel_i830_alloc_by_type(size_t pg_count,int type)
825 if (type == AGP_PHYS_MEMORY)
826 return alloc_agpphysmem_i8xx(pg_count, type);
827 /* always return NULL for other allocation types for now */
831 static int intel_alloc_chipset_flush_resource(void)
834 ret = pci_bus_alloc_resource(agp_bridge->dev->bus, &intel_private.ifp_resource, PAGE_SIZE,
835 PAGE_SIZE, PCIBIOS_MIN_MEM, 0,
836 pcibios_align_resource, agp_bridge->dev);
841 static void intel_i915_setup_chipset_flush(void)
846 pci_read_config_dword(agp_bridge->dev, I915_IFPADDR, &temp);
848 intel_alloc_chipset_flush_resource();
850 pci_write_config_dword(agp_bridge->dev, I915_IFPADDR, (intel_private.ifp_resource.start & 0xffffffff) | 0x1);
854 intel_private.ifp_resource.start = temp;
855 intel_private.ifp_resource.end = temp + PAGE_SIZE;
856 ret = request_resource(&iomem_resource, &intel_private.ifp_resource);
858 intel_private.ifp_resource.start = 0;
859 printk("Failed inserting resource into tree\n");
864 static void intel_i965_g33_setup_chipset_flush(void)
866 u32 temp_hi, temp_lo;
869 pci_read_config_dword(agp_bridge->dev, I965_IFPADDR + 4, &temp_hi);
870 pci_read_config_dword(agp_bridge->dev, I965_IFPADDR, &temp_lo);
872 if (!(temp_lo & 0x1)) {
874 intel_alloc_chipset_flush_resource();
876 pci_write_config_dword(agp_bridge->dev, I965_IFPADDR + 4,
877 upper_32_bits(intel_private.ifp_resource.start));
878 pci_write_config_dword(agp_bridge->dev, I965_IFPADDR, (intel_private.ifp_resource.start & 0xffffffff) | 0x1);
883 l64 = ((u64)temp_hi << 32) | temp_lo;
885 intel_private.ifp_resource.start = l64;
886 intel_private.ifp_resource.end = l64 + PAGE_SIZE;
887 ret = request_resource(&iomem_resource, &intel_private.ifp_resource);
889 printk("Failed inserting resource into tree - continuing\n");
894 static void intel_i9xx_setup_flush(void)
896 /* setup a resource for this object */
897 memset(&intel_private.ifp_resource, 0, sizeof(intel_private.ifp_resource));
899 intel_private.ifp_resource.name = "Intel Flush Page";
900 intel_private.ifp_resource.flags = IORESOURCE_MEM;
902 /* Setup chipset flush for 915 */
903 if (IS_I965 || IS_G33) {
904 intel_i965_g33_setup_chipset_flush();
906 intel_i915_setup_chipset_flush();
909 if (intel_private.ifp_resource.start) {
910 intel_private.i9xx_flush_page = ioremap_nocache(intel_private.ifp_resource.start, PAGE_SIZE);
911 if (!intel_private.i9xx_flush_page)
912 printk("unable to ioremap flush page - no chipset flushing");
916 static int intel_i915_configure(void)
918 struct aper_size_info_fixed *current_size;
923 current_size = A_SIZE_FIX(agp_bridge->current_size);
925 pci_read_config_dword(intel_private.pcidev, I915_GMADDR, &temp);
927 agp_bridge->gart_bus_addr = (temp & PCI_BASE_ADDRESS_MEM_MASK);
929 pci_read_config_word(agp_bridge->dev,I830_GMCH_CTRL,&gmch_ctrl);
930 gmch_ctrl |= I830_GMCH_ENABLED;
931 pci_write_config_word(agp_bridge->dev,I830_GMCH_CTRL,gmch_ctrl);
933 writel(agp_bridge->gatt_bus_addr|I810_PGETBL_ENABLED, intel_private.registers+I810_PGETBL_CTL);
934 readl(intel_private.registers+I810_PGETBL_CTL); /* PCI Posting. */
936 if (agp_bridge->driver->needs_scratch_page) {
937 for (i = intel_private.gtt_entries; i < current_size->num_entries; i++) {
938 writel(agp_bridge->scratch_page, intel_private.gtt+i);
939 readl(intel_private.gtt+i); /* PCI Posting. */
943 global_cache_flush();
945 intel_i9xx_setup_flush();
950 static void intel_i915_cleanup(void)
952 if (intel_private.i9xx_flush_page)
953 iounmap(intel_private.i9xx_flush_page);
954 iounmap(intel_private.gtt);
955 iounmap(intel_private.registers);
958 static void intel_i915_chipset_flush(struct agp_bridge_data *bridge)
960 if (intel_private.i9xx_flush_page)
961 writel(1, intel_private.i9xx_flush_page);
964 static int intel_i915_insert_entries(struct agp_memory *mem,off_t pg_start,
972 if (mem->page_count == 0)
975 temp = agp_bridge->current_size;
976 num_entries = A_SIZE_FIX(temp)->num_entries;
978 if (pg_start < intel_private.gtt_entries) {
979 printk (KERN_DEBUG PFX "pg_start == 0x%.8lx,intel_private.gtt_entries == 0x%.8x\n",
980 pg_start,intel_private.gtt_entries);
982 printk (KERN_INFO PFX "Trying to insert into local/stolen memory\n");
986 if ((pg_start + mem->page_count) > num_entries)
989 /* The i915 can't check the GTT for entries since its read only,
990 * depend on the caller to make the correct offset decisions.
993 if (type != mem->type)
996 mask_type = agp_bridge->driver->agp_type_to_mask_type(agp_bridge, type);
998 if (mask_type != 0 && mask_type != AGP_PHYS_MEMORY &&
999 mask_type != INTEL_AGP_CACHED_MEMORY)
1002 if (!mem->is_flushed)
1003 global_cache_flush();
1005 for (i = 0, j = pg_start; i < mem->page_count; i++, j++) {
1006 writel(agp_bridge->driver->mask_memory(agp_bridge,
1007 mem->memory[i], mask_type), intel_private.gtt+j);
1010 readl(intel_private.gtt+j-1);
1011 agp_bridge->driver->tlb_flush(mem);
1016 mem->is_flushed = 1;
1020 static int intel_i915_remove_entries(struct agp_memory *mem,off_t pg_start,
1025 if (mem->page_count == 0)
1028 if (pg_start < intel_private.gtt_entries) {
1029 printk (KERN_INFO PFX "Trying to disable local/stolen memory\n");
1033 for (i = pg_start; i < (mem->page_count + pg_start); i++) {
1034 writel(agp_bridge->scratch_page, intel_private.gtt+i);
1036 readl(intel_private.gtt+i-1);
1038 agp_bridge->driver->tlb_flush(mem);
1042 /* Return the aperture size by just checking the resource length. The effect
1043 * described in the spec of the MSAC registers is just changing of the
1046 static int intel_i9xx_fetch_size(void)
1048 int num_sizes = ARRAY_SIZE(intel_i830_sizes);
1049 int aper_size; /* size in megabytes */
1052 aper_size = pci_resource_len(intel_private.pcidev, 2) / MB(1);
1054 for (i = 0; i < num_sizes; i++) {
1055 if (aper_size == intel_i830_sizes[i].size) {
1056 agp_bridge->current_size = intel_i830_sizes + i;
1057 agp_bridge->previous_size = agp_bridge->current_size;
1065 /* The intel i915 automatically initializes the agp aperture during POST.
1066 * Use the memory already set aside for in the GTT.
1068 static int intel_i915_create_gatt_table(struct agp_bridge_data *bridge)
1071 struct aper_size_info_fixed *size;
1074 int gtt_map_size = 256 * 1024;
1076 size = agp_bridge->current_size;
1077 page_order = size->page_order;
1078 num_entries = size->num_entries;
1079 agp_bridge->gatt_table_real = NULL;
1081 pci_read_config_dword(intel_private.pcidev, I915_MMADDR, &temp);
1082 pci_read_config_dword(intel_private.pcidev, I915_PTEADDR,&temp2);
1085 gtt_map_size = 1024 * 1024; /* 1M on G33 */
1086 intel_private.gtt = ioremap(temp2, gtt_map_size);
1087 if (!intel_private.gtt)
1092 intel_private.registers = ioremap(temp,128 * 4096);
1093 if (!intel_private.registers) {
1094 iounmap(intel_private.gtt);
1098 temp = readl(intel_private.registers+I810_PGETBL_CTL) & 0xfffff000;
1099 global_cache_flush(); /* FIXME: ? */
1101 /* we have to call this as early as possible after the MMIO base address is known */
1102 intel_i830_init_gtt_entries();
1104 agp_bridge->gatt_table = NULL;
1106 agp_bridge->gatt_bus_addr = temp;
1112 * The i965 supports 36-bit physical addresses, but to keep
1113 * the format of the GTT the same, the bits that don't fit
1114 * in a 32-bit word are shifted down to bits 4..7.
1116 * Gcc is smart enough to notice that "(addr >> 28) & 0xf0"
1117 * is always zero on 32-bit architectures, so no need to make
1120 static unsigned long intel_i965_mask_memory(struct agp_bridge_data *bridge,
1121 unsigned long addr, int type)
1123 /* Shift high bits down */
1124 addr |= (addr >> 28) & 0xf0;
1126 /* Type checking must be done elsewhere */
1127 return addr | bridge->driver->masks[type].mask;
1130 /* The intel i965 automatically initializes the agp aperture during POST.
1131 * Use the memory already set aside for in the GTT.
1133 static int intel_i965_create_gatt_table(struct agp_bridge_data *bridge)
1136 struct aper_size_info_fixed *size;
1139 int gtt_offset, gtt_size;
1141 size = agp_bridge->current_size;
1142 page_order = size->page_order;
1143 num_entries = size->num_entries;
1144 agp_bridge->gatt_table_real = NULL;
1146 pci_read_config_dword(intel_private.pcidev, I915_MMADDR, &temp);
1150 if (agp_bridge->dev->device == PCI_DEVICE_ID_INTEL_IGD_HB)
1151 gtt_offset = gtt_size = MB(2);
1153 gtt_offset = gtt_size = KB(512);
1155 intel_private.gtt = ioremap((temp + gtt_offset) , gtt_size);
1157 if (!intel_private.gtt)
1160 intel_private.registers = ioremap(temp, 128 * 4096);
1161 if (!intel_private.registers) {
1162 iounmap(intel_private.gtt);
1166 temp = readl(intel_private.registers+I810_PGETBL_CTL) & 0xfffff000;
1167 global_cache_flush(); /* FIXME: ? */
1169 /* we have to call this as early as possible after the MMIO base address is known */
1170 intel_i830_init_gtt_entries();
1172 agp_bridge->gatt_table = NULL;
1174 agp_bridge->gatt_bus_addr = temp;
1180 static int intel_fetch_size(void)
1184 struct aper_size_info_16 *values;
1186 pci_read_config_word(agp_bridge->dev, INTEL_APSIZE, &temp);
1187 values = A_SIZE_16(agp_bridge->driver->aperture_sizes);
1189 for (i = 0; i < agp_bridge->driver->num_aperture_sizes; i++) {
1190 if (temp == values[i].size_value) {
1191 agp_bridge->previous_size = agp_bridge->current_size = (void *) (values + i);
1192 agp_bridge->aperture_size_idx = i;
1193 return values[i].size;
1200 static int __intel_8xx_fetch_size(u8 temp)
1203 struct aper_size_info_8 *values;
1205 values = A_SIZE_8(agp_bridge->driver->aperture_sizes);
1207 for (i = 0; i < agp_bridge->driver->num_aperture_sizes; i++) {
1208 if (temp == values[i].size_value) {
1209 agp_bridge->previous_size =
1210 agp_bridge->current_size = (void *) (values + i);
1211 agp_bridge->aperture_size_idx = i;
1212 return values[i].size;
1218 static int intel_8xx_fetch_size(void)
1222 pci_read_config_byte(agp_bridge->dev, INTEL_APSIZE, &temp);
1223 return __intel_8xx_fetch_size(temp);
1226 static int intel_815_fetch_size(void)
1230 /* Intel 815 chipsets have a _weird_ APSIZE register with only
1231 * one non-reserved bit, so mask the others out ... */
1232 pci_read_config_byte(agp_bridge->dev, INTEL_APSIZE, &temp);
1235 return __intel_8xx_fetch_size(temp);
1238 static void intel_tlbflush(struct agp_memory *mem)
1240 pci_write_config_dword(agp_bridge->dev, INTEL_AGPCTRL, 0x2200);
1241 pci_write_config_dword(agp_bridge->dev, INTEL_AGPCTRL, 0x2280);
1245 static void intel_8xx_tlbflush(struct agp_memory *mem)
1248 pci_read_config_dword(agp_bridge->dev, INTEL_AGPCTRL, &temp);
1249 pci_write_config_dword(agp_bridge->dev, INTEL_AGPCTRL, temp & ~(1 << 7));
1250 pci_read_config_dword(agp_bridge->dev, INTEL_AGPCTRL, &temp);
1251 pci_write_config_dword(agp_bridge->dev, INTEL_AGPCTRL, temp | (1 << 7));
1255 static void intel_cleanup(void)
1258 struct aper_size_info_16 *previous_size;
1260 previous_size = A_SIZE_16(agp_bridge->previous_size);
1261 pci_read_config_word(agp_bridge->dev, INTEL_NBXCFG, &temp);
1262 pci_write_config_word(agp_bridge->dev, INTEL_NBXCFG, temp & ~(1 << 9));
1263 pci_write_config_word(agp_bridge->dev, INTEL_APSIZE, previous_size->size_value);
1267 static void intel_8xx_cleanup(void)
1270 struct aper_size_info_8 *previous_size;
1272 previous_size = A_SIZE_8(agp_bridge->previous_size);
1273 pci_read_config_word(agp_bridge->dev, INTEL_NBXCFG, &temp);
1274 pci_write_config_word(agp_bridge->dev, INTEL_NBXCFG, temp & ~(1 << 9));
1275 pci_write_config_byte(agp_bridge->dev, INTEL_APSIZE, previous_size->size_value);
1279 static int intel_configure(void)
1283 struct aper_size_info_16 *current_size;
1285 current_size = A_SIZE_16(agp_bridge->current_size);
1288 pci_write_config_word(agp_bridge->dev, INTEL_APSIZE, current_size->size_value);
1290 /* address to map to */
1291 pci_read_config_dword(agp_bridge->dev, AGP_APBASE, &temp);
1292 agp_bridge->gart_bus_addr = (temp & PCI_BASE_ADDRESS_MEM_MASK);
1294 /* attbase - aperture base */
1295 pci_write_config_dword(agp_bridge->dev, INTEL_ATTBASE, agp_bridge->gatt_bus_addr);
1298 pci_write_config_dword(agp_bridge->dev, INTEL_AGPCTRL, 0x2280);
1301 pci_read_config_word(agp_bridge->dev, INTEL_NBXCFG, &temp2);
1302 pci_write_config_word(agp_bridge->dev, INTEL_NBXCFG,
1303 (temp2 & ~(1 << 10)) | (1 << 9));
1304 /* clear any possible error conditions */
1305 pci_write_config_byte(agp_bridge->dev, INTEL_ERRSTS + 1, 7);
1309 static int intel_815_configure(void)
1313 struct aper_size_info_8 *current_size;
1315 /* attbase - aperture base */
1316 /* the Intel 815 chipset spec. says that bits 29-31 in the
1317 * ATTBASE register are reserved -> try not to write them */
1318 if (agp_bridge->gatt_bus_addr & INTEL_815_ATTBASE_MASK) {
1319 printk (KERN_EMERG PFX "gatt bus addr too high");
1323 current_size = A_SIZE_8(agp_bridge->current_size);
1326 pci_write_config_byte(agp_bridge->dev, INTEL_APSIZE,
1327 current_size->size_value);
1329 /* address to map to */
1330 pci_read_config_dword(agp_bridge->dev, AGP_APBASE, &temp);
1331 agp_bridge->gart_bus_addr = (temp & PCI_BASE_ADDRESS_MEM_MASK);
1333 pci_read_config_dword(agp_bridge->dev, INTEL_ATTBASE, &addr);
1334 addr &= INTEL_815_ATTBASE_MASK;
1335 addr |= agp_bridge->gatt_bus_addr;
1336 pci_write_config_dword(agp_bridge->dev, INTEL_ATTBASE, addr);
1339 pci_write_config_dword(agp_bridge->dev, INTEL_AGPCTRL, 0x0000);
1342 pci_read_config_byte(agp_bridge->dev, INTEL_815_APCONT, &temp2);
1343 pci_write_config_byte(agp_bridge->dev, INTEL_815_APCONT, temp2 | (1 << 1));
1345 /* clear any possible error conditions */
1346 /* Oddness : this chipset seems to have no ERRSTS register ! */
1350 static void intel_820_tlbflush(struct agp_memory *mem)
1355 static void intel_820_cleanup(void)
1358 struct aper_size_info_8 *previous_size;
1360 previous_size = A_SIZE_8(agp_bridge->previous_size);
1361 pci_read_config_byte(agp_bridge->dev, INTEL_I820_RDCR, &temp);
1362 pci_write_config_byte(agp_bridge->dev, INTEL_I820_RDCR,
1364 pci_write_config_byte(agp_bridge->dev, INTEL_APSIZE,
1365 previous_size->size_value);
1369 static int intel_820_configure(void)
1373 struct aper_size_info_8 *current_size;
1375 current_size = A_SIZE_8(agp_bridge->current_size);
1378 pci_write_config_byte(agp_bridge->dev, INTEL_APSIZE, current_size->size_value);
1380 /* address to map to */
1381 pci_read_config_dword(agp_bridge->dev, AGP_APBASE, &temp);
1382 agp_bridge->gart_bus_addr = (temp & PCI_BASE_ADDRESS_MEM_MASK);
1384 /* attbase - aperture base */
1385 pci_write_config_dword(agp_bridge->dev, INTEL_ATTBASE, agp_bridge->gatt_bus_addr);
1388 pci_write_config_dword(agp_bridge->dev, INTEL_AGPCTRL, 0x0000);
1390 /* global enable aperture access */
1391 /* This flag is not accessed through MCHCFG register as in */
1393 pci_read_config_byte(agp_bridge->dev, INTEL_I820_RDCR, &temp2);
1394 pci_write_config_byte(agp_bridge->dev, INTEL_I820_RDCR, temp2 | (1 << 1));
1395 /* clear any possible AGP-related error conditions */
1396 pci_write_config_word(agp_bridge->dev, INTEL_I820_ERRSTS, 0x001c);
1400 static int intel_840_configure(void)
1404 struct aper_size_info_8 *current_size;
1406 current_size = A_SIZE_8(agp_bridge->current_size);
1409 pci_write_config_byte(agp_bridge->dev, INTEL_APSIZE, current_size->size_value);
1411 /* address to map to */
1412 pci_read_config_dword(agp_bridge->dev, AGP_APBASE, &temp);
1413 agp_bridge->gart_bus_addr = (temp & PCI_BASE_ADDRESS_MEM_MASK);
1415 /* attbase - aperture base */
1416 pci_write_config_dword(agp_bridge->dev, INTEL_ATTBASE, agp_bridge->gatt_bus_addr);
1419 pci_write_config_dword(agp_bridge->dev, INTEL_AGPCTRL, 0x0000);
1422 pci_read_config_word(agp_bridge->dev, INTEL_I840_MCHCFG, &temp2);
1423 pci_write_config_word(agp_bridge->dev, INTEL_I840_MCHCFG, temp2 | (1 << 9));
1424 /* clear any possible error conditions */
1425 pci_write_config_word(agp_bridge->dev, INTEL_I840_ERRSTS, 0xc000);
1429 static int intel_845_configure(void)
1433 struct aper_size_info_8 *current_size;
1435 current_size = A_SIZE_8(agp_bridge->current_size);
1438 pci_write_config_byte(agp_bridge->dev, INTEL_APSIZE, current_size->size_value);
1440 if (agp_bridge->apbase_config != 0) {
1441 pci_write_config_dword(agp_bridge->dev, AGP_APBASE,
1442 agp_bridge->apbase_config);
1444 /* address to map to */
1445 pci_read_config_dword(agp_bridge->dev, AGP_APBASE, &temp);
1446 agp_bridge->gart_bus_addr = (temp & PCI_BASE_ADDRESS_MEM_MASK);
1447 agp_bridge->apbase_config = temp;
1450 /* attbase - aperture base */
1451 pci_write_config_dword(agp_bridge->dev, INTEL_ATTBASE, agp_bridge->gatt_bus_addr);
1454 pci_write_config_dword(agp_bridge->dev, INTEL_AGPCTRL, 0x0000);
1457 pci_read_config_byte(agp_bridge->dev, INTEL_I845_AGPM, &temp2);
1458 pci_write_config_byte(agp_bridge->dev, INTEL_I845_AGPM, temp2 | (1 << 1));
1459 /* clear any possible error conditions */
1460 pci_write_config_word(agp_bridge->dev, INTEL_I845_ERRSTS, 0x001c);
1462 intel_i830_setup_flush();
1466 static int intel_850_configure(void)
1470 struct aper_size_info_8 *current_size;
1472 current_size = A_SIZE_8(agp_bridge->current_size);
1475 pci_write_config_byte(agp_bridge->dev, INTEL_APSIZE, current_size->size_value);
1477 /* address to map to */
1478 pci_read_config_dword(agp_bridge->dev, AGP_APBASE, &temp);
1479 agp_bridge->gart_bus_addr = (temp & PCI_BASE_ADDRESS_MEM_MASK);
1481 /* attbase - aperture base */
1482 pci_write_config_dword(agp_bridge->dev, INTEL_ATTBASE, agp_bridge->gatt_bus_addr);
1485 pci_write_config_dword(agp_bridge->dev, INTEL_AGPCTRL, 0x0000);
1488 pci_read_config_word(agp_bridge->dev, INTEL_I850_MCHCFG, &temp2);
1489 pci_write_config_word(agp_bridge->dev, INTEL_I850_MCHCFG, temp2 | (1 << 9));
1490 /* clear any possible AGP-related error conditions */
1491 pci_write_config_word(agp_bridge->dev, INTEL_I850_ERRSTS, 0x001c);
1495 static int intel_860_configure(void)
1499 struct aper_size_info_8 *current_size;
1501 current_size = A_SIZE_8(agp_bridge->current_size);
1504 pci_write_config_byte(agp_bridge->dev, INTEL_APSIZE, current_size->size_value);
1506 /* address to map to */
1507 pci_read_config_dword(agp_bridge->dev, AGP_APBASE, &temp);
1508 agp_bridge->gart_bus_addr = (temp & PCI_BASE_ADDRESS_MEM_MASK);
1510 /* attbase - aperture base */
1511 pci_write_config_dword(agp_bridge->dev, INTEL_ATTBASE, agp_bridge->gatt_bus_addr);
1514 pci_write_config_dword(agp_bridge->dev, INTEL_AGPCTRL, 0x0000);
1517 pci_read_config_word(agp_bridge->dev, INTEL_I860_MCHCFG, &temp2);
1518 pci_write_config_word(agp_bridge->dev, INTEL_I860_MCHCFG, temp2 | (1 << 9));
1519 /* clear any possible AGP-related error conditions */
1520 pci_write_config_word(agp_bridge->dev, INTEL_I860_ERRSTS, 0xf700);
1524 static int intel_830mp_configure(void)
1528 struct aper_size_info_8 *current_size;
1530 current_size = A_SIZE_8(agp_bridge->current_size);
1533 pci_write_config_byte(agp_bridge->dev, INTEL_APSIZE, current_size->size_value);
1535 /* address to map to */
1536 pci_read_config_dword(agp_bridge->dev, AGP_APBASE, &temp);
1537 agp_bridge->gart_bus_addr = (temp & PCI_BASE_ADDRESS_MEM_MASK);
1539 /* attbase - aperture base */
1540 pci_write_config_dword(agp_bridge->dev, INTEL_ATTBASE, agp_bridge->gatt_bus_addr);
1543 pci_write_config_dword(agp_bridge->dev, INTEL_AGPCTRL, 0x0000);
1546 pci_read_config_word(agp_bridge->dev, INTEL_NBXCFG, &temp2);
1547 pci_write_config_word(agp_bridge->dev, INTEL_NBXCFG, temp2 | (1 << 9));
1548 /* clear any possible AGP-related error conditions */
1549 pci_write_config_word(agp_bridge->dev, INTEL_I830_ERRSTS, 0x1c);
1553 static int intel_7505_configure(void)
1557 struct aper_size_info_8 *current_size;
1559 current_size = A_SIZE_8(agp_bridge->current_size);
1562 pci_write_config_byte(agp_bridge->dev, INTEL_APSIZE, current_size->size_value);
1564 /* address to map to */
1565 pci_read_config_dword(agp_bridge->dev, AGP_APBASE, &temp);
1566 agp_bridge->gart_bus_addr = (temp & PCI_BASE_ADDRESS_MEM_MASK);
1568 /* attbase - aperture base */
1569 pci_write_config_dword(agp_bridge->dev, INTEL_ATTBASE, agp_bridge->gatt_bus_addr);
1572 pci_write_config_dword(agp_bridge->dev, INTEL_AGPCTRL, 0x0000);
1575 pci_read_config_word(agp_bridge->dev, INTEL_I7505_MCHCFG, &temp2);
1576 pci_write_config_word(agp_bridge->dev, INTEL_I7505_MCHCFG, temp2 | (1 << 9));
1581 /* Setup function */
1582 static const struct gatt_mask intel_generic_masks[] =
1584 {.mask = 0x00000017, .type = 0}
1587 static const struct aper_size_info_8 intel_815_sizes[2] =
1593 static const struct aper_size_info_8 intel_8xx_sizes[7] =
1596 {128, 32768, 5, 32},
1604 static const struct aper_size_info_16 intel_generic_sizes[7] =
1607 {128, 32768, 5, 32},
1615 static const struct aper_size_info_8 intel_830mp_sizes[4] =
1618 {128, 32768, 5, 32},
1623 static const struct agp_bridge_driver intel_generic_driver = {
1624 .owner = THIS_MODULE,
1625 .aperture_sizes = intel_generic_sizes,
1626 .size_type = U16_APER_SIZE,
1627 .num_aperture_sizes = 7,
1628 .configure = intel_configure,
1629 .fetch_size = intel_fetch_size,
1630 .cleanup = intel_cleanup,
1631 .tlb_flush = intel_tlbflush,
1632 .mask_memory = agp_generic_mask_memory,
1633 .masks = intel_generic_masks,
1634 .agp_enable = agp_generic_enable,
1635 .cache_flush = global_cache_flush,
1636 .create_gatt_table = agp_generic_create_gatt_table,
1637 .free_gatt_table = agp_generic_free_gatt_table,
1638 .insert_memory = agp_generic_insert_memory,
1639 .remove_memory = agp_generic_remove_memory,
1640 .alloc_by_type = agp_generic_alloc_by_type,
1641 .free_by_type = agp_generic_free_by_type,
1642 .agp_alloc_page = agp_generic_alloc_page,
1643 .agp_destroy_page = agp_generic_destroy_page,
1644 .agp_type_to_mask_type = agp_generic_type_to_mask_type,
1647 static const struct agp_bridge_driver intel_810_driver = {
1648 .owner = THIS_MODULE,
1649 .aperture_sizes = intel_i810_sizes,
1650 .size_type = FIXED_APER_SIZE,
1651 .num_aperture_sizes = 2,
1652 .needs_scratch_page = TRUE,
1653 .configure = intel_i810_configure,
1654 .fetch_size = intel_i810_fetch_size,
1655 .cleanup = intel_i810_cleanup,
1656 .tlb_flush = intel_i810_tlbflush,
1657 .mask_memory = intel_i810_mask_memory,
1658 .masks = intel_i810_masks,
1659 .agp_enable = intel_i810_agp_enable,
1660 .cache_flush = global_cache_flush,
1661 .create_gatt_table = agp_generic_create_gatt_table,
1662 .free_gatt_table = agp_generic_free_gatt_table,
1663 .insert_memory = intel_i810_insert_entries,
1664 .remove_memory = intel_i810_remove_entries,
1665 .alloc_by_type = intel_i810_alloc_by_type,
1666 .free_by_type = intel_i810_free_by_type,
1667 .agp_alloc_page = agp_generic_alloc_page,
1668 .agp_destroy_page = agp_generic_destroy_page,
1669 .agp_type_to_mask_type = agp_generic_type_to_mask_type,
1672 static const struct agp_bridge_driver intel_815_driver = {
1673 .owner = THIS_MODULE,
1674 .aperture_sizes = intel_815_sizes,
1675 .size_type = U8_APER_SIZE,
1676 .num_aperture_sizes = 2,
1677 .configure = intel_815_configure,
1678 .fetch_size = intel_815_fetch_size,
1679 .cleanup = intel_8xx_cleanup,
1680 .tlb_flush = intel_8xx_tlbflush,
1681 .mask_memory = agp_generic_mask_memory,
1682 .masks = intel_generic_masks,
1683 .agp_enable = agp_generic_enable,
1684 .cache_flush = global_cache_flush,
1685 .create_gatt_table = agp_generic_create_gatt_table,
1686 .free_gatt_table = agp_generic_free_gatt_table,
1687 .insert_memory = agp_generic_insert_memory,
1688 .remove_memory = agp_generic_remove_memory,
1689 .alloc_by_type = agp_generic_alloc_by_type,
1690 .free_by_type = agp_generic_free_by_type,
1691 .agp_alloc_page = agp_generic_alloc_page,
1692 .agp_destroy_page = agp_generic_destroy_page,
1693 .agp_type_to_mask_type = agp_generic_type_to_mask_type,
1696 static const struct agp_bridge_driver intel_830_driver = {
1697 .owner = THIS_MODULE,
1698 .aperture_sizes = intel_i830_sizes,
1699 .size_type = FIXED_APER_SIZE,
1700 .num_aperture_sizes = 4,
1701 .needs_scratch_page = TRUE,
1702 .configure = intel_i830_configure,
1703 .fetch_size = intel_i830_fetch_size,
1704 .cleanup = intel_i830_cleanup,
1705 .tlb_flush = intel_i810_tlbflush,
1706 .mask_memory = intel_i810_mask_memory,
1707 .masks = intel_i810_masks,
1708 .agp_enable = intel_i810_agp_enable,
1709 .cache_flush = global_cache_flush,
1710 .create_gatt_table = intel_i830_create_gatt_table,
1711 .free_gatt_table = intel_i830_free_gatt_table,
1712 .insert_memory = intel_i830_insert_entries,
1713 .remove_memory = intel_i830_remove_entries,
1714 .alloc_by_type = intel_i830_alloc_by_type,
1715 .free_by_type = intel_i810_free_by_type,
1716 .agp_alloc_page = agp_generic_alloc_page,
1717 .agp_destroy_page = agp_generic_destroy_page,
1718 .agp_type_to_mask_type = intel_i830_type_to_mask_type,
1719 .chipset_flush = intel_i830_chipset_flush,
1722 static const struct agp_bridge_driver intel_820_driver = {
1723 .owner = THIS_MODULE,
1724 .aperture_sizes = intel_8xx_sizes,
1725 .size_type = U8_APER_SIZE,
1726 .num_aperture_sizes = 7,
1727 .configure = intel_820_configure,
1728 .fetch_size = intel_8xx_fetch_size,
1729 .cleanup = intel_820_cleanup,
1730 .tlb_flush = intel_820_tlbflush,
1731 .mask_memory = agp_generic_mask_memory,
1732 .masks = intel_generic_masks,
1733 .agp_enable = agp_generic_enable,
1734 .cache_flush = global_cache_flush,
1735 .create_gatt_table = agp_generic_create_gatt_table,
1736 .free_gatt_table = agp_generic_free_gatt_table,
1737 .insert_memory = agp_generic_insert_memory,
1738 .remove_memory = agp_generic_remove_memory,
1739 .alloc_by_type = agp_generic_alloc_by_type,
1740 .free_by_type = agp_generic_free_by_type,
1741 .agp_alloc_page = agp_generic_alloc_page,
1742 .agp_destroy_page = agp_generic_destroy_page,
1743 .agp_type_to_mask_type = agp_generic_type_to_mask_type,
1746 static const struct agp_bridge_driver intel_830mp_driver = {
1747 .owner = THIS_MODULE,
1748 .aperture_sizes = intel_830mp_sizes,
1749 .size_type = U8_APER_SIZE,
1750 .num_aperture_sizes = 4,
1751 .configure = intel_830mp_configure,
1752 .fetch_size = intel_8xx_fetch_size,
1753 .cleanup = intel_8xx_cleanup,
1754 .tlb_flush = intel_8xx_tlbflush,
1755 .mask_memory = agp_generic_mask_memory,
1756 .masks = intel_generic_masks,
1757 .agp_enable = agp_generic_enable,
1758 .cache_flush = global_cache_flush,
1759 .create_gatt_table = agp_generic_create_gatt_table,
1760 .free_gatt_table = agp_generic_free_gatt_table,
1761 .insert_memory = agp_generic_insert_memory,
1762 .remove_memory = agp_generic_remove_memory,
1763 .alloc_by_type = agp_generic_alloc_by_type,
1764 .free_by_type = agp_generic_free_by_type,
1765 .agp_alloc_page = agp_generic_alloc_page,
1766 .agp_destroy_page = agp_generic_destroy_page,
1767 .agp_type_to_mask_type = agp_generic_type_to_mask_type,
1770 static const struct agp_bridge_driver intel_840_driver = {
1771 .owner = THIS_MODULE,
1772 .aperture_sizes = intel_8xx_sizes,
1773 .size_type = U8_APER_SIZE,
1774 .num_aperture_sizes = 7,
1775 .configure = intel_840_configure,
1776 .fetch_size = intel_8xx_fetch_size,
1777 .cleanup = intel_8xx_cleanup,
1778 .tlb_flush = intel_8xx_tlbflush,
1779 .mask_memory = agp_generic_mask_memory,
1780 .masks = intel_generic_masks,
1781 .agp_enable = agp_generic_enable,
1782 .cache_flush = global_cache_flush,
1783 .create_gatt_table = agp_generic_create_gatt_table,
1784 .free_gatt_table = agp_generic_free_gatt_table,
1785 .insert_memory = agp_generic_insert_memory,
1786 .remove_memory = agp_generic_remove_memory,
1787 .alloc_by_type = agp_generic_alloc_by_type,
1788 .free_by_type = agp_generic_free_by_type,
1789 .agp_alloc_page = agp_generic_alloc_page,
1790 .agp_destroy_page = agp_generic_destroy_page,
1791 .agp_type_to_mask_type = agp_generic_type_to_mask_type,
1794 static const struct agp_bridge_driver intel_845_driver = {
1795 .owner = THIS_MODULE,
1796 .aperture_sizes = intel_8xx_sizes,
1797 .size_type = U8_APER_SIZE,
1798 .num_aperture_sizes = 7,
1799 .configure = intel_845_configure,
1800 .fetch_size = intel_8xx_fetch_size,
1801 .cleanup = intel_8xx_cleanup,
1802 .tlb_flush = intel_8xx_tlbflush,
1803 .mask_memory = agp_generic_mask_memory,
1804 .masks = intel_generic_masks,
1805 .agp_enable = agp_generic_enable,
1806 .cache_flush = global_cache_flush,
1807 .create_gatt_table = agp_generic_create_gatt_table,
1808 .free_gatt_table = agp_generic_free_gatt_table,
1809 .insert_memory = agp_generic_insert_memory,
1810 .remove_memory = agp_generic_remove_memory,
1811 .alloc_by_type = agp_generic_alloc_by_type,
1812 .free_by_type = agp_generic_free_by_type,
1813 .agp_alloc_page = agp_generic_alloc_page,
1814 .agp_destroy_page = agp_generic_destroy_page,
1815 .agp_type_to_mask_type = agp_generic_type_to_mask_type,
1816 .chipset_flush = intel_i830_chipset_flush,
1819 static const struct agp_bridge_driver intel_850_driver = {
1820 .owner = THIS_MODULE,
1821 .aperture_sizes = intel_8xx_sizes,
1822 .size_type = U8_APER_SIZE,
1823 .num_aperture_sizes = 7,
1824 .configure = intel_850_configure,
1825 .fetch_size = intel_8xx_fetch_size,
1826 .cleanup = intel_8xx_cleanup,
1827 .tlb_flush = intel_8xx_tlbflush,
1828 .mask_memory = agp_generic_mask_memory,
1829 .masks = intel_generic_masks,
1830 .agp_enable = agp_generic_enable,
1831 .cache_flush = global_cache_flush,
1832 .create_gatt_table = agp_generic_create_gatt_table,
1833 .free_gatt_table = agp_generic_free_gatt_table,
1834 .insert_memory = agp_generic_insert_memory,
1835 .remove_memory = agp_generic_remove_memory,
1836 .alloc_by_type = agp_generic_alloc_by_type,
1837 .free_by_type = agp_generic_free_by_type,
1838 .agp_alloc_page = agp_generic_alloc_page,
1839 .agp_destroy_page = agp_generic_destroy_page,
1840 .agp_type_to_mask_type = agp_generic_type_to_mask_type,
1843 static const struct agp_bridge_driver intel_860_driver = {
1844 .owner = THIS_MODULE,
1845 .aperture_sizes = intel_8xx_sizes,
1846 .size_type = U8_APER_SIZE,
1847 .num_aperture_sizes = 7,
1848 .configure = intel_860_configure,
1849 .fetch_size = intel_8xx_fetch_size,
1850 .cleanup = intel_8xx_cleanup,
1851 .tlb_flush = intel_8xx_tlbflush,
1852 .mask_memory = agp_generic_mask_memory,
1853 .masks = intel_generic_masks,
1854 .agp_enable = agp_generic_enable,
1855 .cache_flush = global_cache_flush,
1856 .create_gatt_table = agp_generic_create_gatt_table,
1857 .free_gatt_table = agp_generic_free_gatt_table,
1858 .insert_memory = agp_generic_insert_memory,
1859 .remove_memory = agp_generic_remove_memory,
1860 .alloc_by_type = agp_generic_alloc_by_type,
1861 .free_by_type = agp_generic_free_by_type,
1862 .agp_alloc_page = agp_generic_alloc_page,
1863 .agp_destroy_page = agp_generic_destroy_page,
1864 .agp_type_to_mask_type = agp_generic_type_to_mask_type,
1867 static const struct agp_bridge_driver intel_915_driver = {
1868 .owner = THIS_MODULE,
1869 .aperture_sizes = intel_i830_sizes,
1870 .size_type = FIXED_APER_SIZE,
1871 .num_aperture_sizes = 4,
1872 .needs_scratch_page = TRUE,
1873 .configure = intel_i915_configure,
1874 .fetch_size = intel_i9xx_fetch_size,
1875 .cleanup = intel_i915_cleanup,
1876 .tlb_flush = intel_i810_tlbflush,
1877 .mask_memory = intel_i810_mask_memory,
1878 .masks = intel_i810_masks,
1879 .agp_enable = intel_i810_agp_enable,
1880 .cache_flush = global_cache_flush,
1881 .create_gatt_table = intel_i915_create_gatt_table,
1882 .free_gatt_table = intel_i830_free_gatt_table,
1883 .insert_memory = intel_i915_insert_entries,
1884 .remove_memory = intel_i915_remove_entries,
1885 .alloc_by_type = intel_i830_alloc_by_type,
1886 .free_by_type = intel_i810_free_by_type,
1887 .agp_alloc_page = agp_generic_alloc_page,
1888 .agp_destroy_page = agp_generic_destroy_page,
1889 .agp_type_to_mask_type = intel_i830_type_to_mask_type,
1890 .chipset_flush = intel_i915_chipset_flush,
1893 static const struct agp_bridge_driver intel_i965_driver = {
1894 .owner = THIS_MODULE,
1895 .aperture_sizes = intel_i830_sizes,
1896 .size_type = FIXED_APER_SIZE,
1897 .num_aperture_sizes = 4,
1898 .needs_scratch_page = TRUE,
1899 .configure = intel_i915_configure,
1900 .fetch_size = intel_i9xx_fetch_size,
1901 .cleanup = intel_i915_cleanup,
1902 .tlb_flush = intel_i810_tlbflush,
1903 .mask_memory = intel_i965_mask_memory,
1904 .masks = intel_i810_masks,
1905 .agp_enable = intel_i810_agp_enable,
1906 .cache_flush = global_cache_flush,
1907 .create_gatt_table = intel_i965_create_gatt_table,
1908 .free_gatt_table = intel_i830_free_gatt_table,
1909 .insert_memory = intel_i915_insert_entries,
1910 .remove_memory = intel_i915_remove_entries,
1911 .alloc_by_type = intel_i830_alloc_by_type,
1912 .free_by_type = intel_i810_free_by_type,
1913 .agp_alloc_page = agp_generic_alloc_page,
1914 .agp_destroy_page = agp_generic_destroy_page,
1915 .agp_type_to_mask_type = intel_i830_type_to_mask_type,
1916 .chipset_flush = intel_i915_chipset_flush,
1919 static const struct agp_bridge_driver intel_7505_driver = {
1920 .owner = THIS_MODULE,
1921 .aperture_sizes = intel_8xx_sizes,
1922 .size_type = U8_APER_SIZE,
1923 .num_aperture_sizes = 7,
1924 .configure = intel_7505_configure,
1925 .fetch_size = intel_8xx_fetch_size,
1926 .cleanup = intel_8xx_cleanup,
1927 .tlb_flush = intel_8xx_tlbflush,
1928 .mask_memory = agp_generic_mask_memory,
1929 .masks = intel_generic_masks,
1930 .agp_enable = agp_generic_enable,
1931 .cache_flush = global_cache_flush,
1932 .create_gatt_table = agp_generic_create_gatt_table,
1933 .free_gatt_table = agp_generic_free_gatt_table,
1934 .insert_memory = agp_generic_insert_memory,
1935 .remove_memory = agp_generic_remove_memory,
1936 .alloc_by_type = agp_generic_alloc_by_type,
1937 .free_by_type = agp_generic_free_by_type,
1938 .agp_alloc_page = agp_generic_alloc_page,
1939 .agp_destroy_page = agp_generic_destroy_page,
1940 .agp_type_to_mask_type = agp_generic_type_to_mask_type,
1943 static const struct agp_bridge_driver intel_g33_driver = {
1944 .owner = THIS_MODULE,
1945 .aperture_sizes = intel_i830_sizes,
1946 .size_type = FIXED_APER_SIZE,
1947 .num_aperture_sizes = 4,
1948 .needs_scratch_page = TRUE,
1949 .configure = intel_i915_configure,
1950 .fetch_size = intel_i9xx_fetch_size,
1951 .cleanup = intel_i915_cleanup,
1952 .tlb_flush = intel_i810_tlbflush,
1953 .mask_memory = intel_i965_mask_memory,
1954 .masks = intel_i810_masks,
1955 .agp_enable = intel_i810_agp_enable,
1956 .cache_flush = global_cache_flush,
1957 .create_gatt_table = intel_i915_create_gatt_table,
1958 .free_gatt_table = intel_i830_free_gatt_table,
1959 .insert_memory = intel_i915_insert_entries,
1960 .remove_memory = intel_i915_remove_entries,
1961 .alloc_by_type = intel_i830_alloc_by_type,
1962 .free_by_type = intel_i810_free_by_type,
1963 .agp_alloc_page = agp_generic_alloc_page,
1964 .agp_destroy_page = agp_generic_destroy_page,
1965 .agp_type_to_mask_type = intel_i830_type_to_mask_type,
1966 .chipset_flush = intel_i915_chipset_flush,
1969 static int find_gmch(u16 device)
1971 struct pci_dev *gmch_device;
1973 gmch_device = pci_get_device(PCI_VENDOR_ID_INTEL, device, NULL);
1974 if (gmch_device && PCI_FUNC(gmch_device->devfn) != 0) {
1975 gmch_device = pci_get_device(PCI_VENDOR_ID_INTEL,
1976 device, gmch_device);
1982 intel_private.pcidev = gmch_device;
1986 /* Table to describe Intel GMCH and AGP/PCIE GART drivers. At least one of
1987 * driver and gmch_driver must be non-null, and find_gmch will determine
1988 * which one should be used if a gmch_chip_id is present.
1990 static const struct intel_driver_description {
1991 unsigned int chip_id;
1992 unsigned int gmch_chip_id;
1993 unsigned int multi_gmch_chip; /* if we have more gfx chip type on this HB. */
1995 const struct agp_bridge_driver *driver;
1996 const struct agp_bridge_driver *gmch_driver;
1997 } intel_agp_chipsets[] = {
1998 { PCI_DEVICE_ID_INTEL_82443LX_0, 0, 0, "440LX", &intel_generic_driver, NULL },
1999 { PCI_DEVICE_ID_INTEL_82443BX_0, 0, 0, "440BX", &intel_generic_driver, NULL },
2000 { PCI_DEVICE_ID_INTEL_82443GX_0, 0, 0, "440GX", &intel_generic_driver, NULL },
2001 { PCI_DEVICE_ID_INTEL_82810_MC1, PCI_DEVICE_ID_INTEL_82810_IG1, 0, "i810",
2002 NULL, &intel_810_driver },
2003 { PCI_DEVICE_ID_INTEL_82810_MC3, PCI_DEVICE_ID_INTEL_82810_IG3, 0, "i810",
2004 NULL, &intel_810_driver },
2005 { PCI_DEVICE_ID_INTEL_82810E_MC, PCI_DEVICE_ID_INTEL_82810E_IG, 0, "i810",
2006 NULL, &intel_810_driver },
2007 { PCI_DEVICE_ID_INTEL_82815_MC, PCI_DEVICE_ID_INTEL_82815_CGC, 0, "i815",
2008 &intel_815_driver, &intel_810_driver },
2009 { PCI_DEVICE_ID_INTEL_82820_HB, 0, 0, "i820", &intel_820_driver, NULL },
2010 { PCI_DEVICE_ID_INTEL_82820_UP_HB, 0, 0, "i820", &intel_820_driver, NULL },
2011 { PCI_DEVICE_ID_INTEL_82830_HB, PCI_DEVICE_ID_INTEL_82830_CGC, 0, "830M",
2012 &intel_830mp_driver, &intel_830_driver },
2013 { PCI_DEVICE_ID_INTEL_82840_HB, 0, 0, "i840", &intel_840_driver, NULL },
2014 { PCI_DEVICE_ID_INTEL_82845_HB, 0, 0, "845G", &intel_845_driver, NULL },
2015 { PCI_DEVICE_ID_INTEL_82845G_HB, PCI_DEVICE_ID_INTEL_82845G_IG, 0, "830M",
2016 &intel_845_driver, &intel_830_driver },
2017 { PCI_DEVICE_ID_INTEL_82850_HB, 0, 0, "i850", &intel_850_driver, NULL },
2018 { PCI_DEVICE_ID_INTEL_82855PM_HB, 0, 0, "855PM", &intel_845_driver, NULL },
2019 { PCI_DEVICE_ID_INTEL_82855GM_HB, PCI_DEVICE_ID_INTEL_82855GM_IG, 0, "855GM",
2020 &intel_845_driver, &intel_830_driver },
2021 { PCI_DEVICE_ID_INTEL_82860_HB, 0, 0, "i860", &intel_860_driver, NULL },
2022 { PCI_DEVICE_ID_INTEL_82865_HB, PCI_DEVICE_ID_INTEL_82865_IG, 0, "865",
2023 &intel_845_driver, &intel_830_driver },
2024 { PCI_DEVICE_ID_INTEL_82875_HB, 0, 0, "i875", &intel_845_driver, NULL },
2025 { PCI_DEVICE_ID_INTEL_E7221_HB, PCI_DEVICE_ID_INTEL_E7221_IG, 0, "E7221 (i915)",
2026 NULL, &intel_915_driver },
2027 { PCI_DEVICE_ID_INTEL_82915G_HB, PCI_DEVICE_ID_INTEL_82915G_IG, 0, "915G",
2028 NULL, &intel_915_driver },
2029 { PCI_DEVICE_ID_INTEL_82915GM_HB, PCI_DEVICE_ID_INTEL_82915GM_IG, 0, "915GM",
2030 NULL, &intel_915_driver },
2031 { PCI_DEVICE_ID_INTEL_82945G_HB, PCI_DEVICE_ID_INTEL_82945G_IG, 0, "945G",
2032 NULL, &intel_915_driver },
2033 { PCI_DEVICE_ID_INTEL_82945GM_HB, PCI_DEVICE_ID_INTEL_82945GM_IG, 0, "945GM",
2034 NULL, &intel_915_driver },
2035 { PCI_DEVICE_ID_INTEL_82945GME_HB, PCI_DEVICE_ID_INTEL_82945GME_IG, 0, "945GME",
2036 NULL, &intel_915_driver },
2037 { PCI_DEVICE_ID_INTEL_82946GZ_HB, PCI_DEVICE_ID_INTEL_82946GZ_IG, 0, "946GZ",
2038 NULL, &intel_i965_driver },
2039 { PCI_DEVICE_ID_INTEL_82965G_1_HB, PCI_DEVICE_ID_INTEL_82965G_1_IG, 0, "965G",
2040 NULL, &intel_i965_driver },
2041 { PCI_DEVICE_ID_INTEL_82965Q_HB, PCI_DEVICE_ID_INTEL_82965Q_IG, 0, "965Q",
2042 NULL, &intel_i965_driver },
2043 { PCI_DEVICE_ID_INTEL_82965G_HB, PCI_DEVICE_ID_INTEL_82965G_IG, 0, "965G",
2044 NULL, &intel_i965_driver },
2045 { PCI_DEVICE_ID_INTEL_82965GM_HB, PCI_DEVICE_ID_INTEL_82965GM_IG, 0, "965GM",
2046 NULL, &intel_i965_driver },
2047 { PCI_DEVICE_ID_INTEL_82965GME_HB, PCI_DEVICE_ID_INTEL_82965GME_IG, 0, "965GME/GLE",
2048 NULL, &intel_i965_driver },
2049 { PCI_DEVICE_ID_INTEL_7505_0, 0, 0, "E7505", &intel_7505_driver, NULL },
2050 { PCI_DEVICE_ID_INTEL_7205_0, 0, 0, "E7205", &intel_7505_driver, NULL },
2051 { PCI_DEVICE_ID_INTEL_G33_HB, PCI_DEVICE_ID_INTEL_G33_IG, 0, "G33",
2052 NULL, &intel_g33_driver },
2053 { PCI_DEVICE_ID_INTEL_Q35_HB, PCI_DEVICE_ID_INTEL_Q35_IG, 0, "Q35",
2054 NULL, &intel_g33_driver },
2055 { PCI_DEVICE_ID_INTEL_Q33_HB, PCI_DEVICE_ID_INTEL_Q33_IG, 0, "Q33",
2056 NULL, &intel_g33_driver },
2057 { PCI_DEVICE_ID_INTEL_IGD_HB, PCI_DEVICE_ID_INTEL_IGD_IG, 0,
2058 "Intel Integrated Graphics Device", NULL, &intel_i965_driver },
2059 { 0, 0, 0, NULL, NULL, NULL }
2062 static int __devinit agp_intel_probe(struct pci_dev *pdev,
2063 const struct pci_device_id *ent)
2065 struct agp_bridge_data *bridge;
2070 cap_ptr = pci_find_capability(pdev, PCI_CAP_ID_AGP);
2072 bridge = agp_alloc_bridge();
2076 for (i = 0; intel_agp_chipsets[i].name != NULL; i++) {
2077 /* In case that multiple models of gfx chip may
2078 stand on same host bridge type, this can be
2079 sure we detect the right IGD. */
2080 if (pdev->device == intel_agp_chipsets[i].chip_id) {
2081 if ((intel_agp_chipsets[i].gmch_chip_id != 0) &&
2082 find_gmch(intel_agp_chipsets[i].gmch_chip_id)) {
2084 intel_agp_chipsets[i].gmch_driver;
2086 } else if (intel_agp_chipsets[i].multi_gmch_chip) {
2089 bridge->driver = intel_agp_chipsets[i].driver;
2095 if (intel_agp_chipsets[i].name == NULL) {
2097 printk(KERN_WARNING PFX "Unsupported Intel chipset"
2098 "(device id: %04x)\n", pdev->device);
2099 agp_put_bridge(bridge);
2103 if (bridge->driver == NULL) {
2104 /* bridge has no AGP and no IGD detected */
2106 printk(KERN_WARNING PFX "Failed to find bridge device "
2107 "(chip_id: %04x)\n",
2108 intel_agp_chipsets[i].gmch_chip_id);
2109 agp_put_bridge(bridge);
2114 bridge->capndx = cap_ptr;
2115 bridge->dev_private_data = &intel_private;
2117 printk(KERN_INFO PFX "Detected an Intel %s Chipset.\n",
2118 intel_agp_chipsets[i].name);
2121 * The following fixes the case where the BIOS has "forgotten" to
2122 * provide an address range for the GART.
2123 * 20030610 - hamish@zot.org
2125 r = &pdev->resource[0];
2126 if (!r->start && r->end) {
2127 if (pci_assign_resource(pdev, 0)) {
2128 printk(KERN_ERR PFX "could not assign resource 0\n");
2129 agp_put_bridge(bridge);
2135 * If the device has not been properly setup, the following will catch
2136 * the problem and should stop the system from crashing.
2137 * 20030610 - hamish@zot.org
2139 if (pci_enable_device(pdev)) {
2140 printk(KERN_ERR PFX "Unable to Enable PCI device\n");
2141 agp_put_bridge(bridge);
2145 /* Fill in the mode register */
2147 pci_read_config_dword(pdev,
2148 bridge->capndx+PCI_AGP_STATUS,
2152 pci_set_drvdata(pdev, bridge);
2153 return agp_add_bridge(bridge);
2156 static void __devexit agp_intel_remove(struct pci_dev *pdev)
2158 struct agp_bridge_data *bridge = pci_get_drvdata(pdev);
2160 agp_remove_bridge(bridge);
2162 if (intel_private.pcidev)
2163 pci_dev_put(intel_private.pcidev);
2165 agp_put_bridge(bridge);
2169 static int agp_intel_resume(struct pci_dev *pdev)
2171 struct agp_bridge_data *bridge = pci_get_drvdata(pdev);
2173 pci_restore_state(pdev);
2175 /* We should restore our graphics device's config space,
2176 * as host bridge (00:00) resumes before graphics device (02:00),
2177 * then our access to its pci space can work right.
2179 if (intel_private.pcidev)
2180 pci_restore_state(intel_private.pcidev);
2182 if (bridge->driver == &intel_generic_driver)
2184 else if (bridge->driver == &intel_850_driver)
2185 intel_850_configure();
2186 else if (bridge->driver == &intel_845_driver)
2187 intel_845_configure();
2188 else if (bridge->driver == &intel_830mp_driver)
2189 intel_830mp_configure();
2190 else if (bridge->driver == &intel_915_driver)
2191 intel_i915_configure();
2192 else if (bridge->driver == &intel_830_driver)
2193 intel_i830_configure();
2194 else if (bridge->driver == &intel_810_driver)
2195 intel_i810_configure();
2196 else if (bridge->driver == &intel_i965_driver)
2197 intel_i915_configure();
2203 static struct pci_device_id agp_intel_pci_table[] = {
2206 .class = (PCI_CLASS_BRIDGE_HOST << 8), \
2208 .vendor = PCI_VENDOR_ID_INTEL, \
2210 .subvendor = PCI_ANY_ID, \
2211 .subdevice = PCI_ANY_ID, \
2213 ID(PCI_DEVICE_ID_INTEL_82443LX_0),
2214 ID(PCI_DEVICE_ID_INTEL_82443BX_0),
2215 ID(PCI_DEVICE_ID_INTEL_82443GX_0),
2216 ID(PCI_DEVICE_ID_INTEL_82810_MC1),
2217 ID(PCI_DEVICE_ID_INTEL_82810_MC3),
2218 ID(PCI_DEVICE_ID_INTEL_82810E_MC),
2219 ID(PCI_DEVICE_ID_INTEL_82815_MC),
2220 ID(PCI_DEVICE_ID_INTEL_82820_HB),
2221 ID(PCI_DEVICE_ID_INTEL_82820_UP_HB),
2222 ID(PCI_DEVICE_ID_INTEL_82830_HB),
2223 ID(PCI_DEVICE_ID_INTEL_82840_HB),
2224 ID(PCI_DEVICE_ID_INTEL_82845_HB),
2225 ID(PCI_DEVICE_ID_INTEL_82845G_HB),
2226 ID(PCI_DEVICE_ID_INTEL_82850_HB),
2227 ID(PCI_DEVICE_ID_INTEL_82855PM_HB),
2228 ID(PCI_DEVICE_ID_INTEL_82855GM_HB),
2229 ID(PCI_DEVICE_ID_INTEL_82860_HB),
2230 ID(PCI_DEVICE_ID_INTEL_82865_HB),
2231 ID(PCI_DEVICE_ID_INTEL_82875_HB),
2232 ID(PCI_DEVICE_ID_INTEL_7505_0),
2233 ID(PCI_DEVICE_ID_INTEL_7205_0),
2234 ID(PCI_DEVICE_ID_INTEL_E7221_HB),
2235 ID(PCI_DEVICE_ID_INTEL_82915G_HB),
2236 ID(PCI_DEVICE_ID_INTEL_82915GM_HB),
2237 ID(PCI_DEVICE_ID_INTEL_82945G_HB),
2238 ID(PCI_DEVICE_ID_INTEL_82945GM_HB),
2239 ID(PCI_DEVICE_ID_INTEL_82945GME_HB),
2240 ID(PCI_DEVICE_ID_INTEL_82946GZ_HB),
2241 ID(PCI_DEVICE_ID_INTEL_82965G_1_HB),
2242 ID(PCI_DEVICE_ID_INTEL_82965Q_HB),
2243 ID(PCI_DEVICE_ID_INTEL_82965G_HB),
2244 ID(PCI_DEVICE_ID_INTEL_82965GM_HB),
2245 ID(PCI_DEVICE_ID_INTEL_82965GME_HB),
2246 ID(PCI_DEVICE_ID_INTEL_G33_HB),
2247 ID(PCI_DEVICE_ID_INTEL_Q35_HB),
2248 ID(PCI_DEVICE_ID_INTEL_Q33_HB),
2249 ID(PCI_DEVICE_ID_INTEL_IGD_HB),
2253 MODULE_DEVICE_TABLE(pci, agp_intel_pci_table);
2255 static struct pci_driver agp_intel_pci_driver = {
2256 .name = "agpgart-intel",
2257 .id_table = agp_intel_pci_table,
2258 .probe = agp_intel_probe,
2259 .remove = __devexit_p(agp_intel_remove),
2261 .resume = agp_intel_resume,
2265 static int __init agp_intel_init(void)
2269 return pci_register_driver(&agp_intel_pci_driver);
2272 static void __exit agp_intel_cleanup(void)
2274 pci_unregister_driver(&agp_intel_pci_driver);
2277 module_init(agp_intel_init);
2278 module_exit(agp_intel_cleanup);
2280 MODULE_AUTHOR("Dave Jones <davej@codemonkey.org.uk>");
2281 MODULE_LICENSE("GPL and additional rights");