2 * sata_svw.c - ServerWorks / Apple K2 SATA
4 * Maintained by: Benjamin Herrenschmidt <benh@kernel.crashing.org> and
5 * Jeff Garzik <jgarzik@pobox.com>
6 * Please ALWAYS copy linux-ide@vger.kernel.org
9 * Copyright 2003 Benjamin Herrenschmidt <benh@kernel.crashing.org>
11 * Bits from Jeff Garzik, Copyright RedHat, Inc.
13 * This driver probably works with non-Apple versions of the
17 * This program is free software; you can redistribute it and/or modify
18 * it under the terms of the GNU General Public License as published by
19 * the Free Software Foundation; either version 2, or (at your option)
22 * This program is distributed in the hope that it will be useful,
23 * but WITHOUT ANY WARRANTY; without even the implied warranty of
24 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
25 * GNU General Public License for more details.
27 * You should have received a copy of the GNU General Public License
28 * along with this program; see the file COPYING. If not, write to
29 * the Free Software Foundation, 675 Mass Ave, Cambridge, MA 02139, USA.
32 * libata documentation is available via 'make {ps|pdf}docs',
33 * as Documentation/DocBook/libata.*
35 * Hardware documentation available under NDA.
39 #include <linux/kernel.h>
40 #include <linux/module.h>
41 #include <linux/pci.h>
42 #include <linux/init.h>
43 #include <linux/blkdev.h>
44 #include <linux/delay.h>
45 #include <linux/interrupt.h>
46 #include <linux/device.h>
47 #include <scsi/scsi_host.h>
48 #include <scsi/scsi_cmnd.h>
49 #include <scsi/scsi.h>
50 #include <linux/libata.h>
54 #include <asm/pci-bridge.h>
55 #endif /* CONFIG_PPC_OF */
57 #define DRV_NAME "sata_svw"
58 #define DRV_VERSION "2.3"
62 K2_FLAG_SATA_8_PORTS = (1 << 24),
63 K2_FLAG_NO_ATAPI_DMA = (1 << 25),
64 K2_FLAG_BAR_POS_3 = (1 << 26),
66 /* Taskfile registers offsets */
67 K2_SATA_TF_CMD_OFFSET = 0x00,
68 K2_SATA_TF_DATA_OFFSET = 0x00,
69 K2_SATA_TF_ERROR_OFFSET = 0x04,
70 K2_SATA_TF_NSECT_OFFSET = 0x08,
71 K2_SATA_TF_LBAL_OFFSET = 0x0c,
72 K2_SATA_TF_LBAM_OFFSET = 0x10,
73 K2_SATA_TF_LBAH_OFFSET = 0x14,
74 K2_SATA_TF_DEVICE_OFFSET = 0x18,
75 K2_SATA_TF_CMDSTAT_OFFSET = 0x1c,
76 K2_SATA_TF_CTL_OFFSET = 0x20,
79 K2_SATA_DMA_CMD_OFFSET = 0x30,
82 K2_SATA_SCR_STATUS_OFFSET = 0x40,
83 K2_SATA_SCR_ERROR_OFFSET = 0x44,
84 K2_SATA_SCR_CONTROL_OFFSET = 0x48,
87 K2_SATA_SICR1_OFFSET = 0x80,
88 K2_SATA_SICR2_OFFSET = 0x84,
89 K2_SATA_SIM_OFFSET = 0x88,
92 K2_SATA_PORT_OFFSET = 0x100,
96 chip_svw42 = 2, /* bar 3 */
97 chip_svw43 = 3, /* bar 5 */
100 static u8 k2_stat_check_status(struct ata_port *ap);
103 static int k2_sata_check_atapi_dma(struct ata_queued_cmd *qc)
105 u8 cmnd = qc->scsicmd->cmnd[0];
107 if (qc->ap->flags & K2_FLAG_NO_ATAPI_DMA)
108 return -1; /* ATAPI DMA not supported */
126 static int k2_sata_scr_read(struct ata_port *ap, unsigned int sc_reg, u32 *val)
128 if (sc_reg > SCR_CONTROL)
130 *val = readl(ap->ioaddr.scr_addr + (sc_reg * 4));
135 static int k2_sata_scr_write(struct ata_port *ap, unsigned int sc_reg, u32 val)
137 if (sc_reg > SCR_CONTROL)
139 writel(val, ap->ioaddr.scr_addr + (sc_reg * 4));
144 static void k2_sata_tf_load(struct ata_port *ap, const struct ata_taskfile *tf)
146 struct ata_ioports *ioaddr = &ap->ioaddr;
147 unsigned int is_addr = tf->flags & ATA_TFLAG_ISADDR;
149 if (tf->ctl != ap->last_ctl) {
150 writeb(tf->ctl, ioaddr->ctl_addr);
151 ap->last_ctl = tf->ctl;
154 if (is_addr && (tf->flags & ATA_TFLAG_LBA48)) {
155 writew(tf->feature | (((u16)tf->hob_feature) << 8),
156 ioaddr->feature_addr);
157 writew(tf->nsect | (((u16)tf->hob_nsect) << 8),
159 writew(tf->lbal | (((u16)tf->hob_lbal) << 8),
161 writew(tf->lbam | (((u16)tf->hob_lbam) << 8),
163 writew(tf->lbah | (((u16)tf->hob_lbah) << 8),
165 } else if (is_addr) {
166 writew(tf->feature, ioaddr->feature_addr);
167 writew(tf->nsect, ioaddr->nsect_addr);
168 writew(tf->lbal, ioaddr->lbal_addr);
169 writew(tf->lbam, ioaddr->lbam_addr);
170 writew(tf->lbah, ioaddr->lbah_addr);
173 if (tf->flags & ATA_TFLAG_DEVICE)
174 writeb(tf->device, ioaddr->device_addr);
180 static void k2_sata_tf_read(struct ata_port *ap, struct ata_taskfile *tf)
182 struct ata_ioports *ioaddr = &ap->ioaddr;
183 u16 nsect, lbal, lbam, lbah, feature;
185 tf->command = k2_stat_check_status(ap);
186 tf->device = readw(ioaddr->device_addr);
187 feature = readw(ioaddr->error_addr);
188 nsect = readw(ioaddr->nsect_addr);
189 lbal = readw(ioaddr->lbal_addr);
190 lbam = readw(ioaddr->lbam_addr);
191 lbah = readw(ioaddr->lbah_addr);
193 tf->feature = feature;
199 if (tf->flags & ATA_TFLAG_LBA48) {
200 tf->hob_feature = feature >> 8;
201 tf->hob_nsect = nsect >> 8;
202 tf->hob_lbal = lbal >> 8;
203 tf->hob_lbam = lbam >> 8;
204 tf->hob_lbah = lbah >> 8;
209 * k2_bmdma_setup_mmio - Set up PCI IDE BMDMA transaction (MMIO)
210 * @qc: Info associated with this ATA transaction.
213 * spin_lock_irqsave(host lock)
216 static void k2_bmdma_setup_mmio(struct ata_queued_cmd *qc)
218 struct ata_port *ap = qc->ap;
219 unsigned int rw = (qc->tf.flags & ATA_TFLAG_WRITE);
221 void __iomem *mmio = ap->ioaddr.bmdma_addr;
223 /* load PRD table addr. */
224 mb(); /* make sure PRD table writes are visible to controller */
225 writel(ap->prd_dma, mmio + ATA_DMA_TABLE_OFS);
227 /* specify data direction, triple-check start bit is clear */
228 dmactl = readb(mmio + ATA_DMA_CMD);
229 dmactl &= ~(ATA_DMA_WR | ATA_DMA_START);
231 dmactl |= ATA_DMA_WR;
232 writeb(dmactl, mmio + ATA_DMA_CMD);
234 /* issue r/w command if this is not a ATA DMA command*/
235 if (qc->tf.protocol != ATA_PROT_DMA)
236 ap->ops->exec_command(ap, &qc->tf);
240 * k2_bmdma_start_mmio - Start a PCI IDE BMDMA transaction (MMIO)
241 * @qc: Info associated with this ATA transaction.
244 * spin_lock_irqsave(host lock)
247 static void k2_bmdma_start_mmio(struct ata_queued_cmd *qc)
249 struct ata_port *ap = qc->ap;
250 void __iomem *mmio = ap->ioaddr.bmdma_addr;
253 /* start host DMA transaction */
254 dmactl = readb(mmio + ATA_DMA_CMD);
255 writeb(dmactl | ATA_DMA_START, mmio + ATA_DMA_CMD);
256 /* There is a race condition in certain SATA controllers that can
257 be seen when the r/w command is given to the controller before the
258 host DMA is started. On a Read command, the controller would initiate
259 the command to the drive even before it sees the DMA start. When there
260 are very fast drives connected to the controller, or when the data request
261 hits in the drive cache, there is the possibility that the drive returns a part
262 or all of the requested data to the controller before the DMA start is issued.
263 In this case, the controller would become confused as to what to do with the data.
264 In the worst case when all the data is returned back to the controller, the
265 controller could hang. In other cases it could return partial data returning
266 in data corruption. This problem has been seen in PPC systems and can also appear
267 on an system with very fast disks, where the SATA controller is sitting behind a
268 number of bridges, and hence there is significant latency between the r/w command
269 and the start command. */
270 /* issue r/w command if the access is to ATA*/
271 if (qc->tf.protocol == ATA_PROT_DMA)
272 ap->ops->exec_command(ap, &qc->tf);
276 static u8 k2_stat_check_status(struct ata_port *ap)
278 return readl(ap->ioaddr.status_addr);
284 * inout : decides on the direction of the dataflow and the meaning of the
286 * buffer: If inout==FALSE data is being written to it else read from it
287 * *start: If inout==FALSE start of the valid data in the buffer
288 * offset: If inout==FALSE offset from the beginning of the imaginary file
289 * from which we start writing into the buffer
290 * length: If inout==FALSE max number of bytes to be written into the buffer
291 * else number of bytes in the buffer
293 static int k2_sata_proc_info(struct Scsi_Host *shost, char *page, char **start,
294 off_t offset, int count, int inout)
297 struct device_node *np;
300 /* Find the ata_port */
301 ap = ata_shost_to_port(shost);
305 /* Find the OF node for the PCI device proper */
306 np = pci_device_to_OF_node(to_pci_dev(ap->host->dev));
310 /* Match it to a port node */
311 index = (ap == ap->host->ports[0]) ? 0 : 1;
312 for (np = np->child; np != NULL; np = np->sibling) {
313 const u32 *reg = of_get_property(np, "reg", NULL);
322 len = sprintf(page, "devspec: %s\n", np->full_name);
326 #endif /* CONFIG_PPC_OF */
329 static struct scsi_host_template k2_sata_sht = {
330 ATA_BMDMA_SHT(DRV_NAME),
332 .proc_info = k2_sata_proc_info,
337 static const struct ata_port_operations k2_sata_ops = {
338 .tf_load = k2_sata_tf_load,
339 .tf_read = k2_sata_tf_read,
340 .check_status = k2_stat_check_status,
341 .exec_command = ata_exec_command,
342 .dev_select = ata_std_dev_select,
343 .check_atapi_dma = k2_sata_check_atapi_dma,
344 .bmdma_setup = k2_bmdma_setup_mmio,
345 .bmdma_start = k2_bmdma_start_mmio,
346 .bmdma_stop = ata_bmdma_stop,
347 .bmdma_status = ata_bmdma_status,
348 .qc_prep = ata_qc_prep,
349 .qc_issue = ata_qc_issue_prot,
350 .data_xfer = ata_data_xfer,
351 .mode_filter = ata_pci_default_filter,
352 .freeze = ata_bmdma_freeze,
353 .thaw = ata_bmdma_thaw,
354 .error_handler = ata_bmdma_error_handler,
355 .post_internal_cmd = ata_bmdma_post_internal_cmd,
356 .irq_clear = ata_bmdma_irq_clear,
357 .irq_on = ata_irq_on,
358 .scr_read = k2_sata_scr_read,
359 .scr_write = k2_sata_scr_write,
360 .port_start = ata_sff_port_start,
363 static const struct ata_port_info k2_port_info[] = {
366 .flags = ATA_FLAG_SATA | ATA_FLAG_NO_LEGACY |
367 ATA_FLAG_MMIO | K2_FLAG_NO_ATAPI_DMA,
370 .udma_mask = ATA_UDMA6,
371 .port_ops = &k2_sata_ops,
375 .flags = ATA_FLAG_SATA | ATA_FLAG_NO_LEGACY |
376 ATA_FLAG_MMIO | K2_FLAG_NO_ATAPI_DMA |
377 K2_FLAG_SATA_8_PORTS,
380 .udma_mask = ATA_UDMA6,
381 .port_ops = &k2_sata_ops,
385 .flags = ATA_FLAG_SATA | ATA_FLAG_NO_LEGACY |
386 ATA_FLAG_MMIO | K2_FLAG_BAR_POS_3,
389 .udma_mask = ATA_UDMA6,
390 .port_ops = &k2_sata_ops,
394 .flags = ATA_FLAG_SATA | ATA_FLAG_NO_LEGACY |
398 .udma_mask = ATA_UDMA6,
399 .port_ops = &k2_sata_ops,
403 static void k2_sata_setup_port(struct ata_ioports *port, void __iomem *base)
405 port->cmd_addr = base + K2_SATA_TF_CMD_OFFSET;
406 port->data_addr = base + K2_SATA_TF_DATA_OFFSET;
408 port->error_addr = base + K2_SATA_TF_ERROR_OFFSET;
409 port->nsect_addr = base + K2_SATA_TF_NSECT_OFFSET;
410 port->lbal_addr = base + K2_SATA_TF_LBAL_OFFSET;
411 port->lbam_addr = base + K2_SATA_TF_LBAM_OFFSET;
412 port->lbah_addr = base + K2_SATA_TF_LBAH_OFFSET;
413 port->device_addr = base + K2_SATA_TF_DEVICE_OFFSET;
415 port->status_addr = base + K2_SATA_TF_CMDSTAT_OFFSET;
416 port->altstatus_addr =
417 port->ctl_addr = base + K2_SATA_TF_CTL_OFFSET;
418 port->bmdma_addr = base + K2_SATA_DMA_CMD_OFFSET;
419 port->scr_addr = base + K2_SATA_SCR_STATUS_OFFSET;
423 static int k2_sata_init_one(struct pci_dev *pdev, const struct pci_device_id *ent)
425 static int printed_version;
426 const struct ata_port_info *ppi[] =
427 { &k2_port_info[ent->driver_data], NULL };
428 struct ata_host *host;
429 void __iomem *mmio_base;
430 int n_ports, i, rc, bar_pos;
432 if (!printed_version++)
433 dev_printk(KERN_DEBUG, &pdev->dev, "version " DRV_VERSION "\n");
437 if (ppi[0]->flags & K2_FLAG_SATA_8_PORTS)
440 host = ata_host_alloc_pinfo(&pdev->dev, ppi, n_ports);
445 if (ppi[0]->flags & K2_FLAG_BAR_POS_3)
448 * If this driver happens to only be useful on Apple's K2, then
449 * we should check that here as it has a normal Serverworks ID
451 rc = pcim_enable_device(pdev);
456 * Check if we have resources mapped at all (second function may
457 * have been disabled by firmware)
459 if (pci_resource_len(pdev, bar_pos) == 0) {
460 /* In IDE mode we need to pin the device to ensure that
461 pcim_release does not clear the busmaster bit in config
462 space, clearing causes busmaster DMA to fail on
464 pcim_pin_device(pdev);
468 /* Request and iomap PCI regions */
469 rc = pcim_iomap_regions(pdev, 1 << bar_pos, DRV_NAME);
471 pcim_pin_device(pdev);
474 host->iomap = pcim_iomap_table(pdev);
475 mmio_base = host->iomap[bar_pos];
477 /* different controllers have different number of ports - currently 4 or 8 */
478 /* All ports are on the same function. Multi-function device is no
479 * longer available. This should not be seen in any system. */
480 for (i = 0; i < host->n_ports; i++) {
481 struct ata_port *ap = host->ports[i];
482 unsigned int offset = i * K2_SATA_PORT_OFFSET;
484 k2_sata_setup_port(&ap->ioaddr, mmio_base + offset);
486 ata_port_pbar_desc(ap, 5, -1, "mmio");
487 ata_port_pbar_desc(ap, 5, offset, "port");
490 rc = pci_set_dma_mask(pdev, ATA_DMA_MASK);
493 rc = pci_set_consistent_dma_mask(pdev, ATA_DMA_MASK);
497 /* Clear a magic bit in SCR1 according to Darwin, those help
498 * some funky seagate drives (though so far, those were already
499 * set by the firmware on the machines I had access to)
501 writel(readl(mmio_base + K2_SATA_SICR1_OFFSET) & ~0x00040000,
502 mmio_base + K2_SATA_SICR1_OFFSET);
504 /* Clear SATA error & interrupts we don't use */
505 writel(0xffffffff, mmio_base + K2_SATA_SCR_ERROR_OFFSET);
506 writel(0x0, mmio_base + K2_SATA_SIM_OFFSET);
508 pci_set_master(pdev);
509 return ata_host_activate(host, pdev->irq, ata_interrupt, IRQF_SHARED,
513 /* 0x240 is device ID for Apple K2 device
514 * 0x241 is device ID for Serverworks Frodo4
515 * 0x242 is device ID for Serverworks Frodo8
516 * 0x24a is device ID for BCM5785 (aka HT1000) HT southbridge integrated SATA
519 static const struct pci_device_id k2_sata_pci_tbl[] = {
520 { PCI_VDEVICE(SERVERWORKS, 0x0240), chip_svw4 },
521 { PCI_VDEVICE(SERVERWORKS, 0x0241), chip_svw8 },
522 { PCI_VDEVICE(SERVERWORKS, 0x0242), chip_svw4 },
523 { PCI_VDEVICE(SERVERWORKS, 0x024a), chip_svw4 },
524 { PCI_VDEVICE(SERVERWORKS, 0x024b), chip_svw4 },
525 { PCI_VDEVICE(SERVERWORKS, 0x0410), chip_svw42 },
526 { PCI_VDEVICE(SERVERWORKS, 0x0411), chip_svw43 },
531 static struct pci_driver k2_sata_pci_driver = {
533 .id_table = k2_sata_pci_tbl,
534 .probe = k2_sata_init_one,
535 .remove = ata_pci_remove_one,
538 static int __init k2_sata_init(void)
540 return pci_register_driver(&k2_sata_pci_driver);
543 static void __exit k2_sata_exit(void)
545 pci_unregister_driver(&k2_sata_pci_driver);
548 MODULE_AUTHOR("Benjamin Herrenschmidt");
549 MODULE_DESCRIPTION("low-level driver for K2 SATA controller");
550 MODULE_LICENSE("GPL");
551 MODULE_DEVICE_TABLE(pci, k2_sata_pci_tbl);
552 MODULE_VERSION(DRV_VERSION);
554 module_init(k2_sata_init);
555 module_exit(k2_sata_exit);