2 * sata_sis.c - Silicon Integrated Systems SATA
4 * Maintained by: Uwe Koziolek
5 * Please ALWAYS copy linux-ide@vger.kernel.org
8 * Copyright 2004 Uwe Koziolek
11 * This program is free software; you can redistribute it and/or modify
12 * it under the terms of the GNU General Public License as published by
13 * the Free Software Foundation; either version 2, or (at your option)
16 * This program is distributed in the hope that it will be useful,
17 * but WITHOUT ANY WARRANTY; without even the implied warranty of
18 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
19 * GNU General Public License for more details.
21 * You should have received a copy of the GNU General Public License
22 * along with this program; see the file COPYING. If not, write to
23 * the Free Software Foundation, 675 Mass Ave, Cambridge, MA 02139, USA.
26 * libata documentation is available via 'make {ps|pdf}docs',
27 * as Documentation/DocBook/libata.*
29 * Hardware documentation available under NDA.
33 #include <linux/kernel.h>
34 #include <linux/module.h>
35 #include <linux/pci.h>
36 #include <linux/init.h>
37 #include <linux/blkdev.h>
38 #include <linux/delay.h>
39 #include <linux/interrupt.h>
40 #include <linux/device.h>
41 #include <scsi/scsi_host.h>
42 #include <linux/libata.h>
45 #undef DRV_NAME /* already defined in libata.h, for libata-core */
46 #define DRV_NAME "sata_sis"
47 #define DRV_VERSION "0.7"
53 /* PCI configuration registers */
54 SIS_GENCTL = 0x54, /* IDE General Control register */
55 SIS_SCR_BASE = 0xc0, /* sata0 phy SCR registers */
56 SIS180_SATA1_OFS = 0x10, /* offset from sata0->sata1 phy regs */
57 SIS182_SATA1_OFS = 0x20, /* offset from sata0->sata1 phy regs */
58 SIS_PMR = 0x90, /* port mapping register */
59 SIS_PMR_COMBINED = 0x30,
62 SIS_FLAG_CFGSCR = (1 << 30), /* host flag: SCRs via PCI cfg */
64 GENCTL_IOMAPPED_SCR = (1 << 26), /* if set, SCRs are in IO space */
67 static int sis_init_one (struct pci_dev *pdev, const struct pci_device_id *ent);
68 static u32 sis_scr_read (struct ata_port *ap, unsigned int sc_reg);
69 static void sis_scr_write (struct ata_port *ap, unsigned int sc_reg, u32 val);
71 static const struct pci_device_id sis_pci_tbl[] = {
72 { PCI_VDEVICE(SI, 0x0180), sis_180 }, /* SiS 964/180 */
73 { PCI_VDEVICE(SI, 0x0181), sis_180 }, /* SiS 964/180 */
74 { PCI_VDEVICE(SI, 0x0182), sis_180 }, /* SiS 965/965L */
75 { PCI_VDEVICE(SI, 0x0183), sis_180 }, /* SiS 965/965L */
76 { PCI_VDEVICE(SI, 0x1182), sis_180 }, /* SiS 966/966L */
77 { PCI_VDEVICE(SI, 0x1183), sis_180 }, /* SiS 966/966L */
79 { } /* terminate list */
82 static struct pci_driver sis_pci_driver = {
84 .id_table = sis_pci_tbl,
85 .probe = sis_init_one,
86 .remove = ata_pci_remove_one,
89 static struct scsi_host_template sis_sht = {
90 .module = THIS_MODULE,
92 .ioctl = ata_scsi_ioctl,
93 .queuecommand = ata_scsi_queuecmd,
94 .can_queue = ATA_DEF_QUEUE,
95 .this_id = ATA_SHT_THIS_ID,
96 .sg_tablesize = ATA_MAX_PRD,
97 .cmd_per_lun = ATA_SHT_CMD_PER_LUN,
98 .emulated = ATA_SHT_EMULATED,
99 .use_clustering = ATA_SHT_USE_CLUSTERING,
100 .proc_name = DRV_NAME,
101 .dma_boundary = ATA_DMA_BOUNDARY,
102 .slave_configure = ata_scsi_slave_config,
103 .slave_destroy = ata_scsi_slave_destroy,
104 .bios_param = ata_std_bios_param,
107 static const struct ata_port_operations sis_ops = {
108 .port_disable = ata_port_disable,
109 .tf_load = ata_tf_load,
110 .tf_read = ata_tf_read,
111 .check_status = ata_check_status,
112 .exec_command = ata_exec_command,
113 .dev_select = ata_std_dev_select,
114 .bmdma_setup = ata_bmdma_setup,
115 .bmdma_start = ata_bmdma_start,
116 .bmdma_stop = ata_bmdma_stop,
117 .bmdma_status = ata_bmdma_status,
118 .qc_prep = ata_qc_prep,
119 .qc_issue = ata_qc_issue_prot,
120 .data_xfer = ata_data_xfer,
121 .freeze = ata_bmdma_freeze,
122 .thaw = ata_bmdma_thaw,
123 .error_handler = ata_bmdma_error_handler,
124 .post_internal_cmd = ata_bmdma_post_internal_cmd,
125 .irq_handler = ata_interrupt,
126 .irq_clear = ata_bmdma_irq_clear,
127 .irq_on = ata_irq_on,
128 .irq_ack = ata_irq_ack,
129 .scr_read = sis_scr_read,
130 .scr_write = sis_scr_write,
131 .port_start = ata_port_start,
134 static struct ata_port_info sis_port_info = {
136 .flags = ATA_FLAG_SATA | ATA_FLAG_NO_LEGACY,
140 .port_ops = &sis_ops,
143 MODULE_AUTHOR("Uwe Koziolek");
144 MODULE_DESCRIPTION("low-level driver for Silicon Integratad Systems SATA controller");
145 MODULE_LICENSE("GPL");
146 MODULE_DEVICE_TABLE(pci, sis_pci_tbl);
147 MODULE_VERSION(DRV_VERSION);
149 static unsigned int get_scr_cfg_addr(struct ata_port *ap, unsigned int sc_reg)
151 struct pci_dev *pdev = to_pci_dev(ap->host->dev);
152 unsigned int addr = SIS_SCR_BASE + (4 * sc_reg);
156 switch (pdev->device) {
159 pci_read_config_byte(pdev, SIS_PMR, &pmr);
160 if ((pmr & SIS_PMR_COMBINED) == 0)
161 addr += SIS180_SATA1_OFS;
168 addr += SIS182_SATA1_OFS;
175 static u32 sis_scr_cfg_read (struct ata_port *ap, unsigned int sc_reg)
177 struct pci_dev *pdev = to_pci_dev(ap->host->dev);
178 unsigned int cfg_addr = get_scr_cfg_addr(ap, sc_reg);
182 if (sc_reg == SCR_ERROR) /* doesn't exist in PCI cfg space */
185 pci_read_config_byte(pdev, SIS_PMR, &pmr);
187 pci_read_config_dword(pdev, cfg_addr, &val);
189 if ((pdev->device == 0x0182) || (pdev->device == 0x0183) || (pdev->device == 0x1182) ||
190 (pdev->device == 0x1183) || (pmr & SIS_PMR_COMBINED))
191 pci_read_config_dword(pdev, cfg_addr+0x10, &val2);
193 return (val|val2) & 0xfffffffb; /* avoid problems with powerdowned ports */
196 static void sis_scr_cfg_write (struct ata_port *ap, unsigned int sc_reg, u32 val)
198 struct pci_dev *pdev = to_pci_dev(ap->host->dev);
199 unsigned int cfg_addr = get_scr_cfg_addr(ap, sc_reg);
202 if (sc_reg == SCR_ERROR) /* doesn't exist in PCI cfg space */
205 pci_read_config_byte(pdev, SIS_PMR, &pmr);
207 pci_write_config_dword(pdev, cfg_addr, val);
209 if ((pdev->device == 0x0182) || (pdev->device == 0x0183) || (pdev->device == 0x1182) ||
210 (pdev->device == 0x1183) || (pmr & SIS_PMR_COMBINED))
211 pci_write_config_dword(pdev, cfg_addr+0x10, val);
214 static u32 sis_scr_read (struct ata_port *ap, unsigned int sc_reg)
216 struct pci_dev *pdev = to_pci_dev(ap->host->dev);
220 if (sc_reg > SCR_CONTROL)
223 if (ap->flags & SIS_FLAG_CFGSCR)
224 return sis_scr_cfg_read(ap, sc_reg);
226 pci_read_config_byte(pdev, SIS_PMR, &pmr);
228 val = ioread32(ap->ioaddr.scr_addr + (sc_reg * 4));
230 if ((pdev->device == 0x0182) || (pdev->device == 0x0183) || (pdev->device == 0x1182) ||
231 (pdev->device == 0x1183) || (pmr & SIS_PMR_COMBINED))
232 val2 = ioread32(ap->ioaddr.scr_addr + (sc_reg * 4) + 0x10);
234 return (val | val2) & 0xfffffffb;
237 static void sis_scr_write (struct ata_port *ap, unsigned int sc_reg, u32 val)
239 struct pci_dev *pdev = to_pci_dev(ap->host->dev);
242 if (sc_reg > SCR_CONTROL)
245 pci_read_config_byte(pdev, SIS_PMR, &pmr);
247 if (ap->flags & SIS_FLAG_CFGSCR)
248 sis_scr_cfg_write(ap, sc_reg, val);
250 iowrite32(val, ap->ioaddr.scr_addr + (sc_reg * 4));
251 if ((pdev->device == 0x0182) || (pdev->device == 0x0183) || (pdev->device == 0x1182) ||
252 (pdev->device == 0x1183) || (pmr & SIS_PMR_COMBINED))
253 iowrite32(val, ap->ioaddr.scr_addr + (sc_reg * 4)+0x10);
257 static int sis_init_one (struct pci_dev *pdev, const struct pci_device_id *ent)
259 static int printed_version;
260 struct ata_probe_ent *probe_ent = NULL;
263 struct ata_port_info pi = sis_port_info, *ppi[2] = { &pi, &pi };
265 u8 port2_start = 0x20;
267 if (!printed_version++)
268 dev_printk(KERN_INFO, &pdev->dev, "version " DRV_VERSION "\n");
270 rc = pcim_enable_device(pdev);
274 rc = pci_request_regions(pdev, DRV_NAME);
276 pcim_pin_device(pdev);
280 rc = pci_set_dma_mask(pdev, ATA_DMA_MASK);
283 rc = pci_set_consistent_dma_mask(pdev, ATA_DMA_MASK);
287 /* check and see if the SCRs are in IO space or PCI cfg space */
288 pci_read_config_dword(pdev, SIS_GENCTL, &genctl);
289 if ((genctl & GENCTL_IOMAPPED_SCR) == 0)
290 pi.flags |= SIS_FLAG_CFGSCR;
292 /* if hardware thinks SCRs are in IO space, but there are
293 * no IO resources assigned, change to PCI cfg space.
295 if ((!(pi.flags & SIS_FLAG_CFGSCR)) &&
296 ((pci_resource_start(pdev, SIS_SCR_PCI_BAR) == 0) ||
297 (pci_resource_len(pdev, SIS_SCR_PCI_BAR) < 128))) {
298 genctl &= ~GENCTL_IOMAPPED_SCR;
299 pci_write_config_dword(pdev, SIS_GENCTL, genctl);
300 pi.flags |= SIS_FLAG_CFGSCR;
303 pci_read_config_byte(pdev, SIS_PMR, &pmr);
304 switch (ent->device) {
308 /* The PATA-handling is provided by pata_sis */
309 switch (pmr & 0x30) {
311 ppi[1] = &sis_info133;
315 ppi[0] = &sis_info133;
318 if ((pmr & SIS_PMR_COMBINED) == 0) {
319 dev_printk(KERN_INFO, &pdev->dev,
320 "Detected SiS 180/181/964 chipset in SATA mode\n");
323 dev_printk(KERN_INFO, &pdev->dev,
324 "Detected SiS 180/181 chipset in combined mode\n");
326 pi.flags |= ATA_FLAG_SLAVE_POSS;
332 pci_read_config_dword ( pdev, 0x6C, &val);
333 if (val & (1L << 31)) {
334 dev_printk(KERN_INFO, &pdev->dev, "Detected SiS 182/965 chipset\n");
335 pi.flags |= ATA_FLAG_SLAVE_POSS;
337 dev_printk(KERN_INFO, &pdev->dev, "Detected SiS 182/965L chipset\n");
343 pci_read_config_dword(pdev, 0x64, &val);
344 if (val & 0x10000000) {
345 dev_printk(KERN_INFO, &pdev->dev, "Detected SiS 1182/1183/966L SATA controller\n");
347 dev_printk(KERN_INFO, &pdev->dev, "Detected SiS 1182/1183/966 SATA controller\n");
348 pi.flags |= ATA_FLAG_SLAVE_POSS;
353 probe_ent = ata_pci_init_native_mode(pdev, ppi, ATA_PORT_PRIMARY | ATA_PORT_SECONDARY);
357 if (!(probe_ent->port_flags & SIS_FLAG_CFGSCR)) {
360 mmio = pcim_iomap(pdev, SIS_SCR_PCI_BAR, 0);
364 probe_ent->port[0].scr_addr = mmio;
365 probe_ent->port[1].scr_addr = mmio + port2_start;
368 pci_set_master(pdev);
371 if (!ata_device_add(probe_ent))
374 devm_kfree(&pdev->dev, probe_ent);
379 static int __init sis_init(void)
381 return pci_register_driver(&sis_pci_driver);
384 static void __exit sis_exit(void)
386 pci_unregister_driver(&sis_pci_driver);
389 module_init(sis_init);
390 module_exit(sis_exit);