2 * sata_sis.c - Silicon Integrated Systems SATA
4 * Maintained by: Uwe Koziolek
5 * Please ALWAYS copy linux-ide@vger.kernel.org
8 * Copyright 2004 Uwe Koziolek
11 * This program is free software; you can redistribute it and/or modify
12 * it under the terms of the GNU General Public License as published by
13 * the Free Software Foundation; either version 2, or (at your option)
16 * This program is distributed in the hope that it will be useful,
17 * but WITHOUT ANY WARRANTY; without even the implied warranty of
18 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
19 * GNU General Public License for more details.
21 * You should have received a copy of the GNU General Public License
22 * along with this program; see the file COPYING. If not, write to
23 * the Free Software Foundation, 675 Mass Ave, Cambridge, MA 02139, USA.
26 * libata documentation is available via 'make {ps|pdf}docs',
27 * as Documentation/DocBook/libata.*
29 * Hardware documentation available under NDA.
33 #include <linux/kernel.h>
34 #include <linux/module.h>
35 #include <linux/pci.h>
36 #include <linux/init.h>
37 #include <linux/blkdev.h>
38 #include <linux/delay.h>
39 #include <linux/interrupt.h>
40 #include <linux/device.h>
41 #include <scsi/scsi_host.h>
42 #include <linux/libata.h>
44 #define DRV_NAME "sata_sis"
45 #define DRV_VERSION "0.7"
51 /* PCI configuration registers */
52 SIS_GENCTL = 0x54, /* IDE General Control register */
53 SIS_SCR_BASE = 0xc0, /* sata0 phy SCR registers */
54 SIS180_SATA1_OFS = 0x10, /* offset from sata0->sata1 phy regs */
55 SIS182_SATA1_OFS = 0x20, /* offset from sata0->sata1 phy regs */
56 SIS_PMR = 0x90, /* port mapping register */
57 SIS_PMR_COMBINED = 0x30,
60 SIS_FLAG_CFGSCR = (1 << 30), /* host flag: SCRs via PCI cfg */
62 GENCTL_IOMAPPED_SCR = (1 << 26), /* if set, SCRs are in IO space */
65 static int sis_init_one (struct pci_dev *pdev, const struct pci_device_id *ent);
66 static u32 sis_scr_read (struct ata_port *ap, unsigned int sc_reg);
67 static void sis_scr_write (struct ata_port *ap, unsigned int sc_reg, u32 val);
69 static const struct pci_device_id sis_pci_tbl[] = {
70 { PCI_VDEVICE(SI, 0x0180), sis_180 }, /* SiS 964/180 */
71 { PCI_VDEVICE(SI, 0x0181), sis_180 }, /* SiS 964/180 */
72 { PCI_VDEVICE(SI, 0x0182), sis_180 }, /* SiS 965/965L */
73 { PCI_VDEVICE(SI, 0x0183), sis_180 }, /* SiS 965/965L */
74 { PCI_VDEVICE(SI, 0x1182), sis_180 }, /* SiS 966/966L */
75 { PCI_VDEVICE(SI, 0x1183), sis_180 }, /* SiS 966/966L */
77 { } /* terminate list */
80 static struct pci_driver sis_pci_driver = {
82 .id_table = sis_pci_tbl,
83 .probe = sis_init_one,
84 .remove = ata_pci_remove_one,
87 static struct scsi_host_template sis_sht = {
88 .module = THIS_MODULE,
90 .ioctl = ata_scsi_ioctl,
91 .queuecommand = ata_scsi_queuecmd,
92 .can_queue = ATA_DEF_QUEUE,
93 .this_id = ATA_SHT_THIS_ID,
94 .sg_tablesize = ATA_MAX_PRD,
95 .cmd_per_lun = ATA_SHT_CMD_PER_LUN,
96 .emulated = ATA_SHT_EMULATED,
97 .use_clustering = ATA_SHT_USE_CLUSTERING,
98 .proc_name = DRV_NAME,
99 .dma_boundary = ATA_DMA_BOUNDARY,
100 .slave_configure = ata_scsi_slave_config,
101 .slave_destroy = ata_scsi_slave_destroy,
102 .bios_param = ata_std_bios_param,
105 static const struct ata_port_operations sis_ops = {
106 .port_disable = ata_port_disable,
107 .tf_load = ata_tf_load,
108 .tf_read = ata_tf_read,
109 .check_status = ata_check_status,
110 .exec_command = ata_exec_command,
111 .dev_select = ata_std_dev_select,
112 .bmdma_setup = ata_bmdma_setup,
113 .bmdma_start = ata_bmdma_start,
114 .bmdma_stop = ata_bmdma_stop,
115 .bmdma_status = ata_bmdma_status,
116 .qc_prep = ata_qc_prep,
117 .qc_issue = ata_qc_issue_prot,
118 .data_xfer = ata_pio_data_xfer,
119 .freeze = ata_bmdma_freeze,
120 .thaw = ata_bmdma_thaw,
121 .error_handler = ata_bmdma_error_handler,
122 .post_internal_cmd = ata_bmdma_post_internal_cmd,
123 .irq_handler = ata_interrupt,
124 .irq_clear = ata_bmdma_irq_clear,
125 .scr_read = sis_scr_read,
126 .scr_write = sis_scr_write,
127 .port_start = ata_port_start,
128 .port_stop = ata_port_stop,
129 .host_stop = ata_host_stop,
132 static struct ata_port_info sis_port_info = {
134 .flags = ATA_FLAG_SATA | ATA_FLAG_NO_LEGACY,
138 .port_ops = &sis_ops,
142 MODULE_AUTHOR("Uwe Koziolek");
143 MODULE_DESCRIPTION("low-level driver for Silicon Integratad Systems SATA controller");
144 MODULE_LICENSE("GPL");
145 MODULE_DEVICE_TABLE(pci, sis_pci_tbl);
146 MODULE_VERSION(DRV_VERSION);
148 static unsigned int get_scr_cfg_addr(unsigned int port_no, unsigned int sc_reg, struct pci_dev *pdev)
150 unsigned int addr = SIS_SCR_BASE + (4 * sc_reg);
153 switch (pdev->device) {
156 addr += SIS180_SATA1_OFS;
163 addr += SIS182_SATA1_OFS;
170 static u32 sis_scr_cfg_read (struct ata_port *ap, unsigned int sc_reg)
172 struct pci_dev *pdev = to_pci_dev(ap->host->dev);
173 unsigned int cfg_addr = get_scr_cfg_addr(ap->port_no, sc_reg, pdev);
177 if (sc_reg == SCR_ERROR) /* doesn't exist in PCI cfg space */
180 pci_read_config_byte(pdev, SIS_PMR, &pmr);
182 pci_read_config_dword(pdev, cfg_addr, &val);
184 if ((pdev->device == 0x0182) || (pdev->device == 0x0183) || (pdev->device == 0x1182) ||
185 (pdev->device == 0x1183) || (pmr & SIS_PMR_COMBINED))
186 pci_read_config_dword(pdev, cfg_addr+0x10, &val2);
188 return (val|val2) & 0xfffffffb; /* avoid problems with powerdowned ports */
191 static void sis_scr_cfg_write (struct ata_port *ap, unsigned int scr, u32 val)
193 struct pci_dev *pdev = to_pci_dev(ap->host->dev);
194 unsigned int cfg_addr = get_scr_cfg_addr(ap->port_no, scr, pdev);
197 if (scr == SCR_ERROR) /* doesn't exist in PCI cfg space */
200 pci_read_config_byte(pdev, SIS_PMR, &pmr);
202 pci_write_config_dword(pdev, cfg_addr, val);
204 if ((pdev->device == 0x0182) || (pdev->device == 0x0183) || (pdev->device == 0x1182) ||
205 (pdev->device == 0x1183) || (pmr & SIS_PMR_COMBINED))
206 pci_write_config_dword(pdev, cfg_addr+0x10, val);
209 static u32 sis_scr_read (struct ata_port *ap, unsigned int sc_reg)
211 struct pci_dev *pdev = to_pci_dev(ap->host->dev);
215 if (sc_reg > SCR_CONTROL)
218 if (ap->flags & SIS_FLAG_CFGSCR)
219 return sis_scr_cfg_read(ap, sc_reg);
221 pci_read_config_byte(pdev, SIS_PMR, &pmr);
223 val = inl(ap->ioaddr.scr_addr + (sc_reg * 4));
225 if ((pdev->device == 0x0182) || (pdev->device == 0x0183) || (pdev->device == 0x1182) ||
226 (pdev->device == 0x1183) || (pmr & SIS_PMR_COMBINED))
227 val2 = inl(ap->ioaddr.scr_addr + (sc_reg * 4) + 0x10);
229 return (val | val2) & 0xfffffffb;
232 static void sis_scr_write (struct ata_port *ap, unsigned int sc_reg, u32 val)
234 struct pci_dev *pdev = to_pci_dev(ap->host->dev);
237 if (sc_reg > SCR_CONTROL)
240 pci_read_config_byte(pdev, SIS_PMR, &pmr);
242 if (ap->flags & SIS_FLAG_CFGSCR)
243 sis_scr_cfg_write(ap, sc_reg, val);
245 outl(val, ap->ioaddr.scr_addr + (sc_reg * 4));
246 if ((pdev->device == 0x0182) || (pdev->device == 0x0183) || (pdev->device == 0x1182) ||
247 (pdev->device == 0x1183) || (pmr & SIS_PMR_COMBINED))
248 outl(val, ap->ioaddr.scr_addr + (sc_reg * 4)+0x10);
252 static int sis_init_one (struct pci_dev *pdev, const struct pci_device_id *ent)
254 static int printed_version;
255 struct ata_probe_ent *probe_ent = NULL;
258 struct ata_port_info pi = sis_port_info, *ppi[2] = { &pi, &pi };
259 int pci_dev_busy = 0;
261 u8 port2_start = 0x20;
263 if (!printed_version++)
264 dev_printk(KERN_INFO, &pdev->dev, "version " DRV_VERSION "\n");
266 rc = pci_enable_device(pdev);
270 rc = pci_request_regions(pdev, DRV_NAME);
276 rc = pci_set_dma_mask(pdev, ATA_DMA_MASK);
278 goto err_out_regions;
279 rc = pci_set_consistent_dma_mask(pdev, ATA_DMA_MASK);
281 goto err_out_regions;
283 /* check and see if the SCRs are in IO space or PCI cfg space */
284 pci_read_config_dword(pdev, SIS_GENCTL, &genctl);
285 if ((genctl & GENCTL_IOMAPPED_SCR) == 0)
286 pi.flags |= SIS_FLAG_CFGSCR;
288 /* if hardware thinks SCRs are in IO space, but there are
289 * no IO resources assigned, change to PCI cfg space.
291 if ((!(pi.flags & SIS_FLAG_CFGSCR)) &&
292 ((pci_resource_start(pdev, SIS_SCR_PCI_BAR) == 0) ||
293 (pci_resource_len(pdev, SIS_SCR_PCI_BAR) < 128))) {
294 genctl &= ~GENCTL_IOMAPPED_SCR;
295 pci_write_config_dword(pdev, SIS_GENCTL, genctl);
296 pi.flags |= SIS_FLAG_CFGSCR;
299 pci_read_config_byte(pdev, SIS_PMR, &pmr);
300 switch (ent->device) {
303 if ((pmr & SIS_PMR_COMBINED) == 0) {
304 dev_printk(KERN_INFO, &pdev->dev,
305 "Detected SiS 180/181/964 chipset in SATA mode\n");
308 dev_printk(KERN_INFO, &pdev->dev,
309 "Detected SiS 180/181 chipset in combined mode\n");
311 pi.flags |= ATA_FLAG_SLAVE_POSS;
317 pci_read_config_dword ( pdev, 0x6C, &val);
318 if (val & (1L << 31)) {
319 dev_printk(KERN_INFO, &pdev->dev, "Detected SiS 182/965 chipset\n");
320 pi.flags |= ATA_FLAG_SLAVE_POSS;
322 dev_printk(KERN_INFO, &pdev->dev, "Detected SiS 182/965L chipset\n");
328 pci_read_config_dword(pdev, 0x64, &val);
329 if (val & 0x10000000) {
330 dev_printk(KERN_INFO, &pdev->dev, "Detected SiS 1182/1183/966L SATA controller\n");
332 dev_printk(KERN_INFO, &pdev->dev, "Detected SiS 1182/1183/966 SATA controller\n");
333 pi.flags |= ATA_FLAG_SLAVE_POSS;
338 probe_ent = ata_pci_init_native_mode(pdev, ppi, ATA_PORT_PRIMARY | ATA_PORT_SECONDARY);
341 goto err_out_regions;
344 if (!(probe_ent->port_flags & SIS_FLAG_CFGSCR)) {
345 probe_ent->port[0].scr_addr =
346 pci_resource_start(pdev, SIS_SCR_PCI_BAR);
347 probe_ent->port[1].scr_addr =
348 pci_resource_start(pdev, SIS_SCR_PCI_BAR) + port2_start;
351 pci_set_master(pdev);
354 /* FIXME: check ata_device_add return value */
355 ata_device_add(probe_ent);
361 pci_release_regions(pdev);
365 pci_disable_device(pdev);
370 static int __init sis_init(void)
372 return pci_register_driver(&sis_pci_driver);
375 static void __exit sis_exit(void)
377 pci_unregister_driver(&sis_pci_driver);
380 module_init(sis_init);
381 module_exit(sis_exit);