2 * sata_sil24.c - Driver for Silicon Image 3124/3132 SATA-2 controllers
4 * Copyright 2005 Tejun Heo
6 * Based on preview driver from Silicon Image.
8 * This program is free software; you can redistribute it and/or modify it
9 * under the terms of the GNU General Public License as published by the
10 * Free Software Foundation; either version 2, or (at your option) any
13 * This program is distributed in the hope that it will be useful, but
14 * WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
16 * General Public License for more details.
20 #include <linux/kernel.h>
21 #include <linux/module.h>
22 #include <linux/pci.h>
23 #include <linux/blkdev.h>
24 #include <linux/delay.h>
25 #include <linux/interrupt.h>
26 #include <linux/dma-mapping.h>
27 #include <linux/device.h>
28 #include <scsi/scsi_host.h>
29 #include <scsi/scsi_cmnd.h>
30 #include <linux/libata.h>
32 #define DRV_NAME "sata_sil24"
33 #define DRV_VERSION "1.0"
36 * Port request block (PRB) 32 bytes
46 * Scatter gather entry (SGE) 16 bytes
57 struct sil24_port_multiplier {
67 * Global controller registers (128 bytes @ BAR0)
70 HOST_SLOT_STAT = 0x00, /* 32 bit slot stat * 4 */
74 HOST_BIST_CTRL = 0x50,
75 HOST_BIST_PTRN = 0x54,
76 HOST_BIST_STAT = 0x58,
77 HOST_MEM_BIST_STAT = 0x5c,
78 HOST_FLASH_CMD = 0x70,
80 HOST_FLASH_DATA = 0x74,
81 HOST_TRANSITION_DETECT = 0x75,
82 HOST_GPIO_CTRL = 0x76,
83 HOST_I2C_ADDR = 0x78, /* 32 bit */
85 HOST_I2C_XFER_CNT = 0x7e,
88 /* HOST_SLOT_STAT bits */
89 HOST_SSTAT_ATTN = (1 << 31),
92 HOST_CTRL_M66EN = (1 << 16), /* M66EN PCI bus signal */
93 HOST_CTRL_TRDY = (1 << 17), /* latched PCI TRDY */
94 HOST_CTRL_STOP = (1 << 18), /* latched PCI STOP */
95 HOST_CTRL_DEVSEL = (1 << 19), /* latched PCI DEVSEL */
96 HOST_CTRL_REQ64 = (1 << 20), /* latched PCI REQ64 */
97 HOST_CTRL_GLOBAL_RST = (1 << 31), /* global reset */
101 * (8192 bytes @ +0x0000, +0x2000, +0x4000 and +0x6000 @ BAR2)
103 PORT_REGS_SIZE = 0x2000,
105 PORT_LRAM = 0x0000, /* 31 LRAM slots and PMP regs */
106 PORT_LRAM_SLOT_SZ = 0x0080, /* 32 bytes PRB + 2 SGE, ACT... */
108 PORT_PMP = 0x0f80, /* 8 bytes PMP * 16 (128 bytes) */
109 PORT_PMP_STATUS = 0x0000, /* port device status offset */
110 PORT_PMP_QACTIVE = 0x0004, /* port device QActive offset */
111 PORT_PMP_SIZE = 0x0008, /* 8 bytes per PMP */
114 PORT_CTRL_STAT = 0x1000, /* write: ctrl-set, read: stat */
115 PORT_CTRL_CLR = 0x1004, /* write: ctrl-clear */
116 PORT_IRQ_STAT = 0x1008, /* high: status, low: interrupt */
117 PORT_IRQ_ENABLE_SET = 0x1010, /* write: enable-set */
118 PORT_IRQ_ENABLE_CLR = 0x1014, /* write: enable-clear */
119 PORT_ACTIVATE_UPPER_ADDR= 0x101c,
120 PORT_EXEC_FIFO = 0x1020, /* command execution fifo */
121 PORT_CMD_ERR = 0x1024, /* command error number */
122 PORT_FIS_CFG = 0x1028,
123 PORT_FIFO_THRES = 0x102c,
125 PORT_DECODE_ERR_CNT = 0x1040,
126 PORT_DECODE_ERR_THRESH = 0x1042,
127 PORT_CRC_ERR_CNT = 0x1044,
128 PORT_CRC_ERR_THRESH = 0x1046,
129 PORT_HSHK_ERR_CNT = 0x1048,
130 PORT_HSHK_ERR_THRESH = 0x104a,
132 PORT_PHY_CFG = 0x1050,
133 PORT_SLOT_STAT = 0x1800,
134 PORT_CMD_ACTIVATE = 0x1c00, /* 64 bit cmd activate * 31 (248 bytes) */
135 PORT_CONTEXT = 0x1e04,
136 PORT_EXEC_DIAG = 0x1e00, /* 32bit exec diag * 16 (64 bytes, 0-10 used on 3124) */
137 PORT_PSD_DIAG = 0x1e40, /* 32bit psd diag * 16 (64 bytes, 0-8 used on 3124) */
138 PORT_SCONTROL = 0x1f00,
139 PORT_SSTATUS = 0x1f04,
140 PORT_SERROR = 0x1f08,
141 PORT_SACTIVE = 0x1f0c,
143 /* PORT_CTRL_STAT bits */
144 PORT_CS_PORT_RST = (1 << 0), /* port reset */
145 PORT_CS_DEV_RST = (1 << 1), /* device reset */
146 PORT_CS_INIT = (1 << 2), /* port initialize */
147 PORT_CS_IRQ_WOC = (1 << 3), /* interrupt write one to clear */
148 PORT_CS_CDB16 = (1 << 5), /* 0=12b cdb, 1=16b cdb */
149 PORT_CS_PMP_RESUME = (1 << 6), /* PMP resume */
150 PORT_CS_32BIT_ACTV = (1 << 10), /* 32-bit activation */
151 PORT_CS_PMP_EN = (1 << 13), /* port multiplier enable */
152 PORT_CS_RDY = (1 << 31), /* port ready to accept commands */
154 /* PORT_IRQ_STAT/ENABLE_SET/CLR */
155 /* bits[11:0] are masked */
156 PORT_IRQ_COMPLETE = (1 << 0), /* command(s) completed */
157 PORT_IRQ_ERROR = (1 << 1), /* command execution error */
158 PORT_IRQ_PORTRDY_CHG = (1 << 2), /* port ready change */
159 PORT_IRQ_PWR_CHG = (1 << 3), /* power management change */
160 PORT_IRQ_PHYRDY_CHG = (1 << 4), /* PHY ready change */
161 PORT_IRQ_COMWAKE = (1 << 5), /* COMWAKE received */
162 PORT_IRQ_UNK_FIS = (1 << 6), /* unknown FIS received */
163 PORT_IRQ_DEV_XCHG = (1 << 7), /* device exchanged */
164 PORT_IRQ_8B10B = (1 << 8), /* 8b/10b decode error threshold */
165 PORT_IRQ_CRC = (1 << 9), /* CRC error threshold */
166 PORT_IRQ_HANDSHAKE = (1 << 10), /* handshake error threshold */
167 PORT_IRQ_SDB_NOTIFY = (1 << 11), /* SDB notify received */
169 DEF_PORT_IRQ = PORT_IRQ_COMPLETE | PORT_IRQ_ERROR |
170 PORT_IRQ_PHYRDY_CHG | PORT_IRQ_DEV_XCHG |
171 PORT_IRQ_UNK_FIS | PORT_IRQ_SDB_NOTIFY,
173 /* bits[27:16] are unmasked (raw) */
174 PORT_IRQ_RAW_SHIFT = 16,
175 PORT_IRQ_MASKED_MASK = 0x7ff,
176 PORT_IRQ_RAW_MASK = (0x7ff << PORT_IRQ_RAW_SHIFT),
178 /* ENABLE_SET/CLR specific, intr steering - 2 bit field */
179 PORT_IRQ_STEER_SHIFT = 30,
180 PORT_IRQ_STEER_MASK = (3 << PORT_IRQ_STEER_SHIFT),
182 /* PORT_CMD_ERR constants */
183 PORT_CERR_DEV = 1, /* Error bit in D2H Register FIS */
184 PORT_CERR_SDB = 2, /* Error bit in SDB FIS */
185 PORT_CERR_DATA = 3, /* Error in data FIS not detected by dev */
186 PORT_CERR_SEND = 4, /* Initial cmd FIS transmission failure */
187 PORT_CERR_INCONSISTENT = 5, /* Protocol mismatch */
188 PORT_CERR_DIRECTION = 6, /* Data direction mismatch */
189 PORT_CERR_UNDERRUN = 7, /* Ran out of SGEs while writing */
190 PORT_CERR_OVERRUN = 8, /* Ran out of SGEs while reading */
191 PORT_CERR_PKT_PROT = 11, /* DIR invalid in 1st PIO setup of ATAPI */
192 PORT_CERR_SGT_BOUNDARY = 16, /* PLD ecode 00 - SGT not on qword boundary */
193 PORT_CERR_SGT_TGTABRT = 17, /* PLD ecode 01 - target abort */
194 PORT_CERR_SGT_MSTABRT = 18, /* PLD ecode 10 - master abort */
195 PORT_CERR_SGT_PCIPERR = 19, /* PLD ecode 11 - PCI parity err while fetching SGT */
196 PORT_CERR_CMD_BOUNDARY = 24, /* ctrl[15:13] 001 - PRB not on qword boundary */
197 PORT_CERR_CMD_TGTABRT = 25, /* ctrl[15:13] 010 - target abort */
198 PORT_CERR_CMD_MSTABRT = 26, /* ctrl[15:13] 100 - master abort */
199 PORT_CERR_CMD_PCIPERR = 27, /* ctrl[15:13] 110 - PCI parity err while fetching PRB */
200 PORT_CERR_XFR_UNDEF = 32, /* PSD ecode 00 - undefined */
201 PORT_CERR_XFR_TGTABRT = 33, /* PSD ecode 01 - target abort */
202 PORT_CERR_XFR_MSTABRT = 34, /* PSD ecode 10 - master abort */
203 PORT_CERR_XFR_PCIPERR = 35, /* PSD ecode 11 - PCI prity err during transfer */
204 PORT_CERR_SENDSERVICE = 36, /* FIS received while sending service */
206 /* bits of PRB control field */
207 PRB_CTRL_PROTOCOL = (1 << 0), /* override def. ATA protocol */
208 PRB_CTRL_PACKET_READ = (1 << 4), /* PACKET cmd read */
209 PRB_CTRL_PACKET_WRITE = (1 << 5), /* PACKET cmd write */
210 PRB_CTRL_NIEN = (1 << 6), /* Mask completion irq */
211 PRB_CTRL_SRST = (1 << 7), /* Soft reset request (ign BSY?) */
213 /* PRB protocol field */
214 PRB_PROT_PACKET = (1 << 0),
215 PRB_PROT_TCQ = (1 << 1),
216 PRB_PROT_NCQ = (1 << 2),
217 PRB_PROT_READ = (1 << 3),
218 PRB_PROT_WRITE = (1 << 4),
219 PRB_PROT_TRANSPARENT = (1 << 5),
224 SGE_TRM = (1 << 31), /* Last SGE in chain */
225 SGE_LNK = (1 << 30), /* linked list
226 Points to SGT, not SGE */
227 SGE_DRD = (1 << 29), /* discard data read (/dev/null)
228 data address ignored */
238 SIL24_COMMON_FLAGS = ATA_FLAG_SATA | ATA_FLAG_NO_LEGACY |
239 ATA_FLAG_MMIO | ATA_FLAG_PIO_DMA |
240 ATA_FLAG_NCQ | ATA_FLAG_ACPI_SATA |
242 SIL24_COMMON_LFLAGS = ATA_LFLAG_SKIP_D2H_BSY,
243 SIL24_FLAG_PCIX_IRQ_WOC = (1 << 24), /* IRQ loss errata on PCI-X */
245 IRQ_STAT_4PORTS = 0xf,
248 struct sil24_ata_block {
249 struct sil24_prb prb;
250 struct sil24_sge sge[LIBATA_MAX_PRD];
253 struct sil24_atapi_block {
254 struct sil24_prb prb;
256 struct sil24_sge sge[LIBATA_MAX_PRD - 1];
259 union sil24_cmd_block {
260 struct sil24_ata_block ata;
261 struct sil24_atapi_block atapi;
264 static struct sil24_cerr_info {
265 unsigned int err_mask, action;
267 } sil24_cerr_db[] = {
268 [0] = { AC_ERR_DEV, ATA_EH_REVALIDATE,
270 [PORT_CERR_DEV] = { AC_ERR_DEV, ATA_EH_REVALIDATE,
271 "device error via D2H FIS" },
272 [PORT_CERR_SDB] = { AC_ERR_DEV, ATA_EH_REVALIDATE,
273 "device error via SDB FIS" },
274 [PORT_CERR_DATA] = { AC_ERR_ATA_BUS, ATA_EH_SOFTRESET,
275 "error in data FIS" },
276 [PORT_CERR_SEND] = { AC_ERR_ATA_BUS, ATA_EH_SOFTRESET,
277 "failed to transmit command FIS" },
278 [PORT_CERR_INCONSISTENT] = { AC_ERR_HSM, ATA_EH_SOFTRESET,
279 "protocol mismatch" },
280 [PORT_CERR_DIRECTION] = { AC_ERR_HSM, ATA_EH_SOFTRESET,
281 "data directon mismatch" },
282 [PORT_CERR_UNDERRUN] = { AC_ERR_HSM, ATA_EH_SOFTRESET,
283 "ran out of SGEs while writing" },
284 [PORT_CERR_OVERRUN] = { AC_ERR_HSM, ATA_EH_SOFTRESET,
285 "ran out of SGEs while reading" },
286 [PORT_CERR_PKT_PROT] = { AC_ERR_HSM, ATA_EH_SOFTRESET,
287 "invalid data directon for ATAPI CDB" },
288 [PORT_CERR_SGT_BOUNDARY] = { AC_ERR_SYSTEM, ATA_EH_SOFTRESET,
289 "SGT no on qword boundary" },
290 [PORT_CERR_SGT_TGTABRT] = { AC_ERR_HOST_BUS, ATA_EH_SOFTRESET,
291 "PCI target abort while fetching SGT" },
292 [PORT_CERR_SGT_MSTABRT] = { AC_ERR_HOST_BUS, ATA_EH_SOFTRESET,
293 "PCI master abort while fetching SGT" },
294 [PORT_CERR_SGT_PCIPERR] = { AC_ERR_HOST_BUS, ATA_EH_SOFTRESET,
295 "PCI parity error while fetching SGT" },
296 [PORT_CERR_CMD_BOUNDARY] = { AC_ERR_SYSTEM, ATA_EH_SOFTRESET,
297 "PRB not on qword boundary" },
298 [PORT_CERR_CMD_TGTABRT] = { AC_ERR_HOST_BUS, ATA_EH_SOFTRESET,
299 "PCI target abort while fetching PRB" },
300 [PORT_CERR_CMD_MSTABRT] = { AC_ERR_HOST_BUS, ATA_EH_SOFTRESET,
301 "PCI master abort while fetching PRB" },
302 [PORT_CERR_CMD_PCIPERR] = { AC_ERR_HOST_BUS, ATA_EH_SOFTRESET,
303 "PCI parity error while fetching PRB" },
304 [PORT_CERR_XFR_UNDEF] = { AC_ERR_HOST_BUS, ATA_EH_SOFTRESET,
305 "undefined error while transferring data" },
306 [PORT_CERR_XFR_TGTABRT] = { AC_ERR_HOST_BUS, ATA_EH_SOFTRESET,
307 "PCI target abort while transferring data" },
308 [PORT_CERR_XFR_MSTABRT] = { AC_ERR_HOST_BUS, ATA_EH_SOFTRESET,
309 "PCI master abort while transferring data" },
310 [PORT_CERR_XFR_PCIPERR] = { AC_ERR_HOST_BUS, ATA_EH_SOFTRESET,
311 "PCI parity error while transferring data" },
312 [PORT_CERR_SENDSERVICE] = { AC_ERR_HSM, ATA_EH_SOFTRESET,
313 "FIS received while sending service FIS" },
319 * The preview driver always returned 0 for status. We emulate it
320 * here from the previous interrupt.
322 struct sil24_port_priv {
323 union sil24_cmd_block *cmd_block; /* 32 cmd blocks */
324 dma_addr_t cmd_block_dma; /* DMA base addr for them */
325 struct ata_taskfile tf; /* Cached taskfile registers */
328 static void sil24_dev_config(struct ata_device *dev);
329 static u8 sil24_check_status(struct ata_port *ap);
330 static int sil24_scr_read(struct ata_port *ap, unsigned sc_reg, u32 *val);
331 static int sil24_scr_write(struct ata_port *ap, unsigned sc_reg, u32 val);
332 static void sil24_tf_read(struct ata_port *ap, struct ata_taskfile *tf);
333 static void sil24_qc_prep(struct ata_queued_cmd *qc);
334 static unsigned int sil24_qc_issue(struct ata_queued_cmd *qc);
335 static void sil24_irq_clear(struct ata_port *ap);
336 static void sil24_freeze(struct ata_port *ap);
337 static void sil24_thaw(struct ata_port *ap);
338 static void sil24_error_handler(struct ata_port *ap);
339 static void sil24_post_internal_cmd(struct ata_queued_cmd *qc);
340 static int sil24_port_start(struct ata_port *ap);
341 static int sil24_init_one(struct pci_dev *pdev, const struct pci_device_id *ent);
343 static int sil24_pci_device_resume(struct pci_dev *pdev);
346 static const struct pci_device_id sil24_pci_tbl[] = {
347 { PCI_VDEVICE(CMD, 0x3124), BID_SIL3124 },
348 { PCI_VDEVICE(INTEL, 0x3124), BID_SIL3124 },
349 { PCI_VDEVICE(CMD, 0x3132), BID_SIL3132 },
350 { PCI_VDEVICE(CMD, 0x0242), BID_SIL3132 },
351 { PCI_VDEVICE(CMD, 0x3131), BID_SIL3131 },
352 { PCI_VDEVICE(CMD, 0x3531), BID_SIL3131 },
354 { } /* terminate list */
357 static struct pci_driver sil24_pci_driver = {
359 .id_table = sil24_pci_tbl,
360 .probe = sil24_init_one,
361 .remove = ata_pci_remove_one,
363 .suspend = ata_pci_device_suspend,
364 .resume = sil24_pci_device_resume,
368 static struct scsi_host_template sil24_sht = {
369 .module = THIS_MODULE,
371 .ioctl = ata_scsi_ioctl,
372 .queuecommand = ata_scsi_queuecmd,
373 .change_queue_depth = ata_scsi_change_queue_depth,
374 .can_queue = SIL24_MAX_CMDS,
375 .this_id = ATA_SHT_THIS_ID,
376 .sg_tablesize = LIBATA_MAX_PRD,
377 .cmd_per_lun = ATA_SHT_CMD_PER_LUN,
378 .emulated = ATA_SHT_EMULATED,
379 .use_clustering = ATA_SHT_USE_CLUSTERING,
380 .proc_name = DRV_NAME,
381 .dma_boundary = ATA_DMA_BOUNDARY,
382 .slave_configure = ata_scsi_slave_config,
383 .slave_destroy = ata_scsi_slave_destroy,
384 .bios_param = ata_std_bios_param,
387 static const struct ata_port_operations sil24_ops = {
388 .dev_config = sil24_dev_config,
390 .check_status = sil24_check_status,
391 .check_altstatus = sil24_check_status,
392 .dev_select = ata_noop_dev_select,
394 .tf_read = sil24_tf_read,
396 .qc_prep = sil24_qc_prep,
397 .qc_issue = sil24_qc_issue,
399 .irq_clear = sil24_irq_clear,
401 .scr_read = sil24_scr_read,
402 .scr_write = sil24_scr_write,
404 .freeze = sil24_freeze,
406 .error_handler = sil24_error_handler,
407 .post_internal_cmd = sil24_post_internal_cmd,
409 .port_start = sil24_port_start,
413 * Use bits 30-31 of port_flags to encode available port numbers.
414 * Current maxium is 4.
416 #define SIL24_NPORTS2FLAG(nports) ((((unsigned)(nports) - 1) & 0x3) << 30)
417 #define SIL24_FLAG2NPORTS(flag) ((((flag) >> 30) & 0x3) + 1)
419 static const struct ata_port_info sil24_port_info[] = {
422 .flags = SIL24_COMMON_FLAGS | SIL24_NPORTS2FLAG(4) |
423 SIL24_FLAG_PCIX_IRQ_WOC,
424 .link_flags = SIL24_COMMON_LFLAGS,
425 .pio_mask = 0x1f, /* pio0-4 */
426 .mwdma_mask = 0x07, /* mwdma0-2 */
427 .udma_mask = ATA_UDMA5, /* udma0-5 */
428 .port_ops = &sil24_ops,
432 .flags = SIL24_COMMON_FLAGS | SIL24_NPORTS2FLAG(2),
433 .link_flags = SIL24_COMMON_LFLAGS,
434 .pio_mask = 0x1f, /* pio0-4 */
435 .mwdma_mask = 0x07, /* mwdma0-2 */
436 .udma_mask = ATA_UDMA5, /* udma0-5 */
437 .port_ops = &sil24_ops,
439 /* sil_3131/sil_3531 */
441 .flags = SIL24_COMMON_FLAGS | SIL24_NPORTS2FLAG(1),
442 .link_flags = SIL24_COMMON_LFLAGS,
443 .pio_mask = 0x1f, /* pio0-4 */
444 .mwdma_mask = 0x07, /* mwdma0-2 */
445 .udma_mask = ATA_UDMA5, /* udma0-5 */
446 .port_ops = &sil24_ops,
450 static int sil24_tag(int tag)
452 if (unlikely(ata_tag_internal(tag)))
457 static void sil24_dev_config(struct ata_device *dev)
459 void __iomem *port = dev->link->ap->ioaddr.cmd_addr;
461 if (dev->cdb_len == 16)
462 writel(PORT_CS_CDB16, port + PORT_CTRL_STAT);
464 writel(PORT_CS_CDB16, port + PORT_CTRL_CLR);
467 static void sil24_read_tf(struct ata_port *ap, int tag, struct ata_taskfile *tf)
469 void __iomem *port = ap->ioaddr.cmd_addr;
470 struct sil24_prb __iomem *prb;
473 prb = port + PORT_LRAM + sil24_tag(tag) * PORT_LRAM_SLOT_SZ;
474 memcpy_fromio(fis, prb->fis, sizeof(fis));
475 ata_tf_from_fis(fis, tf);
478 static u8 sil24_check_status(struct ata_port *ap)
480 struct sil24_port_priv *pp = ap->private_data;
481 return pp->tf.command;
484 static int sil24_scr_map[] = {
491 static int sil24_scr_read(struct ata_port *ap, unsigned sc_reg, u32 *val)
493 void __iomem *scr_addr = ap->ioaddr.scr_addr;
495 if (sc_reg < ARRAY_SIZE(sil24_scr_map)) {
497 addr = scr_addr + sil24_scr_map[sc_reg] * 4;
498 *val = readl(scr_addr + sil24_scr_map[sc_reg] * 4);
504 static int sil24_scr_write(struct ata_port *ap, unsigned sc_reg, u32 val)
506 void __iomem *scr_addr = ap->ioaddr.scr_addr;
508 if (sc_reg < ARRAY_SIZE(sil24_scr_map)) {
510 addr = scr_addr + sil24_scr_map[sc_reg] * 4;
511 writel(val, scr_addr + sil24_scr_map[sc_reg] * 4);
517 static void sil24_tf_read(struct ata_port *ap, struct ata_taskfile *tf)
519 struct sil24_port_priv *pp = ap->private_data;
523 static int sil24_init_port(struct ata_port *ap)
525 void __iomem *port = ap->ioaddr.cmd_addr;
528 writel(PORT_CS_INIT, port + PORT_CTRL_STAT);
529 ata_wait_register(port + PORT_CTRL_STAT,
530 PORT_CS_INIT, PORT_CS_INIT, 10, 100);
531 tmp = ata_wait_register(port + PORT_CTRL_STAT,
532 PORT_CS_RDY, 0, 10, 100);
534 if ((tmp & (PORT_CS_INIT | PORT_CS_RDY)) != PORT_CS_RDY)
539 static int sil24_exec_polled_cmd(struct ata_port *ap, int pmp,
540 const struct ata_taskfile *tf,
541 int is_cmd, u32 ctrl,
542 unsigned long timeout_msec)
544 void __iomem *port = ap->ioaddr.cmd_addr;
545 struct sil24_port_priv *pp = ap->private_data;
546 struct sil24_prb *prb = &pp->cmd_block[0].ata.prb;
547 dma_addr_t paddr = pp->cmd_block_dma;
548 u32 irq_enabled, irq_mask, irq_stat;
551 prb->ctrl = cpu_to_le16(ctrl);
552 ata_tf_to_fis(tf, pmp, is_cmd, prb->fis);
554 /* temporarily plug completion and error interrupts */
555 irq_enabled = readl(port + PORT_IRQ_ENABLE_SET);
556 writel(PORT_IRQ_COMPLETE | PORT_IRQ_ERROR, port + PORT_IRQ_ENABLE_CLR);
558 writel((u32)paddr, port + PORT_CMD_ACTIVATE);
559 writel((u64)paddr >> 32, port + PORT_CMD_ACTIVATE + 4);
561 irq_mask = (PORT_IRQ_COMPLETE | PORT_IRQ_ERROR) << PORT_IRQ_RAW_SHIFT;
562 irq_stat = ata_wait_register(port + PORT_IRQ_STAT, irq_mask, 0x0,
565 writel(irq_mask, port + PORT_IRQ_STAT); /* clear IRQs */
566 irq_stat >>= PORT_IRQ_RAW_SHIFT;
568 if (irq_stat & PORT_IRQ_COMPLETE)
571 /* force port into known state */
574 if (irq_stat & PORT_IRQ_ERROR)
580 /* restore IRQ enabled */
581 writel(irq_enabled, port + PORT_IRQ_ENABLE_SET);
586 static int sil24_do_softreset(struct ata_link *link, unsigned int *class,
587 int pmp, unsigned long deadline)
589 struct ata_port *ap = link->ap;
590 unsigned long timeout_msec = 0;
591 struct ata_taskfile tf;
597 if (ata_link_offline(link)) {
598 DPRINTK("PHY reports no device\n");
599 *class = ATA_DEV_NONE;
603 /* put the port into known state */
604 if (sil24_init_port(ap)) {
605 reason ="port not ready";
610 if (time_after(deadline, jiffies))
611 timeout_msec = jiffies_to_msecs(deadline - jiffies);
613 ata_tf_init(link->device, &tf); /* doesn't really matter */
614 rc = sil24_exec_polled_cmd(ap, pmp, &tf, 0, PRB_CTRL_SRST,
620 reason = "SRST command error";
624 sil24_read_tf(ap, 0, &tf);
625 *class = ata_dev_classify(&tf);
627 if (*class == ATA_DEV_UNKNOWN)
628 *class = ATA_DEV_NONE;
631 DPRINTK("EXIT, class=%u\n", *class);
635 ata_link_printk(link, KERN_ERR, "softreset failed (%s)\n", reason);
639 static int sil24_softreset(struct ata_link *link, unsigned int *class,
640 unsigned long deadline)
642 return sil24_do_softreset(link, class, 0, deadline);
645 static int sil24_hardreset(struct ata_link *link, unsigned int *class,
646 unsigned long deadline)
648 struct ata_port *ap = link->ap;
649 void __iomem *port = ap->ioaddr.cmd_addr;
654 /* sil24 does the right thing(tm) without any protection */
658 if (ata_link_online(link))
661 writel(PORT_CS_DEV_RST, port + PORT_CTRL_STAT);
662 tmp = ata_wait_register(port + PORT_CTRL_STAT,
663 PORT_CS_DEV_RST, PORT_CS_DEV_RST, 10, tout_msec);
665 /* SStatus oscillates between zero and valid status after
666 * DEV_RST, debounce it.
668 rc = sata_link_debounce(link, sata_deb_timing_long, deadline);
670 reason = "PHY debouncing failed";
674 if (tmp & PORT_CS_DEV_RST) {
675 if (ata_link_offline(link))
677 reason = "link not ready";
681 /* Sil24 doesn't store signature FIS after hardreset, so we
682 * can't wait for BSY to clear. Some devices take a long time
683 * to get ready and those devices will choke if we don't wait
684 * for BSY clearance here. Tell libata to perform follow-up
690 ata_link_printk(link, KERN_ERR, "hardreset failed (%s)\n", reason);
694 static inline void sil24_fill_sg(struct ata_queued_cmd *qc,
695 struct sil24_sge *sge)
697 struct scatterlist *sg;
699 ata_for_each_sg(sg, qc) {
700 sge->addr = cpu_to_le64(sg_dma_address(sg));
701 sge->cnt = cpu_to_le32(sg_dma_len(sg));
702 if (ata_sg_is_last(sg, qc))
703 sge->flags = cpu_to_le32(SGE_TRM);
710 static void sil24_qc_prep(struct ata_queued_cmd *qc)
712 struct ata_port *ap = qc->ap;
713 struct sil24_port_priv *pp = ap->private_data;
714 union sil24_cmd_block *cb;
715 struct sil24_prb *prb;
716 struct sil24_sge *sge;
719 cb = &pp->cmd_block[sil24_tag(qc->tag)];
721 switch (qc->tf.protocol) {
725 case ATA_PROT_NODATA:
731 case ATA_PROT_ATAPI_DMA:
732 case ATA_PROT_ATAPI_NODATA:
733 prb = &cb->atapi.prb;
735 memset(cb->atapi.cdb, 0, 32);
736 memcpy(cb->atapi.cdb, qc->cdb, qc->dev->cdb_len);
738 if (qc->tf.protocol != ATA_PROT_ATAPI_NODATA) {
739 if (qc->tf.flags & ATA_TFLAG_WRITE)
740 ctrl = PRB_CTRL_PACKET_WRITE;
742 ctrl = PRB_CTRL_PACKET_READ;
747 prb = NULL; /* shut up, gcc */
752 prb->ctrl = cpu_to_le16(ctrl);
753 ata_tf_to_fis(&qc->tf, 0, 1, prb->fis);
755 if (qc->flags & ATA_QCFLAG_DMAMAP)
756 sil24_fill_sg(qc, sge);
759 static unsigned int sil24_qc_issue(struct ata_queued_cmd *qc)
761 struct ata_port *ap = qc->ap;
762 struct sil24_port_priv *pp = ap->private_data;
763 void __iomem *port = ap->ioaddr.cmd_addr;
764 unsigned int tag = sil24_tag(qc->tag);
766 void __iomem *activate;
768 paddr = pp->cmd_block_dma + tag * sizeof(*pp->cmd_block);
769 activate = port + PORT_CMD_ACTIVATE + tag * 8;
771 writel((u32)paddr, activate);
772 writel((u64)paddr >> 32, activate + 4);
777 static void sil24_irq_clear(struct ata_port *ap)
782 static void sil24_freeze(struct ata_port *ap)
784 void __iomem *port = ap->ioaddr.cmd_addr;
786 /* Port-wide IRQ mask in HOST_CTRL doesn't really work, clear
787 * PORT_IRQ_ENABLE instead.
789 writel(0xffff, port + PORT_IRQ_ENABLE_CLR);
792 static void sil24_thaw(struct ata_port *ap)
794 void __iomem *port = ap->ioaddr.cmd_addr;
798 tmp = readl(port + PORT_IRQ_STAT);
799 writel(tmp, port + PORT_IRQ_STAT);
801 /* turn IRQ back on */
802 writel(DEF_PORT_IRQ, port + PORT_IRQ_ENABLE_SET);
805 static void sil24_error_intr(struct ata_port *ap)
807 void __iomem *port = ap->ioaddr.cmd_addr;
808 struct sil24_port_priv *pp = ap->private_data;
809 struct ata_eh_info *ehi = &ap->link.eh_info;
813 /* on error, we need to clear IRQ explicitly */
814 irq_stat = readl(port + PORT_IRQ_STAT);
815 writel(irq_stat, port + PORT_IRQ_STAT);
817 /* first, analyze and record host port events */
818 ata_ehi_clear_desc(ehi);
820 ata_ehi_push_desc(ehi, "irq_stat 0x%08x", irq_stat);
822 if (irq_stat & PORT_IRQ_SDB_NOTIFY) {
823 struct ata_device *dev = ap->link.device;
825 ata_ehi_push_desc(ehi, "SDB notify");
826 if (dev->flags & ATA_DFLAG_AN)
827 ata_scsi_media_change_notify(dev);
830 if (irq_stat & (PORT_IRQ_PHYRDY_CHG | PORT_IRQ_DEV_XCHG)) {
831 ata_ehi_hotplugged(ehi);
832 ata_ehi_push_desc(ehi, "%s",
833 irq_stat & PORT_IRQ_PHYRDY_CHG ?
834 "PHY RDY changed" : "device exchanged");
838 if (irq_stat & PORT_IRQ_UNK_FIS) {
839 ehi->err_mask |= AC_ERR_HSM;
840 ehi->action |= ATA_EH_SOFTRESET;
841 ata_ehi_push_desc(ehi, "unknown FIS");
845 /* deal with command error */
846 if (irq_stat & PORT_IRQ_ERROR) {
847 struct sil24_cerr_info *ci = NULL;
848 unsigned int err_mask = 0, action = 0;
849 struct ata_queued_cmd *qc;
852 /* analyze CMD_ERR */
853 cerr = readl(port + PORT_CMD_ERR);
854 if (cerr < ARRAY_SIZE(sil24_cerr_db))
855 ci = &sil24_cerr_db[cerr];
857 if (ci && ci->desc) {
858 err_mask |= ci->err_mask;
859 action |= ci->action;
860 ata_ehi_push_desc(ehi, "%s", ci->desc);
862 err_mask |= AC_ERR_OTHER;
863 action |= ATA_EH_SOFTRESET;
864 ata_ehi_push_desc(ehi, "unknown command error %d",
868 /* record error info */
869 qc = ata_qc_from_tag(ap, ap->link.active_tag);
871 sil24_read_tf(ap, qc->tag, &pp->tf);
872 qc->err_mask |= err_mask;
874 ehi->err_mask |= err_mask;
876 ehi->action |= action;
879 /* freeze or abort */
886 static void sil24_finish_qc(struct ata_queued_cmd *qc)
888 struct ata_port *ap = qc->ap;
889 struct sil24_port_priv *pp = ap->private_data;
891 if (qc->flags & ATA_QCFLAG_RESULT_TF)
892 sil24_read_tf(ap, qc->tag, &pp->tf);
895 static inline void sil24_host_intr(struct ata_port *ap)
897 void __iomem *port = ap->ioaddr.cmd_addr;
898 u32 slot_stat, qc_active;
901 /* If PCIX_IRQ_WOC, there's an inherent race window between
902 * clearing IRQ pending status and reading PORT_SLOT_STAT
903 * which may cause spurious interrupts afterwards. This is
904 * unavoidable and much better than losing interrupts which
905 * happens if IRQ pending is cleared after reading
908 if (ap->flags & SIL24_FLAG_PCIX_IRQ_WOC)
909 writel(PORT_IRQ_COMPLETE, port + PORT_IRQ_STAT);
911 slot_stat = readl(port + PORT_SLOT_STAT);
913 if (unlikely(slot_stat & HOST_SSTAT_ATTN)) {
914 sil24_error_intr(ap);
918 qc_active = slot_stat & ~HOST_SSTAT_ATTN;
919 rc = ata_qc_complete_multiple(ap, qc_active, sil24_finish_qc);
923 struct ata_eh_info *ehi = &ap->link.eh_info;
924 ehi->err_mask |= AC_ERR_HSM;
925 ehi->action |= ATA_EH_SOFTRESET;
930 /* spurious interrupts are expected if PCIX_IRQ_WOC */
931 if (!(ap->flags & SIL24_FLAG_PCIX_IRQ_WOC) && ata_ratelimit())
932 ata_port_printk(ap, KERN_INFO, "spurious interrupt "
933 "(slot_stat 0x%x active_tag %d sactive 0x%x)\n",
934 slot_stat, ap->link.active_tag, ap->link.sactive);
937 static irqreturn_t sil24_interrupt(int irq, void *dev_instance)
939 struct ata_host *host = dev_instance;
940 void __iomem *host_base = host->iomap[SIL24_HOST_BAR];
941 unsigned handled = 0;
945 status = readl(host_base + HOST_IRQ_STAT);
947 if (status == 0xffffffff) {
948 printk(KERN_ERR DRV_NAME ": IRQ status == 0xffffffff, "
949 "PCI fault or device removal?\n");
953 if (!(status & IRQ_STAT_4PORTS))
956 spin_lock(&host->lock);
958 for (i = 0; i < host->n_ports; i++)
959 if (status & (1 << i)) {
960 struct ata_port *ap = host->ports[i];
961 if (ap && !(ap->flags & ATA_FLAG_DISABLED)) {
965 printk(KERN_ERR DRV_NAME
966 ": interrupt from disabled port %d\n", i);
969 spin_unlock(&host->lock);
971 return IRQ_RETVAL(handled);
974 static void sil24_error_handler(struct ata_port *ap)
976 struct ata_eh_context *ehc = &ap->link.eh_context;
978 if (sil24_init_port(ap)) {
979 ata_eh_freeze_port(ap);
980 ehc->i.action |= ATA_EH_HARDRESET;
983 /* perform recovery */
984 ata_do_eh(ap, ata_std_prereset, sil24_softreset, sil24_hardreset,
988 static void sil24_post_internal_cmd(struct ata_queued_cmd *qc)
990 struct ata_port *ap = qc->ap;
992 /* make DMA engine forget about the failed command */
993 if (qc->flags & ATA_QCFLAG_FAILED)
997 static int sil24_port_start(struct ata_port *ap)
999 struct device *dev = ap->host->dev;
1000 struct sil24_port_priv *pp;
1001 union sil24_cmd_block *cb;
1002 size_t cb_size = sizeof(*cb) * SIL24_MAX_CMDS;
1006 pp = devm_kzalloc(dev, sizeof(*pp), GFP_KERNEL);
1010 pp->tf.command = ATA_DRDY;
1012 cb = dmam_alloc_coherent(dev, cb_size, &cb_dma, GFP_KERNEL);
1015 memset(cb, 0, cb_size);
1017 rc = ata_pad_alloc(ap, dev);
1022 pp->cmd_block_dma = cb_dma;
1024 ap->private_data = pp;
1029 static void sil24_init_controller(struct ata_host *host)
1031 void __iomem *host_base = host->iomap[SIL24_HOST_BAR];
1032 void __iomem *port_base = host->iomap[SIL24_PORT_BAR];
1037 writel(0, host_base + HOST_FLASH_CMD);
1039 /* clear global reset & mask interrupts during initialization */
1040 writel(0, host_base + HOST_CTRL);
1043 for (i = 0; i < host->n_ports; i++) {
1044 void __iomem *port = port_base + i * PORT_REGS_SIZE;
1046 /* Initial PHY setting */
1047 writel(0x20c, port + PORT_PHY_CFG);
1049 /* Clear port RST */
1050 tmp = readl(port + PORT_CTRL_STAT);
1051 if (tmp & PORT_CS_PORT_RST) {
1052 writel(PORT_CS_PORT_RST, port + PORT_CTRL_CLR);
1053 tmp = ata_wait_register(port + PORT_CTRL_STAT,
1055 PORT_CS_PORT_RST, 10, 100);
1056 if (tmp & PORT_CS_PORT_RST)
1057 dev_printk(KERN_ERR, host->dev,
1058 "failed to clear port RST\n");
1061 /* Configure IRQ WoC */
1062 if (host->ports[0]->flags & SIL24_FLAG_PCIX_IRQ_WOC)
1063 writel(PORT_CS_IRQ_WOC, port + PORT_CTRL_STAT);
1065 writel(PORT_CS_IRQ_WOC, port + PORT_CTRL_CLR);
1067 /* Zero error counters. */
1068 writel(0x8000, port + PORT_DECODE_ERR_THRESH);
1069 writel(0x8000, port + PORT_CRC_ERR_THRESH);
1070 writel(0x8000, port + PORT_HSHK_ERR_THRESH);
1071 writel(0x0000, port + PORT_DECODE_ERR_CNT);
1072 writel(0x0000, port + PORT_CRC_ERR_CNT);
1073 writel(0x0000, port + PORT_HSHK_ERR_CNT);
1075 /* Always use 64bit activation */
1076 writel(PORT_CS_32BIT_ACTV, port + PORT_CTRL_CLR);
1078 /* Clear port multiplier enable and resume bits */
1079 writel(PORT_CS_PMP_EN | PORT_CS_PMP_RESUME,
1080 port + PORT_CTRL_CLR);
1083 /* Turn on interrupts */
1084 writel(IRQ_STAT_4PORTS, host_base + HOST_CTRL);
1087 static int sil24_init_one(struct pci_dev *pdev, const struct pci_device_id *ent)
1089 static int printed_version = 0;
1090 struct ata_port_info pi = sil24_port_info[ent->driver_data];
1091 const struct ata_port_info *ppi[] = { &pi, NULL };
1092 void __iomem * const *iomap;
1093 struct ata_host *host;
1097 if (!printed_version++)
1098 dev_printk(KERN_DEBUG, &pdev->dev, "version " DRV_VERSION "\n");
1100 /* acquire resources */
1101 rc = pcim_enable_device(pdev);
1105 rc = pcim_iomap_regions(pdev,
1106 (1 << SIL24_HOST_BAR) | (1 << SIL24_PORT_BAR),
1110 iomap = pcim_iomap_table(pdev);
1112 /* apply workaround for completion IRQ loss on PCI-X errata */
1113 if (pi.flags & SIL24_FLAG_PCIX_IRQ_WOC) {
1114 tmp = readl(iomap[SIL24_HOST_BAR] + HOST_CTRL);
1115 if (tmp & (HOST_CTRL_TRDY | HOST_CTRL_STOP | HOST_CTRL_DEVSEL))
1116 dev_printk(KERN_INFO, &pdev->dev,
1117 "Applying completion IRQ loss on PCI-X "
1120 pi.flags &= ~SIL24_FLAG_PCIX_IRQ_WOC;
1123 /* allocate and fill host */
1124 host = ata_host_alloc_pinfo(&pdev->dev, ppi,
1125 SIL24_FLAG2NPORTS(ppi[0]->flags));
1128 host->iomap = iomap;
1130 for (i = 0; i < host->n_ports; i++) {
1131 struct ata_port *ap = host->ports[i];
1132 size_t offset = ap->port_no * PORT_REGS_SIZE;
1133 void __iomem *port = iomap[SIL24_PORT_BAR] + offset;
1135 host->ports[i]->ioaddr.cmd_addr = port;
1136 host->ports[i]->ioaddr.scr_addr = port + PORT_SCONTROL;
1138 ata_port_pbar_desc(ap, SIL24_HOST_BAR, -1, "host");
1139 ata_port_pbar_desc(ap, SIL24_PORT_BAR, offset, "port");
1142 /* configure and activate the device */
1143 if (!pci_set_dma_mask(pdev, DMA_64BIT_MASK)) {
1144 rc = pci_set_consistent_dma_mask(pdev, DMA_64BIT_MASK);
1146 rc = pci_set_consistent_dma_mask(pdev, DMA_32BIT_MASK);
1148 dev_printk(KERN_ERR, &pdev->dev,
1149 "64-bit DMA enable failed\n");
1154 rc = pci_set_dma_mask(pdev, DMA_32BIT_MASK);
1156 dev_printk(KERN_ERR, &pdev->dev,
1157 "32-bit DMA enable failed\n");
1160 rc = pci_set_consistent_dma_mask(pdev, DMA_32BIT_MASK);
1162 dev_printk(KERN_ERR, &pdev->dev,
1163 "32-bit consistent DMA enable failed\n");
1168 sil24_init_controller(host);
1170 pci_set_master(pdev);
1171 return ata_host_activate(host, pdev->irq, sil24_interrupt, IRQF_SHARED,
1176 static int sil24_pci_device_resume(struct pci_dev *pdev)
1178 struct ata_host *host = dev_get_drvdata(&pdev->dev);
1179 void __iomem *host_base = host->iomap[SIL24_HOST_BAR];
1182 rc = ata_pci_device_do_resume(pdev);
1186 if (pdev->dev.power.power_state.event == PM_EVENT_SUSPEND)
1187 writel(HOST_CTRL_GLOBAL_RST, host_base + HOST_CTRL);
1189 sil24_init_controller(host);
1191 ata_host_resume(host);
1197 static int __init sil24_init(void)
1199 return pci_register_driver(&sil24_pci_driver);
1202 static void __exit sil24_exit(void)
1204 pci_unregister_driver(&sil24_pci_driver);
1207 MODULE_AUTHOR("Tejun Heo");
1208 MODULE_DESCRIPTION("Silicon Image 3124/3132 SATA low-level driver");
1209 MODULE_LICENSE("GPL");
1210 MODULE_DEVICE_TABLE(pci, sil24_pci_tbl);
1212 module_init(sil24_init);
1213 module_exit(sil24_exit);