2 * sata_promise.c - Promise SATA
4 * Maintained by: Jeff Garzik <jgarzik@pobox.com>
5 * Please ALWAYS copy linux-ide@vger.kernel.org
8 * Copyright 2003-2004 Red Hat, Inc.
11 * This program is free software; you can redistribute it and/or modify
12 * it under the terms of the GNU General Public License as published by
13 * the Free Software Foundation; either version 2, or (at your option)
16 * This program is distributed in the hope that it will be useful,
17 * but WITHOUT ANY WARRANTY; without even the implied warranty of
18 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
19 * GNU General Public License for more details.
21 * You should have received a copy of the GNU General Public License
22 * along with this program; see the file COPYING. If not, write to
23 * the Free Software Foundation, 675 Mass Ave, Cambridge, MA 02139, USA.
26 * libata documentation is available via 'make {ps|pdf}docs',
27 * as Documentation/DocBook/libata.*
29 * Hardware information only available under NDA.
33 #include <linux/kernel.h>
34 #include <linux/module.h>
35 #include <linux/pci.h>
36 #include <linux/init.h>
37 #include <linux/blkdev.h>
38 #include <linux/delay.h>
39 #include <linux/interrupt.h>
40 #include <linux/sched.h>
41 #include <linux/device.h>
42 #include <scsi/scsi_host.h>
43 #include <scsi/scsi_cmnd.h>
44 #include <linux/libata.h>
46 #include "sata_promise.h"
48 #define DRV_NAME "sata_promise"
49 #define DRV_VERSION "1.05"
53 PDC_PKT_SUBMIT = 0x40, /* Command packet pointer addr */
54 PDC_INT_SEQMASK = 0x40, /* Mask of asserted SEQ INTs */
55 PDC_FLASH_CTL = 0x44, /* Flash control register */
56 PDC_GLOBAL_CTL = 0x48, /* Global control/status (per port) */
57 PDC_CTLSTAT = 0x60, /* IDE control and status (per port) */
58 PDC_SATA_PLUG_CSR = 0x6C, /* SATA Plug control/status reg */
59 PDC2_SATA_PLUG_CSR = 0x60, /* SATAII Plug control/status reg */
60 PDC_TBG_MODE = 0x41C, /* TBG mode (not SATAII) */
61 PDC_SLEW_CTL = 0x470, /* slew rate control reg (not SATAII) */
63 PDC_ERR_MASK = (1<<19) | (1<<20) | (1<<21) | (1<<22) |
64 (1<<8) | (1<<9) | (1<<10),
66 board_2037x = 0, /* FastTrak S150 TX2plus */
67 board_20319 = 1, /* FastTrak S150 TX4 */
68 board_20619 = 2, /* FastTrak TX4000 */
69 board_2057x = 3, /* SATAII150 Tx2plus */
70 board_40518 = 4, /* SATAII150 Tx4 */
72 PDC_HAS_PATA = (1 << 1), /* PDC20375/20575 has PATA */
74 PDC_RESET = (1 << 11), /* HDMA reset */
76 PDC_COMMON_FLAGS = ATA_FLAG_NO_LEGACY | ATA_FLAG_SRST |
77 ATA_FLAG_MMIO | ATA_FLAG_NO_ATAPI |
81 PDC_FLAG_GEN_II = (1 << 0),
85 struct pdc_port_priv {
90 struct pdc_host_priv {
94 static u32 pdc_sata_scr_read (struct ata_port *ap, unsigned int sc_reg);
95 static void pdc_sata_scr_write (struct ata_port *ap, unsigned int sc_reg, u32 val);
96 static int pdc_ata_init_one (struct pci_dev *pdev, const struct pci_device_id *ent);
97 static irqreturn_t pdc_interrupt (int irq, void *dev_instance);
98 static void pdc_eng_timeout(struct ata_port *ap);
99 static int pdc_port_start(struct ata_port *ap);
100 static void pdc_port_stop(struct ata_port *ap);
101 static void pdc_pata_phy_reset(struct ata_port *ap);
102 static void pdc_sata_phy_reset(struct ata_port *ap);
103 static void pdc_qc_prep(struct ata_queued_cmd *qc);
104 static void pdc_tf_load_mmio(struct ata_port *ap, const struct ata_taskfile *tf);
105 static void pdc_exec_command_mmio(struct ata_port *ap, const struct ata_taskfile *tf);
106 static void pdc_irq_clear(struct ata_port *ap);
107 static unsigned int pdc_qc_issue_prot(struct ata_queued_cmd *qc);
108 static void pdc_host_stop(struct ata_host *host);
111 static struct scsi_host_template pdc_ata_sht = {
112 .module = THIS_MODULE,
114 .ioctl = ata_scsi_ioctl,
115 .queuecommand = ata_scsi_queuecmd,
116 .can_queue = ATA_DEF_QUEUE,
117 .this_id = ATA_SHT_THIS_ID,
118 .sg_tablesize = LIBATA_MAX_PRD,
119 .cmd_per_lun = ATA_SHT_CMD_PER_LUN,
120 .emulated = ATA_SHT_EMULATED,
121 .use_clustering = ATA_SHT_USE_CLUSTERING,
122 .proc_name = DRV_NAME,
123 .dma_boundary = ATA_DMA_BOUNDARY,
124 .slave_configure = ata_scsi_slave_config,
125 .slave_destroy = ata_scsi_slave_destroy,
126 .bios_param = ata_std_bios_param,
129 static const struct ata_port_operations pdc_sata_ops = {
130 .port_disable = ata_port_disable,
131 .tf_load = pdc_tf_load_mmio,
132 .tf_read = ata_tf_read,
133 .check_status = ata_check_status,
134 .exec_command = pdc_exec_command_mmio,
135 .dev_select = ata_std_dev_select,
137 .phy_reset = pdc_sata_phy_reset,
139 .qc_prep = pdc_qc_prep,
140 .qc_issue = pdc_qc_issue_prot,
141 .eng_timeout = pdc_eng_timeout,
142 .data_xfer = ata_mmio_data_xfer,
143 .irq_handler = pdc_interrupt,
144 .irq_clear = pdc_irq_clear,
146 .scr_read = pdc_sata_scr_read,
147 .scr_write = pdc_sata_scr_write,
148 .port_start = pdc_port_start,
149 .port_stop = pdc_port_stop,
150 .host_stop = pdc_host_stop,
153 static const struct ata_port_operations pdc_pata_ops = {
154 .port_disable = ata_port_disable,
155 .tf_load = pdc_tf_load_mmio,
156 .tf_read = ata_tf_read,
157 .check_status = ata_check_status,
158 .exec_command = pdc_exec_command_mmio,
159 .dev_select = ata_std_dev_select,
161 .phy_reset = pdc_pata_phy_reset,
163 .qc_prep = pdc_qc_prep,
164 .qc_issue = pdc_qc_issue_prot,
165 .data_xfer = ata_mmio_data_xfer,
166 .eng_timeout = pdc_eng_timeout,
167 .irq_handler = pdc_interrupt,
168 .irq_clear = pdc_irq_clear,
170 .port_start = pdc_port_start,
171 .port_stop = pdc_port_stop,
172 .host_stop = pdc_host_stop,
175 static const struct ata_port_info pdc_port_info[] = {
179 .flags = PDC_COMMON_FLAGS | ATA_FLAG_SATA,
180 .pio_mask = 0x1f, /* pio0-4 */
181 .mwdma_mask = 0x07, /* mwdma0-2 */
182 .udma_mask = 0x7f, /* udma0-6 ; FIXME */
183 .port_ops = &pdc_sata_ops,
189 .flags = PDC_COMMON_FLAGS | ATA_FLAG_SATA,
190 .pio_mask = 0x1f, /* pio0-4 */
191 .mwdma_mask = 0x07, /* mwdma0-2 */
192 .udma_mask = 0x7f, /* udma0-6 ; FIXME */
193 .port_ops = &pdc_sata_ops,
199 .flags = PDC_COMMON_FLAGS | ATA_FLAG_SLAVE_POSS,
200 .pio_mask = 0x1f, /* pio0-4 */
201 .mwdma_mask = 0x07, /* mwdma0-2 */
202 .udma_mask = 0x7f, /* udma0-6 ; FIXME */
203 .port_ops = &pdc_pata_ops,
209 .flags = PDC_COMMON_FLAGS | ATA_FLAG_SATA,
210 .pio_mask = 0x1f, /* pio0-4 */
211 .mwdma_mask = 0x07, /* mwdma0-2 */
212 .udma_mask = 0x7f, /* udma0-6 ; FIXME */
213 .port_ops = &pdc_sata_ops,
219 .flags = PDC_COMMON_FLAGS | ATA_FLAG_SATA,
220 .pio_mask = 0x1f, /* pio0-4 */
221 .mwdma_mask = 0x07, /* mwdma0-2 */
222 .udma_mask = 0x7f, /* udma0-6 ; FIXME */
223 .port_ops = &pdc_sata_ops,
227 static const struct pci_device_id pdc_ata_pci_tbl[] = {
228 { PCI_VDEVICE(PROMISE, 0x3371), board_2037x },
229 { PCI_VDEVICE(PROMISE, 0x3373), board_2037x },
230 { PCI_VDEVICE(PROMISE, 0x3375), board_2037x },
231 { PCI_VDEVICE(PROMISE, 0x3376), board_2037x },
232 { PCI_VDEVICE(PROMISE, 0x3570), board_2057x },
233 { PCI_VDEVICE(PROMISE, 0x3571), board_2057x },
234 { PCI_VDEVICE(PROMISE, 0x3574), board_2057x },
235 { PCI_VDEVICE(PROMISE, 0x3577), board_2057x },
236 { PCI_VDEVICE(PROMISE, 0x3d73), board_2057x },
237 { PCI_VDEVICE(PROMISE, 0x3d75), board_2057x },
239 { PCI_VDEVICE(PROMISE, 0x3318), board_20319 },
240 { PCI_VDEVICE(PROMISE, 0x3319), board_20319 },
241 { PCI_VDEVICE(PROMISE, 0x3515), board_20319 },
242 { PCI_VDEVICE(PROMISE, 0x3519), board_20319 },
243 { PCI_VDEVICE(PROMISE, 0x3d17), board_40518 },
244 { PCI_VDEVICE(PROMISE, 0x3d18), board_40518 },
246 { PCI_VDEVICE(PROMISE, 0x6629), board_20619 },
248 { } /* terminate list */
252 static struct pci_driver pdc_ata_pci_driver = {
254 .id_table = pdc_ata_pci_tbl,
255 .probe = pdc_ata_init_one,
256 .remove = ata_pci_remove_one,
260 static int pdc_port_start(struct ata_port *ap)
262 struct device *dev = ap->host->dev;
263 struct pdc_host_priv *hp = ap->host->private_data;
264 struct pdc_port_priv *pp;
267 rc = ata_port_start(ap);
271 pp = kzalloc(sizeof(*pp), GFP_KERNEL);
277 pp->pkt = dma_alloc_coherent(dev, 128, &pp->pkt_dma, GFP_KERNEL);
283 ap->private_data = pp;
285 /* fix up PHYMODE4 align timing */
286 if ((hp->flags & PDC_FLAG_GEN_II) && sata_scr_valid(ap)) {
287 void __iomem *mmio = (void __iomem *) ap->ioaddr.scr_addr;
290 tmp = readl(mmio + 0x014);
291 tmp = (tmp & ~3) | 1; /* set bits 1:0 = 0:1 */
292 writel(tmp, mmio + 0x014);
305 static void pdc_port_stop(struct ata_port *ap)
307 struct device *dev = ap->host->dev;
308 struct pdc_port_priv *pp = ap->private_data;
310 ap->private_data = NULL;
311 dma_free_coherent(dev, 128, pp->pkt, pp->pkt_dma);
317 static void pdc_host_stop(struct ata_host *host)
319 struct pdc_host_priv *hp = host->private_data;
321 ata_pci_host_stop(host);
327 static void pdc_reset_port(struct ata_port *ap)
329 void __iomem *mmio = (void __iomem *) ap->ioaddr.cmd_addr + PDC_CTLSTAT;
333 for (i = 11; i > 0; i--) {
346 readl(mmio); /* flush */
349 static void pdc_sata_phy_reset(struct ata_port *ap)
355 static void pdc_pata_cbl_detect(struct ata_port *ap)
358 void __iomem *mmio = (void __iomem *) ap->ioaddr.cmd_addr + PDC_CTLSTAT + 0x03;
363 ap->cbl = ATA_CBL_PATA40;
364 ap->udma_mask &= ATA_UDMA_MASK_40C;
366 ap->cbl = ATA_CBL_PATA80;
369 static void pdc_pata_phy_reset(struct ata_port *ap)
371 pdc_pata_cbl_detect(ap);
377 static u32 pdc_sata_scr_read (struct ata_port *ap, unsigned int sc_reg)
379 if (sc_reg > SCR_CONTROL)
381 return readl((void __iomem *) ap->ioaddr.scr_addr + (sc_reg * 4));
385 static void pdc_sata_scr_write (struct ata_port *ap, unsigned int sc_reg,
388 if (sc_reg > SCR_CONTROL)
390 writel(val, (void __iomem *) ap->ioaddr.scr_addr + (sc_reg * 4));
393 static void pdc_qc_prep(struct ata_queued_cmd *qc)
395 struct pdc_port_priv *pp = qc->ap->private_data;
400 switch (qc->tf.protocol) {
405 case ATA_PROT_NODATA:
406 i = pdc_pkt_header(&qc->tf, qc->ap->prd_dma,
407 qc->dev->devno, pp->pkt);
409 if (qc->tf.flags & ATA_TFLAG_LBA48)
410 i = pdc_prep_lba48(&qc->tf, pp->pkt, i);
412 i = pdc_prep_lba28(&qc->tf, pp->pkt, i);
414 pdc_pkt_footer(&qc->tf, pp->pkt, i);
422 static void pdc_eng_timeout(struct ata_port *ap)
424 struct ata_host *host = ap->host;
426 struct ata_queued_cmd *qc;
431 spin_lock_irqsave(&host->lock, flags);
433 qc = ata_qc_from_tag(ap, ap->active_tag);
435 switch (qc->tf.protocol) {
437 case ATA_PROT_NODATA:
438 ata_port_printk(ap, KERN_ERR, "command timeout\n");
439 drv_stat = ata_wait_idle(ap);
440 qc->err_mask |= __ac_err_mask(drv_stat);
444 drv_stat = ata_busy_wait(ap, ATA_BUSY | ATA_DRQ, 1000);
446 ata_port_printk(ap, KERN_ERR,
447 "unknown timeout, cmd 0x%x stat 0x%x\n",
448 qc->tf.command, drv_stat);
450 qc->err_mask |= ac_err_mask(drv_stat);
454 spin_unlock_irqrestore(&host->lock, flags);
455 ata_eh_qc_complete(qc);
459 static inline unsigned int pdc_host_intr( struct ata_port *ap,
460 struct ata_queued_cmd *qc)
462 unsigned int handled = 0;
464 void __iomem *mmio = (void __iomem *) ap->ioaddr.cmd_addr + PDC_GLOBAL_CTL;
467 if (tmp & PDC_ERR_MASK) {
468 qc->err_mask |= AC_ERR_DEV;
472 switch (qc->tf.protocol) {
474 case ATA_PROT_NODATA:
475 qc->err_mask |= ac_err_mask(ata_wait_idle(ap));
481 ap->stats.idle_irq++;
488 static void pdc_irq_clear(struct ata_port *ap)
490 struct ata_host *host = ap->host;
491 void __iomem *mmio = host->mmio_base;
493 readl(mmio + PDC_INT_SEQMASK);
496 static irqreturn_t pdc_interrupt (int irq, void *dev_instance)
498 struct ata_host *host = dev_instance;
502 unsigned int handled = 0;
503 void __iomem *mmio_base;
507 if (!host || !host->mmio_base) {
508 VPRINTK("QUICK EXIT\n");
512 mmio_base = host->mmio_base;
514 /* reading should also clear interrupts */
515 mask = readl(mmio_base + PDC_INT_SEQMASK);
517 if (mask == 0xffffffff) {
518 VPRINTK("QUICK EXIT 2\n");
522 spin_lock(&host->lock);
524 mask &= 0xffff; /* only 16 tags possible */
526 VPRINTK("QUICK EXIT 3\n");
530 writel(mask, mmio_base + PDC_INT_SEQMASK);
532 for (i = 0; i < host->n_ports; i++) {
533 VPRINTK("port %u\n", i);
535 tmp = mask & (1 << (i + 1));
537 !(ap->flags & ATA_FLAG_DISABLED)) {
538 struct ata_queued_cmd *qc;
540 qc = ata_qc_from_tag(ap, ap->active_tag);
541 if (qc && (!(qc->tf.flags & ATA_TFLAG_POLLING)))
542 handled += pdc_host_intr(ap, qc);
549 spin_unlock(&host->lock);
550 return IRQ_RETVAL(handled);
553 static inline void pdc_packet_start(struct ata_queued_cmd *qc)
555 struct ata_port *ap = qc->ap;
556 struct pdc_port_priv *pp = ap->private_data;
557 unsigned int port_no = ap->port_no;
558 u8 seq = (u8) (port_no + 1);
560 VPRINTK("ENTER, ap %p\n", ap);
562 writel(0x00000001, ap->host->mmio_base + (seq * 4));
563 readl(ap->host->mmio_base + (seq * 4)); /* flush */
566 wmb(); /* flush PRD, pkt writes */
567 writel(pp->pkt_dma, (void __iomem *) ap->ioaddr.cmd_addr + PDC_PKT_SUBMIT);
568 readl((void __iomem *) ap->ioaddr.cmd_addr + PDC_PKT_SUBMIT); /* flush */
571 static unsigned int pdc_qc_issue_prot(struct ata_queued_cmd *qc)
573 switch (qc->tf.protocol) {
575 case ATA_PROT_NODATA:
576 pdc_packet_start(qc);
579 case ATA_PROT_ATAPI_DMA:
587 return ata_qc_issue_prot(qc);
590 static void pdc_tf_load_mmio(struct ata_port *ap, const struct ata_taskfile *tf)
592 WARN_ON (tf->protocol == ATA_PROT_DMA ||
593 tf->protocol == ATA_PROT_NODATA);
598 static void pdc_exec_command_mmio(struct ata_port *ap, const struct ata_taskfile *tf)
600 WARN_ON (tf->protocol == ATA_PROT_DMA ||
601 tf->protocol == ATA_PROT_NODATA);
602 ata_exec_command(ap, tf);
606 static void pdc_ata_setup_port(struct ata_ioports *port, unsigned long base)
608 port->cmd_addr = base;
609 port->data_addr = base;
611 port->error_addr = base + 0x4;
612 port->nsect_addr = base + 0x8;
613 port->lbal_addr = base + 0xc;
614 port->lbam_addr = base + 0x10;
615 port->lbah_addr = base + 0x14;
616 port->device_addr = base + 0x18;
618 port->status_addr = base + 0x1c;
619 port->altstatus_addr =
620 port->ctl_addr = base + 0x38;
624 static void pdc_host_init(unsigned int chip_id, struct ata_probe_ent *pe)
626 void __iomem *mmio = pe->mmio_base;
627 struct pdc_host_priv *hp = pe->private_data;
631 if (hp->flags & PDC_FLAG_GEN_II)
632 hotplug_offset = PDC2_SATA_PLUG_CSR;
634 hotplug_offset = PDC_SATA_PLUG_CSR;
637 * Except for the hotplug stuff, this is voodoo from the
638 * Promise driver. Label this entire section
639 * "TODO: figure out why we do this"
642 /* enable BMR_BURST, maybe change FIFO_SHD to 8 dwords */
643 tmp = readl(mmio + PDC_FLASH_CTL);
644 tmp |= 0x02000; /* bit 13 (enable bmr burst) */
645 if (!(hp->flags & PDC_FLAG_GEN_II))
646 tmp |= 0x10000; /* bit 16 (fifo threshold at 8 dw) */
647 writel(tmp, mmio + PDC_FLASH_CTL);
649 /* clear plug/unplug flags for all ports */
650 tmp = readl(mmio + hotplug_offset);
651 writel(tmp | 0xff, mmio + hotplug_offset);
653 /* mask plug/unplug ints */
654 tmp = readl(mmio + hotplug_offset);
655 writel(tmp | 0xff0000, mmio + hotplug_offset);
657 /* don't initialise TBG or SLEW on 2nd generation chips */
658 if (hp->flags & PDC_FLAG_GEN_II)
661 /* reduce TBG clock to 133 Mhz. */
662 tmp = readl(mmio + PDC_TBG_MODE);
663 tmp &= ~0x30000; /* clear bit 17, 16*/
664 tmp |= 0x10000; /* set bit 17:16 = 0:1 */
665 writel(tmp, mmio + PDC_TBG_MODE);
667 readl(mmio + PDC_TBG_MODE); /* flush */
670 /* adjust slew rate control register. */
671 tmp = readl(mmio + PDC_SLEW_CTL);
672 tmp &= 0xFFFFF03F; /* clear bit 11 ~ 6 */
673 tmp |= 0x00000900; /* set bit 11-9 = 100b , bit 8-6 = 100 */
674 writel(tmp, mmio + PDC_SLEW_CTL);
677 static int pdc_ata_init_one (struct pci_dev *pdev, const struct pci_device_id *ent)
679 static int printed_version;
680 struct ata_probe_ent *probe_ent = NULL;
681 struct pdc_host_priv *hp;
683 void __iomem *mmio_base;
684 unsigned int board_idx = (unsigned int) ent->driver_data;
685 int pci_dev_busy = 0;
688 if (!printed_version++)
689 dev_printk(KERN_DEBUG, &pdev->dev, "version " DRV_VERSION "\n");
691 rc = pci_enable_device(pdev);
695 rc = pci_request_regions(pdev, DRV_NAME);
701 rc = pci_set_dma_mask(pdev, ATA_DMA_MASK);
703 goto err_out_regions;
704 rc = pci_set_consistent_dma_mask(pdev, ATA_DMA_MASK);
706 goto err_out_regions;
708 probe_ent = kzalloc(sizeof(*probe_ent), GFP_KERNEL);
709 if (probe_ent == NULL) {
711 goto err_out_regions;
714 probe_ent->dev = pci_dev_to_dev(pdev);
715 INIT_LIST_HEAD(&probe_ent->node);
717 mmio_base = pci_iomap(pdev, 3, 0);
718 if (mmio_base == NULL) {
720 goto err_out_free_ent;
722 base = (unsigned long) mmio_base;
724 hp = kzalloc(sizeof(*hp), GFP_KERNEL);
727 goto err_out_free_ent;
730 probe_ent->private_data = hp;
732 probe_ent->sht = pdc_port_info[board_idx].sht;
733 probe_ent->port_flags = pdc_port_info[board_idx].flags;
734 probe_ent->pio_mask = pdc_port_info[board_idx].pio_mask;
735 probe_ent->mwdma_mask = pdc_port_info[board_idx].mwdma_mask;
736 probe_ent->udma_mask = pdc_port_info[board_idx].udma_mask;
737 probe_ent->port_ops = pdc_port_info[board_idx].port_ops;
739 probe_ent->irq = pdev->irq;
740 probe_ent->irq_flags = IRQF_SHARED;
741 probe_ent->mmio_base = mmio_base;
743 pdc_ata_setup_port(&probe_ent->port[0], base + 0x200);
744 pdc_ata_setup_port(&probe_ent->port[1], base + 0x280);
746 probe_ent->port[0].scr_addr = base + 0x400;
747 probe_ent->port[1].scr_addr = base + 0x500;
749 /* notice 4-port boards */
752 hp->flags |= PDC_FLAG_GEN_II;
755 probe_ent->n_ports = 4;
757 pdc_ata_setup_port(&probe_ent->port[2], base + 0x300);
758 pdc_ata_setup_port(&probe_ent->port[3], base + 0x380);
760 probe_ent->port[2].scr_addr = base + 0x600;
761 probe_ent->port[3].scr_addr = base + 0x700;
764 hp->flags |= PDC_FLAG_GEN_II;
767 probe_ent->n_ports = 2;
770 probe_ent->n_ports = 4;
772 pdc_ata_setup_port(&probe_ent->port[2], base + 0x300);
773 pdc_ata_setup_port(&probe_ent->port[3], base + 0x380);
775 probe_ent->port[2].scr_addr = base + 0x600;
776 probe_ent->port[3].scr_addr = base + 0x700;
783 pci_set_master(pdev);
785 /* initialize adapter */
786 pdc_host_init(board_idx, probe_ent);
788 /* FIXME: Need any other frees than hp? */
789 if (!ata_device_add(probe_ent))
799 pci_release_regions(pdev);
802 pci_disable_device(pdev);
807 static int __init pdc_ata_init(void)
809 return pci_register_driver(&pdc_ata_pci_driver);
813 static void __exit pdc_ata_exit(void)
815 pci_unregister_driver(&pdc_ata_pci_driver);
819 MODULE_AUTHOR("Jeff Garzik");
820 MODULE_DESCRIPTION("Promise ATA TX2/TX4/TX4000 low-level driver");
821 MODULE_LICENSE("GPL");
822 MODULE_DEVICE_TABLE(pci, pdc_ata_pci_tbl);
823 MODULE_VERSION(DRV_VERSION);
825 module_init(pdc_ata_init);
826 module_exit(pdc_ata_exit);