2 * sata_promise.c - Promise SATA
4 * Maintained by: Jeff Garzik <jgarzik@pobox.com>
5 * Please ALWAYS copy linux-ide@vger.kernel.org
8 * Copyright 2003-2004 Red Hat, Inc.
11 * This program is free software; you can redistribute it and/or modify
12 * it under the terms of the GNU General Public License as published by
13 * the Free Software Foundation; either version 2, or (at your option)
16 * This program is distributed in the hope that it will be useful,
17 * but WITHOUT ANY WARRANTY; without even the implied warranty of
18 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
19 * GNU General Public License for more details.
21 * You should have received a copy of the GNU General Public License
22 * along with this program; see the file COPYING. If not, write to
23 * the Free Software Foundation, 675 Mass Ave, Cambridge, MA 02139, USA.
26 * libata documentation is available via 'make {ps|pdf}docs',
27 * as Documentation/DocBook/libata.*
29 * Hardware information only available under NDA.
33 #include <linux/kernel.h>
34 #include <linux/module.h>
35 #include <linux/pci.h>
36 #include <linux/init.h>
37 #include <linux/blkdev.h>
38 #include <linux/delay.h>
39 #include <linux/interrupt.h>
40 #include <linux/device.h>
41 #include <scsi/scsi.h>
42 #include <scsi/scsi_host.h>
43 #include <scsi/scsi_cmnd.h>
44 #include <linux/libata.h>
45 #include "sata_promise.h"
47 #define DRV_NAME "sata_promise"
48 #define DRV_VERSION "2.10"
53 PDC_MAX_PRD = LIBATA_MAX_PRD - 1, /* -1 for ASIC PRD bug workaround */
55 /* register offsets */
56 PDC_FEATURE = 0x04, /* Feature/Error reg (per port) */
57 PDC_SECTOR_COUNT = 0x08, /* Sector count reg (per port) */
58 PDC_SECTOR_NUMBER = 0x0C, /* Sector number reg (per port) */
59 PDC_CYLINDER_LOW = 0x10, /* Cylinder low reg (per port) */
60 PDC_CYLINDER_HIGH = 0x14, /* Cylinder high reg (per port) */
61 PDC_DEVICE = 0x18, /* Device/Head reg (per port) */
62 PDC_COMMAND = 0x1C, /* Command/status reg (per port) */
63 PDC_ALTSTATUS = 0x38, /* Alternate-status/device-control reg (per port) */
64 PDC_PKT_SUBMIT = 0x40, /* Command packet pointer addr */
65 PDC_INT_SEQMASK = 0x40, /* Mask of asserted SEQ INTs */
66 PDC_FLASH_CTL = 0x44, /* Flash control register */
67 PDC_GLOBAL_CTL = 0x48, /* Global control/status (per port) */
68 PDC_CTLSTAT = 0x60, /* IDE control and status (per port) */
69 PDC_SATA_PLUG_CSR = 0x6C, /* SATA Plug control/status reg */
70 PDC2_SATA_PLUG_CSR = 0x60, /* SATAII Plug control/status reg */
71 PDC_TBG_MODE = 0x41C, /* TBG mode (not SATAII) */
72 PDC_SLEW_CTL = 0x470, /* slew rate control reg (not SATAII) */
74 /* PDC_GLOBAL_CTL bit definitions */
75 PDC_PH_ERR = (1 << 8), /* PCI error while loading packet */
76 PDC_SH_ERR = (1 << 9), /* PCI error while loading S/G table */
77 PDC_DH_ERR = (1 << 10), /* PCI error while loading data */
78 PDC2_HTO_ERR = (1 << 12), /* host bus timeout */
79 PDC2_ATA_HBA_ERR = (1 << 13), /* error during SATA DATA FIS transmission */
80 PDC2_ATA_DMA_CNT_ERR = (1 << 14), /* DMA DATA FIS size differs from S/G count */
81 PDC_OVERRUN_ERR = (1 << 19), /* S/G byte count larger than HD requires */
82 PDC_UNDERRUN_ERR = (1 << 20), /* S/G byte count less than HD requires */
83 PDC_DRIVE_ERR = (1 << 21), /* drive error */
84 PDC_PCI_SYS_ERR = (1 << 22), /* PCI system error */
85 PDC1_PCI_PARITY_ERR = (1 << 23), /* PCI parity error (from SATA150 driver) */
86 PDC1_ERR_MASK = PDC1_PCI_PARITY_ERR,
87 PDC2_ERR_MASK = PDC2_HTO_ERR | PDC2_ATA_HBA_ERR |
89 PDC_ERR_MASK = PDC_PH_ERR | PDC_SH_ERR | PDC_DH_ERR |
90 PDC_OVERRUN_ERR | PDC_UNDERRUN_ERR |
91 PDC_DRIVE_ERR | PDC_PCI_SYS_ERR |
92 PDC1_ERR_MASK | PDC2_ERR_MASK,
94 board_2037x = 0, /* FastTrak S150 TX2plus */
95 board_2037x_pata = 1, /* FastTrak S150 TX2plus PATA port */
96 board_20319 = 2, /* FastTrak S150 TX4 */
97 board_20619 = 3, /* FastTrak TX4000 */
98 board_2057x = 4, /* SATAII150 Tx2plus */
99 board_2057x_pata = 5, /* SATAII150 Tx2plus PATA port */
100 board_40518 = 6, /* SATAII150 Tx4 */
102 PDC_HAS_PATA = (1 << 1), /* PDC20375/20575 has PATA */
104 /* Sequence counter control registers bit definitions */
105 PDC_SEQCNTRL_INT_MASK = (1 << 5), /* Sequence Interrupt Mask */
107 /* Feature register values */
108 PDC_FEATURE_ATAPI_PIO = 0x00, /* ATAPI data xfer by PIO */
109 PDC_FEATURE_ATAPI_DMA = 0x01, /* ATAPI data xfer by DMA */
111 /* Device/Head register values */
112 PDC_DEVICE_SATA = 0xE0, /* Device/Head value for SATA devices */
114 /* PDC_CTLSTAT bit definitions */
115 PDC_DMA_ENABLE = (1 << 7),
116 PDC_IRQ_DISABLE = (1 << 10),
117 PDC_RESET = (1 << 11), /* HDMA reset */
119 PDC_COMMON_FLAGS = ATA_FLAG_NO_LEGACY |
121 ATA_FLAG_PIO_POLLING,
124 PDC_FLAG_GEN_II = (1 << 24),
125 PDC_FLAG_SATA_PATA = (1 << 25), /* supports SATA + PATA */
126 PDC_FLAG_4_PORTS = (1 << 26), /* 4 ports */
129 struct pdc_port_priv {
134 static int pdc_sata_scr_read(struct ata_port *ap, unsigned int sc_reg, u32 *val);
135 static int pdc_sata_scr_write(struct ata_port *ap, unsigned int sc_reg, u32 val);
136 static int pdc_ata_init_one (struct pci_dev *pdev, const struct pci_device_id *ent);
137 static int pdc_common_port_start(struct ata_port *ap);
138 static int pdc_sata_port_start(struct ata_port *ap);
139 static void pdc_qc_prep(struct ata_queued_cmd *qc);
140 static void pdc_tf_load_mmio(struct ata_port *ap, const struct ata_taskfile *tf);
141 static void pdc_exec_command_mmio(struct ata_port *ap, const struct ata_taskfile *tf);
142 static int pdc_check_atapi_dma(struct ata_queued_cmd *qc);
143 static int pdc_old_sata_check_atapi_dma(struct ata_queued_cmd *qc);
144 static void pdc_irq_clear(struct ata_port *ap);
145 static unsigned int pdc_qc_issue_prot(struct ata_queued_cmd *qc);
146 static void pdc_freeze(struct ata_port *ap);
147 static void pdc_thaw(struct ata_port *ap);
148 static void pdc_pata_error_handler(struct ata_port *ap);
149 static void pdc_sata_error_handler(struct ata_port *ap);
150 static void pdc_post_internal_cmd(struct ata_queued_cmd *qc);
151 static int pdc_pata_cable_detect(struct ata_port *ap);
152 static int pdc_sata_cable_detect(struct ata_port *ap);
154 static struct scsi_host_template pdc_ata_sht = {
155 .module = THIS_MODULE,
157 .ioctl = ata_scsi_ioctl,
158 .queuecommand = ata_scsi_queuecmd,
159 .can_queue = ATA_DEF_QUEUE,
160 .this_id = ATA_SHT_THIS_ID,
161 .sg_tablesize = PDC_MAX_PRD,
162 .cmd_per_lun = ATA_SHT_CMD_PER_LUN,
163 .emulated = ATA_SHT_EMULATED,
164 .use_clustering = ATA_SHT_USE_CLUSTERING,
165 .proc_name = DRV_NAME,
166 .dma_boundary = ATA_DMA_BOUNDARY,
167 .slave_configure = ata_scsi_slave_config,
168 .slave_destroy = ata_scsi_slave_destroy,
169 .bios_param = ata_std_bios_param,
172 static const struct ata_port_operations pdc_sata_ops = {
173 .tf_load = pdc_tf_load_mmio,
174 .tf_read = ata_tf_read,
175 .check_status = ata_check_status,
176 .exec_command = pdc_exec_command_mmio,
177 .dev_select = ata_std_dev_select,
178 .check_atapi_dma = pdc_check_atapi_dma,
180 .qc_prep = pdc_qc_prep,
181 .qc_issue = pdc_qc_issue_prot,
182 .freeze = pdc_freeze,
184 .error_handler = pdc_sata_error_handler,
185 .post_internal_cmd = pdc_post_internal_cmd,
186 .cable_detect = pdc_sata_cable_detect,
187 .data_xfer = ata_data_xfer,
188 .irq_clear = pdc_irq_clear,
189 .irq_on = ata_irq_on,
191 .scr_read = pdc_sata_scr_read,
192 .scr_write = pdc_sata_scr_write,
193 .port_start = pdc_sata_port_start,
196 /* First-generation chips need a more restrictive ->check_atapi_dma op */
197 static const struct ata_port_operations pdc_old_sata_ops = {
198 .tf_load = pdc_tf_load_mmio,
199 .tf_read = ata_tf_read,
200 .check_status = ata_check_status,
201 .exec_command = pdc_exec_command_mmio,
202 .dev_select = ata_std_dev_select,
203 .check_atapi_dma = pdc_old_sata_check_atapi_dma,
205 .qc_prep = pdc_qc_prep,
206 .qc_issue = pdc_qc_issue_prot,
207 .freeze = pdc_freeze,
209 .error_handler = pdc_sata_error_handler,
210 .post_internal_cmd = pdc_post_internal_cmd,
211 .cable_detect = pdc_sata_cable_detect,
212 .data_xfer = ata_data_xfer,
213 .irq_clear = pdc_irq_clear,
214 .irq_on = ata_irq_on,
216 .scr_read = pdc_sata_scr_read,
217 .scr_write = pdc_sata_scr_write,
218 .port_start = pdc_sata_port_start,
221 static const struct ata_port_operations pdc_pata_ops = {
222 .tf_load = pdc_tf_load_mmio,
223 .tf_read = ata_tf_read,
224 .check_status = ata_check_status,
225 .exec_command = pdc_exec_command_mmio,
226 .dev_select = ata_std_dev_select,
227 .check_atapi_dma = pdc_check_atapi_dma,
229 .qc_prep = pdc_qc_prep,
230 .qc_issue = pdc_qc_issue_prot,
231 .freeze = pdc_freeze,
233 .error_handler = pdc_pata_error_handler,
234 .post_internal_cmd = pdc_post_internal_cmd,
235 .cable_detect = pdc_pata_cable_detect,
236 .data_xfer = ata_data_xfer,
237 .irq_clear = pdc_irq_clear,
238 .irq_on = ata_irq_on,
240 .port_start = pdc_common_port_start,
243 static const struct ata_port_info pdc_port_info[] = {
246 .flags = PDC_COMMON_FLAGS | ATA_FLAG_SATA |
248 .pio_mask = 0x1f, /* pio0-4 */
249 .mwdma_mask = 0x07, /* mwdma0-2 */
250 .udma_mask = ATA_UDMA6,
251 .port_ops = &pdc_old_sata_ops,
254 /* board_2037x_pata */
256 .flags = PDC_COMMON_FLAGS | ATA_FLAG_SLAVE_POSS,
257 .pio_mask = 0x1f, /* pio0-4 */
258 .mwdma_mask = 0x07, /* mwdma0-2 */
259 .udma_mask = ATA_UDMA6,
260 .port_ops = &pdc_pata_ops,
265 .flags = PDC_COMMON_FLAGS | ATA_FLAG_SATA |
267 .pio_mask = 0x1f, /* pio0-4 */
268 .mwdma_mask = 0x07, /* mwdma0-2 */
269 .udma_mask = ATA_UDMA6,
270 .port_ops = &pdc_old_sata_ops,
275 .flags = PDC_COMMON_FLAGS | ATA_FLAG_SLAVE_POSS |
277 .pio_mask = 0x1f, /* pio0-4 */
278 .mwdma_mask = 0x07, /* mwdma0-2 */
279 .udma_mask = ATA_UDMA6,
280 .port_ops = &pdc_pata_ops,
285 .flags = PDC_COMMON_FLAGS | ATA_FLAG_SATA |
286 PDC_FLAG_GEN_II | PDC_FLAG_SATA_PATA,
287 .pio_mask = 0x1f, /* pio0-4 */
288 .mwdma_mask = 0x07, /* mwdma0-2 */
289 .udma_mask = ATA_UDMA6,
290 .port_ops = &pdc_sata_ops,
293 /* board_2057x_pata */
295 .flags = PDC_COMMON_FLAGS | ATA_FLAG_SLAVE_POSS |
297 .pio_mask = 0x1f, /* pio0-4 */
298 .mwdma_mask = 0x07, /* mwdma0-2 */
299 .udma_mask = ATA_UDMA6,
300 .port_ops = &pdc_pata_ops,
305 .flags = PDC_COMMON_FLAGS | ATA_FLAG_SATA |
306 PDC_FLAG_GEN_II | PDC_FLAG_4_PORTS,
307 .pio_mask = 0x1f, /* pio0-4 */
308 .mwdma_mask = 0x07, /* mwdma0-2 */
309 .udma_mask = ATA_UDMA6,
310 .port_ops = &pdc_sata_ops,
314 static const struct pci_device_id pdc_ata_pci_tbl[] = {
315 { PCI_VDEVICE(PROMISE, 0x3371), board_2037x },
316 { PCI_VDEVICE(PROMISE, 0x3373), board_2037x },
317 { PCI_VDEVICE(PROMISE, 0x3375), board_2037x },
318 { PCI_VDEVICE(PROMISE, 0x3376), board_2037x },
319 { PCI_VDEVICE(PROMISE, 0x3570), board_2057x },
320 { PCI_VDEVICE(PROMISE, 0x3571), board_2057x },
321 { PCI_VDEVICE(PROMISE, 0x3574), board_2057x },
322 { PCI_VDEVICE(PROMISE, 0x3577), board_2057x },
323 { PCI_VDEVICE(PROMISE, 0x3d73), board_2057x },
324 { PCI_VDEVICE(PROMISE, 0x3d75), board_2057x },
326 { PCI_VDEVICE(PROMISE, 0x3318), board_20319 },
327 { PCI_VDEVICE(PROMISE, 0x3319), board_20319 },
328 { PCI_VDEVICE(PROMISE, 0x3515), board_40518 },
329 { PCI_VDEVICE(PROMISE, 0x3519), board_40518 },
330 { PCI_VDEVICE(PROMISE, 0x3d17), board_40518 },
331 { PCI_VDEVICE(PROMISE, 0x3d18), board_40518 },
333 { PCI_VDEVICE(PROMISE, 0x6629), board_20619 },
335 { } /* terminate list */
338 static struct pci_driver pdc_ata_pci_driver = {
340 .id_table = pdc_ata_pci_tbl,
341 .probe = pdc_ata_init_one,
342 .remove = ata_pci_remove_one,
345 static int pdc_common_port_start(struct ata_port *ap)
347 struct device *dev = ap->host->dev;
348 struct pdc_port_priv *pp;
351 rc = ata_port_start(ap);
355 pp = devm_kzalloc(dev, sizeof(*pp), GFP_KERNEL);
359 pp->pkt = dmam_alloc_coherent(dev, 128, &pp->pkt_dma, GFP_KERNEL);
363 ap->private_data = pp;
368 static int pdc_sata_port_start(struct ata_port *ap)
372 rc = pdc_common_port_start(ap);
376 /* fix up PHYMODE4 align timing */
377 if (ap->flags & PDC_FLAG_GEN_II) {
378 void __iomem *mmio = ap->ioaddr.scr_addr;
381 tmp = readl(mmio + 0x014);
382 tmp = (tmp & ~3) | 1; /* set bits 1:0 = 0:1 */
383 writel(tmp, mmio + 0x014);
389 static void pdc_reset_port(struct ata_port *ap)
391 void __iomem *mmio = ap->ioaddr.cmd_addr + PDC_CTLSTAT;
395 for (i = 11; i > 0; i--) {
408 readl(mmio); /* flush */
411 static int pdc_pata_cable_detect(struct ata_port *ap)
414 void __iomem *mmio = ap->ioaddr.cmd_addr + PDC_CTLSTAT + 0x03;
418 return ATA_CBL_PATA40;
419 return ATA_CBL_PATA80;
422 static int pdc_sata_cable_detect(struct ata_port *ap)
427 static int pdc_sata_scr_read(struct ata_port *ap, unsigned int sc_reg, u32 *val)
429 if (sc_reg > SCR_CONTROL)
431 *val = readl(ap->ioaddr.scr_addr + (sc_reg * 4));
435 static int pdc_sata_scr_write(struct ata_port *ap, unsigned int sc_reg, u32 val)
437 if (sc_reg > SCR_CONTROL)
439 writel(val, ap->ioaddr.scr_addr + (sc_reg * 4));
443 static void pdc_atapi_pkt(struct ata_queued_cmd *qc)
445 struct ata_port *ap = qc->ap;
446 dma_addr_t sg_table = ap->prd_dma;
447 unsigned int cdb_len = qc->dev->cdb_len;
449 struct pdc_port_priv *pp = ap->private_data;
451 u32 *buf32 = (u32 *) buf;
452 unsigned int dev_sel, feature, nbytes;
454 /* set control bits (byte 0), zero delay seq id (byte 3),
455 * and seq id (byte 2)
457 switch (qc->tf.protocol) {
458 case ATA_PROT_ATAPI_DMA:
459 if (!(qc->tf.flags & ATA_TFLAG_WRITE))
460 buf32[0] = cpu_to_le32(PDC_PKT_READ);
464 case ATA_PROT_ATAPI_NODATA:
465 buf32[0] = cpu_to_le32(PDC_PKT_NODATA);
471 buf32[1] = cpu_to_le32(sg_table); /* S/G table addr */
472 buf32[2] = 0; /* no next-packet */
475 if (sata_scr_valid(&ap->link)) {
476 dev_sel = PDC_DEVICE_SATA;
478 dev_sel = ATA_DEVICE_OBS;
479 if (qc->dev->devno != 0)
482 buf[12] = (1 << 5) | ATA_REG_DEVICE;
484 buf[14] = (1 << 5) | ATA_REG_DEVICE | PDC_PKT_CLEAR_BSY;
485 buf[15] = dev_sel; /* once more, waiting for BSY to clear */
487 buf[16] = (1 << 5) | ATA_REG_NSECT;
489 buf[18] = (1 << 5) | ATA_REG_LBAL;
492 /* set feature and byte counter registers */
493 if (qc->tf.protocol != ATA_PROT_ATAPI_DMA) {
494 feature = PDC_FEATURE_ATAPI_PIO;
495 /* set byte counter register to real transfer byte count */
500 feature = PDC_FEATURE_ATAPI_DMA;
501 /* set byte counter register to 0 */
504 buf[20] = (1 << 5) | ATA_REG_FEATURE;
506 buf[22] = (1 << 5) | ATA_REG_BYTEL;
507 buf[23] = nbytes & 0xFF;
508 buf[24] = (1 << 5) | ATA_REG_BYTEH;
509 buf[25] = (nbytes >> 8) & 0xFF;
511 /* send ATAPI packet command 0xA0 */
512 buf[26] = (1 << 5) | ATA_REG_CMD;
513 buf[27] = ATA_CMD_PACKET;
515 /* select drive and check DRQ */
516 buf[28] = (1 << 5) | ATA_REG_DEVICE | PDC_PKT_WAIT_DRDY;
519 /* we can represent cdb lengths 2/4/6/8/10/12/14/16 */
520 BUG_ON(cdb_len & ~0x1E);
522 /* append the CDB as the final part */
523 buf[30] = (((cdb_len >> 1) & 7) << 5) | ATA_REG_DATA | PDC_LAST_REG;
524 memcpy(buf+31, cdb, cdb_len);
528 * pdc_fill_sg - Fill PCI IDE PRD table
529 * @qc: Metadata associated with taskfile to be transferred
531 * Fill PCI IDE PRD (scatter-gather) table with segments
532 * associated with the current disk command.
533 * Make sure hardware does not choke on it.
536 * spin_lock_irqsave(host lock)
539 static void pdc_fill_sg(struct ata_queued_cmd *qc)
541 struct ata_port *ap = qc->ap;
542 struct scatterlist *sg;
544 const u32 SG_COUNT_ASIC_BUG = 41*4;
546 if (!(qc->flags & ATA_QCFLAG_DMAMAP))
549 WARN_ON(qc->__sg == NULL);
550 WARN_ON(qc->n_elem == 0 && qc->pad_len == 0);
553 ata_for_each_sg(sg, qc) {
557 /* determine if physical DMA addr spans 64K boundary.
558 * Note h/w doesn't support 64-bit, so we unconditionally
559 * truncate dma_addr_t to u32.
561 addr = (u32) sg_dma_address(sg);
562 sg_len = sg_dma_len(sg);
565 offset = addr & 0xffff;
567 if ((offset + sg_len) > 0x10000)
568 len = 0x10000 - offset;
570 ap->prd[idx].addr = cpu_to_le32(addr);
571 ap->prd[idx].flags_len = cpu_to_le32(len & 0xffff);
572 VPRINTK("PRD[%u] = (0x%X, 0x%X)\n", idx, addr, len);
581 u32 len = le32_to_cpu(ap->prd[idx - 1].flags_len);
583 if (len > SG_COUNT_ASIC_BUG) {
586 VPRINTK("Splitting last PRD.\n");
588 addr = le32_to_cpu(ap->prd[idx - 1].addr);
589 ap->prd[idx - 1].flags_len -= cpu_to_le32(SG_COUNT_ASIC_BUG);
590 VPRINTK("PRD[%u] = (0x%X, 0x%X)\n", idx - 1, addr, SG_COUNT_ASIC_BUG);
592 addr = addr + len - SG_COUNT_ASIC_BUG;
593 len = SG_COUNT_ASIC_BUG;
594 ap->prd[idx].addr = cpu_to_le32(addr);
595 ap->prd[idx].flags_len = cpu_to_le32(len);
596 VPRINTK("PRD[%u] = (0x%X, 0x%X)\n", idx, addr, len);
601 ap->prd[idx - 1].flags_len |= cpu_to_le32(ATA_PRD_EOT);
605 static void pdc_qc_prep(struct ata_queued_cmd *qc)
607 struct pdc_port_priv *pp = qc->ap->private_data;
612 switch (qc->tf.protocol) {
617 case ATA_PROT_NODATA:
618 i = pdc_pkt_header(&qc->tf, qc->ap->prd_dma,
619 qc->dev->devno, pp->pkt);
621 if (qc->tf.flags & ATA_TFLAG_LBA48)
622 i = pdc_prep_lba48(&qc->tf, pp->pkt, i);
624 i = pdc_prep_lba28(&qc->tf, pp->pkt, i);
626 pdc_pkt_footer(&qc->tf, pp->pkt, i);
633 case ATA_PROT_ATAPI_DMA:
636 case ATA_PROT_ATAPI_NODATA:
645 static void pdc_freeze(struct ata_port *ap)
647 void __iomem *mmio = ap->ioaddr.cmd_addr;
650 tmp = readl(mmio + PDC_CTLSTAT);
651 tmp |= PDC_IRQ_DISABLE;
652 tmp &= ~PDC_DMA_ENABLE;
653 writel(tmp, mmio + PDC_CTLSTAT);
654 readl(mmio + PDC_CTLSTAT); /* flush */
657 static void pdc_thaw(struct ata_port *ap)
659 void __iomem *mmio = ap->ioaddr.cmd_addr;
663 readl(mmio + PDC_INT_SEQMASK);
665 /* turn IRQ back on */
666 tmp = readl(mmio + PDC_CTLSTAT);
667 tmp &= ~PDC_IRQ_DISABLE;
668 writel(tmp, mmio + PDC_CTLSTAT);
669 readl(mmio + PDC_CTLSTAT); /* flush */
672 static void pdc_common_error_handler(struct ata_port *ap, ata_reset_fn_t hardreset)
674 if (!(ap->pflags & ATA_PFLAG_FROZEN))
677 /* perform recovery */
678 ata_do_eh(ap, ata_std_prereset, ata_std_softreset, hardreset,
682 static void pdc_pata_error_handler(struct ata_port *ap)
684 pdc_common_error_handler(ap, NULL);
687 static void pdc_sata_error_handler(struct ata_port *ap)
689 pdc_common_error_handler(ap, sata_std_hardreset);
692 static void pdc_post_internal_cmd(struct ata_queued_cmd *qc)
694 struct ata_port *ap = qc->ap;
696 /* make DMA engine forget about the failed command */
697 if (qc->flags & ATA_QCFLAG_FAILED)
701 static void pdc_error_intr(struct ata_port *ap, struct ata_queued_cmd *qc,
702 u32 port_status, u32 err_mask)
704 struct ata_eh_info *ehi = &ap->link.eh_info;
705 unsigned int ac_err_mask = 0;
707 ata_ehi_clear_desc(ehi);
708 ata_ehi_push_desc(ehi, "port_status 0x%08x", port_status);
709 port_status &= err_mask;
711 if (port_status & PDC_DRIVE_ERR)
712 ac_err_mask |= AC_ERR_DEV;
713 if (port_status & (PDC_OVERRUN_ERR | PDC_UNDERRUN_ERR))
714 ac_err_mask |= AC_ERR_HSM;
715 if (port_status & (PDC2_ATA_HBA_ERR | PDC2_ATA_DMA_CNT_ERR))
716 ac_err_mask |= AC_ERR_ATA_BUS;
717 if (port_status & (PDC_PH_ERR | PDC_SH_ERR | PDC_DH_ERR | PDC2_HTO_ERR
718 | PDC_PCI_SYS_ERR | PDC1_PCI_PARITY_ERR))
719 ac_err_mask |= AC_ERR_HOST_BUS;
721 if (sata_scr_valid(&ap->link)) {
724 pdc_sata_scr_read(ap, SCR_ERROR, &serror);
725 ehi->serror |= serror;
728 qc->err_mask |= ac_err_mask;
735 static inline unsigned int pdc_host_intr(struct ata_port *ap,
736 struct ata_queued_cmd *qc)
738 unsigned int handled = 0;
739 void __iomem *port_mmio = ap->ioaddr.cmd_addr;
740 u32 port_status, err_mask;
742 err_mask = PDC_ERR_MASK;
743 if (ap->flags & PDC_FLAG_GEN_II)
744 err_mask &= ~PDC1_ERR_MASK;
746 err_mask &= ~PDC2_ERR_MASK;
747 port_status = readl(port_mmio + PDC_GLOBAL_CTL);
748 if (unlikely(port_status & err_mask)) {
749 pdc_error_intr(ap, qc, port_status, err_mask);
753 switch (qc->tf.protocol) {
755 case ATA_PROT_NODATA:
756 case ATA_PROT_ATAPI_DMA:
757 case ATA_PROT_ATAPI_NODATA:
758 qc->err_mask |= ac_err_mask(ata_wait_idle(ap));
764 ap->stats.idle_irq++;
771 static void pdc_irq_clear(struct ata_port *ap)
773 struct ata_host *host = ap->host;
774 void __iomem *mmio = host->iomap[PDC_MMIO_BAR];
776 readl(mmio + PDC_INT_SEQMASK);
779 static int pdc_is_sataii_tx4(unsigned long flags)
781 const unsigned long mask = PDC_FLAG_GEN_II | PDC_FLAG_4_PORTS;
782 return (flags & mask) == mask;
785 static unsigned int pdc_port_no_to_ata_no(unsigned int port_no,
788 static const unsigned char sataii_tx4_port_remap[4] = { 3, 1, 0, 2};
789 return is_sataii_tx4 ? sataii_tx4_port_remap[port_no] : port_no;
792 static irqreturn_t pdc_interrupt(int irq, void *dev_instance)
794 struct ata_host *host = dev_instance;
798 unsigned int handled = 0;
799 void __iomem *mmio_base;
800 unsigned int hotplug_offset, ata_no;
806 if (!host || !host->iomap[PDC_MMIO_BAR]) {
807 VPRINTK("QUICK EXIT\n");
811 mmio_base = host->iomap[PDC_MMIO_BAR];
813 /* read and clear hotplug flags for all ports */
814 if (host->ports[0]->flags & PDC_FLAG_GEN_II)
815 hotplug_offset = PDC2_SATA_PLUG_CSR;
817 hotplug_offset = PDC_SATA_PLUG_CSR;
818 hotplug_status = readl(mmio_base + hotplug_offset);
819 if (hotplug_status & 0xff)
820 writel(hotplug_status | 0xff, mmio_base + hotplug_offset);
821 hotplug_status &= 0xff; /* clear uninteresting bits */
823 /* reading should also clear interrupts */
824 mask = readl(mmio_base + PDC_INT_SEQMASK);
826 if (mask == 0xffffffff && hotplug_status == 0) {
827 VPRINTK("QUICK EXIT 2\n");
831 spin_lock(&host->lock);
833 mask &= 0xffff; /* only 16 tags possible */
834 if (mask == 0 && hotplug_status == 0) {
835 VPRINTK("QUICK EXIT 3\n");
839 writel(mask, mmio_base + PDC_INT_SEQMASK);
841 is_sataii_tx4 = pdc_is_sataii_tx4(host->ports[0]->flags);
843 for (i = 0; i < host->n_ports; i++) {
844 VPRINTK("port %u\n", i);
847 /* check for a plug or unplug event */
848 ata_no = pdc_port_no_to_ata_no(i, is_sataii_tx4);
849 tmp = hotplug_status & (0x11 << ata_no);
851 !(ap->flags & ATA_FLAG_DISABLED)) {
852 struct ata_eh_info *ehi = &ap->link.eh_info;
853 ata_ehi_clear_desc(ehi);
854 ata_ehi_hotplugged(ehi);
855 ata_ehi_push_desc(ehi, "hotplug_status %#x", tmp);
861 /* check for a packet interrupt */
862 tmp = mask & (1 << (i + 1));
864 !(ap->flags & ATA_FLAG_DISABLED)) {
865 struct ata_queued_cmd *qc;
867 qc = ata_qc_from_tag(ap, ap->link.active_tag);
868 if (qc && (!(qc->tf.flags & ATA_TFLAG_POLLING)))
869 handled += pdc_host_intr(ap, qc);
876 spin_unlock(&host->lock);
877 return IRQ_RETVAL(handled);
880 static inline void pdc_packet_start(struct ata_queued_cmd *qc)
882 struct ata_port *ap = qc->ap;
883 struct pdc_port_priv *pp = ap->private_data;
884 void __iomem *mmio = ap->host->iomap[PDC_MMIO_BAR];
885 unsigned int port_no = ap->port_no;
886 u8 seq = (u8) (port_no + 1);
888 VPRINTK("ENTER, ap %p\n", ap);
890 writel(0x00000001, mmio + (seq * 4));
891 readl(mmio + (seq * 4)); /* flush */
894 wmb(); /* flush PRD, pkt writes */
895 writel(pp->pkt_dma, ap->ioaddr.cmd_addr + PDC_PKT_SUBMIT);
896 readl(ap->ioaddr.cmd_addr + PDC_PKT_SUBMIT); /* flush */
899 static unsigned int pdc_qc_issue_prot(struct ata_queued_cmd *qc)
901 switch (qc->tf.protocol) {
902 case ATA_PROT_ATAPI_NODATA:
903 if (qc->dev->flags & ATA_DFLAG_CDB_INTR)
906 case ATA_PROT_NODATA:
907 if (qc->tf.flags & ATA_TFLAG_POLLING)
910 case ATA_PROT_ATAPI_DMA:
912 pdc_packet_start(qc);
919 return ata_qc_issue_prot(qc);
922 static void pdc_tf_load_mmio(struct ata_port *ap, const struct ata_taskfile *tf)
924 WARN_ON(tf->protocol == ATA_PROT_DMA ||
925 tf->protocol == ATA_PROT_ATAPI_DMA);
929 static void pdc_exec_command_mmio(struct ata_port *ap,
930 const struct ata_taskfile *tf)
932 WARN_ON(tf->protocol == ATA_PROT_DMA ||
933 tf->protocol == ATA_PROT_ATAPI_DMA);
934 ata_exec_command(ap, tf);
937 static int pdc_check_atapi_dma(struct ata_queued_cmd *qc)
939 u8 *scsicmd = qc->scsicmd->cmnd;
940 int pio = 1; /* atapi dma off by default */
942 /* Whitelist commands that may use DMA. */
943 switch (scsicmd[0]) {
950 case 0xad: /* READ_DVD_STRUCTURE */
951 case 0xbe: /* READ_CD */
954 /* -45150 (FFFF4FA2) to -1 (FFFFFFFF) shall use PIO mode */
955 if (scsicmd[0] == WRITE_10) {
961 if (lba >= 0xFFFF4FA2)
967 static int pdc_old_sata_check_atapi_dma(struct ata_queued_cmd *qc)
969 /* First generation chips cannot use ATAPI DMA on SATA ports */
973 static void pdc_ata_setup_port(struct ata_port *ap,
974 void __iomem *base, void __iomem *scr_addr)
976 ap->ioaddr.cmd_addr = base;
977 ap->ioaddr.data_addr = base;
978 ap->ioaddr.feature_addr =
979 ap->ioaddr.error_addr = base + 0x4;
980 ap->ioaddr.nsect_addr = base + 0x8;
981 ap->ioaddr.lbal_addr = base + 0xc;
982 ap->ioaddr.lbam_addr = base + 0x10;
983 ap->ioaddr.lbah_addr = base + 0x14;
984 ap->ioaddr.device_addr = base + 0x18;
985 ap->ioaddr.command_addr =
986 ap->ioaddr.status_addr = base + 0x1c;
987 ap->ioaddr.altstatus_addr =
988 ap->ioaddr.ctl_addr = base + 0x38;
989 ap->ioaddr.scr_addr = scr_addr;
992 static void pdc_host_init(struct ata_host *host)
994 void __iomem *mmio = host->iomap[PDC_MMIO_BAR];
995 int is_gen2 = host->ports[0]->flags & PDC_FLAG_GEN_II;
1000 hotplug_offset = PDC2_SATA_PLUG_CSR;
1002 hotplug_offset = PDC_SATA_PLUG_CSR;
1005 * Except for the hotplug stuff, this is voodoo from the
1006 * Promise driver. Label this entire section
1007 * "TODO: figure out why we do this"
1010 /* enable BMR_BURST, maybe change FIFO_SHD to 8 dwords */
1011 tmp = readl(mmio + PDC_FLASH_CTL);
1012 tmp |= 0x02000; /* bit 13 (enable bmr burst) */
1014 tmp |= 0x10000; /* bit 16 (fifo threshold at 8 dw) */
1015 writel(tmp, mmio + PDC_FLASH_CTL);
1017 /* clear plug/unplug flags for all ports */
1018 tmp = readl(mmio + hotplug_offset);
1019 writel(tmp | 0xff, mmio + hotplug_offset);
1021 /* unmask plug/unplug ints */
1022 tmp = readl(mmio + hotplug_offset);
1023 writel(tmp & ~0xff0000, mmio + hotplug_offset);
1025 /* don't initialise TBG or SLEW on 2nd generation chips */
1029 /* reduce TBG clock to 133 Mhz. */
1030 tmp = readl(mmio + PDC_TBG_MODE);
1031 tmp &= ~0x30000; /* clear bit 17, 16*/
1032 tmp |= 0x10000; /* set bit 17:16 = 0:1 */
1033 writel(tmp, mmio + PDC_TBG_MODE);
1035 readl(mmio + PDC_TBG_MODE); /* flush */
1038 /* adjust slew rate control register. */
1039 tmp = readl(mmio + PDC_SLEW_CTL);
1040 tmp &= 0xFFFFF03F; /* clear bit 11 ~ 6 */
1041 tmp |= 0x00000900; /* set bit 11-9 = 100b , bit 8-6 = 100 */
1042 writel(tmp, mmio + PDC_SLEW_CTL);
1045 static int pdc_ata_init_one(struct pci_dev *pdev,
1046 const struct pci_device_id *ent)
1048 static int printed_version;
1049 const struct ata_port_info *pi = &pdc_port_info[ent->driver_data];
1050 const struct ata_port_info *ppi[PDC_MAX_PORTS];
1051 struct ata_host *host;
1056 if (!printed_version++)
1057 dev_printk(KERN_DEBUG, &pdev->dev, "version " DRV_VERSION "\n");
1059 /* enable and acquire resources */
1060 rc = pcim_enable_device(pdev);
1064 rc = pcim_iomap_regions(pdev, 1 << PDC_MMIO_BAR, DRV_NAME);
1066 pcim_pin_device(pdev);
1069 base = pcim_iomap_table(pdev)[PDC_MMIO_BAR];
1071 /* determine port configuration and setup host */
1073 if (pi->flags & PDC_FLAG_4_PORTS)
1075 for (i = 0; i < n_ports; i++)
1078 if (pi->flags & PDC_FLAG_SATA_PATA) {
1079 u8 tmp = readb(base + PDC_FLASH_CTL+1);
1081 ppi[n_ports++] = pi + 1;
1084 host = ata_host_alloc_pinfo(&pdev->dev, ppi, n_ports);
1086 dev_printk(KERN_ERR, &pdev->dev, "failed to allocate host\n");
1089 host->iomap = pcim_iomap_table(pdev);
1091 is_sataii_tx4 = pdc_is_sataii_tx4(pi->flags);
1092 for (i = 0; i < host->n_ports; i++) {
1093 struct ata_port *ap = host->ports[i];
1094 unsigned int ata_no = pdc_port_no_to_ata_no(i, is_sataii_tx4);
1095 unsigned int port_offset = 0x200 + ata_no * 0x80;
1096 unsigned int scr_offset = 0x400 + ata_no * 0x100;
1098 pdc_ata_setup_port(ap, base + port_offset, base + scr_offset);
1100 ata_port_pbar_desc(ap, PDC_MMIO_BAR, -1, "mmio");
1101 ata_port_pbar_desc(ap, PDC_MMIO_BAR, port_offset, "port");
1104 /* initialize adapter */
1105 pdc_host_init(host);
1107 rc = pci_set_dma_mask(pdev, ATA_DMA_MASK);
1110 rc = pci_set_consistent_dma_mask(pdev, ATA_DMA_MASK);
1114 /* start host, request IRQ and attach */
1115 pci_set_master(pdev);
1116 return ata_host_activate(host, pdev->irq, pdc_interrupt, IRQF_SHARED,
1120 static int __init pdc_ata_init(void)
1122 return pci_register_driver(&pdc_ata_pci_driver);
1125 static void __exit pdc_ata_exit(void)
1127 pci_unregister_driver(&pdc_ata_pci_driver);
1130 MODULE_AUTHOR("Jeff Garzik");
1131 MODULE_DESCRIPTION("Promise ATA TX2/TX4/TX4000 low-level driver");
1132 MODULE_LICENSE("GPL");
1133 MODULE_DEVICE_TABLE(pci, pdc_ata_pci_tbl);
1134 MODULE_VERSION(DRV_VERSION);
1136 module_init(pdc_ata_init);
1137 module_exit(pdc_ata_exit);