2 * sata_promise.c - Promise SATA
4 * Maintained by: Jeff Garzik <jgarzik@pobox.com>
5 * Please ALWAYS copy linux-ide@vger.kernel.org
8 * Copyright 2003-2004 Red Hat, Inc.
11 * This program is free software; you can redistribute it and/or modify
12 * it under the terms of the GNU General Public License as published by
13 * the Free Software Foundation; either version 2, or (at your option)
16 * This program is distributed in the hope that it will be useful,
17 * but WITHOUT ANY WARRANTY; without even the implied warranty of
18 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
19 * GNU General Public License for more details.
21 * You should have received a copy of the GNU General Public License
22 * along with this program; see the file COPYING. If not, write to
23 * the Free Software Foundation, 675 Mass Ave, Cambridge, MA 02139, USA.
26 * libata documentation is available via 'make {ps|pdf}docs',
27 * as Documentation/DocBook/libata.*
29 * Hardware information only available under NDA.
33 #include <linux/kernel.h>
34 #include <linux/module.h>
35 #include <linux/pci.h>
36 #include <linux/init.h>
37 #include <linux/blkdev.h>
38 #include <linux/delay.h>
39 #include <linux/interrupt.h>
40 #include <linux/device.h>
41 #include <scsi/scsi.h>
42 #include <scsi/scsi_host.h>
43 #include <scsi/scsi_cmnd.h>
44 #include <linux/libata.h>
45 #include "sata_promise.h"
47 #define DRV_NAME "sata_promise"
48 #define DRV_VERSION "2.10"
54 /* register offsets */
55 PDC_FEATURE = 0x04, /* Feature/Error reg (per port) */
56 PDC_SECTOR_COUNT = 0x08, /* Sector count reg (per port) */
57 PDC_SECTOR_NUMBER = 0x0C, /* Sector number reg (per port) */
58 PDC_CYLINDER_LOW = 0x10, /* Cylinder low reg (per port) */
59 PDC_CYLINDER_HIGH = 0x14, /* Cylinder high reg (per port) */
60 PDC_DEVICE = 0x18, /* Device/Head reg (per port) */
61 PDC_COMMAND = 0x1C, /* Command/status reg (per port) */
62 PDC_ALTSTATUS = 0x38, /* Alternate-status/device-control reg (per port) */
63 PDC_PKT_SUBMIT = 0x40, /* Command packet pointer addr */
64 PDC_INT_SEQMASK = 0x40, /* Mask of asserted SEQ INTs */
65 PDC_FLASH_CTL = 0x44, /* Flash control register */
66 PDC_GLOBAL_CTL = 0x48, /* Global control/status (per port) */
67 PDC_CTLSTAT = 0x60, /* IDE control and status (per port) */
68 PDC_SATA_PLUG_CSR = 0x6C, /* SATA Plug control/status reg */
69 PDC2_SATA_PLUG_CSR = 0x60, /* SATAII Plug control/status reg */
70 PDC_TBG_MODE = 0x41C, /* TBG mode (not SATAII) */
71 PDC_SLEW_CTL = 0x470, /* slew rate control reg (not SATAII) */
73 /* PDC_GLOBAL_CTL bit definitions */
74 PDC_PH_ERR = (1 << 8), /* PCI error while loading packet */
75 PDC_SH_ERR = (1 << 9), /* PCI error while loading S/G table */
76 PDC_DH_ERR = (1 << 10), /* PCI error while loading data */
77 PDC2_HTO_ERR = (1 << 12), /* host bus timeout */
78 PDC2_ATA_HBA_ERR = (1 << 13), /* error during SATA DATA FIS transmission */
79 PDC2_ATA_DMA_CNT_ERR = (1 << 14), /* DMA DATA FIS size differs from S/G count */
80 PDC_OVERRUN_ERR = (1 << 19), /* S/G byte count larger than HD requires */
81 PDC_UNDERRUN_ERR = (1 << 20), /* S/G byte count less than HD requires */
82 PDC_DRIVE_ERR = (1 << 21), /* drive error */
83 PDC_PCI_SYS_ERR = (1 << 22), /* PCI system error */
84 PDC1_PCI_PARITY_ERR = (1 << 23), /* PCI parity error (from SATA150 driver) */
85 PDC1_ERR_MASK = PDC1_PCI_PARITY_ERR,
86 PDC2_ERR_MASK = PDC2_HTO_ERR | PDC2_ATA_HBA_ERR |
88 PDC_ERR_MASK = PDC_PH_ERR | PDC_SH_ERR | PDC_DH_ERR |
89 PDC_OVERRUN_ERR | PDC_UNDERRUN_ERR |
90 PDC_DRIVE_ERR | PDC_PCI_SYS_ERR |
91 PDC1_ERR_MASK | PDC2_ERR_MASK,
93 board_2037x = 0, /* FastTrak S150 TX2plus */
94 board_2037x_pata = 1, /* FastTrak S150 TX2plus PATA port */
95 board_20319 = 2, /* FastTrak S150 TX4 */
96 board_20619 = 3, /* FastTrak TX4000 */
97 board_2057x = 4, /* SATAII150 Tx2plus */
98 board_2057x_pata = 5, /* SATAII150 Tx2plus PATA port */
99 board_40518 = 6, /* SATAII150 Tx4 */
101 PDC_HAS_PATA = (1 << 1), /* PDC20375/20575 has PATA */
103 /* Sequence counter control registers bit definitions */
104 PDC_SEQCNTRL_INT_MASK = (1 << 5), /* Sequence Interrupt Mask */
106 /* Feature register values */
107 PDC_FEATURE_ATAPI_PIO = 0x00, /* ATAPI data xfer by PIO */
108 PDC_FEATURE_ATAPI_DMA = 0x01, /* ATAPI data xfer by DMA */
110 /* Device/Head register values */
111 PDC_DEVICE_SATA = 0xE0, /* Device/Head value for SATA devices */
113 /* PDC_CTLSTAT bit definitions */
114 PDC_DMA_ENABLE = (1 << 7),
115 PDC_IRQ_DISABLE = (1 << 10),
116 PDC_RESET = (1 << 11), /* HDMA reset */
118 PDC_COMMON_FLAGS = ATA_FLAG_NO_LEGACY |
120 ATA_FLAG_PIO_POLLING,
123 PDC_FLAG_GEN_II = (1 << 24),
124 PDC_FLAG_SATA_PATA = (1 << 25), /* supports SATA + PATA */
125 PDC_FLAG_4_PORTS = (1 << 26), /* 4 ports */
128 struct pdc_port_priv {
133 static int pdc_sata_scr_read(struct ata_port *ap, unsigned int sc_reg, u32 *val);
134 static int pdc_sata_scr_write(struct ata_port *ap, unsigned int sc_reg, u32 val);
135 static int pdc_ata_init_one (struct pci_dev *pdev, const struct pci_device_id *ent);
136 static int pdc_common_port_start(struct ata_port *ap);
137 static int pdc_sata_port_start(struct ata_port *ap);
138 static void pdc_qc_prep(struct ata_queued_cmd *qc);
139 static void pdc_tf_load_mmio(struct ata_port *ap, const struct ata_taskfile *tf);
140 static void pdc_exec_command_mmio(struct ata_port *ap, const struct ata_taskfile *tf);
141 static int pdc_check_atapi_dma(struct ata_queued_cmd *qc);
142 static int pdc_old_sata_check_atapi_dma(struct ata_queued_cmd *qc);
143 static void pdc_irq_clear(struct ata_port *ap);
144 static unsigned int pdc_qc_issue_prot(struct ata_queued_cmd *qc);
145 static void pdc_freeze(struct ata_port *ap);
146 static void pdc_thaw(struct ata_port *ap);
147 static void pdc_pata_error_handler(struct ata_port *ap);
148 static void pdc_sata_error_handler(struct ata_port *ap);
149 static void pdc_post_internal_cmd(struct ata_queued_cmd *qc);
150 static int pdc_pata_cable_detect(struct ata_port *ap);
151 static int pdc_sata_cable_detect(struct ata_port *ap);
153 static struct scsi_host_template pdc_ata_sht = {
154 .module = THIS_MODULE,
156 .ioctl = ata_scsi_ioctl,
157 .queuecommand = ata_scsi_queuecmd,
158 .can_queue = ATA_DEF_QUEUE,
159 .this_id = ATA_SHT_THIS_ID,
160 .sg_tablesize = LIBATA_MAX_PRD,
161 .cmd_per_lun = ATA_SHT_CMD_PER_LUN,
162 .emulated = ATA_SHT_EMULATED,
163 .use_clustering = ATA_SHT_USE_CLUSTERING,
164 .proc_name = DRV_NAME,
165 .dma_boundary = ATA_DMA_BOUNDARY,
166 .slave_configure = ata_scsi_slave_config,
167 .slave_destroy = ata_scsi_slave_destroy,
168 .bios_param = ata_std_bios_param,
171 static const struct ata_port_operations pdc_sata_ops = {
172 .tf_load = pdc_tf_load_mmio,
173 .tf_read = ata_tf_read,
174 .check_status = ata_check_status,
175 .exec_command = pdc_exec_command_mmio,
176 .dev_select = ata_std_dev_select,
177 .check_atapi_dma = pdc_check_atapi_dma,
179 .qc_prep = pdc_qc_prep,
180 .qc_issue = pdc_qc_issue_prot,
181 .freeze = pdc_freeze,
183 .error_handler = pdc_sata_error_handler,
184 .post_internal_cmd = pdc_post_internal_cmd,
185 .cable_detect = pdc_sata_cable_detect,
186 .data_xfer = ata_data_xfer,
187 .irq_clear = pdc_irq_clear,
188 .irq_on = ata_irq_on,
190 .scr_read = pdc_sata_scr_read,
191 .scr_write = pdc_sata_scr_write,
192 .port_start = pdc_sata_port_start,
195 /* First-generation chips need a more restrictive ->check_atapi_dma op */
196 static const struct ata_port_operations pdc_old_sata_ops = {
197 .tf_load = pdc_tf_load_mmio,
198 .tf_read = ata_tf_read,
199 .check_status = ata_check_status,
200 .exec_command = pdc_exec_command_mmio,
201 .dev_select = ata_std_dev_select,
202 .check_atapi_dma = pdc_old_sata_check_atapi_dma,
204 .qc_prep = pdc_qc_prep,
205 .qc_issue = pdc_qc_issue_prot,
206 .freeze = pdc_freeze,
208 .error_handler = pdc_sata_error_handler,
209 .post_internal_cmd = pdc_post_internal_cmd,
210 .cable_detect = pdc_sata_cable_detect,
211 .data_xfer = ata_data_xfer,
212 .irq_clear = pdc_irq_clear,
213 .irq_on = ata_irq_on,
215 .scr_read = pdc_sata_scr_read,
216 .scr_write = pdc_sata_scr_write,
217 .port_start = pdc_sata_port_start,
220 static const struct ata_port_operations pdc_pata_ops = {
221 .tf_load = pdc_tf_load_mmio,
222 .tf_read = ata_tf_read,
223 .check_status = ata_check_status,
224 .exec_command = pdc_exec_command_mmio,
225 .dev_select = ata_std_dev_select,
226 .check_atapi_dma = pdc_check_atapi_dma,
228 .qc_prep = pdc_qc_prep,
229 .qc_issue = pdc_qc_issue_prot,
230 .freeze = pdc_freeze,
232 .error_handler = pdc_pata_error_handler,
233 .post_internal_cmd = pdc_post_internal_cmd,
234 .cable_detect = pdc_pata_cable_detect,
235 .data_xfer = ata_data_xfer,
236 .irq_clear = pdc_irq_clear,
237 .irq_on = ata_irq_on,
239 .port_start = pdc_common_port_start,
242 static const struct ata_port_info pdc_port_info[] = {
245 .flags = PDC_COMMON_FLAGS | ATA_FLAG_SATA |
247 .pio_mask = 0x1f, /* pio0-4 */
248 .mwdma_mask = 0x07, /* mwdma0-2 */
249 .udma_mask = ATA_UDMA6,
250 .port_ops = &pdc_old_sata_ops,
253 /* board_2037x_pata */
255 .flags = PDC_COMMON_FLAGS | ATA_FLAG_SLAVE_POSS,
256 .pio_mask = 0x1f, /* pio0-4 */
257 .mwdma_mask = 0x07, /* mwdma0-2 */
258 .udma_mask = ATA_UDMA6,
259 .port_ops = &pdc_pata_ops,
264 .flags = PDC_COMMON_FLAGS | ATA_FLAG_SATA |
266 .pio_mask = 0x1f, /* pio0-4 */
267 .mwdma_mask = 0x07, /* mwdma0-2 */
268 .udma_mask = ATA_UDMA6,
269 .port_ops = &pdc_old_sata_ops,
274 .flags = PDC_COMMON_FLAGS | ATA_FLAG_SLAVE_POSS |
276 .pio_mask = 0x1f, /* pio0-4 */
277 .mwdma_mask = 0x07, /* mwdma0-2 */
278 .udma_mask = ATA_UDMA6,
279 .port_ops = &pdc_pata_ops,
284 .flags = PDC_COMMON_FLAGS | ATA_FLAG_SATA |
285 PDC_FLAG_GEN_II | PDC_FLAG_SATA_PATA,
286 .pio_mask = 0x1f, /* pio0-4 */
287 .mwdma_mask = 0x07, /* mwdma0-2 */
288 .udma_mask = ATA_UDMA6,
289 .port_ops = &pdc_sata_ops,
292 /* board_2057x_pata */
294 .flags = PDC_COMMON_FLAGS | ATA_FLAG_SLAVE_POSS |
296 .pio_mask = 0x1f, /* pio0-4 */
297 .mwdma_mask = 0x07, /* mwdma0-2 */
298 .udma_mask = ATA_UDMA6,
299 .port_ops = &pdc_pata_ops,
304 .flags = PDC_COMMON_FLAGS | ATA_FLAG_SATA |
305 PDC_FLAG_GEN_II | PDC_FLAG_4_PORTS,
306 .pio_mask = 0x1f, /* pio0-4 */
307 .mwdma_mask = 0x07, /* mwdma0-2 */
308 .udma_mask = ATA_UDMA6,
309 .port_ops = &pdc_sata_ops,
313 static const struct pci_device_id pdc_ata_pci_tbl[] = {
314 { PCI_VDEVICE(PROMISE, 0x3371), board_2037x },
315 { PCI_VDEVICE(PROMISE, 0x3373), board_2037x },
316 { PCI_VDEVICE(PROMISE, 0x3375), board_2037x },
317 { PCI_VDEVICE(PROMISE, 0x3376), board_2037x },
318 { PCI_VDEVICE(PROMISE, 0x3570), board_2057x },
319 { PCI_VDEVICE(PROMISE, 0x3571), board_2057x },
320 { PCI_VDEVICE(PROMISE, 0x3574), board_2057x },
321 { PCI_VDEVICE(PROMISE, 0x3577), board_2057x },
322 { PCI_VDEVICE(PROMISE, 0x3d73), board_2057x },
323 { PCI_VDEVICE(PROMISE, 0x3d75), board_2057x },
325 { PCI_VDEVICE(PROMISE, 0x3318), board_20319 },
326 { PCI_VDEVICE(PROMISE, 0x3319), board_20319 },
327 { PCI_VDEVICE(PROMISE, 0x3515), board_40518 },
328 { PCI_VDEVICE(PROMISE, 0x3519), board_40518 },
329 { PCI_VDEVICE(PROMISE, 0x3d17), board_40518 },
330 { PCI_VDEVICE(PROMISE, 0x3d18), board_40518 },
332 { PCI_VDEVICE(PROMISE, 0x6629), board_20619 },
334 { } /* terminate list */
337 static struct pci_driver pdc_ata_pci_driver = {
339 .id_table = pdc_ata_pci_tbl,
340 .probe = pdc_ata_init_one,
341 .remove = ata_pci_remove_one,
344 static int pdc_common_port_start(struct ata_port *ap)
346 struct device *dev = ap->host->dev;
347 struct pdc_port_priv *pp;
350 rc = ata_port_start(ap);
354 pp = devm_kzalloc(dev, sizeof(*pp), GFP_KERNEL);
358 pp->pkt = dmam_alloc_coherent(dev, 128, &pp->pkt_dma, GFP_KERNEL);
362 ap->private_data = pp;
367 static int pdc_sata_port_start(struct ata_port *ap)
371 rc = pdc_common_port_start(ap);
375 /* fix up PHYMODE4 align timing */
376 if (ap->flags & PDC_FLAG_GEN_II) {
377 void __iomem *mmio = ap->ioaddr.scr_addr;
380 tmp = readl(mmio + 0x014);
381 tmp = (tmp & ~3) | 1; /* set bits 1:0 = 0:1 */
382 writel(tmp, mmio + 0x014);
388 static void pdc_reset_port(struct ata_port *ap)
390 void __iomem *mmio = ap->ioaddr.cmd_addr + PDC_CTLSTAT;
394 for (i = 11; i > 0; i--) {
407 readl(mmio); /* flush */
410 static int pdc_pata_cable_detect(struct ata_port *ap)
413 void __iomem *mmio = ap->ioaddr.cmd_addr + PDC_CTLSTAT + 0x03;
417 return ATA_CBL_PATA40;
418 return ATA_CBL_PATA80;
421 static int pdc_sata_cable_detect(struct ata_port *ap)
426 static int pdc_sata_scr_read(struct ata_port *ap, unsigned int sc_reg, u32 *val)
428 if (sc_reg > SCR_CONTROL)
430 *val = readl(ap->ioaddr.scr_addr + (sc_reg * 4));
434 static int pdc_sata_scr_write(struct ata_port *ap, unsigned int sc_reg, u32 val)
436 if (sc_reg > SCR_CONTROL)
438 writel(val, ap->ioaddr.scr_addr + (sc_reg * 4));
442 static void pdc_atapi_pkt(struct ata_queued_cmd *qc)
444 struct ata_port *ap = qc->ap;
445 dma_addr_t sg_table = ap->prd_dma;
446 unsigned int cdb_len = qc->dev->cdb_len;
448 struct pdc_port_priv *pp = ap->private_data;
450 u32 *buf32 = (u32 *) buf;
451 unsigned int dev_sel, feature, nbytes;
453 /* set control bits (byte 0), zero delay seq id (byte 3),
454 * and seq id (byte 2)
456 switch (qc->tf.protocol) {
457 case ATA_PROT_ATAPI_DMA:
458 if (!(qc->tf.flags & ATA_TFLAG_WRITE))
459 buf32[0] = cpu_to_le32(PDC_PKT_READ);
463 case ATA_PROT_ATAPI_NODATA:
464 buf32[0] = cpu_to_le32(PDC_PKT_NODATA);
470 buf32[1] = cpu_to_le32(sg_table); /* S/G table addr */
471 buf32[2] = 0; /* no next-packet */
474 if (sata_scr_valid(&ap->link)) {
475 dev_sel = PDC_DEVICE_SATA;
477 dev_sel = ATA_DEVICE_OBS;
478 if (qc->dev->devno != 0)
481 buf[12] = (1 << 5) | ATA_REG_DEVICE;
483 buf[14] = (1 << 5) | ATA_REG_DEVICE | PDC_PKT_CLEAR_BSY;
484 buf[15] = dev_sel; /* once more, waiting for BSY to clear */
486 buf[16] = (1 << 5) | ATA_REG_NSECT;
488 buf[18] = (1 << 5) | ATA_REG_LBAL;
491 /* set feature and byte counter registers */
492 if (qc->tf.protocol != ATA_PROT_ATAPI_DMA) {
493 feature = PDC_FEATURE_ATAPI_PIO;
494 /* set byte counter register to real transfer byte count */
499 feature = PDC_FEATURE_ATAPI_DMA;
500 /* set byte counter register to 0 */
503 buf[20] = (1 << 5) | ATA_REG_FEATURE;
505 buf[22] = (1 << 5) | ATA_REG_BYTEL;
506 buf[23] = nbytes & 0xFF;
507 buf[24] = (1 << 5) | ATA_REG_BYTEH;
508 buf[25] = (nbytes >> 8) & 0xFF;
510 /* send ATAPI packet command 0xA0 */
511 buf[26] = (1 << 5) | ATA_REG_CMD;
512 buf[27] = ATA_CMD_PACKET;
514 /* select drive and check DRQ */
515 buf[28] = (1 << 5) | ATA_REG_DEVICE | PDC_PKT_WAIT_DRDY;
518 /* we can represent cdb lengths 2/4/6/8/10/12/14/16 */
519 BUG_ON(cdb_len & ~0x1E);
521 /* append the CDB as the final part */
522 buf[30] = (((cdb_len >> 1) & 7) << 5) | ATA_REG_DATA | PDC_LAST_REG;
523 memcpy(buf+31, cdb, cdb_len);
526 static void pdc_qc_prep(struct ata_queued_cmd *qc)
528 struct pdc_port_priv *pp = qc->ap->private_data;
533 switch (qc->tf.protocol) {
538 case ATA_PROT_NODATA:
539 i = pdc_pkt_header(&qc->tf, qc->ap->prd_dma,
540 qc->dev->devno, pp->pkt);
542 if (qc->tf.flags & ATA_TFLAG_LBA48)
543 i = pdc_prep_lba48(&qc->tf, pp->pkt, i);
545 i = pdc_prep_lba28(&qc->tf, pp->pkt, i);
547 pdc_pkt_footer(&qc->tf, pp->pkt, i);
554 case ATA_PROT_ATAPI_DMA:
557 case ATA_PROT_ATAPI_NODATA:
566 static void pdc_freeze(struct ata_port *ap)
568 void __iomem *mmio = ap->ioaddr.cmd_addr;
571 tmp = readl(mmio + PDC_CTLSTAT);
572 tmp |= PDC_IRQ_DISABLE;
573 tmp &= ~PDC_DMA_ENABLE;
574 writel(tmp, mmio + PDC_CTLSTAT);
575 readl(mmio + PDC_CTLSTAT); /* flush */
578 static void pdc_thaw(struct ata_port *ap)
580 void __iomem *mmio = ap->ioaddr.cmd_addr;
584 readl(mmio + PDC_INT_SEQMASK);
586 /* turn IRQ back on */
587 tmp = readl(mmio + PDC_CTLSTAT);
588 tmp &= ~PDC_IRQ_DISABLE;
589 writel(tmp, mmio + PDC_CTLSTAT);
590 readl(mmio + PDC_CTLSTAT); /* flush */
593 static void pdc_common_error_handler(struct ata_port *ap, ata_reset_fn_t hardreset)
595 if (!(ap->pflags & ATA_PFLAG_FROZEN))
598 /* perform recovery */
599 ata_do_eh(ap, ata_std_prereset, ata_std_softreset, hardreset,
603 static void pdc_pata_error_handler(struct ata_port *ap)
605 pdc_common_error_handler(ap, NULL);
608 static void pdc_sata_error_handler(struct ata_port *ap)
610 pdc_common_error_handler(ap, sata_std_hardreset);
613 static void pdc_post_internal_cmd(struct ata_queued_cmd *qc)
615 struct ata_port *ap = qc->ap;
617 /* make DMA engine forget about the failed command */
618 if (qc->flags & ATA_QCFLAG_FAILED)
622 static void pdc_error_intr(struct ata_port *ap, struct ata_queued_cmd *qc,
623 u32 port_status, u32 err_mask)
625 struct ata_eh_info *ehi = &ap->link.eh_info;
626 unsigned int ac_err_mask = 0;
628 ata_ehi_clear_desc(ehi);
629 ata_ehi_push_desc(ehi, "port_status 0x%08x", port_status);
630 port_status &= err_mask;
632 if (port_status & PDC_DRIVE_ERR)
633 ac_err_mask |= AC_ERR_DEV;
634 if (port_status & (PDC_OVERRUN_ERR | PDC_UNDERRUN_ERR))
635 ac_err_mask |= AC_ERR_HSM;
636 if (port_status & (PDC2_ATA_HBA_ERR | PDC2_ATA_DMA_CNT_ERR))
637 ac_err_mask |= AC_ERR_ATA_BUS;
638 if (port_status & (PDC_PH_ERR | PDC_SH_ERR | PDC_DH_ERR | PDC2_HTO_ERR
639 | PDC_PCI_SYS_ERR | PDC1_PCI_PARITY_ERR))
640 ac_err_mask |= AC_ERR_HOST_BUS;
642 if (sata_scr_valid(&ap->link)) {
645 pdc_sata_scr_read(ap, SCR_ERROR, &serror);
646 ehi->serror |= serror;
649 qc->err_mask |= ac_err_mask;
656 static inline unsigned int pdc_host_intr(struct ata_port *ap,
657 struct ata_queued_cmd *qc)
659 unsigned int handled = 0;
660 void __iomem *port_mmio = ap->ioaddr.cmd_addr;
661 u32 port_status, err_mask;
663 err_mask = PDC_ERR_MASK;
664 if (ap->flags & PDC_FLAG_GEN_II)
665 err_mask &= ~PDC1_ERR_MASK;
667 err_mask &= ~PDC2_ERR_MASK;
668 port_status = readl(port_mmio + PDC_GLOBAL_CTL);
669 if (unlikely(port_status & err_mask)) {
670 pdc_error_intr(ap, qc, port_status, err_mask);
674 switch (qc->tf.protocol) {
676 case ATA_PROT_NODATA:
677 case ATA_PROT_ATAPI_DMA:
678 case ATA_PROT_ATAPI_NODATA:
679 qc->err_mask |= ac_err_mask(ata_wait_idle(ap));
685 ap->stats.idle_irq++;
692 static void pdc_irq_clear(struct ata_port *ap)
694 struct ata_host *host = ap->host;
695 void __iomem *mmio = host->iomap[PDC_MMIO_BAR];
697 readl(mmio + PDC_INT_SEQMASK);
700 static int pdc_is_sataii_tx4(unsigned long flags)
702 const unsigned long mask = PDC_FLAG_GEN_II | PDC_FLAG_4_PORTS;
703 return (flags & mask) == mask;
706 static unsigned int pdc_port_no_to_ata_no(unsigned int port_no,
709 static const unsigned char sataii_tx4_port_remap[4] = { 3, 1, 0, 2};
710 return is_sataii_tx4 ? sataii_tx4_port_remap[port_no] : port_no;
713 static irqreturn_t pdc_interrupt(int irq, void *dev_instance)
715 struct ata_host *host = dev_instance;
719 unsigned int handled = 0;
720 void __iomem *mmio_base;
721 unsigned int hotplug_offset, ata_no;
727 if (!host || !host->iomap[PDC_MMIO_BAR]) {
728 VPRINTK("QUICK EXIT\n");
732 mmio_base = host->iomap[PDC_MMIO_BAR];
734 /* read and clear hotplug flags for all ports */
735 if (host->ports[0]->flags & PDC_FLAG_GEN_II)
736 hotplug_offset = PDC2_SATA_PLUG_CSR;
738 hotplug_offset = PDC_SATA_PLUG_CSR;
739 hotplug_status = readl(mmio_base + hotplug_offset);
740 if (hotplug_status & 0xff)
741 writel(hotplug_status | 0xff, mmio_base + hotplug_offset);
742 hotplug_status &= 0xff; /* clear uninteresting bits */
744 /* reading should also clear interrupts */
745 mask = readl(mmio_base + PDC_INT_SEQMASK);
747 if (mask == 0xffffffff && hotplug_status == 0) {
748 VPRINTK("QUICK EXIT 2\n");
752 spin_lock(&host->lock);
754 mask &= 0xffff; /* only 16 tags possible */
755 if (mask == 0 && hotplug_status == 0) {
756 VPRINTK("QUICK EXIT 3\n");
760 writel(mask, mmio_base + PDC_INT_SEQMASK);
762 is_sataii_tx4 = pdc_is_sataii_tx4(host->ports[0]->flags);
764 for (i = 0; i < host->n_ports; i++) {
765 VPRINTK("port %u\n", i);
768 /* check for a plug or unplug event */
769 ata_no = pdc_port_no_to_ata_no(i, is_sataii_tx4);
770 tmp = hotplug_status & (0x11 << ata_no);
772 !(ap->flags & ATA_FLAG_DISABLED)) {
773 struct ata_eh_info *ehi = &ap->link.eh_info;
774 ata_ehi_clear_desc(ehi);
775 ata_ehi_hotplugged(ehi);
776 ata_ehi_push_desc(ehi, "hotplug_status %#x", tmp);
782 /* check for a packet interrupt */
783 tmp = mask & (1 << (i + 1));
785 !(ap->flags & ATA_FLAG_DISABLED)) {
786 struct ata_queued_cmd *qc;
788 qc = ata_qc_from_tag(ap, ap->link.active_tag);
789 if (qc && (!(qc->tf.flags & ATA_TFLAG_POLLING)))
790 handled += pdc_host_intr(ap, qc);
797 spin_unlock(&host->lock);
798 return IRQ_RETVAL(handled);
801 static inline void pdc_packet_start(struct ata_queued_cmd *qc)
803 struct ata_port *ap = qc->ap;
804 struct pdc_port_priv *pp = ap->private_data;
805 void __iomem *mmio = ap->host->iomap[PDC_MMIO_BAR];
806 unsigned int port_no = ap->port_no;
807 u8 seq = (u8) (port_no + 1);
809 VPRINTK("ENTER, ap %p\n", ap);
811 writel(0x00000001, mmio + (seq * 4));
812 readl(mmio + (seq * 4)); /* flush */
815 wmb(); /* flush PRD, pkt writes */
816 writel(pp->pkt_dma, ap->ioaddr.cmd_addr + PDC_PKT_SUBMIT);
817 readl(ap->ioaddr.cmd_addr + PDC_PKT_SUBMIT); /* flush */
820 static unsigned int pdc_qc_issue_prot(struct ata_queued_cmd *qc)
822 switch (qc->tf.protocol) {
823 case ATA_PROT_ATAPI_NODATA:
824 if (qc->dev->flags & ATA_DFLAG_CDB_INTR)
827 case ATA_PROT_NODATA:
828 if (qc->tf.flags & ATA_TFLAG_POLLING)
831 case ATA_PROT_ATAPI_DMA:
833 pdc_packet_start(qc);
840 return ata_qc_issue_prot(qc);
843 static void pdc_tf_load_mmio(struct ata_port *ap, const struct ata_taskfile *tf)
845 WARN_ON(tf->protocol == ATA_PROT_DMA ||
846 tf->protocol == ATA_PROT_ATAPI_DMA);
850 static void pdc_exec_command_mmio(struct ata_port *ap,
851 const struct ata_taskfile *tf)
853 WARN_ON(tf->protocol == ATA_PROT_DMA ||
854 tf->protocol == ATA_PROT_ATAPI_DMA);
855 ata_exec_command(ap, tf);
858 static int pdc_check_atapi_dma(struct ata_queued_cmd *qc)
860 u8 *scsicmd = qc->scsicmd->cmnd;
861 int pio = 1; /* atapi dma off by default */
863 /* Whitelist commands that may use DMA. */
864 switch (scsicmd[0]) {
871 case 0xad: /* READ_DVD_STRUCTURE */
872 case 0xbe: /* READ_CD */
875 /* -45150 (FFFF4FA2) to -1 (FFFFFFFF) shall use PIO mode */
876 if (scsicmd[0] == WRITE_10) {
882 if (lba >= 0xFFFF4FA2)
888 static int pdc_old_sata_check_atapi_dma(struct ata_queued_cmd *qc)
890 /* First generation chips cannot use ATAPI DMA on SATA ports */
894 static void pdc_ata_setup_port(struct ata_port *ap,
895 void __iomem *base, void __iomem *scr_addr)
897 ap->ioaddr.cmd_addr = base;
898 ap->ioaddr.data_addr = base;
899 ap->ioaddr.feature_addr =
900 ap->ioaddr.error_addr = base + 0x4;
901 ap->ioaddr.nsect_addr = base + 0x8;
902 ap->ioaddr.lbal_addr = base + 0xc;
903 ap->ioaddr.lbam_addr = base + 0x10;
904 ap->ioaddr.lbah_addr = base + 0x14;
905 ap->ioaddr.device_addr = base + 0x18;
906 ap->ioaddr.command_addr =
907 ap->ioaddr.status_addr = base + 0x1c;
908 ap->ioaddr.altstatus_addr =
909 ap->ioaddr.ctl_addr = base + 0x38;
910 ap->ioaddr.scr_addr = scr_addr;
913 static void pdc_host_init(struct ata_host *host)
915 void __iomem *mmio = host->iomap[PDC_MMIO_BAR];
916 int is_gen2 = host->ports[0]->flags & PDC_FLAG_GEN_II;
921 hotplug_offset = PDC2_SATA_PLUG_CSR;
923 hotplug_offset = PDC_SATA_PLUG_CSR;
926 * Except for the hotplug stuff, this is voodoo from the
927 * Promise driver. Label this entire section
928 * "TODO: figure out why we do this"
931 /* enable BMR_BURST, maybe change FIFO_SHD to 8 dwords */
932 tmp = readl(mmio + PDC_FLASH_CTL);
933 tmp |= 0x02000; /* bit 13 (enable bmr burst) */
935 tmp |= 0x10000; /* bit 16 (fifo threshold at 8 dw) */
936 writel(tmp, mmio + PDC_FLASH_CTL);
938 /* clear plug/unplug flags for all ports */
939 tmp = readl(mmio + hotplug_offset);
940 writel(tmp | 0xff, mmio + hotplug_offset);
942 /* unmask plug/unplug ints */
943 tmp = readl(mmio + hotplug_offset);
944 writel(tmp & ~0xff0000, mmio + hotplug_offset);
946 /* don't initialise TBG or SLEW on 2nd generation chips */
950 /* reduce TBG clock to 133 Mhz. */
951 tmp = readl(mmio + PDC_TBG_MODE);
952 tmp &= ~0x30000; /* clear bit 17, 16*/
953 tmp |= 0x10000; /* set bit 17:16 = 0:1 */
954 writel(tmp, mmio + PDC_TBG_MODE);
956 readl(mmio + PDC_TBG_MODE); /* flush */
959 /* adjust slew rate control register. */
960 tmp = readl(mmio + PDC_SLEW_CTL);
961 tmp &= 0xFFFFF03F; /* clear bit 11 ~ 6 */
962 tmp |= 0x00000900; /* set bit 11-9 = 100b , bit 8-6 = 100 */
963 writel(tmp, mmio + PDC_SLEW_CTL);
966 static int pdc_ata_init_one(struct pci_dev *pdev,
967 const struct pci_device_id *ent)
969 static int printed_version;
970 const struct ata_port_info *pi = &pdc_port_info[ent->driver_data];
971 const struct ata_port_info *ppi[PDC_MAX_PORTS];
972 struct ata_host *host;
977 if (!printed_version++)
978 dev_printk(KERN_DEBUG, &pdev->dev, "version " DRV_VERSION "\n");
980 /* enable and acquire resources */
981 rc = pcim_enable_device(pdev);
985 rc = pcim_iomap_regions(pdev, 1 << PDC_MMIO_BAR, DRV_NAME);
987 pcim_pin_device(pdev);
990 base = pcim_iomap_table(pdev)[PDC_MMIO_BAR];
992 /* determine port configuration and setup host */
994 if (pi->flags & PDC_FLAG_4_PORTS)
996 for (i = 0; i < n_ports; i++)
999 if (pi->flags & PDC_FLAG_SATA_PATA) {
1000 u8 tmp = readb(base + PDC_FLASH_CTL+1);
1002 ppi[n_ports++] = pi + 1;
1005 host = ata_host_alloc_pinfo(&pdev->dev, ppi, n_ports);
1007 dev_printk(KERN_ERR, &pdev->dev, "failed to allocate host\n");
1010 host->iomap = pcim_iomap_table(pdev);
1012 is_sataii_tx4 = pdc_is_sataii_tx4(pi->flags);
1013 for (i = 0; i < host->n_ports; i++) {
1014 struct ata_port *ap = host->ports[i];
1015 unsigned int ata_no = pdc_port_no_to_ata_no(i, is_sataii_tx4);
1016 unsigned int port_offset = 0x200 + ata_no * 0x80;
1017 unsigned int scr_offset = 0x400 + ata_no * 0x100;
1019 pdc_ata_setup_port(ap, base + port_offset, base + scr_offset);
1021 ata_port_pbar_desc(ap, PDC_MMIO_BAR, -1, "mmio");
1022 ata_port_pbar_desc(ap, PDC_MMIO_BAR, port_offset, "port");
1025 /* initialize adapter */
1026 pdc_host_init(host);
1028 rc = pci_set_dma_mask(pdev, ATA_DMA_MASK);
1031 rc = pci_set_consistent_dma_mask(pdev, ATA_DMA_MASK);
1035 /* start host, request IRQ and attach */
1036 pci_set_master(pdev);
1037 return ata_host_activate(host, pdev->irq, pdc_interrupt, IRQF_SHARED,
1041 static int __init pdc_ata_init(void)
1043 return pci_register_driver(&pdc_ata_pci_driver);
1046 static void __exit pdc_ata_exit(void)
1048 pci_unregister_driver(&pdc_ata_pci_driver);
1051 MODULE_AUTHOR("Jeff Garzik");
1052 MODULE_DESCRIPTION("Promise ATA TX2/TX4/TX4000 low-level driver");
1053 MODULE_LICENSE("GPL");
1054 MODULE_DEVICE_TABLE(pci, pdc_ata_pci_tbl);
1055 MODULE_VERSION(DRV_VERSION);
1057 module_init(pdc_ata_init);
1058 module_exit(pdc_ata_exit);