2 * sata_promise.c - Promise SATA
4 * Maintained by: Jeff Garzik <jgarzik@pobox.com>
5 * Please ALWAYS copy linux-ide@vger.kernel.org
8 * Copyright 2003-2004 Red Hat, Inc.
11 * This program is free software; you can redistribute it and/or modify
12 * it under the terms of the GNU General Public License as published by
13 * the Free Software Foundation; either version 2, or (at your option)
16 * This program is distributed in the hope that it will be useful,
17 * but WITHOUT ANY WARRANTY; without even the implied warranty of
18 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
19 * GNU General Public License for more details.
21 * You should have received a copy of the GNU General Public License
22 * along with this program; see the file COPYING. If not, write to
23 * the Free Software Foundation, 675 Mass Ave, Cambridge, MA 02139, USA.
26 * libata documentation is available via 'make {ps|pdf}docs',
27 * as Documentation/DocBook/libata.*
29 * Hardware information only available under NDA.
33 #include <linux/kernel.h>
34 #include <linux/module.h>
35 #include <linux/pci.h>
36 #include <linux/init.h>
37 #include <linux/blkdev.h>
38 #include <linux/delay.h>
39 #include <linux/interrupt.h>
40 #include <linux/sched.h>
41 #include <linux/device.h>
42 #include <scsi/scsi.h>
43 #include <scsi/scsi_host.h>
44 #include <scsi/scsi_cmnd.h>
45 #include <linux/libata.h>
47 #include "sata_promise.h"
49 #define DRV_NAME "sata_promise"
50 #define DRV_VERSION "1.05"
54 /* register offsets */
55 PDC_FEATURE = 0x04, /* Feature/Error reg (per port) */
56 PDC_SECTOR_COUNT = 0x08, /* Sector count reg (per port) */
57 PDC_SECTOR_NUMBER = 0x0C, /* Sector number reg (per port) */
58 PDC_CYLINDER_LOW = 0x10, /* Cylinder low reg (per port) */
59 PDC_CYLINDER_HIGH = 0x14, /* Cylinder high reg (per port) */
60 PDC_DEVICE = 0x18, /* Device/Head reg (per port) */
61 PDC_COMMAND = 0x1C, /* Command/status reg (per port) */
62 PDC_PKT_SUBMIT = 0x40, /* Command packet pointer addr */
63 PDC_INT_SEQMASK = 0x40, /* Mask of asserted SEQ INTs */
64 PDC_FLASH_CTL = 0x44, /* Flash control register */
65 PDC_GLOBAL_CTL = 0x48, /* Global control/status (per port) */
66 PDC_CTLSTAT = 0x60, /* IDE control and status (per port) */
67 PDC_SATA_PLUG_CSR = 0x6C, /* SATA Plug control/status reg */
68 PDC2_SATA_PLUG_CSR = 0x60, /* SATAII Plug control/status reg */
69 PDC_TBG_MODE = 0x41C, /* TBG mode (not SATAII) */
70 PDC_SLEW_CTL = 0x470, /* slew rate control reg (not SATAII) */
72 PDC_ERR_MASK = (1<<19) | (1<<20) | (1<<21) | (1<<22) |
73 (1<<8) | (1<<9) | (1<<10),
75 board_2037x = 0, /* FastTrak S150 TX2plus */
76 board_20319 = 1, /* FastTrak S150 TX4 */
77 board_20619 = 2, /* FastTrak TX4000 */
78 board_2057x = 3, /* SATAII150 Tx2plus */
79 board_40518 = 4, /* SATAII150 Tx4 */
81 PDC_HAS_PATA = (1 << 1), /* PDC20375/20575 has PATA */
83 /* Sequence counter control registers bit definitions */
84 PDC_SEQCNTRL_INT_MASK = (1 << 5), /* Sequence Interrupt Mask */
86 /* Feature register values */
87 PDC_FEATURE_ATAPI_PIO = 0x00, /* ATAPI data xfer by PIO */
88 PDC_FEATURE_ATAPI_DMA = 0x01, /* ATAPI data xfer by DMA */
90 /* Device/Head register values */
91 PDC_DEVICE_SATA = 0xE0, /* Device/Head value for SATA devices */
93 /* PDC_CTLSTAT bit definitions */
94 PDC_DMA_ENABLE = (1 << 7),
95 PDC_IRQ_DISABLE = (1 << 10),
96 PDC_RESET = (1 << 11), /* HDMA reset */
98 PDC_COMMON_FLAGS = ATA_FLAG_NO_LEGACY |
100 ATA_FLAG_PIO_POLLING,
103 PDC_FLAG_GEN_II = (1 << 0),
107 struct pdc_port_priv {
112 struct pdc_host_priv {
114 unsigned long port_flags[ATA_MAX_PORTS];
117 static u32 pdc_sata_scr_read (struct ata_port *ap, unsigned int sc_reg);
118 static void pdc_sata_scr_write (struct ata_port *ap, unsigned int sc_reg, u32 val);
119 static int pdc_ata_init_one (struct pci_dev *pdev, const struct pci_device_id *ent);
120 static irqreturn_t pdc_interrupt (int irq, void *dev_instance);
121 static void pdc_eng_timeout(struct ata_port *ap);
122 static int pdc_port_start(struct ata_port *ap);
123 static void pdc_port_stop(struct ata_port *ap);
124 static void pdc_pata_phy_reset(struct ata_port *ap);
125 static void pdc_qc_prep(struct ata_queued_cmd *qc);
126 static void pdc_tf_load_mmio(struct ata_port *ap, const struct ata_taskfile *tf);
127 static void pdc_exec_command_mmio(struct ata_port *ap, const struct ata_taskfile *tf);
128 static int pdc_check_atapi_dma(struct ata_queued_cmd *qc);
129 static int pdc_old_check_atapi_dma(struct ata_queued_cmd *qc);
130 static void pdc_irq_clear(struct ata_port *ap);
131 static unsigned int pdc_qc_issue_prot(struct ata_queued_cmd *qc);
132 static void pdc_host_stop(struct ata_host *host);
133 static void pdc_freeze(struct ata_port *ap);
134 static void pdc_thaw(struct ata_port *ap);
135 static void pdc_error_handler(struct ata_port *ap);
136 static void pdc_post_internal_cmd(struct ata_queued_cmd *qc);
139 static struct scsi_host_template pdc_ata_sht = {
140 .module = THIS_MODULE,
142 .ioctl = ata_scsi_ioctl,
143 .queuecommand = ata_scsi_queuecmd,
144 .can_queue = ATA_DEF_QUEUE,
145 .this_id = ATA_SHT_THIS_ID,
146 .sg_tablesize = LIBATA_MAX_PRD,
147 .cmd_per_lun = ATA_SHT_CMD_PER_LUN,
148 .emulated = ATA_SHT_EMULATED,
149 .use_clustering = ATA_SHT_USE_CLUSTERING,
150 .proc_name = DRV_NAME,
151 .dma_boundary = ATA_DMA_BOUNDARY,
152 .slave_configure = ata_scsi_slave_config,
153 .slave_destroy = ata_scsi_slave_destroy,
154 .bios_param = ata_std_bios_param,
157 static const struct ata_port_operations pdc_sata_ops = {
158 .port_disable = ata_port_disable,
159 .tf_load = pdc_tf_load_mmio,
160 .tf_read = ata_tf_read,
161 .check_status = ata_check_status,
162 .exec_command = pdc_exec_command_mmio,
163 .dev_select = ata_std_dev_select,
164 .check_atapi_dma = pdc_check_atapi_dma,
166 .qc_prep = pdc_qc_prep,
167 .qc_issue = pdc_qc_issue_prot,
168 .freeze = pdc_freeze,
170 .error_handler = pdc_error_handler,
171 .post_internal_cmd = pdc_post_internal_cmd,
172 .data_xfer = ata_mmio_data_xfer,
173 .irq_handler = pdc_interrupt,
174 .irq_clear = pdc_irq_clear,
176 .scr_read = pdc_sata_scr_read,
177 .scr_write = pdc_sata_scr_write,
178 .port_start = pdc_port_start,
179 .port_stop = pdc_port_stop,
180 .host_stop = pdc_host_stop,
183 /* First-generation chips need a more restrictive ->check_atapi_dma op */
184 static const struct ata_port_operations pdc_old_sata_ops = {
185 .port_disable = ata_port_disable,
186 .tf_load = pdc_tf_load_mmio,
187 .tf_read = ata_tf_read,
188 .check_status = ata_check_status,
189 .exec_command = pdc_exec_command_mmio,
190 .dev_select = ata_std_dev_select,
191 .check_atapi_dma = pdc_old_check_atapi_dma,
193 .qc_prep = pdc_qc_prep,
194 .qc_issue = pdc_qc_issue_prot,
195 .freeze = pdc_freeze,
197 .error_handler = pdc_error_handler,
198 .post_internal_cmd = pdc_post_internal_cmd,
199 .data_xfer = ata_mmio_data_xfer,
200 .irq_handler = pdc_interrupt,
201 .irq_clear = pdc_irq_clear,
203 .scr_read = pdc_sata_scr_read,
204 .scr_write = pdc_sata_scr_write,
205 .port_start = pdc_port_start,
206 .port_stop = pdc_port_stop,
207 .host_stop = pdc_host_stop,
210 static const struct ata_port_operations pdc_pata_ops = {
211 .port_disable = ata_port_disable,
212 .tf_load = pdc_tf_load_mmio,
213 .tf_read = ata_tf_read,
214 .check_status = ata_check_status,
215 .exec_command = pdc_exec_command_mmio,
216 .dev_select = ata_std_dev_select,
217 .check_atapi_dma = pdc_check_atapi_dma,
219 .phy_reset = pdc_pata_phy_reset,
221 .qc_prep = pdc_qc_prep,
222 .qc_issue = pdc_qc_issue_prot,
223 .data_xfer = ata_mmio_data_xfer,
224 .eng_timeout = pdc_eng_timeout,
225 .irq_handler = pdc_interrupt,
226 .irq_clear = pdc_irq_clear,
228 .port_start = pdc_port_start,
229 .port_stop = pdc_port_stop,
230 .host_stop = pdc_host_stop,
233 static const struct ata_port_info pdc_port_info[] = {
237 .flags = PDC_COMMON_FLAGS,
238 .pio_mask = 0x1f, /* pio0-4 */
239 .mwdma_mask = 0x07, /* mwdma0-2 */
240 .udma_mask = 0x7f, /* udma0-6 ; FIXME */
241 .port_ops = &pdc_old_sata_ops,
247 .flags = PDC_COMMON_FLAGS | ATA_FLAG_SATA,
248 .pio_mask = 0x1f, /* pio0-4 */
249 .mwdma_mask = 0x07, /* mwdma0-2 */
250 .udma_mask = 0x7f, /* udma0-6 ; FIXME */
251 .port_ops = &pdc_old_sata_ops,
257 .flags = PDC_COMMON_FLAGS | ATA_FLAG_SRST | ATA_FLAG_SLAVE_POSS,
258 .pio_mask = 0x1f, /* pio0-4 */
259 .mwdma_mask = 0x07, /* mwdma0-2 */
260 .udma_mask = 0x7f, /* udma0-6 ; FIXME */
261 .port_ops = &pdc_pata_ops,
267 .flags = PDC_COMMON_FLAGS,
268 .pio_mask = 0x1f, /* pio0-4 */
269 .mwdma_mask = 0x07, /* mwdma0-2 */
270 .udma_mask = 0x7f, /* udma0-6 ; FIXME */
271 .port_ops = &pdc_sata_ops,
277 .flags = PDC_COMMON_FLAGS | ATA_FLAG_SATA,
278 .pio_mask = 0x1f, /* pio0-4 */
279 .mwdma_mask = 0x07, /* mwdma0-2 */
280 .udma_mask = 0x7f, /* udma0-6 ; FIXME */
281 .port_ops = &pdc_sata_ops,
285 static const struct pci_device_id pdc_ata_pci_tbl[] = {
286 { PCI_VDEVICE(PROMISE, 0x3371), board_2037x },
287 { PCI_VDEVICE(PROMISE, 0x3373), board_2037x },
288 { PCI_VDEVICE(PROMISE, 0x3375), board_2037x },
289 { PCI_VDEVICE(PROMISE, 0x3376), board_2037x },
290 { PCI_VDEVICE(PROMISE, 0x3570), board_2057x },
291 { PCI_VDEVICE(PROMISE, 0x3571), board_2057x },
292 { PCI_VDEVICE(PROMISE, 0x3574), board_2057x },
293 { PCI_VDEVICE(PROMISE, 0x3577), board_2057x },
294 { PCI_VDEVICE(PROMISE, 0x3d73), board_2057x },
295 { PCI_VDEVICE(PROMISE, 0x3d75), board_2057x },
297 { PCI_VDEVICE(PROMISE, 0x3318), board_20319 },
298 { PCI_VDEVICE(PROMISE, 0x3319), board_20319 },
299 { PCI_VDEVICE(PROMISE, 0x3515), board_20319 },
300 { PCI_VDEVICE(PROMISE, 0x3519), board_20319 },
301 { PCI_VDEVICE(PROMISE, 0x3d17), board_40518 },
302 { PCI_VDEVICE(PROMISE, 0x3d18), board_40518 },
304 { PCI_VDEVICE(PROMISE, 0x6629), board_20619 },
306 { } /* terminate list */
310 static struct pci_driver pdc_ata_pci_driver = {
312 .id_table = pdc_ata_pci_tbl,
313 .probe = pdc_ata_init_one,
314 .remove = ata_pci_remove_one,
318 static int pdc_port_start(struct ata_port *ap)
320 struct device *dev = ap->host->dev;
321 struct pdc_host_priv *hp = ap->host->private_data;
322 struct pdc_port_priv *pp;
325 /* fix up port flags and cable type for SATA+PATA chips */
326 ap->flags |= hp->port_flags[ap->port_no];
327 if (ap->flags & ATA_FLAG_SATA)
328 ap->cbl = ATA_CBL_SATA;
330 rc = ata_port_start(ap);
334 pp = kzalloc(sizeof(*pp), GFP_KERNEL);
340 pp->pkt = dma_alloc_coherent(dev, 128, &pp->pkt_dma, GFP_KERNEL);
346 ap->private_data = pp;
348 /* fix up PHYMODE4 align timing */
349 if ((hp->flags & PDC_FLAG_GEN_II) && sata_scr_valid(ap)) {
350 void __iomem *mmio = (void __iomem *) ap->ioaddr.scr_addr;
353 tmp = readl(mmio + 0x014);
354 tmp = (tmp & ~3) | 1; /* set bits 1:0 = 0:1 */
355 writel(tmp, mmio + 0x014);
368 static void pdc_port_stop(struct ata_port *ap)
370 struct device *dev = ap->host->dev;
371 struct pdc_port_priv *pp = ap->private_data;
373 ap->private_data = NULL;
374 dma_free_coherent(dev, 128, pp->pkt, pp->pkt_dma);
380 static void pdc_host_stop(struct ata_host *host)
382 struct pdc_host_priv *hp = host->private_data;
384 ata_pci_host_stop(host);
390 static void pdc_reset_port(struct ata_port *ap)
392 void __iomem *mmio = (void __iomem *) ap->ioaddr.cmd_addr + PDC_CTLSTAT;
396 for (i = 11; i > 0; i--) {
409 readl(mmio); /* flush */
412 static void pdc_pata_cbl_detect(struct ata_port *ap)
415 void __iomem *mmio = (void __iomem *) ap->ioaddr.cmd_addr + PDC_CTLSTAT + 0x03;
420 ap->cbl = ATA_CBL_PATA40;
421 ap->udma_mask &= ATA_UDMA_MASK_40C;
423 ap->cbl = ATA_CBL_PATA80;
426 static void pdc_pata_phy_reset(struct ata_port *ap)
428 pdc_pata_cbl_detect(ap);
434 static u32 pdc_sata_scr_read (struct ata_port *ap, unsigned int sc_reg)
436 if (sc_reg > SCR_CONTROL || ap->cbl != ATA_CBL_SATA)
438 return readl((void __iomem *) ap->ioaddr.scr_addr + (sc_reg * 4));
442 static void pdc_sata_scr_write (struct ata_port *ap, unsigned int sc_reg,
445 if (sc_reg > SCR_CONTROL || ap->cbl != ATA_CBL_SATA)
447 writel(val, (void __iomem *) ap->ioaddr.scr_addr + (sc_reg * 4));
450 static void pdc_atapi_dma_pkt(struct ata_taskfile *tf,
452 unsigned int cdb_len, u8 *cdb,
455 u32 *buf32 = (u32 *) buf;
457 /* set control bits (byte 0), zero delay seq id (byte 3),
458 * and seq id (byte 2)
460 if (!(tf->flags & ATA_TFLAG_WRITE))
461 buf32[0] = cpu_to_le32(PDC_PKT_READ);
464 buf32[1] = cpu_to_le32(sg_table); /* S/G table addr */
465 buf32[2] = 0; /* no next-packet */
467 /* we can represent cdb lengths 2/4/6/8/10/12/14/16 */
468 BUG_ON(cdb_len & ~0x1E);
470 buf[12] = (((cdb_len >> 1) & 7) << 5) | ATA_REG_DATA | PDC_LAST_REG;
471 memcpy(buf+13, cdb, cdb_len);
474 static void pdc_qc_prep(struct ata_queued_cmd *qc)
476 struct pdc_port_priv *pp = qc->ap->private_data;
481 switch (qc->tf.protocol) {
486 case ATA_PROT_NODATA:
487 i = pdc_pkt_header(&qc->tf, qc->ap->prd_dma,
488 qc->dev->devno, pp->pkt);
490 if (qc->tf.flags & ATA_TFLAG_LBA48)
491 i = pdc_prep_lba48(&qc->tf, pp->pkt, i);
493 i = pdc_prep_lba28(&qc->tf, pp->pkt, i);
495 pdc_pkt_footer(&qc->tf, pp->pkt, i);
499 case ATA_PROT_ATAPI_NODATA:
503 case ATA_PROT_ATAPI_DMA:
505 pdc_atapi_dma_pkt(&qc->tf, qc->ap->prd_dma, qc->dev->cdb_len, qc->cdb, pp->pkt);
513 static void pdc_freeze(struct ata_port *ap)
515 void __iomem *mmio = (void __iomem *) ap->ioaddr.cmd_addr;
518 tmp = readl(mmio + PDC_CTLSTAT);
519 tmp |= PDC_IRQ_DISABLE;
520 tmp &= ~PDC_DMA_ENABLE;
521 writel(tmp, mmio + PDC_CTLSTAT);
522 readl(mmio + PDC_CTLSTAT); /* flush */
525 static void pdc_thaw(struct ata_port *ap)
527 void __iomem *mmio = (void __iomem *) ap->ioaddr.cmd_addr;
531 readl(mmio + PDC_INT_SEQMASK);
533 /* turn IRQ back on */
534 tmp = readl(mmio + PDC_CTLSTAT);
535 tmp &= ~PDC_IRQ_DISABLE;
536 writel(tmp, mmio + PDC_CTLSTAT);
537 readl(mmio + PDC_CTLSTAT); /* flush */
540 static void pdc_error_handler(struct ata_port *ap)
542 ata_reset_fn_t hardreset;
544 if (!(ap->pflags & ATA_PFLAG_FROZEN))
548 if (sata_scr_valid(ap))
549 hardreset = sata_std_hardreset;
551 /* perform recovery */
552 ata_do_eh(ap, ata_std_prereset, ata_std_softreset, hardreset,
556 static void pdc_post_internal_cmd(struct ata_queued_cmd *qc)
558 struct ata_port *ap = qc->ap;
560 if (qc->flags & ATA_QCFLAG_FAILED)
561 qc->err_mask |= AC_ERR_OTHER;
563 /* make DMA engine forget about the failed command */
568 static void pdc_eng_timeout(struct ata_port *ap)
570 struct ata_host *host = ap->host;
572 struct ata_queued_cmd *qc;
577 spin_lock_irqsave(&host->lock, flags);
579 qc = ata_qc_from_tag(ap, ap->active_tag);
581 switch (qc->tf.protocol) {
583 case ATA_PROT_NODATA:
584 ata_port_printk(ap, KERN_ERR, "command timeout\n");
585 drv_stat = ata_wait_idle(ap);
586 qc->err_mask |= __ac_err_mask(drv_stat);
590 drv_stat = ata_busy_wait(ap, ATA_BUSY | ATA_DRQ, 1000);
592 ata_port_printk(ap, KERN_ERR,
593 "unknown timeout, cmd 0x%x stat 0x%x\n",
594 qc->tf.command, drv_stat);
596 qc->err_mask |= ac_err_mask(drv_stat);
600 spin_unlock_irqrestore(&host->lock, flags);
601 ata_eh_qc_complete(qc);
605 static inline unsigned int pdc_host_intr( struct ata_port *ap,
606 struct ata_queued_cmd *qc)
608 unsigned int handled = 0;
610 void __iomem *mmio = (void __iomem *) ap->ioaddr.cmd_addr + PDC_GLOBAL_CTL;
613 if (tmp & PDC_ERR_MASK) {
614 qc->err_mask |= AC_ERR_DEV;
618 switch (qc->tf.protocol) {
620 case ATA_PROT_NODATA:
621 case ATA_PROT_ATAPI_DMA:
622 qc->err_mask |= ac_err_mask(ata_wait_idle(ap));
628 ap->stats.idle_irq++;
635 static void pdc_irq_clear(struct ata_port *ap)
637 struct ata_host *host = ap->host;
638 void __iomem *mmio = host->mmio_base;
640 readl(mmio + PDC_INT_SEQMASK);
643 static irqreturn_t pdc_interrupt (int irq, void *dev_instance)
645 struct ata_host *host = dev_instance;
649 unsigned int handled = 0;
650 void __iomem *mmio_base;
654 if (!host || !host->mmio_base) {
655 VPRINTK("QUICK EXIT\n");
659 mmio_base = host->mmio_base;
661 /* reading should also clear interrupts */
662 mask = readl(mmio_base + PDC_INT_SEQMASK);
664 if (mask == 0xffffffff) {
665 VPRINTK("QUICK EXIT 2\n");
669 spin_lock(&host->lock);
671 mask &= 0xffff; /* only 16 tags possible */
673 VPRINTK("QUICK EXIT 3\n");
677 writel(mask, mmio_base + PDC_INT_SEQMASK);
679 for (i = 0; i < host->n_ports; i++) {
680 VPRINTK("port %u\n", i);
682 tmp = mask & (1 << (i + 1));
684 !(ap->flags & ATA_FLAG_DISABLED)) {
685 struct ata_queued_cmd *qc;
687 qc = ata_qc_from_tag(ap, ap->active_tag);
688 if (qc && (!(qc->tf.flags & ATA_TFLAG_POLLING)))
689 handled += pdc_host_intr(ap, qc);
696 spin_unlock(&host->lock);
697 return IRQ_RETVAL(handled);
700 static inline void pdc_packet_start(struct ata_queued_cmd *qc)
702 struct ata_port *ap = qc->ap;
703 struct pdc_port_priv *pp = ap->private_data;
704 unsigned int port_no = ap->port_no;
705 u8 seq = (u8) (port_no + 1);
707 VPRINTK("ENTER, ap %p\n", ap);
709 writel(0x00000001, ap->host->mmio_base + (seq * 4));
710 readl(ap->host->mmio_base + (seq * 4)); /* flush */
713 wmb(); /* flush PRD, pkt writes */
714 writel(pp->pkt_dma, (void __iomem *) ap->ioaddr.cmd_addr + PDC_PKT_SUBMIT);
715 readl((void __iomem *) ap->ioaddr.cmd_addr + PDC_PKT_SUBMIT); /* flush */
718 static unsigned int pdc_wait_for_drq(struct ata_port *ap)
720 void __iomem *port_mmio = (void __iomem *) ap->ioaddr.cmd_addr;
724 /* Following pdc-ultra's WaitForDrq() we loop here until BSY
725 * is clear and DRQ is set in altstatus. We could possibly call
726 * ata_busy_wait() and loop until DRQ is set, but since we don't
727 * know how much time a call to ata_busy_wait() took, we don't
728 * know when to time out the outer loop.
730 for(i = 0; i < 1000; ++i) {
731 status = readb(port_mmio + 0x38); /* altstatus */
734 if (status & ATA_BUSY)
736 else if (status & (ATA_DRQ | ATA_ERR))
741 ata_port_printk(ap, KERN_WARNING, "%s timed out", __FUNCTION__);
745 static void pdc_issue_atapi_pkt_cmd(struct ata_queued_cmd *qc)
747 struct ata_port *ap = qc->ap;
748 void __iomem *port_mmio = (void __iomem *) ap->ioaddr.cmd_addr;
749 void __iomem *host_mmio = ap->host->mmio_base;
753 writeb(0x00, port_mmio + PDC_CTLSTAT); /* route drive INT to SEQ 0 */
754 writeb(PDC_SEQCNTRL_INT_MASK, host_mmio + 0); /* but mask SEQ 0 INT */
757 if (sata_scr_valid(ap)) {
758 tmp = PDC_DEVICE_SATA;
760 tmp = ATA_DEVICE_OBS;
761 if (qc->dev->devno != 0)
764 writeb(tmp, port_mmio + PDC_DEVICE);
765 ata_busy_wait(ap, ATA_BUSY, 1000);
767 writeb(0x00, port_mmio + PDC_SECTOR_COUNT);
768 writeb(0x00, port_mmio + PDC_SECTOR_NUMBER);
770 /* set feature and byte counter registers */
771 if (qc->tf.protocol != ATA_PROT_ATAPI_DMA) {
772 tmp = PDC_FEATURE_ATAPI_PIO;
773 /* set byte counter register to real transfer byte count */
776 nbytes = qc->nsect << 9;
780 tmp = PDC_FEATURE_ATAPI_DMA;
781 /* set byte counter register to 0 */
784 writeb(tmp, port_mmio + PDC_FEATURE);
785 writeb(nbytes & 0xFF, port_mmio + PDC_CYLINDER_LOW);
786 writeb((nbytes >> 8) & 0xFF, port_mmio + PDC_CYLINDER_HIGH);
788 /* send ATAPI packet command 0xA0 */
789 writeb(ATA_CMD_PACKET, port_mmio + PDC_COMMAND);
792 * At this point in the issuing of a packet command, the Promise
793 * driver busy-waits for INT (CTLSTAT bit 27) if it detected
794 * (at port init time) that the device interrupts with assertion
795 * of DRQ after receiving a packet command.
797 * XXX: Do we need to handle this case as well? Does libata detect
798 * this case for us, or do we have to do our own per-port init?
801 pdc_wait_for_drq(ap);
803 /* now the device only waits for the CDB */
806 static unsigned int pdc_qc_issue_prot(struct ata_queued_cmd *qc)
808 switch (qc->tf.protocol) {
809 case ATA_PROT_ATAPI_DMA:
810 pdc_issue_atapi_pkt_cmd(qc);
813 case ATA_PROT_NODATA:
814 pdc_packet_start(qc);
821 return ata_qc_issue_prot(qc);
824 static void pdc_tf_load_mmio(struct ata_port *ap, const struct ata_taskfile *tf)
826 WARN_ON (tf->protocol == ATA_PROT_DMA ||
827 tf->protocol == ATA_PROT_NODATA);
832 static void pdc_exec_command_mmio(struct ata_port *ap, const struct ata_taskfile *tf)
834 WARN_ON (tf->protocol == ATA_PROT_DMA ||
835 tf->protocol == ATA_PROT_NODATA);
836 ata_exec_command(ap, tf);
839 static int pdc_check_atapi_dma(struct ata_queued_cmd *qc)
841 u8 *scsicmd = qc->scsicmd->cmnd;
842 int pio = 1; /* atapi dma off by default */
844 /* Whitelist commands that may use DMA. */
845 switch (scsicmd[0]) {
852 case 0xad: /* READ_DVD_STRUCTURE */
853 case 0xbe: /* READ_CD */
856 /* -45150 (FFFF4FA2) to -1 (FFFFFFFF) shall use PIO mode */
857 if (scsicmd[0] == WRITE_10) {
859 lba = (scsicmd[2] << 24) | (scsicmd[3] << 16) | (scsicmd[4] << 8) | scsicmd[5];
860 if (lba >= 0xFFFF4FA2)
866 static int pdc_old_check_atapi_dma(struct ata_queued_cmd *qc)
868 struct ata_port *ap = qc->ap;
870 /* First generation chips cannot use ATAPI DMA on SATA ports */
871 if (sata_scr_valid(ap))
873 return pdc_check_atapi_dma(qc);
876 static void pdc_ata_setup_port(struct ata_ioports *port, unsigned long base)
878 port->cmd_addr = base;
879 port->data_addr = base;
881 port->error_addr = base + 0x4;
882 port->nsect_addr = base + 0x8;
883 port->lbal_addr = base + 0xc;
884 port->lbam_addr = base + 0x10;
885 port->lbah_addr = base + 0x14;
886 port->device_addr = base + 0x18;
888 port->status_addr = base + 0x1c;
889 port->altstatus_addr =
890 port->ctl_addr = base + 0x38;
894 static void pdc_host_init(unsigned int chip_id, struct ata_probe_ent *pe)
896 void __iomem *mmio = pe->mmio_base;
897 struct pdc_host_priv *hp = pe->private_data;
901 if (hp->flags & PDC_FLAG_GEN_II)
902 hotplug_offset = PDC2_SATA_PLUG_CSR;
904 hotplug_offset = PDC_SATA_PLUG_CSR;
907 * Except for the hotplug stuff, this is voodoo from the
908 * Promise driver. Label this entire section
909 * "TODO: figure out why we do this"
912 /* enable BMR_BURST, maybe change FIFO_SHD to 8 dwords */
913 tmp = readl(mmio + PDC_FLASH_CTL);
914 tmp |= 0x02000; /* bit 13 (enable bmr burst) */
915 if (!(hp->flags & PDC_FLAG_GEN_II))
916 tmp |= 0x10000; /* bit 16 (fifo threshold at 8 dw) */
917 writel(tmp, mmio + PDC_FLASH_CTL);
919 /* clear plug/unplug flags for all ports */
920 tmp = readl(mmio + hotplug_offset);
921 writel(tmp | 0xff, mmio + hotplug_offset);
923 /* mask plug/unplug ints */
924 tmp = readl(mmio + hotplug_offset);
925 writel(tmp | 0xff0000, mmio + hotplug_offset);
927 /* don't initialise TBG or SLEW on 2nd generation chips */
928 if (hp->flags & PDC_FLAG_GEN_II)
931 /* reduce TBG clock to 133 Mhz. */
932 tmp = readl(mmio + PDC_TBG_MODE);
933 tmp &= ~0x30000; /* clear bit 17, 16*/
934 tmp |= 0x10000; /* set bit 17:16 = 0:1 */
935 writel(tmp, mmio + PDC_TBG_MODE);
937 readl(mmio + PDC_TBG_MODE); /* flush */
940 /* adjust slew rate control register. */
941 tmp = readl(mmio + PDC_SLEW_CTL);
942 tmp &= 0xFFFFF03F; /* clear bit 11 ~ 6 */
943 tmp |= 0x00000900; /* set bit 11-9 = 100b , bit 8-6 = 100 */
944 writel(tmp, mmio + PDC_SLEW_CTL);
947 static int pdc_ata_init_one (struct pci_dev *pdev, const struct pci_device_id *ent)
949 static int printed_version;
950 struct ata_probe_ent *probe_ent = NULL;
951 struct pdc_host_priv *hp;
953 void __iomem *mmio_base;
954 unsigned int board_idx = (unsigned int) ent->driver_data;
955 int pci_dev_busy = 0;
959 if (!printed_version++)
960 dev_printk(KERN_DEBUG, &pdev->dev, "version " DRV_VERSION "\n");
962 rc = pci_enable_device(pdev);
966 rc = pci_request_regions(pdev, DRV_NAME);
972 rc = pci_set_dma_mask(pdev, ATA_DMA_MASK);
974 goto err_out_regions;
975 rc = pci_set_consistent_dma_mask(pdev, ATA_DMA_MASK);
977 goto err_out_regions;
979 probe_ent = kzalloc(sizeof(*probe_ent), GFP_KERNEL);
980 if (probe_ent == NULL) {
982 goto err_out_regions;
985 probe_ent->dev = pci_dev_to_dev(pdev);
986 INIT_LIST_HEAD(&probe_ent->node);
988 mmio_base = pci_iomap(pdev, 3, 0);
989 if (mmio_base == NULL) {
991 goto err_out_free_ent;
993 base = (unsigned long) mmio_base;
995 hp = kzalloc(sizeof(*hp), GFP_KERNEL);
998 goto err_out_free_ent;
1001 probe_ent->private_data = hp;
1003 probe_ent->sht = pdc_port_info[board_idx].sht;
1004 probe_ent->port_flags = pdc_port_info[board_idx].flags;
1005 probe_ent->pio_mask = pdc_port_info[board_idx].pio_mask;
1006 probe_ent->mwdma_mask = pdc_port_info[board_idx].mwdma_mask;
1007 probe_ent->udma_mask = pdc_port_info[board_idx].udma_mask;
1008 probe_ent->port_ops = pdc_port_info[board_idx].port_ops;
1010 probe_ent->irq = pdev->irq;
1011 probe_ent->irq_flags = IRQF_SHARED;
1012 probe_ent->mmio_base = mmio_base;
1014 pdc_ata_setup_port(&probe_ent->port[0], base + 0x200);
1015 pdc_ata_setup_port(&probe_ent->port[1], base + 0x280);
1017 probe_ent->port[0].scr_addr = base + 0x400;
1018 probe_ent->port[1].scr_addr = base + 0x500;
1020 /* notice 4-port boards */
1021 switch (board_idx) {
1023 hp->flags |= PDC_FLAG_GEN_II;
1026 probe_ent->n_ports = 4;
1028 pdc_ata_setup_port(&probe_ent->port[2], base + 0x300);
1029 pdc_ata_setup_port(&probe_ent->port[3], base + 0x380);
1031 probe_ent->port[2].scr_addr = base + 0x600;
1032 probe_ent->port[3].scr_addr = base + 0x700;
1035 hp->flags |= PDC_FLAG_GEN_II;
1038 /* TX2plus boards also have a PATA port */
1039 tmp = readb(mmio_base + PDC_FLASH_CTL+1);
1040 if (!(tmp & 0x80)) {
1041 probe_ent->n_ports = 3;
1042 pdc_ata_setup_port(&probe_ent->port[2], base + 0x300);
1043 hp->port_flags[2] = ATA_FLAG_SLAVE_POSS;
1044 printk(KERN_INFO DRV_NAME " PATA port found\n");
1046 probe_ent->n_ports = 2;
1047 hp->port_flags[0] = ATA_FLAG_SATA;
1048 hp->port_flags[1] = ATA_FLAG_SATA;
1051 probe_ent->n_ports = 4;
1053 pdc_ata_setup_port(&probe_ent->port[2], base + 0x300);
1054 pdc_ata_setup_port(&probe_ent->port[3], base + 0x380);
1056 probe_ent->port[2].scr_addr = base + 0x600;
1057 probe_ent->port[3].scr_addr = base + 0x700;
1064 pci_set_master(pdev);
1066 /* initialize adapter */
1067 pdc_host_init(board_idx, probe_ent);
1069 /* FIXME: Need any other frees than hp? */
1070 if (!ata_device_add(probe_ent))
1080 pci_release_regions(pdev);
1083 pci_disable_device(pdev);
1088 static int __init pdc_ata_init(void)
1090 return pci_register_driver(&pdc_ata_pci_driver);
1094 static void __exit pdc_ata_exit(void)
1096 pci_unregister_driver(&pdc_ata_pci_driver);
1100 MODULE_AUTHOR("Jeff Garzik");
1101 MODULE_DESCRIPTION("Promise ATA TX2/TX4/TX4000 low-level driver");
1102 MODULE_LICENSE("GPL");
1103 MODULE_DEVICE_TABLE(pci, pdc_ata_pci_tbl);
1104 MODULE_VERSION(DRV_VERSION);
1106 module_init(pdc_ata_init);
1107 module_exit(pdc_ata_exit);