2 * sata_nv.c - NVIDIA nForce SATA
4 * Copyright 2004 NVIDIA Corp. All rights reserved.
5 * Copyright 2004 Andrew Chew
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License as published by
10 * the Free Software Foundation; either version 2, or (at your option)
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
18 * You should have received a copy of the GNU General Public License
19 * along with this program; see the file COPYING. If not, write to
20 * the Free Software Foundation, 675 Mass Ave, Cambridge, MA 02139, USA.
23 * libata documentation is available via 'make {ps|pdf}docs',
24 * as Documentation/DocBook/libata.*
26 * No hardware documentation available outside of NVIDIA.
27 * This driver programs the NVIDIA SATA controller in a similar
28 * fashion as with other PCI IDE BMDMA controllers, with a few
29 * NV-specific details such as register offsets, SATA phy location,
32 * CK804/MCP04 controllers support an alternate programming interface
33 * similar to the ADMA specification (with some modifications).
34 * This allows the use of NCQ. Non-DMA-mapped ATA commands are still
35 * sent through the legacy interface.
39 #include <linux/kernel.h>
40 #include <linux/module.h>
41 #include <linux/pci.h>
42 #include <linux/init.h>
43 #include <linux/blkdev.h>
44 #include <linux/delay.h>
45 #include <linux/interrupt.h>
46 #include <linux/device.h>
47 #include <scsi/scsi_host.h>
48 #include <scsi/scsi_device.h>
49 #include <linux/libata.h>
51 #define DRV_NAME "sata_nv"
52 #define DRV_VERSION "3.1"
54 #define NV_ADMA_DMA_BOUNDARY 0xffffffffUL
61 NV_PORT0_SCR_REG_OFFSET = 0x00,
62 NV_PORT1_SCR_REG_OFFSET = 0x40,
64 /* INT_STATUS/ENABLE */
67 NV_INT_STATUS_CK804 = 0x440,
68 NV_INT_ENABLE_CK804 = 0x441,
70 /* INT_STATUS/ENABLE bits */
74 NV_INT_REMOVED = 0x08,
76 NV_INT_PORT_SHIFT = 4, /* each port occupies 4 bits */
79 NV_INT_MASK = NV_INT_DEV |
80 NV_INT_ADDED | NV_INT_REMOVED,
84 NV_INT_CONFIG_METHD = 0x01, // 0 = INT, 1 = SMI
86 // For PCI config register 20
87 NV_MCP_SATA_CFG_20 = 0x50,
88 NV_MCP_SATA_CFG_20_SATA_SPACE_EN = 0x04,
89 NV_MCP_SATA_CFG_20_PORT0_EN = (1 << 17),
90 NV_MCP_SATA_CFG_20_PORT1_EN = (1 << 16),
91 NV_MCP_SATA_CFG_20_PORT0_PWB_EN = (1 << 14),
92 NV_MCP_SATA_CFG_20_PORT1_PWB_EN = (1 << 12),
94 NV_ADMA_MAX_CPBS = 32,
97 NV_ADMA_SGTBL_LEN = (1024 - NV_ADMA_CPB_SZ) /
99 NV_ADMA_SGTBL_TOTAL_LEN = NV_ADMA_SGTBL_LEN + 5,
100 NV_ADMA_SGTBL_SZ = NV_ADMA_SGTBL_LEN * NV_ADMA_APRD_SZ,
101 NV_ADMA_PORT_PRIV_DMA_SZ = NV_ADMA_MAX_CPBS *
102 (NV_ADMA_CPB_SZ + NV_ADMA_SGTBL_SZ),
104 /* BAR5 offset to ADMA general registers */
106 NV_ADMA_GEN_CTL = 0x00,
107 NV_ADMA_NOTIFIER_CLEAR = 0x30,
109 /* BAR5 offset to ADMA ports */
110 NV_ADMA_PORT = 0x480,
112 /* size of ADMA port register space */
113 NV_ADMA_PORT_SIZE = 0x100,
115 /* ADMA port registers */
117 NV_ADMA_CPB_COUNT = 0x42,
118 NV_ADMA_NEXT_CPB_IDX = 0x43,
120 NV_ADMA_CPB_BASE_LOW = 0x48,
121 NV_ADMA_CPB_BASE_HIGH = 0x4C,
122 NV_ADMA_APPEND = 0x50,
123 NV_ADMA_NOTIFIER = 0x68,
124 NV_ADMA_NOTIFIER_ERROR = 0x6C,
126 /* NV_ADMA_CTL register bits */
127 NV_ADMA_CTL_HOTPLUG_IEN = (1 << 0),
128 NV_ADMA_CTL_CHANNEL_RESET = (1 << 5),
129 NV_ADMA_CTL_GO = (1 << 7),
130 NV_ADMA_CTL_AIEN = (1 << 8),
131 NV_ADMA_CTL_READ_NON_COHERENT = (1 << 11),
132 NV_ADMA_CTL_WRITE_NON_COHERENT = (1 << 12),
134 /* CPB response flag bits */
135 NV_CPB_RESP_DONE = (1 << 0),
136 NV_CPB_RESP_ATA_ERR = (1 << 3),
137 NV_CPB_RESP_CMD_ERR = (1 << 4),
138 NV_CPB_RESP_CPB_ERR = (1 << 7),
140 /* CPB control flag bits */
141 NV_CPB_CTL_CPB_VALID = (1 << 0),
142 NV_CPB_CTL_QUEUE = (1 << 1),
143 NV_CPB_CTL_APRD_VALID = (1 << 2),
144 NV_CPB_CTL_IEN = (1 << 3),
145 NV_CPB_CTL_FPDMA = (1 << 4),
148 NV_APRD_WRITE = (1 << 1),
149 NV_APRD_END = (1 << 2),
150 NV_APRD_CONT = (1 << 3),
152 /* NV_ADMA_STAT flags */
153 NV_ADMA_STAT_TIMEOUT = (1 << 0),
154 NV_ADMA_STAT_HOTUNPLUG = (1 << 1),
155 NV_ADMA_STAT_HOTPLUG = (1 << 2),
156 NV_ADMA_STAT_CPBERR = (1 << 4),
157 NV_ADMA_STAT_SERROR = (1 << 5),
158 NV_ADMA_STAT_CMD_COMPLETE = (1 << 6),
159 NV_ADMA_STAT_IDLE = (1 << 8),
160 NV_ADMA_STAT_LEGACY = (1 << 9),
161 NV_ADMA_STAT_STOPPED = (1 << 10),
162 NV_ADMA_STAT_DONE = (1 << 12),
163 NV_ADMA_STAT_ERR = NV_ADMA_STAT_CPBERR |
164 NV_ADMA_STAT_TIMEOUT,
167 NV_ADMA_PORT_REGISTER_MODE = (1 << 0),
171 /* ADMA Physical Region Descriptor - one SG segment */
180 enum nv_adma_regbits {
181 CMDEND = (1 << 15), /* end of command list */
182 WNB = (1 << 14), /* wait-not-BSY */
183 IGN = (1 << 13), /* ignore this entry */
184 CS1n = (1 << (4 + 8)), /* std. PATA signals follow... */
185 DA2 = (1 << (2 + 8)),
186 DA1 = (1 << (1 + 8)),
187 DA0 = (1 << (0 + 8)),
190 /* ADMA Command Parameter Block
191 The first 5 SG segments are stored inside the Command Parameter Block itself.
192 If there are more than 5 segments the remainder are stored in a separate
193 memory area indicated by next_aprd. */
195 u8 resp_flags; /* 0 */
196 u8 reserved1; /* 1 */
197 u8 ctl_flags; /* 2 */
198 /* len is length of taskfile in 64 bit words */
201 u8 next_cpb_idx; /* 5 */
202 __le16 reserved2; /* 6-7 */
203 __le16 tf[12]; /* 8-31 */
204 struct nv_adma_prd aprd[5]; /* 32-111 */
205 __le64 next_aprd; /* 112-119 */
206 __le64 reserved3; /* 120-127 */
210 struct nv_adma_port_priv {
211 struct nv_adma_cpb *cpb;
213 struct nv_adma_prd *aprd;
218 #define NV_ADMA_CHECK_INTR(GCTL, PORT) ((GCTL) & ( 1 << (19 + (12 * (PORT)))))
220 static int nv_init_one (struct pci_dev *pdev, const struct pci_device_id *ent);
221 static void nv_ck804_host_stop(struct ata_host *host);
222 static irqreturn_t nv_generic_interrupt(int irq, void *dev_instance);
223 static irqreturn_t nv_nf2_interrupt(int irq, void *dev_instance);
224 static irqreturn_t nv_ck804_interrupt(int irq, void *dev_instance);
225 static u32 nv_scr_read (struct ata_port *ap, unsigned int sc_reg);
226 static void nv_scr_write (struct ata_port *ap, unsigned int sc_reg, u32 val);
228 static void nv_nf2_freeze(struct ata_port *ap);
229 static void nv_nf2_thaw(struct ata_port *ap);
230 static void nv_ck804_freeze(struct ata_port *ap);
231 static void nv_ck804_thaw(struct ata_port *ap);
232 static void nv_error_handler(struct ata_port *ap);
233 static int nv_adma_slave_config(struct scsi_device *sdev);
234 static void nv_adma_qc_prep(struct ata_queued_cmd *qc);
235 static unsigned int nv_adma_qc_issue(struct ata_queued_cmd *qc);
236 static irqreturn_t nv_adma_interrupt(int irq, void *dev_instance);
237 static void nv_adma_irq_clear(struct ata_port *ap);
238 static int nv_adma_port_start(struct ata_port *ap);
239 static void nv_adma_port_stop(struct ata_port *ap);
240 static void nv_adma_error_handler(struct ata_port *ap);
241 static void nv_adma_host_stop(struct ata_host *host);
242 static void nv_adma_bmdma_setup(struct ata_queued_cmd *qc);
243 static void nv_adma_bmdma_start(struct ata_queued_cmd *qc);
244 static void nv_adma_bmdma_stop(struct ata_queued_cmd *qc);
245 static u8 nv_adma_bmdma_status(struct ata_port *ap);
251 NFORCE3 = NFORCE2, /* NF2 == NF3 as far as sata_nv is concerned */
256 static const struct pci_device_id nv_pci_tbl[] = {
257 { PCI_VDEVICE(NVIDIA, PCI_DEVICE_ID_NVIDIA_NFORCE2S_SATA), NFORCE2 },
258 { PCI_VDEVICE(NVIDIA, PCI_DEVICE_ID_NVIDIA_NFORCE3S_SATA), NFORCE3 },
259 { PCI_VDEVICE(NVIDIA, PCI_DEVICE_ID_NVIDIA_NFORCE3S_SATA2), NFORCE3 },
260 { PCI_VDEVICE(NVIDIA, PCI_DEVICE_ID_NVIDIA_NFORCE_CK804_SATA), CK804 },
261 { PCI_VDEVICE(NVIDIA, PCI_DEVICE_ID_NVIDIA_NFORCE_CK804_SATA2), CK804 },
262 { PCI_VDEVICE(NVIDIA, PCI_DEVICE_ID_NVIDIA_NFORCE_MCP04_SATA), CK804 },
263 { PCI_VDEVICE(NVIDIA, PCI_DEVICE_ID_NVIDIA_NFORCE_MCP04_SATA2), CK804 },
264 { PCI_VDEVICE(NVIDIA, PCI_DEVICE_ID_NVIDIA_NFORCE_MCP51_SATA), GENERIC },
265 { PCI_VDEVICE(NVIDIA, PCI_DEVICE_ID_NVIDIA_NFORCE_MCP51_SATA2), GENERIC },
266 { PCI_VDEVICE(NVIDIA, PCI_DEVICE_ID_NVIDIA_NFORCE_MCP55_SATA), GENERIC },
267 { PCI_VDEVICE(NVIDIA, PCI_DEVICE_ID_NVIDIA_NFORCE_MCP55_SATA2), GENERIC },
268 { PCI_VDEVICE(NVIDIA, PCI_DEVICE_ID_NVIDIA_NFORCE_MCP61_SATA), GENERIC },
269 { PCI_VDEVICE(NVIDIA, PCI_DEVICE_ID_NVIDIA_NFORCE_MCP61_SATA2), GENERIC },
270 { PCI_VDEVICE(NVIDIA, PCI_DEVICE_ID_NVIDIA_NFORCE_MCP61_SATA3), GENERIC },
271 { PCI_VDEVICE(NVIDIA, 0x045c), GENERIC }, /* MCP65 */
272 { PCI_VDEVICE(NVIDIA, 0x045d), GENERIC }, /* MCP65 */
273 { PCI_VDEVICE(NVIDIA, 0x045e), GENERIC }, /* MCP65 */
274 { PCI_VDEVICE(NVIDIA, 0x045f), GENERIC }, /* MCP65 */
275 { PCI_VDEVICE(NVIDIA, 0x0550), GENERIC }, /* MCP67 */
276 { PCI_VDEVICE(NVIDIA, 0x0551), GENERIC }, /* MCP67 */
277 { PCI_VDEVICE(NVIDIA, 0x0552), GENERIC }, /* MCP67 */
278 { PCI_VDEVICE(NVIDIA, 0x0553), GENERIC }, /* MCP67 */
279 { PCI_VENDOR_ID_NVIDIA, PCI_ANY_ID,
280 PCI_ANY_ID, PCI_ANY_ID,
281 PCI_CLASS_STORAGE_IDE<<8, 0xffff00, GENERIC },
282 { PCI_VENDOR_ID_NVIDIA, PCI_ANY_ID,
283 PCI_ANY_ID, PCI_ANY_ID,
284 PCI_CLASS_STORAGE_RAID<<8, 0xffff00, GENERIC },
286 { } /* terminate list */
289 static struct pci_driver nv_pci_driver = {
291 .id_table = nv_pci_tbl,
292 .probe = nv_init_one,
293 .remove = ata_pci_remove_one,
296 static struct scsi_host_template nv_sht = {
297 .module = THIS_MODULE,
299 .ioctl = ata_scsi_ioctl,
300 .queuecommand = ata_scsi_queuecmd,
301 .can_queue = ATA_DEF_QUEUE,
302 .this_id = ATA_SHT_THIS_ID,
303 .sg_tablesize = LIBATA_MAX_PRD,
304 .cmd_per_lun = ATA_SHT_CMD_PER_LUN,
305 .emulated = ATA_SHT_EMULATED,
306 .use_clustering = ATA_SHT_USE_CLUSTERING,
307 .proc_name = DRV_NAME,
308 .dma_boundary = ATA_DMA_BOUNDARY,
309 .slave_configure = ata_scsi_slave_config,
310 .slave_destroy = ata_scsi_slave_destroy,
311 .bios_param = ata_std_bios_param,
314 static struct scsi_host_template nv_adma_sht = {
315 .module = THIS_MODULE,
317 .ioctl = ata_scsi_ioctl,
318 .queuecommand = ata_scsi_queuecmd,
319 .can_queue = NV_ADMA_MAX_CPBS,
320 .this_id = ATA_SHT_THIS_ID,
321 .sg_tablesize = NV_ADMA_SGTBL_TOTAL_LEN,
322 .max_sectors = ATA_MAX_SECTORS,
323 .cmd_per_lun = ATA_SHT_CMD_PER_LUN,
324 .emulated = ATA_SHT_EMULATED,
325 .use_clustering = ATA_SHT_USE_CLUSTERING,
326 .proc_name = DRV_NAME,
327 .dma_boundary = NV_ADMA_DMA_BOUNDARY,
328 .slave_configure = nv_adma_slave_config,
329 .slave_destroy = ata_scsi_slave_destroy,
330 .bios_param = ata_std_bios_param,
333 static const struct ata_port_operations nv_generic_ops = {
334 .port_disable = ata_port_disable,
335 .tf_load = ata_tf_load,
336 .tf_read = ata_tf_read,
337 .exec_command = ata_exec_command,
338 .check_status = ata_check_status,
339 .dev_select = ata_std_dev_select,
340 .bmdma_setup = ata_bmdma_setup,
341 .bmdma_start = ata_bmdma_start,
342 .bmdma_stop = ata_bmdma_stop,
343 .bmdma_status = ata_bmdma_status,
344 .qc_prep = ata_qc_prep,
345 .qc_issue = ata_qc_issue_prot,
346 .freeze = ata_bmdma_freeze,
347 .thaw = ata_bmdma_thaw,
348 .error_handler = nv_error_handler,
349 .post_internal_cmd = ata_bmdma_post_internal_cmd,
350 .data_xfer = ata_pio_data_xfer,
351 .irq_handler = nv_generic_interrupt,
352 .irq_clear = ata_bmdma_irq_clear,
353 .scr_read = nv_scr_read,
354 .scr_write = nv_scr_write,
355 .port_start = ata_port_start,
356 .port_stop = ata_port_stop,
357 .host_stop = ata_pci_host_stop,
360 static const struct ata_port_operations nv_nf2_ops = {
361 .port_disable = ata_port_disable,
362 .tf_load = ata_tf_load,
363 .tf_read = ata_tf_read,
364 .exec_command = ata_exec_command,
365 .check_status = ata_check_status,
366 .dev_select = ata_std_dev_select,
367 .bmdma_setup = ata_bmdma_setup,
368 .bmdma_start = ata_bmdma_start,
369 .bmdma_stop = ata_bmdma_stop,
370 .bmdma_status = ata_bmdma_status,
371 .qc_prep = ata_qc_prep,
372 .qc_issue = ata_qc_issue_prot,
373 .freeze = nv_nf2_freeze,
375 .error_handler = nv_error_handler,
376 .post_internal_cmd = ata_bmdma_post_internal_cmd,
377 .data_xfer = ata_pio_data_xfer,
378 .irq_handler = nv_nf2_interrupt,
379 .irq_clear = ata_bmdma_irq_clear,
380 .scr_read = nv_scr_read,
381 .scr_write = nv_scr_write,
382 .port_start = ata_port_start,
383 .port_stop = ata_port_stop,
384 .host_stop = ata_pci_host_stop,
387 static const struct ata_port_operations nv_ck804_ops = {
388 .port_disable = ata_port_disable,
389 .tf_load = ata_tf_load,
390 .tf_read = ata_tf_read,
391 .exec_command = ata_exec_command,
392 .check_status = ata_check_status,
393 .dev_select = ata_std_dev_select,
394 .bmdma_setup = ata_bmdma_setup,
395 .bmdma_start = ata_bmdma_start,
396 .bmdma_stop = ata_bmdma_stop,
397 .bmdma_status = ata_bmdma_status,
398 .qc_prep = ata_qc_prep,
399 .qc_issue = ata_qc_issue_prot,
400 .freeze = nv_ck804_freeze,
401 .thaw = nv_ck804_thaw,
402 .error_handler = nv_error_handler,
403 .post_internal_cmd = ata_bmdma_post_internal_cmd,
404 .data_xfer = ata_pio_data_xfer,
405 .irq_handler = nv_ck804_interrupt,
406 .irq_clear = ata_bmdma_irq_clear,
407 .scr_read = nv_scr_read,
408 .scr_write = nv_scr_write,
409 .port_start = ata_port_start,
410 .port_stop = ata_port_stop,
411 .host_stop = nv_ck804_host_stop,
414 static const struct ata_port_operations nv_adma_ops = {
415 .port_disable = ata_port_disable,
416 .tf_load = ata_tf_load,
417 .tf_read = ata_tf_read,
418 .exec_command = ata_exec_command,
419 .check_status = ata_check_status,
420 .dev_select = ata_std_dev_select,
421 .bmdma_setup = nv_adma_bmdma_setup,
422 .bmdma_start = nv_adma_bmdma_start,
423 .bmdma_stop = nv_adma_bmdma_stop,
424 .bmdma_status = nv_adma_bmdma_status,
425 .qc_prep = nv_adma_qc_prep,
426 .qc_issue = nv_adma_qc_issue,
427 .freeze = nv_ck804_freeze,
428 .thaw = nv_ck804_thaw,
429 .error_handler = nv_adma_error_handler,
430 .post_internal_cmd = nv_adma_bmdma_stop,
431 .data_xfer = ata_mmio_data_xfer,
432 .irq_handler = nv_adma_interrupt,
433 .irq_clear = nv_adma_irq_clear,
434 .scr_read = nv_scr_read,
435 .scr_write = nv_scr_write,
436 .port_start = nv_adma_port_start,
437 .port_stop = nv_adma_port_stop,
438 .host_stop = nv_adma_host_stop,
441 static struct ata_port_info nv_port_info[] = {
445 .flags = ATA_FLAG_SATA | ATA_FLAG_NO_LEGACY,
446 .pio_mask = NV_PIO_MASK,
447 .mwdma_mask = NV_MWDMA_MASK,
448 .udma_mask = NV_UDMA_MASK,
449 .port_ops = &nv_generic_ops,
454 .flags = ATA_FLAG_SATA | ATA_FLAG_NO_LEGACY,
455 .pio_mask = NV_PIO_MASK,
456 .mwdma_mask = NV_MWDMA_MASK,
457 .udma_mask = NV_UDMA_MASK,
458 .port_ops = &nv_nf2_ops,
463 .flags = ATA_FLAG_SATA | ATA_FLAG_NO_LEGACY,
464 .pio_mask = NV_PIO_MASK,
465 .mwdma_mask = NV_MWDMA_MASK,
466 .udma_mask = NV_UDMA_MASK,
467 .port_ops = &nv_ck804_ops,
472 .flags = ATA_FLAG_SATA | ATA_FLAG_NO_LEGACY |
473 ATA_FLAG_MMIO | ATA_FLAG_NCQ,
474 .pio_mask = NV_PIO_MASK,
475 .mwdma_mask = NV_MWDMA_MASK,
476 .udma_mask = NV_UDMA_MASK,
477 .port_ops = &nv_adma_ops,
481 MODULE_AUTHOR("NVIDIA");
482 MODULE_DESCRIPTION("low-level driver for NVIDIA nForce SATA controller");
483 MODULE_LICENSE("GPL");
484 MODULE_DEVICE_TABLE(pci, nv_pci_tbl);
485 MODULE_VERSION(DRV_VERSION);
487 static int adma_enabled = 1;
489 static int nv_adma_slave_config(struct scsi_device *sdev)
491 struct ata_port *ap = ata_shost_to_port(sdev->host);
493 unsigned long segment_boundary;
494 unsigned short sg_tablesize;
497 rc = ata_scsi_slave_config(sdev);
499 if (sdev->id >= ATA_MAX_DEVICES || sdev->channel || sdev->lun)
500 /* Not a proper libata device, ignore */
503 if (ap->device[sdev->id].class == ATA_DEV_ATAPI) {
505 * NVIDIA reports that ADMA mode does not support ATAPI commands.
506 * Therefore ATAPI commands are sent through the legacy interface.
507 * However, the legacy interface only supports 32-bit DMA.
508 * Restrict DMA parameters as required by the legacy interface
509 * when an ATAPI device is connected.
511 bounce_limit = ATA_DMA_MASK;
512 segment_boundary = ATA_DMA_BOUNDARY;
513 /* Subtract 1 since an extra entry may be needed for padding, see
515 sg_tablesize = LIBATA_MAX_PRD - 1;
518 bounce_limit = *ap->dev->dma_mask;
519 segment_boundary = NV_ADMA_DMA_BOUNDARY;
520 sg_tablesize = NV_ADMA_SGTBL_TOTAL_LEN;
523 blk_queue_bounce_limit(sdev->request_queue, bounce_limit);
524 blk_queue_segment_boundary(sdev->request_queue, segment_boundary);
525 blk_queue_max_hw_segments(sdev->request_queue, sg_tablesize);
526 ata_port_printk(ap, KERN_INFO,
527 "bounce limit 0x%llX, segment boundary 0x%lX, hw segs %hu\n",
528 (unsigned long long)bounce_limit, segment_boundary, sg_tablesize);
532 static unsigned int nv_adma_tf_to_cpb(struct ata_taskfile *tf, u16 *cpb)
534 unsigned int idx = 0;
536 cpb[idx++] = cpu_to_le16((ATA_REG_DEVICE << 8) | tf->device | WNB);
538 if ((tf->flags & ATA_TFLAG_LBA48) == 0) {
539 cpb[idx++] = cpu_to_le16(IGN);
540 cpb[idx++] = cpu_to_le16(IGN);
541 cpb[idx++] = cpu_to_le16(IGN);
542 cpb[idx++] = cpu_to_le16(IGN);
543 cpb[idx++] = cpu_to_le16(IGN);
546 cpb[idx++] = cpu_to_le16((ATA_REG_ERR << 8) | tf->hob_feature);
547 cpb[idx++] = cpu_to_le16((ATA_REG_NSECT << 8) | tf->hob_nsect);
548 cpb[idx++] = cpu_to_le16((ATA_REG_LBAL << 8) | tf->hob_lbal);
549 cpb[idx++] = cpu_to_le16((ATA_REG_LBAM << 8) | tf->hob_lbam);
550 cpb[idx++] = cpu_to_le16((ATA_REG_LBAH << 8) | tf->hob_lbah);
552 cpb[idx++] = cpu_to_le16((ATA_REG_ERR << 8) | tf->feature);
553 cpb[idx++] = cpu_to_le16((ATA_REG_NSECT << 8) | tf->nsect);
554 cpb[idx++] = cpu_to_le16((ATA_REG_LBAL << 8) | tf->lbal);
555 cpb[idx++] = cpu_to_le16((ATA_REG_LBAM << 8) | tf->lbam);
556 cpb[idx++] = cpu_to_le16((ATA_REG_LBAH << 8) | tf->lbah);
558 cpb[idx++] = cpu_to_le16((ATA_REG_CMD << 8) | tf->command | CMDEND);
563 static inline void __iomem *__nv_adma_ctl_block(void __iomem *mmio,
564 unsigned int port_no)
566 mmio += NV_ADMA_PORT + port_no * NV_ADMA_PORT_SIZE;
570 static inline void __iomem *nv_adma_ctl_block(struct ata_port *ap)
572 return __nv_adma_ctl_block(ap->host->mmio_base, ap->port_no);
575 static inline void __iomem *nv_adma_gen_block(struct ata_port *ap)
577 return (ap->host->mmio_base + NV_ADMA_GEN);
580 static inline void __iomem *nv_adma_notifier_clear_block(struct ata_port *ap)
582 return (nv_adma_gen_block(ap) + NV_ADMA_NOTIFIER_CLEAR + (4 * ap->port_no));
585 static void nv_adma_check_cpb(struct ata_port *ap, int cpb_num, int force_err)
587 struct nv_adma_port_priv *pp = ap->private_data;
588 int complete = 0, have_err = 0;
589 u16 flags = pp->cpb[cpb_num].resp_flags;
591 VPRINTK("CPB %d, flags=0x%x\n", cpb_num, flags);
593 if (flags & NV_CPB_RESP_DONE) {
594 VPRINTK("CPB flags done, flags=0x%x\n", flags);
597 if (flags & NV_CPB_RESP_ATA_ERR) {
598 ata_port_printk(ap, KERN_ERR, "CPB flags ATA err, flags=0x%x\n", flags);
602 if (flags & NV_CPB_RESP_CMD_ERR) {
603 ata_port_printk(ap, KERN_ERR, "CPB flags CMD err, flags=0x%x\n", flags);
607 if (flags & NV_CPB_RESP_CPB_ERR) {
608 ata_port_printk(ap, KERN_ERR, "CPB flags CPB err, flags=0x%x\n", flags);
612 if(complete || force_err)
614 struct ata_queued_cmd *qc = ata_qc_from_tag(ap, cpb_num);
617 /* Only use the ATA port status for non-NCQ commands.
618 For NCQ commands the current status may have nothing to do with
619 the command just completed. */
620 if(qc->tf.protocol != ATA_PROT_NCQ)
621 ata_status = readb(nv_adma_ctl_block(ap) + (ATA_REG_STATUS * 4));
623 if(have_err || force_err)
624 ata_status |= ATA_ERR;
626 qc->err_mask |= ac_err_mask(ata_status);
627 DPRINTK("Completing qc from tag %d with err_mask %u\n",cpb_num,
634 static irqreturn_t nv_adma_interrupt(int irq, void *dev_instance)
636 struct ata_host *host = dev_instance;
639 spin_lock(&host->lock);
641 for (i = 0; i < host->n_ports; i++) {
642 struct ata_port *ap = host->ports[i];
644 if (ap && !(ap->flags & ATA_FLAG_DISABLED)) {
645 struct nv_adma_port_priv *pp = ap->private_data;
646 void __iomem *mmio = nv_adma_ctl_block(ap);
649 int have_global_err = 0;
650 u32 notifier, notifier_error;
652 /* if in ATA register mode, use standard ata interrupt handler */
653 if (pp->flags & NV_ADMA_PORT_REGISTER_MODE) {
654 struct ata_queued_cmd *qc;
655 VPRINTK("in ATA register mode\n");
656 qc = ata_qc_from_tag(ap, ap->active_tag);
657 if (qc && (!(qc->tf.flags & ATA_TFLAG_POLLING)))
658 handled += ata_host_intr(ap, qc);
660 /* No request pending? Clear interrupt status
661 anyway, in case there's one pending. */
662 ap->ops->check_status(ap);
668 notifier = readl(mmio + NV_ADMA_NOTIFIER);
669 notifier_error = readl(mmio + NV_ADMA_NOTIFIER_ERROR);
671 gen_ctl = readl(nv_adma_gen_block(ap) + NV_ADMA_GEN_CTL);
673 /* Seems necessary to clear notifiers even when they were 0.
674 Otherwise we seem to stop receiving further interrupts.
676 writel(notifier | notifier_error, nv_adma_notifier_clear_block(ap));
678 if( !NV_ADMA_CHECK_INTR(gen_ctl, ap->port_no) && !notifier &&
683 status = readw(mmio + NV_ADMA_STAT);
685 /* Clear status. Ensure the controller sees the clearing before we start
686 looking at any of the CPB statuses, so that any CPB completions after
687 this point in the handler will raise another interrupt. */
688 writew(status, mmio + NV_ADMA_STAT);
689 readw(mmio + NV_ADMA_STAT); /* flush posted write */
692 /* freeze if hotplugged */
693 if (unlikely(status & (NV_ADMA_STAT_HOTPLUG | NV_ADMA_STAT_HOTUNPLUG))) {
694 ata_port_printk(ap, KERN_NOTICE, "Hotplug event, freezing\n");
700 if (status & NV_ADMA_STAT_TIMEOUT) {
701 ata_port_printk(ap, KERN_ERR, "timeout, stat=0x%x\n", status);
704 if (status & NV_ADMA_STAT_CPBERR) {
705 ata_port_printk(ap, KERN_ERR, "CPB error, stat=0x%x\n", status);
708 if ((status & NV_ADMA_STAT_DONE) || have_global_err) {
709 /** Check CPBs for completed commands */
711 if(ata_tag_valid(ap->active_tag))
712 /* Non-NCQ command */
713 nv_adma_check_cpb(ap, ap->active_tag, have_global_err ||
714 (notifier_error & (1 << ap->active_tag)));
717 u32 active = ap->sactive;
718 while( (pos = ffs(active)) ) {
720 nv_adma_check_cpb(ap, pos, have_global_err ||
721 (notifier_error & (1 << pos)) );
722 active &= ~(1 << pos );
727 handled++; /* irq handled if we got here */
731 spin_unlock(&host->lock);
733 return IRQ_RETVAL(handled);
736 static void nv_adma_irq_clear(struct ata_port *ap)
738 void __iomem *mmio = nv_adma_ctl_block(ap);
739 u16 status = readw(mmio + NV_ADMA_STAT);
740 u32 notifier = readl(mmio + NV_ADMA_NOTIFIER);
741 u32 notifier_error = readl(mmio + NV_ADMA_NOTIFIER_ERROR);
743 /* clear ADMA status */
744 writew(status, mmio + NV_ADMA_STAT);
745 writel(notifier | notifier_error,
746 nv_adma_notifier_clear_block(ap));
748 /** clear legacy status */
749 ap->flags &= ~ATA_FLAG_MMIO;
750 ata_bmdma_irq_clear(ap);
751 ap->flags |= ATA_FLAG_MMIO;
754 static void nv_adma_bmdma_setup(struct ata_queued_cmd *qc)
756 struct nv_adma_port_priv *pp = qc->ap->private_data;
758 if(pp->flags & NV_ADMA_PORT_REGISTER_MODE) {
763 qc->ap->flags &= ~ATA_FLAG_MMIO;
765 qc->ap->flags |= ATA_FLAG_MMIO;
768 static void nv_adma_bmdma_start(struct ata_queued_cmd *qc)
770 struct nv_adma_port_priv *pp = qc->ap->private_data;
772 if(pp->flags & NV_ADMA_PORT_REGISTER_MODE) {
777 qc->ap->flags &= ~ATA_FLAG_MMIO;
779 qc->ap->flags |= ATA_FLAG_MMIO;
782 static void nv_adma_bmdma_stop(struct ata_queued_cmd *qc)
784 struct nv_adma_port_priv *pp = qc->ap->private_data;
786 if(pp->flags & NV_ADMA_PORT_REGISTER_MODE)
789 qc->ap->flags &= ~ATA_FLAG_MMIO;
791 qc->ap->flags |= ATA_FLAG_MMIO;
794 static u8 nv_adma_bmdma_status(struct ata_port *ap)
797 struct nv_adma_port_priv *pp = ap->private_data;
799 WARN_ON(pp->flags & NV_ADMA_PORT_REGISTER_MODE);
801 ap->flags &= ~ATA_FLAG_MMIO;
802 status = ata_bmdma_status(ap);
803 ap->flags |= ATA_FLAG_MMIO;
807 static void nv_adma_register_mode(struct ata_port *ap)
809 void __iomem *mmio = nv_adma_ctl_block(ap);
810 struct nv_adma_port_priv *pp = ap->private_data;
813 if (pp->flags & NV_ADMA_PORT_REGISTER_MODE)
816 tmp = readw(mmio + NV_ADMA_CTL);
817 writew(tmp & ~NV_ADMA_CTL_GO, mmio + NV_ADMA_CTL);
819 pp->flags |= NV_ADMA_PORT_REGISTER_MODE;
822 static void nv_adma_mode(struct ata_port *ap)
824 void __iomem *mmio = nv_adma_ctl_block(ap);
825 struct nv_adma_port_priv *pp = ap->private_data;
828 if (!(pp->flags & NV_ADMA_PORT_REGISTER_MODE))
831 tmp = readw(mmio + NV_ADMA_CTL);
832 writew(tmp | NV_ADMA_CTL_GO, mmio + NV_ADMA_CTL);
834 pp->flags &= ~NV_ADMA_PORT_REGISTER_MODE;
837 static int nv_adma_port_start(struct ata_port *ap)
839 struct device *dev = ap->host->dev;
840 struct nv_adma_port_priv *pp;
844 void __iomem *mmio = nv_adma_ctl_block(ap);
849 rc = ata_port_start(ap);
853 pp = kzalloc(sizeof(*pp), GFP_KERNEL);
859 mem = dma_alloc_coherent(dev, NV_ADMA_PORT_PRIV_DMA_SZ,
860 &mem_dma, GFP_KERNEL);
866 memset(mem, 0, NV_ADMA_PORT_PRIV_DMA_SZ);
869 * First item in chunk of DMA memory:
870 * 128-byte command parameter block (CPB)
871 * one for each command tag
874 pp->cpb_dma = mem_dma;
876 writel(mem_dma & 0xFFFFFFFF, mmio + NV_ADMA_CPB_BASE_LOW);
877 writel((mem_dma >> 16 ) >> 16, mmio + NV_ADMA_CPB_BASE_HIGH);
879 mem += NV_ADMA_MAX_CPBS * NV_ADMA_CPB_SZ;
880 mem_dma += NV_ADMA_MAX_CPBS * NV_ADMA_CPB_SZ;
883 * Second item: block of ADMA_SGTBL_LEN s/g entries
886 pp->aprd_dma = mem_dma;
888 ap->private_data = pp;
890 /* clear any outstanding interrupt conditions */
891 writew(0xffff, mmio + NV_ADMA_STAT);
893 /* initialize port variables */
894 pp->flags = NV_ADMA_PORT_REGISTER_MODE;
896 /* clear CPB fetch count */
897 writew(0, mmio + NV_ADMA_CPB_COUNT);
899 /* clear GO for register mode */
900 tmp = readw(mmio + NV_ADMA_CTL);
901 writew(tmp & ~NV_ADMA_CTL_GO, mmio + NV_ADMA_CTL);
903 tmp = readw(mmio + NV_ADMA_CTL);
904 writew(tmp | NV_ADMA_CTL_CHANNEL_RESET, mmio + NV_ADMA_CTL);
905 readl( mmio + NV_ADMA_CTL ); /* flush posted write */
907 writew(tmp & ~NV_ADMA_CTL_CHANNEL_RESET, mmio + NV_ADMA_CTL);
908 readl( mmio + NV_ADMA_CTL ); /* flush posted write */
919 static void nv_adma_port_stop(struct ata_port *ap)
921 struct device *dev = ap->host->dev;
922 struct nv_adma_port_priv *pp = ap->private_data;
923 void __iomem *mmio = nv_adma_ctl_block(ap);
927 writew(0, mmio + NV_ADMA_CTL);
929 ap->private_data = NULL;
930 dma_free_coherent(dev, NV_ADMA_PORT_PRIV_DMA_SZ, pp->cpb, pp->cpb_dma);
936 static void nv_adma_setup_port(struct ata_probe_ent *probe_ent, unsigned int port)
938 void __iomem *mmio = probe_ent->mmio_base;
939 struct ata_ioports *ioport = &probe_ent->port[port];
943 mmio += NV_ADMA_PORT + port * NV_ADMA_PORT_SIZE;
945 ioport->cmd_addr = (unsigned long) mmio;
946 ioport->data_addr = (unsigned long) mmio + (ATA_REG_DATA * 4);
948 ioport->feature_addr = (unsigned long) mmio + (ATA_REG_ERR * 4);
949 ioport->nsect_addr = (unsigned long) mmio + (ATA_REG_NSECT * 4);
950 ioport->lbal_addr = (unsigned long) mmio + (ATA_REG_LBAL * 4);
951 ioport->lbam_addr = (unsigned long) mmio + (ATA_REG_LBAM * 4);
952 ioport->lbah_addr = (unsigned long) mmio + (ATA_REG_LBAH * 4);
953 ioport->device_addr = (unsigned long) mmio + (ATA_REG_DEVICE * 4);
954 ioport->status_addr =
955 ioport->command_addr = (unsigned long) mmio + (ATA_REG_STATUS * 4);
956 ioport->altstatus_addr =
957 ioport->ctl_addr = (unsigned long) mmio + 0x20;
960 static int nv_adma_host_init(struct ata_probe_ent *probe_ent)
962 struct pci_dev *pdev = to_pci_dev(probe_ent->dev);
968 /* enable ADMA on the ports */
969 pci_read_config_dword(pdev, NV_MCP_SATA_CFG_20, &tmp32);
970 tmp32 |= NV_MCP_SATA_CFG_20_PORT0_EN |
971 NV_MCP_SATA_CFG_20_PORT0_PWB_EN |
972 NV_MCP_SATA_CFG_20_PORT1_EN |
973 NV_MCP_SATA_CFG_20_PORT1_PWB_EN;
975 pci_write_config_dword(pdev, NV_MCP_SATA_CFG_20, tmp32);
977 for (i = 0; i < probe_ent->n_ports; i++)
978 nv_adma_setup_port(probe_ent, i);
980 for (i = 0; i < probe_ent->n_ports; i++) {
981 void __iomem *mmio = __nv_adma_ctl_block(probe_ent->mmio_base, i);
984 /* enable interrupt, clear reset if not already clear */
985 tmp = readw(mmio + NV_ADMA_CTL);
986 writew(tmp | NV_ADMA_CTL_AIEN, mmio + NV_ADMA_CTL);
992 static void nv_adma_fill_aprd(struct ata_queued_cmd *qc,
993 struct scatterlist *sg,
995 struct nv_adma_prd *aprd)
999 memset(aprd, 0, sizeof(struct nv_adma_prd));
1002 if (qc->tf.flags & ATA_TFLAG_WRITE)
1003 flags |= NV_APRD_WRITE;
1004 if (idx == qc->n_elem - 1)
1005 flags |= NV_APRD_END;
1007 flags |= NV_APRD_CONT;
1009 aprd->addr = cpu_to_le64(((u64)sg_dma_address(sg)));
1010 aprd->len = cpu_to_le32(((u32)sg_dma_len(sg))); /* len in bytes */
1011 aprd->flags = cpu_to_le32(flags);
1014 static void nv_adma_fill_sg(struct ata_queued_cmd *qc, struct nv_adma_cpb *cpb)
1016 struct nv_adma_port_priv *pp = qc->ap->private_data;
1018 struct nv_adma_prd *aprd;
1019 struct scatterlist *sg;
1025 ata_for_each_sg(sg, qc) {
1026 aprd = (idx < 5) ? &cpb->aprd[idx] : &pp->aprd[NV_ADMA_SGTBL_LEN * qc->tag + (idx-5)];
1027 nv_adma_fill_aprd(qc, sg, idx, aprd);
1031 cpb->next_aprd = cpu_to_le64(((u64)(pp->aprd_dma + NV_ADMA_SGTBL_SZ * qc->tag)));
1034 static void nv_adma_qc_prep(struct ata_queued_cmd *qc)
1036 struct nv_adma_port_priv *pp = qc->ap->private_data;
1037 struct nv_adma_cpb *cpb = &pp->cpb[qc->tag];
1038 u8 ctl_flags = NV_CPB_CTL_CPB_VALID |
1039 NV_CPB_CTL_APRD_VALID |
1042 VPRINTK("qc->flags = 0x%lx\n", qc->flags);
1044 if (!(qc->flags & ATA_QCFLAG_DMAMAP) ||
1045 qc->tf.protocol == ATA_PROT_ATAPI_DMA) {
1050 memset(cpb, 0, sizeof(struct nv_adma_cpb));
1054 cpb->next_cpb_idx = 0;
1056 /* turn on NCQ flags for NCQ commands */
1057 if (qc->tf.protocol == ATA_PROT_NCQ)
1058 ctl_flags |= NV_CPB_CTL_QUEUE | NV_CPB_CTL_FPDMA;
1060 nv_adma_tf_to_cpb(&qc->tf, cpb->tf);
1062 nv_adma_fill_sg(qc, cpb);
1064 /* Be paranoid and don't let the device see NV_CPB_CTL_CPB_VALID until we are
1065 finished filling in all of the contents */
1067 cpb->ctl_flags = ctl_flags;
1070 static unsigned int nv_adma_qc_issue(struct ata_queued_cmd *qc)
1072 void __iomem *mmio = nv_adma_ctl_block(qc->ap);
1076 if (!(qc->flags & ATA_QCFLAG_DMAMAP) ||
1077 qc->tf.protocol == ATA_PROT_ATAPI_DMA) {
1078 /* use ATA register mode */
1079 VPRINTK("no dmamap or ATAPI, using ATA register mode: 0x%lx\n", qc->flags);
1080 nv_adma_register_mode(qc->ap);
1081 return ata_qc_issue_prot(qc);
1083 nv_adma_mode(qc->ap);
1085 /* write append register, command tag in lower 8 bits
1086 and (number of cpbs to append -1) in top 8 bits */
1088 writew(qc->tag, mmio + NV_ADMA_APPEND);
1090 DPRINTK("Issued tag %u\n",qc->tag);
1095 static irqreturn_t nv_generic_interrupt(int irq, void *dev_instance)
1097 struct ata_host *host = dev_instance;
1099 unsigned int handled = 0;
1100 unsigned long flags;
1102 spin_lock_irqsave(&host->lock, flags);
1104 for (i = 0; i < host->n_ports; i++) {
1105 struct ata_port *ap;
1107 ap = host->ports[i];
1109 !(ap->flags & ATA_FLAG_DISABLED)) {
1110 struct ata_queued_cmd *qc;
1112 qc = ata_qc_from_tag(ap, ap->active_tag);
1113 if (qc && (!(qc->tf.flags & ATA_TFLAG_POLLING)))
1114 handled += ata_host_intr(ap, qc);
1116 // No request pending? Clear interrupt status
1117 // anyway, in case there's one pending.
1118 ap->ops->check_status(ap);
1123 spin_unlock_irqrestore(&host->lock, flags);
1125 return IRQ_RETVAL(handled);
1128 static int nv_host_intr(struct ata_port *ap, u8 irq_stat)
1130 struct ata_queued_cmd *qc = ata_qc_from_tag(ap, ap->active_tag);
1133 /* freeze if hotplugged */
1134 if (unlikely(irq_stat & (NV_INT_ADDED | NV_INT_REMOVED))) {
1135 ata_port_freeze(ap);
1139 /* bail out if not our interrupt */
1140 if (!(irq_stat & NV_INT_DEV))
1143 /* DEV interrupt w/ no active qc? */
1144 if (unlikely(!qc || (qc->tf.flags & ATA_TFLAG_POLLING))) {
1145 ata_check_status(ap);
1149 /* handle interrupt */
1150 handled = ata_host_intr(ap, qc);
1151 if (unlikely(!handled)) {
1152 /* spurious, clear it */
1153 ata_check_status(ap);
1159 static irqreturn_t nv_do_interrupt(struct ata_host *host, u8 irq_stat)
1163 for (i = 0; i < host->n_ports; i++) {
1164 struct ata_port *ap = host->ports[i];
1166 if (ap && !(ap->flags & ATA_FLAG_DISABLED))
1167 handled += nv_host_intr(ap, irq_stat);
1169 irq_stat >>= NV_INT_PORT_SHIFT;
1172 return IRQ_RETVAL(handled);
1175 static irqreturn_t nv_nf2_interrupt(int irq, void *dev_instance)
1177 struct ata_host *host = dev_instance;
1181 spin_lock(&host->lock);
1182 irq_stat = inb(host->ports[0]->ioaddr.scr_addr + NV_INT_STATUS);
1183 ret = nv_do_interrupt(host, irq_stat);
1184 spin_unlock(&host->lock);
1189 static irqreturn_t nv_ck804_interrupt(int irq, void *dev_instance)
1191 struct ata_host *host = dev_instance;
1195 spin_lock(&host->lock);
1196 irq_stat = readb(host->mmio_base + NV_INT_STATUS_CK804);
1197 ret = nv_do_interrupt(host, irq_stat);
1198 spin_unlock(&host->lock);
1203 static u32 nv_scr_read (struct ata_port *ap, unsigned int sc_reg)
1205 if (sc_reg > SCR_CONTROL)
1208 return ioread32((void __iomem *)ap->ioaddr.scr_addr + (sc_reg * 4));
1211 static void nv_scr_write (struct ata_port *ap, unsigned int sc_reg, u32 val)
1213 if (sc_reg > SCR_CONTROL)
1216 iowrite32(val, (void __iomem *)ap->ioaddr.scr_addr + (sc_reg * 4));
1219 static void nv_nf2_freeze(struct ata_port *ap)
1221 unsigned long scr_addr = ap->host->ports[0]->ioaddr.scr_addr;
1222 int shift = ap->port_no * NV_INT_PORT_SHIFT;
1225 mask = inb(scr_addr + NV_INT_ENABLE);
1226 mask &= ~(NV_INT_ALL << shift);
1227 outb(mask, scr_addr + NV_INT_ENABLE);
1230 static void nv_nf2_thaw(struct ata_port *ap)
1232 unsigned long scr_addr = ap->host->ports[0]->ioaddr.scr_addr;
1233 int shift = ap->port_no * NV_INT_PORT_SHIFT;
1236 outb(NV_INT_ALL << shift, scr_addr + NV_INT_STATUS);
1238 mask = inb(scr_addr + NV_INT_ENABLE);
1239 mask |= (NV_INT_MASK << shift);
1240 outb(mask, scr_addr + NV_INT_ENABLE);
1243 static void nv_ck804_freeze(struct ata_port *ap)
1245 void __iomem *mmio_base = ap->host->mmio_base;
1246 int shift = ap->port_no * NV_INT_PORT_SHIFT;
1249 mask = readb(mmio_base + NV_INT_ENABLE_CK804);
1250 mask &= ~(NV_INT_ALL << shift);
1251 writeb(mask, mmio_base + NV_INT_ENABLE_CK804);
1254 static void nv_ck804_thaw(struct ata_port *ap)
1256 void __iomem *mmio_base = ap->host->mmio_base;
1257 int shift = ap->port_no * NV_INT_PORT_SHIFT;
1260 writeb(NV_INT_ALL << shift, mmio_base + NV_INT_STATUS_CK804);
1262 mask = readb(mmio_base + NV_INT_ENABLE_CK804);
1263 mask |= (NV_INT_MASK << shift);
1264 writeb(mask, mmio_base + NV_INT_ENABLE_CK804);
1267 static int nv_hardreset(struct ata_port *ap, unsigned int *class)
1271 /* SATA hardreset fails to retrieve proper device signature on
1272 * some controllers. Don't classify on hardreset. For more
1273 * info, see http://bugme.osdl.org/show_bug.cgi?id=3352
1275 return sata_std_hardreset(ap, &dummy);
1278 static void nv_error_handler(struct ata_port *ap)
1280 ata_bmdma_drive_eh(ap, ata_std_prereset, ata_std_softreset,
1281 nv_hardreset, ata_std_postreset);
1284 static void nv_adma_error_handler(struct ata_port *ap)
1286 struct nv_adma_port_priv *pp = ap->private_data;
1287 if(!(pp->flags & NV_ADMA_PORT_REGISTER_MODE)) {
1288 void __iomem *mmio = nv_adma_ctl_block(ap);
1292 u32 notifier = readl(mmio + NV_ADMA_NOTIFIER);
1293 u32 notifier_error = readl(mmio + NV_ADMA_NOTIFIER_ERROR);
1294 u32 gen_ctl = readl(nv_adma_gen_block(ap) + NV_ADMA_GEN_CTL);
1295 u32 status = readw(mmio + NV_ADMA_STAT);
1297 ata_port_printk(ap, KERN_ERR, "EH in ADMA mode, notifier 0x%X "
1298 "notifier_error 0x%X gen_ctl 0x%X status 0x%X\n",
1299 notifier, notifier_error, gen_ctl, status);
1301 for( i=0;i<NV_ADMA_MAX_CPBS;i++) {
1302 struct nv_adma_cpb *cpb = &pp->cpb[i];
1303 if( cpb->ctl_flags || cpb->resp_flags )
1304 ata_port_printk(ap, KERN_ERR,
1305 "CPB %d: ctl_flags 0x%x, resp_flags 0x%x\n",
1306 i, cpb->ctl_flags, cpb->resp_flags);
1309 /* Push us back into port register mode for error handling. */
1310 nv_adma_register_mode(ap);
1312 ata_port_printk(ap, KERN_ERR, "Resetting port\n");
1314 /* Mark all of the CPBs as invalid to prevent them from being executed */
1315 for( i=0;i<NV_ADMA_MAX_CPBS;i++)
1316 pp->cpb[i].ctl_flags &= ~NV_CPB_CTL_CPB_VALID;
1318 /* clear CPB fetch count */
1319 writew(0, mmio + NV_ADMA_CPB_COUNT);
1322 tmp = readw(mmio + NV_ADMA_CTL);
1323 writew(tmp | NV_ADMA_CTL_CHANNEL_RESET, mmio + NV_ADMA_CTL);
1324 readl( mmio + NV_ADMA_CTL ); /* flush posted write */
1326 writew(tmp & ~NV_ADMA_CTL_CHANNEL_RESET, mmio + NV_ADMA_CTL);
1327 readl( mmio + NV_ADMA_CTL ); /* flush posted write */
1330 ata_bmdma_drive_eh(ap, ata_std_prereset, ata_std_softreset,
1331 nv_hardreset, ata_std_postreset);
1334 static int nv_init_one (struct pci_dev *pdev, const struct pci_device_id *ent)
1336 static int printed_version = 0;
1337 struct ata_port_info *ppi[2];
1338 struct ata_probe_ent *probe_ent;
1339 int pci_dev_busy = 0;
1343 unsigned long type = ent->driver_data;
1346 // Make sure this is a SATA controller by counting the number of bars
1347 // (NVIDIA SATA controllers will always have six bars). Otherwise,
1348 // it's an IDE controller and we ignore it.
1349 for (bar=0; bar<6; bar++)
1350 if (pci_resource_start(pdev, bar) == 0)
1353 if ( !printed_version++)
1354 dev_printk(KERN_DEBUG, &pdev->dev, "version " DRV_VERSION "\n");
1356 rc = pci_enable_device(pdev);
1360 rc = pci_request_regions(pdev, DRV_NAME);
1363 goto err_out_disable;
1366 if(type >= CK804 && adma_enabled) {
1367 dev_printk(KERN_NOTICE, &pdev->dev, "Using ADMA mode\n");
1369 if(!pci_set_dma_mask(pdev, DMA_64BIT_MASK) &&
1370 !pci_set_consistent_dma_mask(pdev, DMA_64BIT_MASK))
1375 rc = pci_set_dma_mask(pdev, ATA_DMA_MASK);
1377 goto err_out_regions;
1378 rc = pci_set_consistent_dma_mask(pdev, ATA_DMA_MASK);
1380 goto err_out_regions;
1385 ppi[0] = ppi[1] = &nv_port_info[type];
1386 probe_ent = ata_pci_init_native_mode(pdev, ppi, ATA_PORT_PRIMARY | ATA_PORT_SECONDARY);
1388 goto err_out_regions;
1390 probe_ent->mmio_base = pci_iomap(pdev, 5, 0);
1391 if (!probe_ent->mmio_base) {
1393 goto err_out_free_ent;
1396 base = (unsigned long)probe_ent->mmio_base;
1398 probe_ent->port[0].scr_addr = base + NV_PORT0_SCR_REG_OFFSET;
1399 probe_ent->port[1].scr_addr = base + NV_PORT1_SCR_REG_OFFSET;
1401 /* enable SATA space for CK804 */
1402 if (type >= CK804) {
1405 pci_read_config_byte(pdev, NV_MCP_SATA_CFG_20, ®val);
1406 regval |= NV_MCP_SATA_CFG_20_SATA_SPACE_EN;
1407 pci_write_config_byte(pdev, NV_MCP_SATA_CFG_20, regval);
1410 pci_set_master(pdev);
1413 rc = nv_adma_host_init(probe_ent);
1415 goto err_out_iounmap;
1418 rc = ata_device_add(probe_ent);
1420 goto err_out_iounmap;
1427 pci_iounmap(pdev, probe_ent->mmio_base);
1431 pci_release_regions(pdev);
1434 pci_disable_device(pdev);
1439 static void nv_ck804_host_stop(struct ata_host *host)
1441 struct pci_dev *pdev = to_pci_dev(host->dev);
1444 /* disable SATA space for CK804 */
1445 pci_read_config_byte(pdev, NV_MCP_SATA_CFG_20, ®val);
1446 regval &= ~NV_MCP_SATA_CFG_20_SATA_SPACE_EN;
1447 pci_write_config_byte(pdev, NV_MCP_SATA_CFG_20, regval);
1449 ata_pci_host_stop(host);
1452 static void nv_adma_host_stop(struct ata_host *host)
1454 struct pci_dev *pdev = to_pci_dev(host->dev);
1458 for (i = 0; i < host->n_ports; i++) {
1459 void __iomem *mmio = __nv_adma_ctl_block(host->mmio_base, i);
1462 /* disable interrupt */
1463 tmp = readw(mmio + NV_ADMA_CTL);
1464 writew(tmp & ~NV_ADMA_CTL_AIEN, mmio + NV_ADMA_CTL);
1467 /* disable ADMA on the ports */
1468 pci_read_config_dword(pdev, NV_MCP_SATA_CFG_20, &tmp32);
1469 tmp32 &= ~(NV_MCP_SATA_CFG_20_PORT0_EN |
1470 NV_MCP_SATA_CFG_20_PORT0_PWB_EN |
1471 NV_MCP_SATA_CFG_20_PORT1_EN |
1472 NV_MCP_SATA_CFG_20_PORT1_PWB_EN);
1474 pci_write_config_dword(pdev, NV_MCP_SATA_CFG_20, tmp32);
1476 nv_ck804_host_stop(host);
1479 static int __init nv_init(void)
1481 return pci_register_driver(&nv_pci_driver);
1484 static void __exit nv_exit(void)
1486 pci_unregister_driver(&nv_pci_driver);
1489 module_init(nv_init);
1490 module_exit(nv_exit);
1491 module_param_named(adma, adma_enabled, bool, 0444);
1492 MODULE_PARM_DESC(adma, "Enable use of ADMA (Default: true)");