2 * sata_mv.c - Marvell SATA support
4 * Copyright 2008: Marvell Corporation, all rights reserved.
5 * Copyright 2005: EMC Corporation, all rights reserved.
6 * Copyright 2005 Red Hat, Inc. All rights reserved.
8 * Please ALWAYS copy linux-ide@vger.kernel.org on emails.
10 * This program is free software; you can redistribute it and/or modify
11 * it under the terms of the GNU General Public License as published by
12 * the Free Software Foundation; version 2 of the License.
14 * This program is distributed in the hope that it will be useful,
15 * but WITHOUT ANY WARRANTY; without even the implied warranty of
16 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17 * GNU General Public License for more details.
19 * You should have received a copy of the GNU General Public License
20 * along with this program; if not, write to the Free Software
21 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
28 * --> Errata workaround for NCQ device errors.
30 * --> More errata workarounds for PCI-X.
32 * --> Complete a full errata audit for all chipsets to identify others.
34 * --> ATAPI support (Marvell claims the 60xx/70xx chips can do it).
36 * --> Investigate problems with PCI Message Signalled Interrupts (MSI).
38 * --> Cache frequently-accessed registers in mv_port_priv to reduce overhead.
40 * --> Develop a low-power-consumption strategy, and implement it.
42 * --> [Experiment, low priority] Investigate interrupt coalescing.
43 * Quite often, especially with PCI Message Signalled Interrupts (MSI),
44 * the overhead reduced by interrupt mitigation is quite often not
45 * worth the latency cost.
47 * --> [Experiment, Marvell value added] Is it possible to use target
48 * mode to cross-connect two Linux boxes with Marvell cards? If so,
49 * creating LibATA target mode support would be very interesting.
51 * Target mode, for those without docs, is the ability to directly
52 * connect two SATA ports.
55 #include <linux/kernel.h>
56 #include <linux/module.h>
57 #include <linux/pci.h>
58 #include <linux/init.h>
59 #include <linux/blkdev.h>
60 #include <linux/delay.h>
61 #include <linux/interrupt.h>
62 #include <linux/dmapool.h>
63 #include <linux/dma-mapping.h>
64 #include <linux/device.h>
65 #include <linux/platform_device.h>
66 #include <linux/ata_platform.h>
67 #include <linux/mbus.h>
68 #include <linux/bitops.h>
69 #include <scsi/scsi_host.h>
70 #include <scsi/scsi_cmnd.h>
71 #include <scsi/scsi_device.h>
72 #include <linux/libata.h>
74 #define DRV_NAME "sata_mv"
75 #define DRV_VERSION "1.20"
78 /* BAR's are enumerated in terms of pci_resource_start() terms */
79 MV_PRIMARY_BAR = 0, /* offset 0x10: memory space */
80 MV_IO_BAR = 2, /* offset 0x18: IO space */
81 MV_MISC_BAR = 3, /* offset 0x1c: FLASH, NVRAM, SRAM */
83 MV_MAJOR_REG_AREA_SZ = 0x10000, /* 64KB */
84 MV_MINOR_REG_AREA_SZ = 0x2000, /* 8KB */
87 MV_IRQ_COAL_REG_BASE = 0x18000, /* 6xxx part only */
88 MV_IRQ_COAL_CAUSE = (MV_IRQ_COAL_REG_BASE + 0x08),
89 MV_IRQ_COAL_CAUSE_LO = (MV_IRQ_COAL_REG_BASE + 0x88),
90 MV_IRQ_COAL_CAUSE_HI = (MV_IRQ_COAL_REG_BASE + 0x8c),
91 MV_IRQ_COAL_THRESHOLD = (MV_IRQ_COAL_REG_BASE + 0xcc),
92 MV_IRQ_COAL_TIME_THRESHOLD = (MV_IRQ_COAL_REG_BASE + 0xd0),
94 MV_SATAHC0_REG_BASE = 0x20000,
95 MV_FLASH_CTL_OFS = 0x1046c,
96 MV_GPIO_PORT_CTL_OFS = 0x104f0,
97 MV_RESET_CFG_OFS = 0x180d8,
99 MV_PCI_REG_SZ = MV_MAJOR_REG_AREA_SZ,
100 MV_SATAHC_REG_SZ = MV_MAJOR_REG_AREA_SZ,
101 MV_SATAHC_ARBTR_REG_SZ = MV_MINOR_REG_AREA_SZ, /* arbiter */
102 MV_PORT_REG_SZ = MV_MINOR_REG_AREA_SZ,
105 MV_MAX_Q_DEPTH_MASK = MV_MAX_Q_DEPTH - 1,
107 /* CRQB needs alignment on a 1KB boundary. Size == 1KB
108 * CRPB needs alignment on a 256B boundary. Size == 256B
109 * ePRD (SG) entries need alignment on a 16B boundary. Size == 16B
111 MV_CRQB_Q_SZ = (32 * MV_MAX_Q_DEPTH),
112 MV_CRPB_Q_SZ = (8 * MV_MAX_Q_DEPTH),
114 MV_SG_TBL_SZ = (16 * MV_MAX_SG_CT),
116 /* Determine hc from 0-7 port: hc = port >> MV_PORT_HC_SHIFT */
117 MV_PORT_HC_SHIFT = 2,
118 MV_PORTS_PER_HC = (1 << MV_PORT_HC_SHIFT), /* 4 */
119 /* Determine hc port from 0-7 port: hardport = port & MV_PORT_MASK */
120 MV_PORT_MASK = (MV_PORTS_PER_HC - 1), /* 3 */
123 MV_FLAG_DUAL_HC = (1 << 30), /* two SATA Host Controllers */
124 MV_FLAG_IRQ_COALESCE = (1 << 29), /* IRQ coalescing capability */
125 /* SoC integrated controllers, no PCI interface */
126 MV_FLAG_SOC = (1 << 28),
128 MV_COMMON_FLAGS = ATA_FLAG_SATA | ATA_FLAG_NO_LEGACY |
129 ATA_FLAG_MMIO | ATA_FLAG_NO_ATAPI |
130 ATA_FLAG_PIO_POLLING,
132 MV_6XXX_FLAGS = MV_FLAG_IRQ_COALESCE,
134 MV_GENIIE_FLAGS = MV_COMMON_FLAGS | MV_6XXX_FLAGS |
135 ATA_FLAG_PMP | ATA_FLAG_ACPI_SATA |
136 ATA_FLAG_NCQ | ATA_FLAG_AN,
138 CRQB_FLAG_READ = (1 << 0),
140 CRQB_IOID_SHIFT = 6, /* CRQB Gen-II/IIE IO Id shift */
141 CRQB_PMP_SHIFT = 12, /* CRQB Gen-II/IIE PMP shift */
142 CRQB_HOSTQ_SHIFT = 17, /* CRQB Gen-II/IIE HostQueTag shift */
143 CRQB_CMD_ADDR_SHIFT = 8,
144 CRQB_CMD_CS = (0x2 << 11),
145 CRQB_CMD_LAST = (1 << 15),
147 CRPB_FLAG_STATUS_SHIFT = 8,
148 CRPB_IOID_SHIFT_6 = 5, /* CRPB Gen-II IO Id shift */
149 CRPB_IOID_SHIFT_7 = 7, /* CRPB Gen-IIE IO Id shift */
151 EPRD_FLAG_END_OF_TBL = (1 << 31),
153 /* PCI interface registers */
155 PCI_COMMAND_OFS = 0xc00,
156 PCI_COMMAND_MRDTRIG = (1 << 7), /* PCI Master Read Trigger */
158 PCI_MAIN_CMD_STS_OFS = 0xd30,
159 STOP_PCI_MASTER = (1 << 2),
160 PCI_MASTER_EMPTY = (1 << 3),
161 GLOB_SFT_RST = (1 << 4),
163 MV_PCI_MODE_OFS = 0xd00,
164 MV_PCI_MODE_MASK = 0x30,
166 MV_PCI_EXP_ROM_BAR_CTL = 0xd2c,
167 MV_PCI_DISC_TIMER = 0xd04,
168 MV_PCI_MSI_TRIGGER = 0xc38,
169 MV_PCI_SERR_MASK = 0xc28,
170 MV_PCI_XBAR_TMOUT_OFS = 0x1d04,
171 MV_PCI_ERR_LOW_ADDRESS = 0x1d40,
172 MV_PCI_ERR_HIGH_ADDRESS = 0x1d44,
173 MV_PCI_ERR_ATTRIBUTE = 0x1d48,
174 MV_PCI_ERR_COMMAND = 0x1d50,
176 PCI_IRQ_CAUSE_OFS = 0x1d58,
177 PCI_IRQ_MASK_OFS = 0x1d5c,
178 PCI_UNMASK_ALL_IRQS = 0x7fffff, /* bits 22-0 */
180 PCIE_IRQ_CAUSE_OFS = 0x1900,
181 PCIE_IRQ_MASK_OFS = 0x1910,
182 PCIE_UNMASK_ALL_IRQS = 0x40a, /* assorted bits */
184 /* Host Controller Main Interrupt Cause/Mask registers (1 per-chip) */
185 PCI_HC_MAIN_IRQ_CAUSE_OFS = 0x1d60,
186 PCI_HC_MAIN_IRQ_MASK_OFS = 0x1d64,
187 SOC_HC_MAIN_IRQ_CAUSE_OFS = 0x20020,
188 SOC_HC_MAIN_IRQ_MASK_OFS = 0x20024,
189 ERR_IRQ = (1 << 0), /* shift by port # */
190 DONE_IRQ = (1 << 1), /* shift by port # */
191 HC0_IRQ_PEND = 0x1ff, /* bits 0-8 = HC0's ports */
192 HC_SHIFT = 9, /* bits 9-17 = HC1's ports */
194 TRAN_LO_DONE = (1 << 19), /* 6xxx: IRQ coalescing */
195 TRAN_HI_DONE = (1 << 20), /* 6xxx: IRQ coalescing */
196 PORTS_0_3_COAL_DONE = (1 << 8),
197 PORTS_4_7_COAL_DONE = (1 << 17),
198 PORTS_0_7_COAL_DONE = (1 << 21), /* 6xxx: IRQ coalescing */
199 GPIO_INT = (1 << 22),
200 SELF_INT = (1 << 23),
201 TWSI_INT = (1 << 24),
202 HC_MAIN_RSVD = (0x7f << 25), /* bits 31-25 */
203 HC_MAIN_RSVD_5 = (0x1fff << 19), /* bits 31-19 */
204 HC_MAIN_RSVD_SOC = (0x3fffffb << 6), /* bits 31-9, 7-6 */
206 /* SATAHC registers */
209 HC_IRQ_CAUSE_OFS = 0x14,
210 DMA_IRQ = (1 << 0), /* shift by port # */
211 HC_COAL_IRQ = (1 << 4), /* IRQ coalescing */
212 DEV_IRQ = (1 << 8), /* shift by port # */
214 /* Shadow block registers */
216 SHD_CTL_AST_OFS = 0x20, /* ofs from SHD_BLK_OFS */
219 SATA_STATUS_OFS = 0x300, /* ctrl, err regs follow status */
220 SATA_ACTIVE_OFS = 0x350,
221 SATA_FIS_IRQ_CAUSE_OFS = 0x364,
222 SATA_FIS_IRQ_AN = (1 << 9), /* async notification */
225 LTMODE_BIT8 = (1 << 8), /* unknown, but necessary */
230 SATA_IFCTL_OFS = 0x344,
231 SATA_TESTCTL_OFS = 0x348,
232 SATA_IFSTAT_OFS = 0x34c,
233 VENDOR_UNIQUE_FIS_OFS = 0x35c,
236 FISCFG_WAIT_DEV_ERR = (1 << 8), /* wait for host on DevErr */
237 FISCFG_SINGLE_SYNC = (1 << 16), /* SYNC on DMA activation */
240 MV5_LTMODE_OFS = 0x30,
241 MV5_PHY_CTL_OFS = 0x0C,
242 SATA_INTERFACE_CFG_OFS = 0x050,
244 MV_M2_PREAMP_MASK = 0x7e0,
248 EDMA_CFG_Q_DEPTH = 0x1f, /* max device queue depth */
249 EDMA_CFG_NCQ = (1 << 5), /* for R/W FPDMA queued */
250 EDMA_CFG_NCQ_GO_ON_ERR = (1 << 14), /* continue on error */
251 EDMA_CFG_RD_BRST_EXT = (1 << 11), /* read burst 512B */
252 EDMA_CFG_WR_BUFF_LEN = (1 << 13), /* write buffer 512B */
253 EDMA_CFG_EDMA_FBS = (1 << 16), /* EDMA FIS-Based Switching */
254 EDMA_CFG_FBS = (1 << 26), /* FIS-Based Switching */
256 EDMA_ERR_IRQ_CAUSE_OFS = 0x8,
257 EDMA_ERR_IRQ_MASK_OFS = 0xc,
258 EDMA_ERR_D_PAR = (1 << 0), /* UDMA data parity err */
259 EDMA_ERR_PRD_PAR = (1 << 1), /* UDMA PRD parity err */
260 EDMA_ERR_DEV = (1 << 2), /* device error */
261 EDMA_ERR_DEV_DCON = (1 << 3), /* device disconnect */
262 EDMA_ERR_DEV_CON = (1 << 4), /* device connected */
263 EDMA_ERR_SERR = (1 << 5), /* SError bits [WBDST] raised */
264 EDMA_ERR_SELF_DIS = (1 << 7), /* Gen II/IIE self-disable */
265 EDMA_ERR_SELF_DIS_5 = (1 << 8), /* Gen I self-disable */
266 EDMA_ERR_BIST_ASYNC = (1 << 8), /* BIST FIS or Async Notify */
267 EDMA_ERR_TRANS_IRQ_7 = (1 << 8), /* Gen IIE transprt layer irq */
268 EDMA_ERR_CRQB_PAR = (1 << 9), /* CRQB parity error */
269 EDMA_ERR_CRPB_PAR = (1 << 10), /* CRPB parity error */
270 EDMA_ERR_INTRL_PAR = (1 << 11), /* internal parity error */
271 EDMA_ERR_IORDY = (1 << 12), /* IORdy timeout */
273 EDMA_ERR_LNK_CTRL_RX = (0xf << 13), /* link ctrl rx error */
274 EDMA_ERR_LNK_CTRL_RX_0 = (1 << 13), /* transient: CRC err */
275 EDMA_ERR_LNK_CTRL_RX_1 = (1 << 14), /* transient: FIFO err */
276 EDMA_ERR_LNK_CTRL_RX_2 = (1 << 15), /* fatal: caught SYNC */
277 EDMA_ERR_LNK_CTRL_RX_3 = (1 << 16), /* transient: FIS rx err */
279 EDMA_ERR_LNK_DATA_RX = (0xf << 17), /* link data rx error */
281 EDMA_ERR_LNK_CTRL_TX = (0x1f << 21), /* link ctrl tx error */
282 EDMA_ERR_LNK_CTRL_TX_0 = (1 << 21), /* transient: CRC err */
283 EDMA_ERR_LNK_CTRL_TX_1 = (1 << 22), /* transient: FIFO err */
284 EDMA_ERR_LNK_CTRL_TX_2 = (1 << 23), /* transient: caught SYNC */
285 EDMA_ERR_LNK_CTRL_TX_3 = (1 << 24), /* transient: caught DMAT */
286 EDMA_ERR_LNK_CTRL_TX_4 = (1 << 25), /* transient: FIS collision */
288 EDMA_ERR_LNK_DATA_TX = (0x1f << 26), /* link data tx error */
290 EDMA_ERR_TRANS_PROTO = (1 << 31), /* transport protocol error */
291 EDMA_ERR_OVERRUN_5 = (1 << 5),
292 EDMA_ERR_UNDERRUN_5 = (1 << 6),
294 EDMA_ERR_IRQ_TRANSIENT = EDMA_ERR_LNK_CTRL_RX_0 |
295 EDMA_ERR_LNK_CTRL_RX_1 |
296 EDMA_ERR_LNK_CTRL_RX_3 |
297 EDMA_ERR_LNK_CTRL_TX,
299 EDMA_EH_FREEZE = EDMA_ERR_D_PAR |
309 EDMA_ERR_LNK_CTRL_RX_2 |
310 EDMA_ERR_LNK_DATA_RX |
311 EDMA_ERR_LNK_DATA_TX |
312 EDMA_ERR_TRANS_PROTO,
314 EDMA_EH_FREEZE_5 = EDMA_ERR_D_PAR |
319 EDMA_ERR_UNDERRUN_5 |
320 EDMA_ERR_SELF_DIS_5 |
326 EDMA_REQ_Q_BASE_HI_OFS = 0x10,
327 EDMA_REQ_Q_IN_PTR_OFS = 0x14, /* also contains BASE_LO */
329 EDMA_REQ_Q_OUT_PTR_OFS = 0x18,
330 EDMA_REQ_Q_PTR_SHIFT = 5,
332 EDMA_RSP_Q_BASE_HI_OFS = 0x1c,
333 EDMA_RSP_Q_IN_PTR_OFS = 0x20,
334 EDMA_RSP_Q_OUT_PTR_OFS = 0x24, /* also contains BASE_LO */
335 EDMA_RSP_Q_PTR_SHIFT = 3,
337 EDMA_CMD_OFS = 0x28, /* EDMA command register */
338 EDMA_EN = (1 << 0), /* enable EDMA */
339 EDMA_DS = (1 << 1), /* disable EDMA; self-negated */
340 EDMA_RESET = (1 << 2), /* reset eng/trans/link/phy */
342 EDMA_STATUS_OFS = 0x30, /* EDMA engine status */
343 EDMA_STATUS_CACHE_EMPTY = (1 << 6), /* GenIIe command cache empty */
344 EDMA_STATUS_IDLE = (1 << 7), /* GenIIe EDMA enabled/idle */
346 EDMA_IORDY_TMOUT_OFS = 0x34,
347 EDMA_ARB_CFG_OFS = 0x38,
349 EDMA_HALTCOND_OFS = 0x60, /* GenIIe halt conditions */
351 GEN_II_NCQ_MAX_SECTORS = 256, /* max sects/io on Gen2 w/NCQ */
353 /* Host private flags (hp_flags) */
354 MV_HP_FLAG_MSI = (1 << 0),
355 MV_HP_ERRATA_50XXB0 = (1 << 1),
356 MV_HP_ERRATA_50XXB2 = (1 << 2),
357 MV_HP_ERRATA_60X1B2 = (1 << 3),
358 MV_HP_ERRATA_60X1C0 = (1 << 4),
359 MV_HP_ERRATA_XX42A0 = (1 << 5),
360 MV_HP_GEN_I = (1 << 6), /* Generation I: 50xx */
361 MV_HP_GEN_II = (1 << 7), /* Generation II: 60xx */
362 MV_HP_GEN_IIE = (1 << 8), /* Generation IIE: 6042/7042 */
363 MV_HP_PCIE = (1 << 9), /* PCIe bus/regs: 7042 */
364 MV_HP_CUT_THROUGH = (1 << 10), /* can use EDMA cut-through */
366 /* Port private flags (pp_flags) */
367 MV_PP_FLAG_EDMA_EN = (1 << 0), /* is EDMA engine enabled? */
368 MV_PP_FLAG_NCQ_EN = (1 << 1), /* is EDMA set up for NCQ? */
369 MV_PP_FLAG_FBS_EN = (1 << 2), /* is EDMA set up for FBS? */
370 MV_PP_FLAG_DELAYED_EH = (1 << 3), /* delayed dev err handling */
373 #define IS_GEN_I(hpriv) ((hpriv)->hp_flags & MV_HP_GEN_I)
374 #define IS_GEN_II(hpriv) ((hpriv)->hp_flags & MV_HP_GEN_II)
375 #define IS_GEN_IIE(hpriv) ((hpriv)->hp_flags & MV_HP_GEN_IIE)
376 #define IS_PCIE(hpriv) ((hpriv)->hp_flags & MV_HP_PCIE)
377 #define HAS_PCI(host) (!((host)->ports[0]->flags & MV_FLAG_SOC))
379 #define WINDOW_CTRL(i) (0x20030 + ((i) << 4))
380 #define WINDOW_BASE(i) (0x20034 + ((i) << 4))
383 /* DMA boundary 0xffff is required by the s/g splitting
384 * we need on /length/ in mv_fill-sg().
386 MV_DMA_BOUNDARY = 0xffffU,
388 /* mask of register bits containing lower 32 bits
389 * of EDMA request queue DMA address
391 EDMA_REQ_Q_BASE_LO_MASK = 0xfffffc00U,
393 /* ditto, for response queue */
394 EDMA_RSP_Q_BASE_LO_MASK = 0xffffff00U,
408 /* Command ReQuest Block: 32B */
424 /* Command ResPonse Block: 8B */
431 /* EDMA Physical Region Descriptor (ePRD); A.K.A. SG */
439 struct mv_port_priv {
440 struct mv_crqb *crqb;
442 struct mv_crpb *crpb;
444 struct mv_sg *sg_tbl[MV_MAX_Q_DEPTH];
445 dma_addr_t sg_tbl_dma[MV_MAX_Q_DEPTH];
447 unsigned int req_idx;
448 unsigned int resp_idx;
451 unsigned int delayed_eh_pmp_map;
454 struct mv_port_signal {
459 struct mv_host_priv {
461 struct mv_port_signal signal[8];
462 const struct mv_hw_ops *ops;
465 void __iomem *main_irq_cause_addr;
466 void __iomem *main_irq_mask_addr;
471 * These consistent DMA memory pools give us guaranteed
472 * alignment for hardware-accessed data structures,
473 * and less memory waste in accomplishing the alignment.
475 struct dma_pool *crqb_pool;
476 struct dma_pool *crpb_pool;
477 struct dma_pool *sg_tbl_pool;
481 void (*phy_errata)(struct mv_host_priv *hpriv, void __iomem *mmio,
483 void (*enable_leds)(struct mv_host_priv *hpriv, void __iomem *mmio);
484 void (*read_preamp)(struct mv_host_priv *hpriv, int idx,
486 int (*reset_hc)(struct mv_host_priv *hpriv, void __iomem *mmio,
488 void (*reset_flash)(struct mv_host_priv *hpriv, void __iomem *mmio);
489 void (*reset_bus)(struct ata_host *host, void __iomem *mmio);
492 static int mv_scr_read(struct ata_port *ap, unsigned int sc_reg_in, u32 *val);
493 static int mv_scr_write(struct ata_port *ap, unsigned int sc_reg_in, u32 val);
494 static int mv5_scr_read(struct ata_port *ap, unsigned int sc_reg_in, u32 *val);
495 static int mv5_scr_write(struct ata_port *ap, unsigned int sc_reg_in, u32 val);
496 static int mv_port_start(struct ata_port *ap);
497 static void mv_port_stop(struct ata_port *ap);
498 static int mv_qc_defer(struct ata_queued_cmd *qc);
499 static void mv_qc_prep(struct ata_queued_cmd *qc);
500 static void mv_qc_prep_iie(struct ata_queued_cmd *qc);
501 static unsigned int mv_qc_issue(struct ata_queued_cmd *qc);
502 static int mv_hardreset(struct ata_link *link, unsigned int *class,
503 unsigned long deadline);
504 static void mv_eh_freeze(struct ata_port *ap);
505 static void mv_eh_thaw(struct ata_port *ap);
506 static void mv6_dev_config(struct ata_device *dev);
508 static void mv5_phy_errata(struct mv_host_priv *hpriv, void __iomem *mmio,
510 static void mv5_enable_leds(struct mv_host_priv *hpriv, void __iomem *mmio);
511 static void mv5_read_preamp(struct mv_host_priv *hpriv, int idx,
513 static int mv5_reset_hc(struct mv_host_priv *hpriv, void __iomem *mmio,
515 static void mv5_reset_flash(struct mv_host_priv *hpriv, void __iomem *mmio);
516 static void mv5_reset_bus(struct ata_host *host, void __iomem *mmio);
518 static void mv6_phy_errata(struct mv_host_priv *hpriv, void __iomem *mmio,
520 static void mv6_enable_leds(struct mv_host_priv *hpriv, void __iomem *mmio);
521 static void mv6_read_preamp(struct mv_host_priv *hpriv, int idx,
523 static int mv6_reset_hc(struct mv_host_priv *hpriv, void __iomem *mmio,
525 static void mv6_reset_flash(struct mv_host_priv *hpriv, void __iomem *mmio);
526 static void mv_soc_enable_leds(struct mv_host_priv *hpriv,
528 static void mv_soc_read_preamp(struct mv_host_priv *hpriv, int idx,
530 static int mv_soc_reset_hc(struct mv_host_priv *hpriv,
531 void __iomem *mmio, unsigned int n_hc);
532 static void mv_soc_reset_flash(struct mv_host_priv *hpriv,
534 static void mv_soc_reset_bus(struct ata_host *host, void __iomem *mmio);
535 static void mv_reset_pci_bus(struct ata_host *host, void __iomem *mmio);
536 static void mv_reset_channel(struct mv_host_priv *hpriv, void __iomem *mmio,
537 unsigned int port_no);
538 static int mv_stop_edma(struct ata_port *ap);
539 static int mv_stop_edma_engine(void __iomem *port_mmio);
540 static void mv_edma_cfg(struct ata_port *ap, int want_ncq);
542 static void mv_pmp_select(struct ata_port *ap, int pmp);
543 static int mv_pmp_hardreset(struct ata_link *link, unsigned int *class,
544 unsigned long deadline);
545 static int mv_softreset(struct ata_link *link, unsigned int *class,
546 unsigned long deadline);
547 static void mv_pmp_error_handler(struct ata_port *ap);
548 static void mv_process_crpb_entries(struct ata_port *ap,
549 struct mv_port_priv *pp);
551 /* .sg_tablesize is (MV_MAX_SG_CT / 2) in the structures below
552 * because we have to allow room for worst case splitting of
553 * PRDs for 64K boundaries in mv_fill_sg().
555 static struct scsi_host_template mv5_sht = {
556 ATA_BASE_SHT(DRV_NAME),
557 .sg_tablesize = MV_MAX_SG_CT / 2,
558 .dma_boundary = MV_DMA_BOUNDARY,
561 static struct scsi_host_template mv6_sht = {
562 ATA_NCQ_SHT(DRV_NAME),
563 .can_queue = MV_MAX_Q_DEPTH - 1,
564 .sg_tablesize = MV_MAX_SG_CT / 2,
565 .dma_boundary = MV_DMA_BOUNDARY,
568 static struct ata_port_operations mv5_ops = {
569 .inherits = &ata_sff_port_ops,
571 .qc_defer = mv_qc_defer,
572 .qc_prep = mv_qc_prep,
573 .qc_issue = mv_qc_issue,
575 .freeze = mv_eh_freeze,
577 .hardreset = mv_hardreset,
578 .error_handler = ata_std_error_handler, /* avoid SFF EH */
579 .post_internal_cmd = ATA_OP_NULL,
581 .scr_read = mv5_scr_read,
582 .scr_write = mv5_scr_write,
584 .port_start = mv_port_start,
585 .port_stop = mv_port_stop,
588 static struct ata_port_operations mv6_ops = {
589 .inherits = &mv5_ops,
590 .dev_config = mv6_dev_config,
591 .scr_read = mv_scr_read,
592 .scr_write = mv_scr_write,
594 .pmp_hardreset = mv_pmp_hardreset,
595 .pmp_softreset = mv_softreset,
596 .softreset = mv_softreset,
597 .error_handler = mv_pmp_error_handler,
600 static struct ata_port_operations mv_iie_ops = {
601 .inherits = &mv6_ops,
602 .dev_config = ATA_OP_NULL,
603 .qc_prep = mv_qc_prep_iie,
606 static const struct ata_port_info mv_port_info[] = {
608 .flags = MV_COMMON_FLAGS,
609 .pio_mask = 0x1f, /* pio0-4 */
610 .udma_mask = ATA_UDMA6,
611 .port_ops = &mv5_ops,
614 .flags = MV_COMMON_FLAGS | MV_FLAG_DUAL_HC,
615 .pio_mask = 0x1f, /* pio0-4 */
616 .udma_mask = ATA_UDMA6,
617 .port_ops = &mv5_ops,
620 .flags = MV_COMMON_FLAGS | MV_FLAG_DUAL_HC,
621 .pio_mask = 0x1f, /* pio0-4 */
622 .udma_mask = ATA_UDMA6,
623 .port_ops = &mv5_ops,
626 .flags = MV_COMMON_FLAGS | MV_6XXX_FLAGS |
627 ATA_FLAG_PMP | ATA_FLAG_ACPI_SATA |
629 .pio_mask = 0x1f, /* pio0-4 */
630 .udma_mask = ATA_UDMA6,
631 .port_ops = &mv6_ops,
634 .flags = MV_COMMON_FLAGS | MV_6XXX_FLAGS |
635 ATA_FLAG_PMP | ATA_FLAG_ACPI_SATA |
636 ATA_FLAG_NCQ | MV_FLAG_DUAL_HC,
637 .pio_mask = 0x1f, /* pio0-4 */
638 .udma_mask = ATA_UDMA6,
639 .port_ops = &mv6_ops,
642 .flags = MV_GENIIE_FLAGS,
643 .pio_mask = 0x1f, /* pio0-4 */
644 .udma_mask = ATA_UDMA6,
645 .port_ops = &mv_iie_ops,
648 .flags = MV_GENIIE_FLAGS,
649 .pio_mask = 0x1f, /* pio0-4 */
650 .udma_mask = ATA_UDMA6,
651 .port_ops = &mv_iie_ops,
654 .flags = MV_GENIIE_FLAGS | MV_FLAG_SOC,
655 .pio_mask = 0x1f, /* pio0-4 */
656 .udma_mask = ATA_UDMA6,
657 .port_ops = &mv_iie_ops,
661 static const struct pci_device_id mv_pci_tbl[] = {
662 { PCI_VDEVICE(MARVELL, 0x5040), chip_504x },
663 { PCI_VDEVICE(MARVELL, 0x5041), chip_504x },
664 { PCI_VDEVICE(MARVELL, 0x5080), chip_5080 },
665 { PCI_VDEVICE(MARVELL, 0x5081), chip_508x },
666 /* RocketRAID 1740/174x have different identifiers */
667 { PCI_VDEVICE(TTI, 0x1740), chip_508x },
668 { PCI_VDEVICE(TTI, 0x1742), chip_508x },
670 { PCI_VDEVICE(MARVELL, 0x6040), chip_604x },
671 { PCI_VDEVICE(MARVELL, 0x6041), chip_604x },
672 { PCI_VDEVICE(MARVELL, 0x6042), chip_6042 },
673 { PCI_VDEVICE(MARVELL, 0x6080), chip_608x },
674 { PCI_VDEVICE(MARVELL, 0x6081), chip_608x },
676 { PCI_VDEVICE(ADAPTEC2, 0x0241), chip_604x },
679 { PCI_VDEVICE(ADAPTEC2, 0x0243), chip_7042 },
681 /* Marvell 7042 support */
682 { PCI_VDEVICE(MARVELL, 0x7042), chip_7042 },
684 /* Highpoint RocketRAID PCIe series */
685 { PCI_VDEVICE(TTI, 0x2300), chip_7042 },
686 { PCI_VDEVICE(TTI, 0x2310), chip_7042 },
688 { } /* terminate list */
691 static const struct mv_hw_ops mv5xxx_ops = {
692 .phy_errata = mv5_phy_errata,
693 .enable_leds = mv5_enable_leds,
694 .read_preamp = mv5_read_preamp,
695 .reset_hc = mv5_reset_hc,
696 .reset_flash = mv5_reset_flash,
697 .reset_bus = mv5_reset_bus,
700 static const struct mv_hw_ops mv6xxx_ops = {
701 .phy_errata = mv6_phy_errata,
702 .enable_leds = mv6_enable_leds,
703 .read_preamp = mv6_read_preamp,
704 .reset_hc = mv6_reset_hc,
705 .reset_flash = mv6_reset_flash,
706 .reset_bus = mv_reset_pci_bus,
709 static const struct mv_hw_ops mv_soc_ops = {
710 .phy_errata = mv6_phy_errata,
711 .enable_leds = mv_soc_enable_leds,
712 .read_preamp = mv_soc_read_preamp,
713 .reset_hc = mv_soc_reset_hc,
714 .reset_flash = mv_soc_reset_flash,
715 .reset_bus = mv_soc_reset_bus,
722 static inline void writelfl(unsigned long data, void __iomem *addr)
725 (void) readl(addr); /* flush to avoid PCI posted write */
728 static inline unsigned int mv_hc_from_port(unsigned int port)
730 return port >> MV_PORT_HC_SHIFT;
733 static inline unsigned int mv_hardport_from_port(unsigned int port)
735 return port & MV_PORT_MASK;
739 * Consolidate some rather tricky bit shift calculations.
740 * This is hot-path stuff, so not a function.
741 * Simple code, with two return values, so macro rather than inline.
743 * port is the sole input, in range 0..7.
744 * shift is one output, for use with main_irq_cause / main_irq_mask registers.
745 * hardport is the other output, in range 0..3.
747 * Note that port and hardport may be the same variable in some cases.
749 #define MV_PORT_TO_SHIFT_AND_HARDPORT(port, shift, hardport) \
751 shift = mv_hc_from_port(port) * HC_SHIFT; \
752 hardport = mv_hardport_from_port(port); \
753 shift += hardport * 2; \
756 static inline void __iomem *mv_hc_base(void __iomem *base, unsigned int hc)
758 return (base + MV_SATAHC0_REG_BASE + (hc * MV_SATAHC_REG_SZ));
761 static inline void __iomem *mv_hc_base_from_port(void __iomem *base,
764 return mv_hc_base(base, mv_hc_from_port(port));
767 static inline void __iomem *mv_port_base(void __iomem *base, unsigned int port)
769 return mv_hc_base_from_port(base, port) +
770 MV_SATAHC_ARBTR_REG_SZ +
771 (mv_hardport_from_port(port) * MV_PORT_REG_SZ);
774 static void __iomem *mv5_phy_base(void __iomem *mmio, unsigned int port)
776 void __iomem *hc_mmio = mv_hc_base_from_port(mmio, port);
777 unsigned long ofs = (mv_hardport_from_port(port) + 1) * 0x100UL;
779 return hc_mmio + ofs;
782 static inline void __iomem *mv_host_base(struct ata_host *host)
784 struct mv_host_priv *hpriv = host->private_data;
788 static inline void __iomem *mv_ap_base(struct ata_port *ap)
790 return mv_port_base(mv_host_base(ap->host), ap->port_no);
793 static inline int mv_get_hc_count(unsigned long port_flags)
795 return ((port_flags & MV_FLAG_DUAL_HC) ? 2 : 1);
798 static void mv_set_edma_ptrs(void __iomem *port_mmio,
799 struct mv_host_priv *hpriv,
800 struct mv_port_priv *pp)
805 * initialize request queue
807 pp->req_idx &= MV_MAX_Q_DEPTH_MASK; /* paranoia */
808 index = pp->req_idx << EDMA_REQ_Q_PTR_SHIFT;
810 WARN_ON(pp->crqb_dma & 0x3ff);
811 writel((pp->crqb_dma >> 16) >> 16, port_mmio + EDMA_REQ_Q_BASE_HI_OFS);
812 writelfl((pp->crqb_dma & EDMA_REQ_Q_BASE_LO_MASK) | index,
813 port_mmio + EDMA_REQ_Q_IN_PTR_OFS);
815 if (hpriv->hp_flags & MV_HP_ERRATA_XX42A0)
816 writelfl((pp->crqb_dma & 0xffffffff) | index,
817 port_mmio + EDMA_REQ_Q_OUT_PTR_OFS);
819 writelfl(index, port_mmio + EDMA_REQ_Q_OUT_PTR_OFS);
822 * initialize response queue
824 pp->resp_idx &= MV_MAX_Q_DEPTH_MASK; /* paranoia */
825 index = pp->resp_idx << EDMA_RSP_Q_PTR_SHIFT;
827 WARN_ON(pp->crpb_dma & 0xff);
828 writel((pp->crpb_dma >> 16) >> 16, port_mmio + EDMA_RSP_Q_BASE_HI_OFS);
830 if (hpriv->hp_flags & MV_HP_ERRATA_XX42A0)
831 writelfl((pp->crpb_dma & 0xffffffff) | index,
832 port_mmio + EDMA_RSP_Q_IN_PTR_OFS);
834 writelfl(index, port_mmio + EDMA_RSP_Q_IN_PTR_OFS);
836 writelfl((pp->crpb_dma & EDMA_RSP_Q_BASE_LO_MASK) | index,
837 port_mmio + EDMA_RSP_Q_OUT_PTR_OFS);
840 static void mv_set_main_irq_mask(struct ata_host *host,
841 u32 disable_bits, u32 enable_bits)
843 struct mv_host_priv *hpriv = host->private_data;
844 u32 old_mask, new_mask;
846 old_mask = readl(hpriv->main_irq_mask_addr);
847 new_mask = (old_mask & ~disable_bits) | enable_bits;
848 if (new_mask != old_mask)
849 writelfl(new_mask, hpriv->main_irq_mask_addr);
852 static void mv_enable_port_irqs(struct ata_port *ap,
853 unsigned int port_bits)
855 unsigned int shift, hardport, port = ap->port_no;
856 u32 disable_bits, enable_bits;
858 MV_PORT_TO_SHIFT_AND_HARDPORT(port, shift, hardport);
860 disable_bits = (DONE_IRQ | ERR_IRQ) << shift;
861 enable_bits = port_bits << shift;
862 mv_set_main_irq_mask(ap->host, disable_bits, enable_bits);
866 * mv_start_dma - Enable eDMA engine
867 * @base: port base address
868 * @pp: port private data
870 * Verify the local cache of the eDMA state is accurate with a
874 * Inherited from caller.
876 static void mv_start_dma(struct ata_port *ap, void __iomem *port_mmio,
877 struct mv_port_priv *pp, u8 protocol)
879 int want_ncq = (protocol == ATA_PROT_NCQ);
881 if (pp->pp_flags & MV_PP_FLAG_EDMA_EN) {
882 int using_ncq = ((pp->pp_flags & MV_PP_FLAG_NCQ_EN) != 0);
883 if (want_ncq != using_ncq)
886 if (!(pp->pp_flags & MV_PP_FLAG_EDMA_EN)) {
887 struct mv_host_priv *hpriv = ap->host->private_data;
888 int hardport = mv_hardport_from_port(ap->port_no);
889 void __iomem *hc_mmio = mv_hc_base_from_port(
890 mv_host_base(ap->host), hardport);
891 u32 hc_irq_cause, ipending;
893 /* clear EDMA event indicators, if any */
894 writelfl(0, port_mmio + EDMA_ERR_IRQ_CAUSE_OFS);
896 /* clear EDMA interrupt indicator, if any */
897 hc_irq_cause = readl(hc_mmio + HC_IRQ_CAUSE_OFS);
898 ipending = (DEV_IRQ | DMA_IRQ) << hardport;
899 if (hc_irq_cause & ipending) {
900 writelfl(hc_irq_cause & ~ipending,
901 hc_mmio + HC_IRQ_CAUSE_OFS);
904 mv_edma_cfg(ap, want_ncq);
906 /* clear FIS IRQ Cause */
907 if (IS_GEN_IIE(hpriv))
908 writelfl(0, port_mmio + SATA_FIS_IRQ_CAUSE_OFS);
910 mv_set_edma_ptrs(port_mmio, hpriv, pp);
912 writelfl(EDMA_EN, port_mmio + EDMA_CMD_OFS);
913 pp->pp_flags |= MV_PP_FLAG_EDMA_EN;
917 static void mv_wait_for_edma_empty_idle(struct ata_port *ap)
919 void __iomem *port_mmio = mv_ap_base(ap);
920 const u32 empty_idle = (EDMA_STATUS_CACHE_EMPTY | EDMA_STATUS_IDLE);
921 const int per_loop = 5, timeout = (15 * 1000 / per_loop);
925 * Wait for the EDMA engine to finish transactions in progress.
926 * No idea what a good "timeout" value might be, but measurements
927 * indicate that it often requires hundreds of microseconds
928 * with two drives in-use. So we use the 15msec value above
929 * as a rough guess at what even more drives might require.
931 for (i = 0; i < timeout; ++i) {
932 u32 edma_stat = readl(port_mmio + EDMA_STATUS_OFS);
933 if ((edma_stat & empty_idle) == empty_idle)
937 /* ata_port_printk(ap, KERN_INFO, "%s: %u+ usecs\n", __func__, i); */
941 * mv_stop_edma_engine - Disable eDMA engine
942 * @port_mmio: io base address
945 * Inherited from caller.
947 static int mv_stop_edma_engine(void __iomem *port_mmio)
951 /* Disable eDMA. The disable bit auto clears. */
952 writelfl(EDMA_DS, port_mmio + EDMA_CMD_OFS);
954 /* Wait for the chip to confirm eDMA is off. */
955 for (i = 10000; i > 0; i--) {
956 u32 reg = readl(port_mmio + EDMA_CMD_OFS);
957 if (!(reg & EDMA_EN))
964 static int mv_stop_edma(struct ata_port *ap)
966 void __iomem *port_mmio = mv_ap_base(ap);
967 struct mv_port_priv *pp = ap->private_data;
969 if (!(pp->pp_flags & MV_PP_FLAG_EDMA_EN))
971 pp->pp_flags &= ~MV_PP_FLAG_EDMA_EN;
972 mv_wait_for_edma_empty_idle(ap);
973 if (mv_stop_edma_engine(port_mmio)) {
974 ata_port_printk(ap, KERN_ERR, "Unable to stop eDMA\n");
981 static void mv_dump_mem(void __iomem *start, unsigned bytes)
984 for (b = 0; b < bytes; ) {
985 DPRINTK("%p: ", start + b);
986 for (w = 0; b < bytes && w < 4; w++) {
987 printk("%08x ", readl(start + b));
995 static void mv_dump_pci_cfg(struct pci_dev *pdev, unsigned bytes)
1000 for (b = 0; b < bytes; ) {
1001 DPRINTK("%02x: ", b);
1002 for (w = 0; b < bytes && w < 4; w++) {
1003 (void) pci_read_config_dword(pdev, b, &dw);
1004 printk("%08x ", dw);
1011 static void mv_dump_all_regs(void __iomem *mmio_base, int port,
1012 struct pci_dev *pdev)
1015 void __iomem *hc_base = mv_hc_base(mmio_base,
1016 port >> MV_PORT_HC_SHIFT);
1017 void __iomem *port_base;
1018 int start_port, num_ports, p, start_hc, num_hcs, hc;
1021 start_hc = start_port = 0;
1022 num_ports = 8; /* shld be benign for 4 port devs */
1025 start_hc = port >> MV_PORT_HC_SHIFT;
1027 num_ports = num_hcs = 1;
1029 DPRINTK("All registers for port(s) %u-%u:\n", start_port,
1030 num_ports > 1 ? num_ports - 1 : start_port);
1033 DPRINTK("PCI config space regs:\n");
1034 mv_dump_pci_cfg(pdev, 0x68);
1036 DPRINTK("PCI regs:\n");
1037 mv_dump_mem(mmio_base+0xc00, 0x3c);
1038 mv_dump_mem(mmio_base+0xd00, 0x34);
1039 mv_dump_mem(mmio_base+0xf00, 0x4);
1040 mv_dump_mem(mmio_base+0x1d00, 0x6c);
1041 for (hc = start_hc; hc < start_hc + num_hcs; hc++) {
1042 hc_base = mv_hc_base(mmio_base, hc);
1043 DPRINTK("HC regs (HC %i):\n", hc);
1044 mv_dump_mem(hc_base, 0x1c);
1046 for (p = start_port; p < start_port + num_ports; p++) {
1047 port_base = mv_port_base(mmio_base, p);
1048 DPRINTK("EDMA regs (port %i):\n", p);
1049 mv_dump_mem(port_base, 0x54);
1050 DPRINTK("SATA regs (port %i):\n", p);
1051 mv_dump_mem(port_base+0x300, 0x60);
1056 static unsigned int mv_scr_offset(unsigned int sc_reg_in)
1060 switch (sc_reg_in) {
1064 ofs = SATA_STATUS_OFS + (sc_reg_in * sizeof(u32));
1067 ofs = SATA_ACTIVE_OFS; /* active is not with the others */
1076 static int mv_scr_read(struct ata_port *ap, unsigned int sc_reg_in, u32 *val)
1078 unsigned int ofs = mv_scr_offset(sc_reg_in);
1080 if (ofs != 0xffffffffU) {
1081 *val = readl(mv_ap_base(ap) + ofs);
1087 static int mv_scr_write(struct ata_port *ap, unsigned int sc_reg_in, u32 val)
1089 unsigned int ofs = mv_scr_offset(sc_reg_in);
1091 if (ofs != 0xffffffffU) {
1092 writelfl(val, mv_ap_base(ap) + ofs);
1098 static void mv6_dev_config(struct ata_device *adev)
1101 * Deal with Gen-II ("mv6") hardware quirks/restrictions:
1103 * Gen-II does not support NCQ over a port multiplier
1104 * (no FIS-based switching).
1106 * We don't have hob_nsect when doing NCQ commands on Gen-II.
1107 * See mv_qc_prep() for more info.
1109 if (adev->flags & ATA_DFLAG_NCQ) {
1110 if (sata_pmp_attached(adev->link->ap)) {
1111 adev->flags &= ~ATA_DFLAG_NCQ;
1112 ata_dev_printk(adev, KERN_INFO,
1113 "NCQ disabled for command-based switching\n");
1114 } else if (adev->max_sectors > GEN_II_NCQ_MAX_SECTORS) {
1115 adev->max_sectors = GEN_II_NCQ_MAX_SECTORS;
1116 ata_dev_printk(adev, KERN_INFO,
1117 "max_sectors limited to %u for NCQ\n",
1123 static int mv_qc_defer(struct ata_queued_cmd *qc)
1125 struct ata_link *link = qc->dev->link;
1126 struct ata_port *ap = link->ap;
1127 struct mv_port_priv *pp = ap->private_data;
1130 * Don't allow new commands if we're in a delayed EH state
1131 * for NCQ and/or FIS-based switching.
1133 if (pp->pp_flags & MV_PP_FLAG_DELAYED_EH)
1134 return ATA_DEFER_PORT;
1136 * If the port is completely idle, then allow the new qc.
1138 if (ap->nr_active_links == 0)
1141 if (pp->pp_flags & MV_PP_FLAG_EDMA_EN) {
1143 * The port is operating in host queuing mode (EDMA).
1144 * It can accomodate a new qc if the qc protocol
1145 * is compatible with the current host queue mode.
1147 if (pp->pp_flags & MV_PP_FLAG_NCQ_EN) {
1149 * The host queue (EDMA) is in NCQ mode.
1150 * If the new qc is also an NCQ command,
1151 * then allow the new qc.
1153 if (qc->tf.protocol == ATA_PROT_NCQ)
1157 * The host queue (EDMA) is in non-NCQ, DMA mode.
1158 * If the new qc is also a non-NCQ, DMA command,
1159 * then allow the new qc.
1161 if (qc->tf.protocol == ATA_PROT_DMA)
1165 return ATA_DEFER_PORT;
1168 static void mv_config_fbs(void __iomem *port_mmio, int want_ncq, int want_fbs)
1170 u32 new_fiscfg, old_fiscfg;
1171 u32 new_ltmode, old_ltmode;
1172 u32 new_haltcond, old_haltcond;
1174 old_fiscfg = readl(port_mmio + FISCFG_OFS);
1175 old_ltmode = readl(port_mmio + LTMODE_OFS);
1176 old_haltcond = readl(port_mmio + EDMA_HALTCOND_OFS);
1178 new_fiscfg = old_fiscfg & ~(FISCFG_SINGLE_SYNC | FISCFG_WAIT_DEV_ERR);
1179 new_ltmode = old_ltmode & ~LTMODE_BIT8;
1180 new_haltcond = old_haltcond | EDMA_ERR_DEV;
1183 new_fiscfg = old_fiscfg | FISCFG_SINGLE_SYNC;
1184 new_ltmode = old_ltmode | LTMODE_BIT8;
1186 new_haltcond &= ~EDMA_ERR_DEV;
1188 new_fiscfg |= FISCFG_WAIT_DEV_ERR;
1191 if (new_fiscfg != old_fiscfg)
1192 writelfl(new_fiscfg, port_mmio + FISCFG_OFS);
1193 if (new_ltmode != old_ltmode)
1194 writelfl(new_ltmode, port_mmio + LTMODE_OFS);
1195 if (new_haltcond != old_haltcond)
1196 writelfl(new_haltcond, port_mmio + EDMA_HALTCOND_OFS);
1199 static void mv_60x1_errata_sata25(struct ata_port *ap, int want_ncq)
1201 struct mv_host_priv *hpriv = ap->host->private_data;
1204 /* workaround for 88SX60x1 FEr SATA#25 (part 1) */
1205 old = readl(hpriv->base + MV_GPIO_PORT_CTL_OFS);
1207 new = old | (1 << 22);
1209 new = old & ~(1 << 22);
1211 writel(new, hpriv->base + MV_GPIO_PORT_CTL_OFS);
1214 static void mv_edma_cfg(struct ata_port *ap, int want_ncq)
1217 struct mv_port_priv *pp = ap->private_data;
1218 struct mv_host_priv *hpriv = ap->host->private_data;
1219 void __iomem *port_mmio = mv_ap_base(ap);
1221 /* set up non-NCQ EDMA configuration */
1222 cfg = EDMA_CFG_Q_DEPTH; /* always 0x1f for *all* chips */
1223 pp->pp_flags &= ~MV_PP_FLAG_FBS_EN;
1225 if (IS_GEN_I(hpriv))
1226 cfg |= (1 << 8); /* enab config burst size mask */
1228 else if (IS_GEN_II(hpriv)) {
1229 cfg |= EDMA_CFG_RD_BRST_EXT | EDMA_CFG_WR_BUFF_LEN;
1230 mv_60x1_errata_sata25(ap, want_ncq);
1232 } else if (IS_GEN_IIE(hpriv)) {
1233 int want_fbs = sata_pmp_attached(ap);
1235 * Possible future enhancement:
1237 * The chip can use FBS with non-NCQ, if we allow it,
1238 * But first we need to have the error handling in place
1239 * for this mode (datasheet section 7.3.15.4.2.3).
1240 * So disallow non-NCQ FBS for now.
1242 want_fbs &= want_ncq;
1244 mv_config_fbs(port_mmio, want_ncq, want_fbs);
1247 pp->pp_flags |= MV_PP_FLAG_FBS_EN;
1248 cfg |= EDMA_CFG_EDMA_FBS; /* FIS-based switching */
1251 cfg |= (1 << 23); /* do not mask PM field in rx'd FIS */
1252 cfg |= (1 << 22); /* enab 4-entry host queue cache */
1253 if (HAS_PCI(ap->host))
1254 cfg |= (1 << 18); /* enab early completion */
1255 if (hpriv->hp_flags & MV_HP_CUT_THROUGH)
1256 cfg |= (1 << 17); /* enab cut-thru (dis stor&forwrd) */
1260 cfg |= EDMA_CFG_NCQ;
1261 pp->pp_flags |= MV_PP_FLAG_NCQ_EN;
1263 pp->pp_flags &= ~MV_PP_FLAG_NCQ_EN;
1265 writelfl(cfg, port_mmio + EDMA_CFG_OFS);
1268 static void mv_port_free_dma_mem(struct ata_port *ap)
1270 struct mv_host_priv *hpriv = ap->host->private_data;
1271 struct mv_port_priv *pp = ap->private_data;
1275 dma_pool_free(hpriv->crqb_pool, pp->crqb, pp->crqb_dma);
1279 dma_pool_free(hpriv->crpb_pool, pp->crpb, pp->crpb_dma);
1283 * For GEN_I, there's no NCQ, so we have only a single sg_tbl.
1284 * For later hardware, we have one unique sg_tbl per NCQ tag.
1286 for (tag = 0; tag < MV_MAX_Q_DEPTH; ++tag) {
1287 if (pp->sg_tbl[tag]) {
1288 if (tag == 0 || !IS_GEN_I(hpriv))
1289 dma_pool_free(hpriv->sg_tbl_pool,
1291 pp->sg_tbl_dma[tag]);
1292 pp->sg_tbl[tag] = NULL;
1298 * mv_port_start - Port specific init/start routine.
1299 * @ap: ATA channel to manipulate
1301 * Allocate and point to DMA memory, init port private memory,
1305 * Inherited from caller.
1307 static int mv_port_start(struct ata_port *ap)
1309 struct device *dev = ap->host->dev;
1310 struct mv_host_priv *hpriv = ap->host->private_data;
1311 struct mv_port_priv *pp;
1314 pp = devm_kzalloc(dev, sizeof(*pp), GFP_KERNEL);
1317 ap->private_data = pp;
1319 pp->crqb = dma_pool_alloc(hpriv->crqb_pool, GFP_KERNEL, &pp->crqb_dma);
1322 memset(pp->crqb, 0, MV_CRQB_Q_SZ);
1324 pp->crpb = dma_pool_alloc(hpriv->crpb_pool, GFP_KERNEL, &pp->crpb_dma);
1326 goto out_port_free_dma_mem;
1327 memset(pp->crpb, 0, MV_CRPB_Q_SZ);
1330 * For GEN_I, there's no NCQ, so we only allocate a single sg_tbl.
1331 * For later hardware, we need one unique sg_tbl per NCQ tag.
1333 for (tag = 0; tag < MV_MAX_Q_DEPTH; ++tag) {
1334 if (tag == 0 || !IS_GEN_I(hpriv)) {
1335 pp->sg_tbl[tag] = dma_pool_alloc(hpriv->sg_tbl_pool,
1336 GFP_KERNEL, &pp->sg_tbl_dma[tag]);
1337 if (!pp->sg_tbl[tag])
1338 goto out_port_free_dma_mem;
1340 pp->sg_tbl[tag] = pp->sg_tbl[0];
1341 pp->sg_tbl_dma[tag] = pp->sg_tbl_dma[0];
1346 out_port_free_dma_mem:
1347 mv_port_free_dma_mem(ap);
1352 * mv_port_stop - Port specific cleanup/stop routine.
1353 * @ap: ATA channel to manipulate
1355 * Stop DMA, cleanup port memory.
1358 * This routine uses the host lock to protect the DMA stop.
1360 static void mv_port_stop(struct ata_port *ap)
1363 mv_port_free_dma_mem(ap);
1367 * mv_fill_sg - Fill out the Marvell ePRD (scatter gather) entries
1368 * @qc: queued command whose SG list to source from
1370 * Populate the SG list and mark the last entry.
1373 * Inherited from caller.
1375 static void mv_fill_sg(struct ata_queued_cmd *qc)
1377 struct mv_port_priv *pp = qc->ap->private_data;
1378 struct scatterlist *sg;
1379 struct mv_sg *mv_sg, *last_sg = NULL;
1382 mv_sg = pp->sg_tbl[qc->tag];
1383 for_each_sg(qc->sg, sg, qc->n_elem, si) {
1384 dma_addr_t addr = sg_dma_address(sg);
1385 u32 sg_len = sg_dma_len(sg);
1388 u32 offset = addr & 0xffff;
1391 if ((offset + sg_len > 0x10000))
1392 len = 0x10000 - offset;
1394 mv_sg->addr = cpu_to_le32(addr & 0xffffffff);
1395 mv_sg->addr_hi = cpu_to_le32((addr >> 16) >> 16);
1396 mv_sg->flags_size = cpu_to_le32(len & 0xffff);
1406 if (likely(last_sg))
1407 last_sg->flags_size |= cpu_to_le32(EPRD_FLAG_END_OF_TBL);
1410 static void mv_crqb_pack_cmd(__le16 *cmdw, u8 data, u8 addr, unsigned last)
1412 u16 tmp = data | (addr << CRQB_CMD_ADDR_SHIFT) | CRQB_CMD_CS |
1413 (last ? CRQB_CMD_LAST : 0);
1414 *cmdw = cpu_to_le16(tmp);
1418 * mv_qc_prep - Host specific command preparation.
1419 * @qc: queued command to prepare
1421 * This routine simply redirects to the general purpose routine
1422 * if command is not DMA. Else, it handles prep of the CRQB
1423 * (command request block), does some sanity checking, and calls
1424 * the SG load routine.
1427 * Inherited from caller.
1429 static void mv_qc_prep(struct ata_queued_cmd *qc)
1431 struct ata_port *ap = qc->ap;
1432 struct mv_port_priv *pp = ap->private_data;
1434 struct ata_taskfile *tf;
1438 if ((qc->tf.protocol != ATA_PROT_DMA) &&
1439 (qc->tf.protocol != ATA_PROT_NCQ))
1442 /* Fill in command request block
1444 if (!(qc->tf.flags & ATA_TFLAG_WRITE))
1445 flags |= CRQB_FLAG_READ;
1446 WARN_ON(MV_MAX_Q_DEPTH <= qc->tag);
1447 flags |= qc->tag << CRQB_TAG_SHIFT;
1448 flags |= (qc->dev->link->pmp & 0xf) << CRQB_PMP_SHIFT;
1450 /* get current queue index from software */
1451 in_index = pp->req_idx;
1453 pp->crqb[in_index].sg_addr =
1454 cpu_to_le32(pp->sg_tbl_dma[qc->tag] & 0xffffffff);
1455 pp->crqb[in_index].sg_addr_hi =
1456 cpu_to_le32((pp->sg_tbl_dma[qc->tag] >> 16) >> 16);
1457 pp->crqb[in_index].ctrl_flags = cpu_to_le16(flags);
1459 cw = &pp->crqb[in_index].ata_cmd[0];
1462 /* Sadly, the CRQB cannot accomodate all registers--there are
1463 * only 11 bytes...so we must pick and choose required
1464 * registers based on the command. So, we drop feature and
1465 * hob_feature for [RW] DMA commands, but they are needed for
1466 * NCQ. NCQ will drop hob_nsect.
1468 switch (tf->command) {
1470 case ATA_CMD_READ_EXT:
1472 case ATA_CMD_WRITE_EXT:
1473 case ATA_CMD_WRITE_FUA_EXT:
1474 mv_crqb_pack_cmd(cw++, tf->hob_nsect, ATA_REG_NSECT, 0);
1476 case ATA_CMD_FPDMA_READ:
1477 case ATA_CMD_FPDMA_WRITE:
1478 mv_crqb_pack_cmd(cw++, tf->hob_feature, ATA_REG_FEATURE, 0);
1479 mv_crqb_pack_cmd(cw++, tf->feature, ATA_REG_FEATURE, 0);
1482 /* The only other commands EDMA supports in non-queued and
1483 * non-NCQ mode are: [RW] STREAM DMA and W DMA FUA EXT, none
1484 * of which are defined/used by Linux. If we get here, this
1485 * driver needs work.
1487 * FIXME: modify libata to give qc_prep a return value and
1488 * return error here.
1490 BUG_ON(tf->command);
1493 mv_crqb_pack_cmd(cw++, tf->nsect, ATA_REG_NSECT, 0);
1494 mv_crqb_pack_cmd(cw++, tf->hob_lbal, ATA_REG_LBAL, 0);
1495 mv_crqb_pack_cmd(cw++, tf->lbal, ATA_REG_LBAL, 0);
1496 mv_crqb_pack_cmd(cw++, tf->hob_lbam, ATA_REG_LBAM, 0);
1497 mv_crqb_pack_cmd(cw++, tf->lbam, ATA_REG_LBAM, 0);
1498 mv_crqb_pack_cmd(cw++, tf->hob_lbah, ATA_REG_LBAH, 0);
1499 mv_crqb_pack_cmd(cw++, tf->lbah, ATA_REG_LBAH, 0);
1500 mv_crqb_pack_cmd(cw++, tf->device, ATA_REG_DEVICE, 0);
1501 mv_crqb_pack_cmd(cw++, tf->command, ATA_REG_CMD, 1); /* last */
1503 if (!(qc->flags & ATA_QCFLAG_DMAMAP))
1509 * mv_qc_prep_iie - Host specific command preparation.
1510 * @qc: queued command to prepare
1512 * This routine simply redirects to the general purpose routine
1513 * if command is not DMA. Else, it handles prep of the CRQB
1514 * (command request block), does some sanity checking, and calls
1515 * the SG load routine.
1518 * Inherited from caller.
1520 static void mv_qc_prep_iie(struct ata_queued_cmd *qc)
1522 struct ata_port *ap = qc->ap;
1523 struct mv_port_priv *pp = ap->private_data;
1524 struct mv_crqb_iie *crqb;
1525 struct ata_taskfile *tf;
1529 if ((qc->tf.protocol != ATA_PROT_DMA) &&
1530 (qc->tf.protocol != ATA_PROT_NCQ))
1533 /* Fill in Gen IIE command request block */
1534 if (!(qc->tf.flags & ATA_TFLAG_WRITE))
1535 flags |= CRQB_FLAG_READ;
1537 WARN_ON(MV_MAX_Q_DEPTH <= qc->tag);
1538 flags |= qc->tag << CRQB_TAG_SHIFT;
1539 flags |= qc->tag << CRQB_HOSTQ_SHIFT;
1540 flags |= (qc->dev->link->pmp & 0xf) << CRQB_PMP_SHIFT;
1542 /* get current queue index from software */
1543 in_index = pp->req_idx;
1545 crqb = (struct mv_crqb_iie *) &pp->crqb[in_index];
1546 crqb->addr = cpu_to_le32(pp->sg_tbl_dma[qc->tag] & 0xffffffff);
1547 crqb->addr_hi = cpu_to_le32((pp->sg_tbl_dma[qc->tag] >> 16) >> 16);
1548 crqb->flags = cpu_to_le32(flags);
1551 crqb->ata_cmd[0] = cpu_to_le32(
1552 (tf->command << 16) |
1555 crqb->ata_cmd[1] = cpu_to_le32(
1561 crqb->ata_cmd[2] = cpu_to_le32(
1562 (tf->hob_lbal << 0) |
1563 (tf->hob_lbam << 8) |
1564 (tf->hob_lbah << 16) |
1565 (tf->hob_feature << 24)
1567 crqb->ata_cmd[3] = cpu_to_le32(
1569 (tf->hob_nsect << 8)
1572 if (!(qc->flags & ATA_QCFLAG_DMAMAP))
1578 * mv_qc_issue - Initiate a command to the host
1579 * @qc: queued command to start
1581 * This routine simply redirects to the general purpose routine
1582 * if command is not DMA. Else, it sanity checks our local
1583 * caches of the request producer/consumer indices then enables
1584 * DMA and bumps the request producer index.
1587 * Inherited from caller.
1589 static unsigned int mv_qc_issue(struct ata_queued_cmd *qc)
1591 struct ata_port *ap = qc->ap;
1592 void __iomem *port_mmio = mv_ap_base(ap);
1593 struct mv_port_priv *pp = ap->private_data;
1596 if ((qc->tf.protocol != ATA_PROT_DMA) &&
1597 (qc->tf.protocol != ATA_PROT_NCQ)) {
1599 * We're about to send a non-EDMA capable command to the
1600 * port. Turn off EDMA so there won't be problems accessing
1601 * shadow block, etc registers.
1604 mv_pmp_select(ap, qc->dev->link->pmp);
1605 return ata_sff_qc_issue(qc);
1608 mv_start_dma(ap, port_mmio, pp, qc->tf.protocol);
1610 pp->req_idx = (pp->req_idx + 1) & MV_MAX_Q_DEPTH_MASK;
1611 in_index = pp->req_idx << EDMA_REQ_Q_PTR_SHIFT;
1613 /* and write the request in pointer to kick the EDMA to life */
1614 writelfl((pp->crqb_dma & EDMA_REQ_Q_BASE_LO_MASK) | in_index,
1615 port_mmio + EDMA_REQ_Q_IN_PTR_OFS);
1620 static struct ata_queued_cmd *mv_get_active_qc(struct ata_port *ap)
1622 struct mv_port_priv *pp = ap->private_data;
1623 struct ata_queued_cmd *qc;
1625 if (pp->pp_flags & MV_PP_FLAG_NCQ_EN)
1627 qc = ata_qc_from_tag(ap, ap->link.active_tag);
1628 if (qc && (qc->tf.flags & ATA_TFLAG_POLLING))
1633 static void mv_pmp_error_handler(struct ata_port *ap)
1635 unsigned int pmp, pmp_map;
1636 struct mv_port_priv *pp = ap->private_data;
1638 if (pp->pp_flags & MV_PP_FLAG_DELAYED_EH) {
1640 * Perform NCQ error analysis on failed PMPs
1641 * before we freeze the port entirely.
1643 * The failed PMPs are marked earlier by mv_pmp_eh_prep().
1645 pmp_map = pp->delayed_eh_pmp_map;
1646 pp->pp_flags &= ~MV_PP_FLAG_DELAYED_EH;
1647 for (pmp = 0; pmp_map != 0; pmp++) {
1648 unsigned int this_pmp = (1 << pmp);
1649 if (pmp_map & this_pmp) {
1650 struct ata_link *link = &ap->pmp_link[pmp];
1651 pmp_map &= ~this_pmp;
1652 ata_eh_analyze_ncq_error(link);
1655 ata_port_freeze(ap);
1657 sata_pmp_error_handler(ap);
1660 static unsigned int mv_get_err_pmp_map(struct ata_port *ap)
1662 void __iomem *port_mmio = mv_ap_base(ap);
1664 return readl(port_mmio + SATA_TESTCTL_OFS) >> 16;
1667 static void mv_pmp_eh_prep(struct ata_port *ap, unsigned int pmp_map)
1669 struct ata_eh_info *ehi;
1673 * Initialize EH info for PMPs which saw device errors
1675 ehi = &ap->link.eh_info;
1676 for (pmp = 0; pmp_map != 0; pmp++) {
1677 unsigned int this_pmp = (1 << pmp);
1678 if (pmp_map & this_pmp) {
1679 struct ata_link *link = &ap->pmp_link[pmp];
1681 pmp_map &= ~this_pmp;
1682 ehi = &link->eh_info;
1683 ata_ehi_clear_desc(ehi);
1684 ata_ehi_push_desc(ehi, "dev err");
1685 ehi->err_mask |= AC_ERR_DEV;
1686 ehi->action |= ATA_EH_RESET;
1687 ata_link_abort(link);
1692 static int mv_handle_fbs_ncq_dev_err(struct ata_port *ap)
1694 struct mv_port_priv *pp = ap->private_data;
1696 unsigned int old_map, new_map;
1699 * Device error during FBS+NCQ operation:
1701 * Set a port flag to prevent further I/O being enqueued.
1702 * Leave the EDMA running to drain outstanding commands from this port.
1703 * Perform the post-mortem/EH only when all responses are complete.
1704 * Follow recovery sequence from 6042/7042 datasheet (7.3.15.4.2.2).
1706 if (!(pp->pp_flags & MV_PP_FLAG_DELAYED_EH)) {
1707 pp->pp_flags |= MV_PP_FLAG_DELAYED_EH;
1708 pp->delayed_eh_pmp_map = 0;
1710 old_map = pp->delayed_eh_pmp_map;
1711 new_map = old_map | mv_get_err_pmp_map(ap);
1713 if (old_map != new_map) {
1714 pp->delayed_eh_pmp_map = new_map;
1715 mv_pmp_eh_prep(ap, new_map & ~old_map);
1717 failed_links = hweight16(new_map);
1719 ata_port_printk(ap, KERN_INFO, "%s: pmp_map=%04x qc_map=%04x "
1720 "failed_links=%d nr_active_links=%d\n",
1721 __func__, pp->delayed_eh_pmp_map,
1722 ap->qc_active, failed_links,
1723 ap->nr_active_links);
1725 if (ap->nr_active_links <= failed_links) {
1726 mv_process_crpb_entries(ap, pp);
1729 ata_port_printk(ap, KERN_INFO, "%s: done\n", __func__);
1730 return 1; /* handled */
1732 ata_port_printk(ap, KERN_INFO, "%s: waiting\n", __func__);
1733 return 1; /* handled */
1736 static int mv_handle_fbs_non_ncq_dev_err(struct ata_port *ap)
1739 * Possible future enhancement:
1741 * FBS+non-NCQ operation is not yet implemented.
1742 * See related notes in mv_edma_cfg().
1744 * Device error during FBS+non-NCQ operation:
1746 * We need to snapshot the shadow registers for each failed command.
1747 * Follow recovery sequence from 6042/7042 datasheet (7.3.15.4.2.3).
1749 return 0; /* not handled */
1752 static int mv_handle_dev_err(struct ata_port *ap, u32 edma_err_cause)
1754 struct mv_port_priv *pp = ap->private_data;
1756 if (!(pp->pp_flags & MV_PP_FLAG_EDMA_EN))
1757 return 0; /* EDMA was not active: not handled */
1758 if (!(pp->pp_flags & MV_PP_FLAG_FBS_EN))
1759 return 0; /* FBS was not active: not handled */
1761 if (!(edma_err_cause & EDMA_ERR_DEV))
1762 return 0; /* non DEV error: not handled */
1763 edma_err_cause &= ~EDMA_ERR_IRQ_TRANSIENT;
1764 if (edma_err_cause & ~(EDMA_ERR_DEV | EDMA_ERR_SELF_DIS))
1765 return 0; /* other problems: not handled */
1767 if (pp->pp_flags & MV_PP_FLAG_NCQ_EN) {
1769 * EDMA should NOT have self-disabled for this case.
1770 * If it did, then something is wrong elsewhere,
1771 * and we cannot handle it here.
1773 if (edma_err_cause & EDMA_ERR_SELF_DIS) {
1774 ata_port_printk(ap, KERN_WARNING,
1775 "%s: err_cause=0x%x pp_flags=0x%x\n",
1776 __func__, edma_err_cause, pp->pp_flags);
1777 return 0; /* not handled */
1779 return mv_handle_fbs_ncq_dev_err(ap);
1782 * EDMA should have self-disabled for this case.
1783 * If it did not, then something is wrong elsewhere,
1784 * and we cannot handle it here.
1786 if (!(edma_err_cause & EDMA_ERR_SELF_DIS)) {
1787 ata_port_printk(ap, KERN_WARNING,
1788 "%s: err_cause=0x%x pp_flags=0x%x\n",
1789 __func__, edma_err_cause, pp->pp_flags);
1790 return 0; /* not handled */
1792 return mv_handle_fbs_non_ncq_dev_err(ap);
1794 return 0; /* not handled */
1797 static void mv_unexpected_intr(struct ata_port *ap, int edma_was_enabled)
1799 struct ata_eh_info *ehi = &ap->link.eh_info;
1800 char *when = "idle";
1802 ata_ehi_clear_desc(ehi);
1803 if (!ap || (ap->flags & ATA_FLAG_DISABLED)) {
1805 } else if (edma_was_enabled) {
1806 when = "EDMA enabled";
1808 struct ata_queued_cmd *qc = ata_qc_from_tag(ap, ap->link.active_tag);
1809 if (qc && (qc->tf.flags & ATA_TFLAG_POLLING))
1812 ata_ehi_push_desc(ehi, "unexpected device interrupt while %s", when);
1813 ehi->err_mask |= AC_ERR_OTHER;
1814 ehi->action |= ATA_EH_RESET;
1815 ata_port_freeze(ap);
1819 * mv_err_intr - Handle error interrupts on the port
1820 * @ap: ATA channel to manipulate
1821 * @qc: affected command (non-NCQ), or NULL
1823 * Most cases require a full reset of the chip's state machine,
1824 * which also performs a COMRESET.
1825 * Also, if the port disabled DMA, update our cached copy to match.
1828 * Inherited from caller.
1830 static void mv_err_intr(struct ata_port *ap)
1832 void __iomem *port_mmio = mv_ap_base(ap);
1833 u32 edma_err_cause, eh_freeze_mask, serr = 0;
1835 struct mv_port_priv *pp = ap->private_data;
1836 struct mv_host_priv *hpriv = ap->host->private_data;
1837 unsigned int action = 0, err_mask = 0;
1838 struct ata_eh_info *ehi = &ap->link.eh_info;
1839 struct ata_queued_cmd *qc;
1843 * Read and clear the SError and err_cause bits.
1844 * For GenIIe, if EDMA_ERR_TRANS_IRQ_7 is set, we also must read/clear
1845 * the FIS_IRQ_CAUSE register before clearing edma_err_cause.
1847 sata_scr_read(&ap->link, SCR_ERROR, &serr);
1848 sata_scr_write_flush(&ap->link, SCR_ERROR, serr);
1850 edma_err_cause = readl(port_mmio + EDMA_ERR_IRQ_CAUSE_OFS);
1851 if (IS_GEN_IIE(hpriv) && (edma_err_cause & EDMA_ERR_TRANS_IRQ_7)) {
1852 fis_cause = readl(port_mmio + SATA_FIS_IRQ_CAUSE_OFS);
1853 writelfl(~fis_cause, port_mmio + SATA_FIS_IRQ_CAUSE_OFS);
1855 writelfl(~edma_err_cause, port_mmio + EDMA_ERR_IRQ_CAUSE_OFS);
1857 if (edma_err_cause & EDMA_ERR_DEV) {
1859 * Device errors during FIS-based switching operation
1860 * require special handling.
1862 if (mv_handle_dev_err(ap, edma_err_cause))
1866 qc = mv_get_active_qc(ap);
1867 ata_ehi_clear_desc(ehi);
1868 ata_ehi_push_desc(ehi, "edma_err_cause=%08x pp_flags=%08x",
1869 edma_err_cause, pp->pp_flags);
1871 if (IS_GEN_IIE(hpriv) && (edma_err_cause & EDMA_ERR_TRANS_IRQ_7)) {
1872 ata_ehi_push_desc(ehi, "fis_cause=%08x", fis_cause);
1873 if (fis_cause & SATA_FIS_IRQ_AN) {
1874 u32 ec = edma_err_cause &
1875 ~(EDMA_ERR_TRANS_IRQ_7 | EDMA_ERR_IRQ_TRANSIENT);
1876 sata_async_notification(ap);
1878 return; /* Just an AN; no need for the nukes */
1879 ata_ehi_push_desc(ehi, "SDB notify");
1883 * All generations share these EDMA error cause bits:
1885 if (edma_err_cause & EDMA_ERR_DEV) {
1886 err_mask |= AC_ERR_DEV;
1887 action |= ATA_EH_RESET;
1888 ata_ehi_push_desc(ehi, "dev error");
1890 if (edma_err_cause & (EDMA_ERR_D_PAR | EDMA_ERR_PRD_PAR |
1891 EDMA_ERR_CRQB_PAR | EDMA_ERR_CRPB_PAR |
1892 EDMA_ERR_INTRL_PAR)) {
1893 err_mask |= AC_ERR_ATA_BUS;
1894 action |= ATA_EH_RESET;
1895 ata_ehi_push_desc(ehi, "parity error");
1897 if (edma_err_cause & (EDMA_ERR_DEV_DCON | EDMA_ERR_DEV_CON)) {
1898 ata_ehi_hotplugged(ehi);
1899 ata_ehi_push_desc(ehi, edma_err_cause & EDMA_ERR_DEV_DCON ?
1900 "dev disconnect" : "dev connect");
1901 action |= ATA_EH_RESET;
1905 * Gen-I has a different SELF_DIS bit,
1906 * different FREEZE bits, and no SERR bit:
1908 if (IS_GEN_I(hpriv)) {
1909 eh_freeze_mask = EDMA_EH_FREEZE_5;
1910 if (edma_err_cause & EDMA_ERR_SELF_DIS_5) {
1911 pp->pp_flags &= ~MV_PP_FLAG_EDMA_EN;
1912 ata_ehi_push_desc(ehi, "EDMA self-disable");
1915 eh_freeze_mask = EDMA_EH_FREEZE;
1916 if (edma_err_cause & EDMA_ERR_SELF_DIS) {
1917 pp->pp_flags &= ~MV_PP_FLAG_EDMA_EN;
1918 ata_ehi_push_desc(ehi, "EDMA self-disable");
1920 if (edma_err_cause & EDMA_ERR_SERR) {
1921 ata_ehi_push_desc(ehi, "SError=%08x", serr);
1922 err_mask |= AC_ERR_ATA_BUS;
1923 action |= ATA_EH_RESET;
1928 err_mask = AC_ERR_OTHER;
1929 action |= ATA_EH_RESET;
1932 ehi->serror |= serr;
1933 ehi->action |= action;
1936 qc->err_mask |= err_mask;
1938 ehi->err_mask |= err_mask;
1940 if (err_mask == AC_ERR_DEV) {
1942 * Cannot do ata_port_freeze() here,
1943 * because it would kill PIO access,
1944 * which is needed for further diagnosis.
1948 } else if (edma_err_cause & eh_freeze_mask) {
1950 * Note to self: ata_port_freeze() calls ata_port_abort()
1952 ata_port_freeze(ap);
1959 ata_link_abort(qc->dev->link);
1965 static void mv_process_crpb_response(struct ata_port *ap,
1966 struct mv_crpb *response, unsigned int tag, int ncq_enabled)
1968 struct ata_queued_cmd *qc = ata_qc_from_tag(ap, tag);
1972 u16 edma_status = le16_to_cpu(response->flags);
1974 * edma_status from a response queue entry:
1975 * LSB is from EDMA_ERR_IRQ_CAUSE_OFS (non-NCQ only).
1976 * MSB is saved ATA status from command completion.
1979 u8 err_cause = edma_status & 0xff & ~EDMA_ERR_DEV;
1982 * Error will be seen/handled by mv_err_intr().
1983 * So do nothing at all here.
1988 ata_status = edma_status >> CRPB_FLAG_STATUS_SHIFT;
1989 if (!ac_err_mask(ata_status))
1990 ata_qc_complete(qc);
1991 /* else: leave it for mv_err_intr() */
1993 ata_port_printk(ap, KERN_ERR, "%s: no qc for tag=%d\n",
1998 static void mv_process_crpb_entries(struct ata_port *ap, struct mv_port_priv *pp)
2000 void __iomem *port_mmio = mv_ap_base(ap);
2001 struct mv_host_priv *hpriv = ap->host->private_data;
2003 bool work_done = false;
2004 int ncq_enabled = (pp->pp_flags & MV_PP_FLAG_NCQ_EN);
2006 /* Get the hardware queue position index */
2007 in_index = (readl(port_mmio + EDMA_RSP_Q_IN_PTR_OFS)
2008 >> EDMA_RSP_Q_PTR_SHIFT) & MV_MAX_Q_DEPTH_MASK;
2010 /* Process new responses from since the last time we looked */
2011 while (in_index != pp->resp_idx) {
2013 struct mv_crpb *response = &pp->crpb[pp->resp_idx];
2015 pp->resp_idx = (pp->resp_idx + 1) & MV_MAX_Q_DEPTH_MASK;
2017 if (IS_GEN_I(hpriv)) {
2018 /* 50xx: no NCQ, only one command active at a time */
2019 tag = ap->link.active_tag;
2021 /* Gen II/IIE: get command tag from CRPB entry */
2022 tag = le16_to_cpu(response->id) & 0x1f;
2024 mv_process_crpb_response(ap, response, tag, ncq_enabled);
2028 /* Update the software queue position index in hardware */
2030 writelfl((pp->crpb_dma & EDMA_RSP_Q_BASE_LO_MASK) |
2031 (pp->resp_idx << EDMA_RSP_Q_PTR_SHIFT),
2032 port_mmio + EDMA_RSP_Q_OUT_PTR_OFS);
2035 static void mv_port_intr(struct ata_port *ap, u32 port_cause)
2037 struct mv_port_priv *pp;
2038 int edma_was_enabled;
2040 if (!ap || (ap->flags & ATA_FLAG_DISABLED)) {
2041 mv_unexpected_intr(ap, 0);
2045 * Grab a snapshot of the EDMA_EN flag setting,
2046 * so that we have a consistent view for this port,
2047 * even if something we call of our routines changes it.
2049 pp = ap->private_data;
2050 edma_was_enabled = (pp->pp_flags & MV_PP_FLAG_EDMA_EN);
2052 * Process completed CRPB response(s) before other events.
2054 if (edma_was_enabled && (port_cause & DONE_IRQ)) {
2055 mv_process_crpb_entries(ap, pp);
2056 if (pp->pp_flags & MV_PP_FLAG_DELAYED_EH)
2057 mv_handle_fbs_ncq_dev_err(ap);
2060 * Handle chip-reported errors, or continue on to handle PIO.
2062 if (unlikely(port_cause & ERR_IRQ)) {
2064 } else if (!edma_was_enabled) {
2065 struct ata_queued_cmd *qc = mv_get_active_qc(ap);
2067 ata_sff_host_intr(ap, qc);
2069 mv_unexpected_intr(ap, edma_was_enabled);
2074 * mv_host_intr - Handle all interrupts on the given host controller
2075 * @host: host specific structure
2076 * @main_irq_cause: Main interrupt cause register for the chip.
2079 * Inherited from caller.
2081 static int mv_host_intr(struct ata_host *host, u32 main_irq_cause)
2083 struct mv_host_priv *hpriv = host->private_data;
2084 void __iomem *mmio = hpriv->base, *hc_mmio;
2085 unsigned int handled = 0, port;
2087 for (port = 0; port < hpriv->n_ports; port++) {
2088 struct ata_port *ap = host->ports[port];
2089 unsigned int p, shift, hardport, port_cause;
2091 MV_PORT_TO_SHIFT_AND_HARDPORT(port, shift, hardport);
2093 * Each hc within the host has its own hc_irq_cause register,
2094 * where the interrupting ports bits get ack'd.
2096 if (hardport == 0) { /* first port on this hc ? */
2097 u32 hc_cause = (main_irq_cause >> shift) & HC0_IRQ_PEND;
2098 u32 port_mask, ack_irqs;
2100 * Skip this entire hc if nothing pending for any ports
2103 port += MV_PORTS_PER_HC - 1;
2107 * We don't need/want to read the hc_irq_cause register,
2108 * because doing so hurts performance, and
2109 * main_irq_cause already gives us everything we need.
2111 * But we do have to *write* to the hc_irq_cause to ack
2112 * the ports that we are handling this time through.
2114 * This requires that we create a bitmap for those
2115 * ports which interrupted us, and use that bitmap
2116 * to ack (only) those ports via hc_irq_cause.
2119 for (p = 0; p < MV_PORTS_PER_HC; ++p) {
2120 if ((port + p) >= hpriv->n_ports)
2122 port_mask = (DONE_IRQ | ERR_IRQ) << (p * 2);
2123 if (hc_cause & port_mask)
2124 ack_irqs |= (DMA_IRQ | DEV_IRQ) << p;
2126 hc_mmio = mv_hc_base_from_port(mmio, port);
2127 writelfl(~ack_irqs, hc_mmio + HC_IRQ_CAUSE_OFS);
2131 * Handle interrupts signalled for this port:
2133 port_cause = (main_irq_cause >> shift) & (DONE_IRQ | ERR_IRQ);
2135 mv_port_intr(ap, port_cause);
2140 static int mv_pci_error(struct ata_host *host, void __iomem *mmio)
2142 struct mv_host_priv *hpriv = host->private_data;
2143 struct ata_port *ap;
2144 struct ata_queued_cmd *qc;
2145 struct ata_eh_info *ehi;
2146 unsigned int i, err_mask, printed = 0;
2149 err_cause = readl(mmio + hpriv->irq_cause_ofs);
2151 dev_printk(KERN_ERR, host->dev, "PCI ERROR; PCI IRQ cause=0x%08x\n",
2154 DPRINTK("All regs @ PCI error\n");
2155 mv_dump_all_regs(mmio, -1, to_pci_dev(host->dev));
2157 writelfl(0, mmio + hpriv->irq_cause_ofs);
2159 for (i = 0; i < host->n_ports; i++) {
2160 ap = host->ports[i];
2161 if (!ata_link_offline(&ap->link)) {
2162 ehi = &ap->link.eh_info;
2163 ata_ehi_clear_desc(ehi);
2165 ata_ehi_push_desc(ehi,
2166 "PCI err cause 0x%08x", err_cause);
2167 err_mask = AC_ERR_HOST_BUS;
2168 ehi->action = ATA_EH_RESET;
2169 qc = ata_qc_from_tag(ap, ap->link.active_tag);
2171 qc->err_mask |= err_mask;
2173 ehi->err_mask |= err_mask;
2175 ata_port_freeze(ap);
2178 return 1; /* handled */
2182 * mv_interrupt - Main interrupt event handler
2184 * @dev_instance: private data; in this case the host structure
2186 * Read the read only register to determine if any host
2187 * controllers have pending interrupts. If so, call lower level
2188 * routine to handle. Also check for PCI errors which are only
2192 * This routine holds the host lock while processing pending
2195 static irqreturn_t mv_interrupt(int irq, void *dev_instance)
2197 struct ata_host *host = dev_instance;
2198 struct mv_host_priv *hpriv = host->private_data;
2199 unsigned int handled = 0;
2200 u32 main_irq_cause, main_irq_mask;
2202 spin_lock(&host->lock);
2203 main_irq_cause = readl(hpriv->main_irq_cause_addr);
2204 main_irq_mask = readl(hpriv->main_irq_mask_addr);
2206 * Deal with cases where we either have nothing pending, or have read
2207 * a bogus register value which can indicate HW removal or PCI fault.
2209 if ((main_irq_cause & main_irq_mask) && (main_irq_cause != 0xffffffffU)) {
2210 if (unlikely((main_irq_cause & PCI_ERR) && HAS_PCI(host)))
2211 handled = mv_pci_error(host, hpriv->base);
2213 handled = mv_host_intr(host, main_irq_cause);
2215 spin_unlock(&host->lock);
2216 return IRQ_RETVAL(handled);
2219 static unsigned int mv5_scr_offset(unsigned int sc_reg_in)
2223 switch (sc_reg_in) {
2227 ofs = sc_reg_in * sizeof(u32);
2236 static int mv5_scr_read(struct ata_port *ap, unsigned int sc_reg_in, u32 *val)
2238 struct mv_host_priv *hpriv = ap->host->private_data;
2239 void __iomem *mmio = hpriv->base;
2240 void __iomem *addr = mv5_phy_base(mmio, ap->port_no);
2241 unsigned int ofs = mv5_scr_offset(sc_reg_in);
2243 if (ofs != 0xffffffffU) {
2244 *val = readl(addr + ofs);
2250 static int mv5_scr_write(struct ata_port *ap, unsigned int sc_reg_in, u32 val)
2252 struct mv_host_priv *hpriv = ap->host->private_data;
2253 void __iomem *mmio = hpriv->base;
2254 void __iomem *addr = mv5_phy_base(mmio, ap->port_no);
2255 unsigned int ofs = mv5_scr_offset(sc_reg_in);
2257 if (ofs != 0xffffffffU) {
2258 writelfl(val, addr + ofs);
2264 static void mv5_reset_bus(struct ata_host *host, void __iomem *mmio)
2266 struct pci_dev *pdev = to_pci_dev(host->dev);
2269 early_5080 = (pdev->device == 0x5080) && (pdev->revision == 0);
2272 u32 tmp = readl(mmio + MV_PCI_EXP_ROM_BAR_CTL);
2274 writel(tmp, mmio + MV_PCI_EXP_ROM_BAR_CTL);
2277 mv_reset_pci_bus(host, mmio);
2280 static void mv5_reset_flash(struct mv_host_priv *hpriv, void __iomem *mmio)
2282 writel(0x0fcfffff, mmio + MV_FLASH_CTL_OFS);
2285 static void mv5_read_preamp(struct mv_host_priv *hpriv, int idx,
2288 void __iomem *phy_mmio = mv5_phy_base(mmio, idx);
2291 tmp = readl(phy_mmio + MV5_PHY_MODE);
2293 hpriv->signal[idx].pre = tmp & 0x1800; /* bits 12:11 */
2294 hpriv->signal[idx].amps = tmp & 0xe0; /* bits 7:5 */
2297 static void mv5_enable_leds(struct mv_host_priv *hpriv, void __iomem *mmio)
2301 writel(0, mmio + MV_GPIO_PORT_CTL_OFS);
2303 /* FIXME: handle MV_HP_ERRATA_50XXB2 errata */
2305 tmp = readl(mmio + MV_PCI_EXP_ROM_BAR_CTL);
2307 writel(tmp, mmio + MV_PCI_EXP_ROM_BAR_CTL);
2310 static void mv5_phy_errata(struct mv_host_priv *hpriv, void __iomem *mmio,
2313 void __iomem *phy_mmio = mv5_phy_base(mmio, port);
2314 const u32 mask = (1<<12) | (1<<11) | (1<<7) | (1<<6) | (1<<5);
2316 int fix_apm_sq = (hpriv->hp_flags & MV_HP_ERRATA_50XXB0);
2319 tmp = readl(phy_mmio + MV5_LTMODE_OFS);
2321 writel(tmp, phy_mmio + MV5_LTMODE_OFS);
2323 tmp = readl(phy_mmio + MV5_PHY_CTL_OFS);
2326 writel(tmp, phy_mmio + MV5_PHY_CTL_OFS);
2329 tmp = readl(phy_mmio + MV5_PHY_MODE);
2331 tmp |= hpriv->signal[port].pre;
2332 tmp |= hpriv->signal[port].amps;
2333 writel(tmp, phy_mmio + MV5_PHY_MODE);
2338 #define ZERO(reg) writel(0, port_mmio + (reg))
2339 static void mv5_reset_hc_port(struct mv_host_priv *hpriv, void __iomem *mmio,
2342 void __iomem *port_mmio = mv_port_base(mmio, port);
2344 mv_reset_channel(hpriv, mmio, port);
2346 ZERO(0x028); /* command */
2347 writel(0x11f, port_mmio + EDMA_CFG_OFS);
2348 ZERO(0x004); /* timer */
2349 ZERO(0x008); /* irq err cause */
2350 ZERO(0x00c); /* irq err mask */
2351 ZERO(0x010); /* rq bah */
2352 ZERO(0x014); /* rq inp */
2353 ZERO(0x018); /* rq outp */
2354 ZERO(0x01c); /* respq bah */
2355 ZERO(0x024); /* respq outp */
2356 ZERO(0x020); /* respq inp */
2357 ZERO(0x02c); /* test control */
2358 writel(0xbc, port_mmio + EDMA_IORDY_TMOUT_OFS);
2362 #define ZERO(reg) writel(0, hc_mmio + (reg))
2363 static void mv5_reset_one_hc(struct mv_host_priv *hpriv, void __iomem *mmio,
2366 void __iomem *hc_mmio = mv_hc_base(mmio, hc);
2374 tmp = readl(hc_mmio + 0x20);
2377 writel(tmp, hc_mmio + 0x20);
2381 static int mv5_reset_hc(struct mv_host_priv *hpriv, void __iomem *mmio,
2384 unsigned int hc, port;
2386 for (hc = 0; hc < n_hc; hc++) {
2387 for (port = 0; port < MV_PORTS_PER_HC; port++)
2388 mv5_reset_hc_port(hpriv, mmio,
2389 (hc * MV_PORTS_PER_HC) + port);
2391 mv5_reset_one_hc(hpriv, mmio, hc);
2398 #define ZERO(reg) writel(0, mmio + (reg))
2399 static void mv_reset_pci_bus(struct ata_host *host, void __iomem *mmio)
2401 struct mv_host_priv *hpriv = host->private_data;
2404 tmp = readl(mmio + MV_PCI_MODE_OFS);
2406 writel(tmp, mmio + MV_PCI_MODE_OFS);
2408 ZERO(MV_PCI_DISC_TIMER);
2409 ZERO(MV_PCI_MSI_TRIGGER);
2410 writel(0x000100ff, mmio + MV_PCI_XBAR_TMOUT_OFS);
2411 ZERO(MV_PCI_SERR_MASK);
2412 ZERO(hpriv->irq_cause_ofs);
2413 ZERO(hpriv->irq_mask_ofs);
2414 ZERO(MV_PCI_ERR_LOW_ADDRESS);
2415 ZERO(MV_PCI_ERR_HIGH_ADDRESS);
2416 ZERO(MV_PCI_ERR_ATTRIBUTE);
2417 ZERO(MV_PCI_ERR_COMMAND);
2421 static void mv6_reset_flash(struct mv_host_priv *hpriv, void __iomem *mmio)
2425 mv5_reset_flash(hpriv, mmio);
2427 tmp = readl(mmio + MV_GPIO_PORT_CTL_OFS);
2429 tmp |= (1 << 5) | (1 << 6);
2430 writel(tmp, mmio + MV_GPIO_PORT_CTL_OFS);
2434 * mv6_reset_hc - Perform the 6xxx global soft reset
2435 * @mmio: base address of the HBA
2437 * This routine only applies to 6xxx parts.
2440 * Inherited from caller.
2442 static int mv6_reset_hc(struct mv_host_priv *hpriv, void __iomem *mmio,
2445 void __iomem *reg = mmio + PCI_MAIN_CMD_STS_OFS;
2449 /* Following procedure defined in PCI "main command and status
2453 writel(t | STOP_PCI_MASTER, reg);
2455 for (i = 0; i < 1000; i++) {
2458 if (PCI_MASTER_EMPTY & t)
2461 if (!(PCI_MASTER_EMPTY & t)) {
2462 printk(KERN_ERR DRV_NAME ": PCI master won't flush\n");
2470 writel(t | GLOB_SFT_RST, reg);
2473 } while (!(GLOB_SFT_RST & t) && (i-- > 0));
2475 if (!(GLOB_SFT_RST & t)) {
2476 printk(KERN_ERR DRV_NAME ": can't set global reset\n");
2481 /* clear reset and *reenable the PCI master* (not mentioned in spec) */
2484 writel(t & ~(GLOB_SFT_RST | STOP_PCI_MASTER), reg);
2487 } while ((GLOB_SFT_RST & t) && (i-- > 0));
2489 if (GLOB_SFT_RST & t) {
2490 printk(KERN_ERR DRV_NAME ": can't clear global reset\n");
2497 static void mv6_read_preamp(struct mv_host_priv *hpriv, int idx,
2500 void __iomem *port_mmio;
2503 tmp = readl(mmio + MV_RESET_CFG_OFS);
2504 if ((tmp & (1 << 0)) == 0) {
2505 hpriv->signal[idx].amps = 0x7 << 8;
2506 hpriv->signal[idx].pre = 0x1 << 5;
2510 port_mmio = mv_port_base(mmio, idx);
2511 tmp = readl(port_mmio + PHY_MODE2);
2513 hpriv->signal[idx].amps = tmp & 0x700; /* bits 10:8 */
2514 hpriv->signal[idx].pre = tmp & 0xe0; /* bits 7:5 */
2517 static void mv6_enable_leds(struct mv_host_priv *hpriv, void __iomem *mmio)
2519 writel(0x00000060, mmio + MV_GPIO_PORT_CTL_OFS);
2522 static void mv6_phy_errata(struct mv_host_priv *hpriv, void __iomem *mmio,
2525 void __iomem *port_mmio = mv_port_base(mmio, port);
2527 u32 hp_flags = hpriv->hp_flags;
2529 hp_flags & (MV_HP_ERRATA_60X1B2 | MV_HP_ERRATA_60X1C0);
2531 hp_flags & (MV_HP_ERRATA_60X1B2 | MV_HP_ERRATA_60X1C0);
2534 if (fix_phy_mode2) {
2535 m2 = readl(port_mmio + PHY_MODE2);
2538 writel(m2, port_mmio + PHY_MODE2);
2542 m2 = readl(port_mmio + PHY_MODE2);
2543 m2 &= ~((1 << 16) | (1 << 31));
2544 writel(m2, port_mmio + PHY_MODE2);
2549 /* who knows what this magic does */
2550 tmp = readl(port_mmio + PHY_MODE3);
2553 writel(tmp, port_mmio + PHY_MODE3);
2555 if (fix_phy_mode4) {
2558 m4 = readl(port_mmio + PHY_MODE4);
2560 if (hp_flags & MV_HP_ERRATA_60X1B2)
2561 tmp = readl(port_mmio + PHY_MODE3);
2563 /* workaround for errata FEr SATA#10 (part 1) */
2564 m4 = (m4 & ~(1 << 1)) | (1 << 0);
2566 writel(m4, port_mmio + PHY_MODE4);
2568 if (hp_flags & MV_HP_ERRATA_60X1B2)
2569 writel(tmp, port_mmio + PHY_MODE3);
2572 /* Revert values of pre-emphasis and signal amps to the saved ones */
2573 m2 = readl(port_mmio + PHY_MODE2);
2575 m2 &= ~MV_M2_PREAMP_MASK;
2576 m2 |= hpriv->signal[port].amps;
2577 m2 |= hpriv->signal[port].pre;
2580 /* according to mvSata 3.6.1, some IIE values are fixed */
2581 if (IS_GEN_IIE(hpriv)) {
2586 writel(m2, port_mmio + PHY_MODE2);
2589 /* TODO: use the generic LED interface to configure the SATA Presence */
2590 /* & Acitivy LEDs on the board */
2591 static void mv_soc_enable_leds(struct mv_host_priv *hpriv,
2597 static void mv_soc_read_preamp(struct mv_host_priv *hpriv, int idx,
2600 void __iomem *port_mmio;
2603 port_mmio = mv_port_base(mmio, idx);
2604 tmp = readl(port_mmio + PHY_MODE2);
2606 hpriv->signal[idx].amps = tmp & 0x700; /* bits 10:8 */
2607 hpriv->signal[idx].pre = tmp & 0xe0; /* bits 7:5 */
2611 #define ZERO(reg) writel(0, port_mmio + (reg))
2612 static void mv_soc_reset_hc_port(struct mv_host_priv *hpriv,
2613 void __iomem *mmio, unsigned int port)
2615 void __iomem *port_mmio = mv_port_base(mmio, port);
2617 mv_reset_channel(hpriv, mmio, port);
2619 ZERO(0x028); /* command */
2620 writel(0x101f, port_mmio + EDMA_CFG_OFS);
2621 ZERO(0x004); /* timer */
2622 ZERO(0x008); /* irq err cause */
2623 ZERO(0x00c); /* irq err mask */
2624 ZERO(0x010); /* rq bah */
2625 ZERO(0x014); /* rq inp */
2626 ZERO(0x018); /* rq outp */
2627 ZERO(0x01c); /* respq bah */
2628 ZERO(0x024); /* respq outp */
2629 ZERO(0x020); /* respq inp */
2630 ZERO(0x02c); /* test control */
2631 writel(0xbc, port_mmio + EDMA_IORDY_TMOUT_OFS);
2636 #define ZERO(reg) writel(0, hc_mmio + (reg))
2637 static void mv_soc_reset_one_hc(struct mv_host_priv *hpriv,
2640 void __iomem *hc_mmio = mv_hc_base(mmio, 0);
2650 static int mv_soc_reset_hc(struct mv_host_priv *hpriv,
2651 void __iomem *mmio, unsigned int n_hc)
2655 for (port = 0; port < hpriv->n_ports; port++)
2656 mv_soc_reset_hc_port(hpriv, mmio, port);
2658 mv_soc_reset_one_hc(hpriv, mmio);
2663 static void mv_soc_reset_flash(struct mv_host_priv *hpriv,
2669 static void mv_soc_reset_bus(struct ata_host *host, void __iomem *mmio)
2674 static void mv_setup_ifcfg(void __iomem *port_mmio, int want_gen2i)
2676 u32 ifcfg = readl(port_mmio + SATA_INTERFACE_CFG_OFS);
2678 ifcfg = (ifcfg & 0xf7f) | 0x9b1000; /* from chip spec */
2680 ifcfg |= (1 << 7); /* enable gen2i speed */
2681 writelfl(ifcfg, port_mmio + SATA_INTERFACE_CFG_OFS);
2684 static void mv_reset_channel(struct mv_host_priv *hpriv, void __iomem *mmio,
2685 unsigned int port_no)
2687 void __iomem *port_mmio = mv_port_base(mmio, port_no);
2690 * The datasheet warns against setting EDMA_RESET when EDMA is active
2691 * (but doesn't say what the problem might be). So we first try
2692 * to disable the EDMA engine before doing the EDMA_RESET operation.
2694 mv_stop_edma_engine(port_mmio);
2695 writelfl(EDMA_RESET, port_mmio + EDMA_CMD_OFS);
2697 if (!IS_GEN_I(hpriv)) {
2698 /* Enable 3.0gb/s link speed: this survives EDMA_RESET */
2699 mv_setup_ifcfg(port_mmio, 1);
2702 * Strobing EDMA_RESET here causes a hard reset of the SATA transport,
2703 * link, and physical layers. It resets all SATA interface registers
2704 * (except for SATA_INTERFACE_CFG), and issues a COMRESET to the dev.
2706 writelfl(EDMA_RESET, port_mmio + EDMA_CMD_OFS);
2707 udelay(25); /* allow reset propagation */
2708 writelfl(0, port_mmio + EDMA_CMD_OFS);
2710 hpriv->ops->phy_errata(hpriv, mmio, port_no);
2712 if (IS_GEN_I(hpriv))
2716 static void mv_pmp_select(struct ata_port *ap, int pmp)
2718 if (sata_pmp_supported(ap)) {
2719 void __iomem *port_mmio = mv_ap_base(ap);
2720 u32 reg = readl(port_mmio + SATA_IFCTL_OFS);
2721 int old = reg & 0xf;
2724 reg = (reg & ~0xf) | pmp;
2725 writelfl(reg, port_mmio + SATA_IFCTL_OFS);
2730 static int mv_pmp_hardreset(struct ata_link *link, unsigned int *class,
2731 unsigned long deadline)
2733 mv_pmp_select(link->ap, sata_srst_pmp(link));
2734 return sata_std_hardreset(link, class, deadline);
2737 static int mv_softreset(struct ata_link *link, unsigned int *class,
2738 unsigned long deadline)
2740 mv_pmp_select(link->ap, sata_srst_pmp(link));
2741 return ata_sff_softreset(link, class, deadline);
2744 static int mv_hardreset(struct ata_link *link, unsigned int *class,
2745 unsigned long deadline)
2747 struct ata_port *ap = link->ap;
2748 struct mv_host_priv *hpriv = ap->host->private_data;
2749 struct mv_port_priv *pp = ap->private_data;
2750 void __iomem *mmio = hpriv->base;
2751 int rc, attempts = 0, extra = 0;
2755 mv_reset_channel(hpriv, mmio, ap->port_no);
2756 pp->pp_flags &= ~MV_PP_FLAG_EDMA_EN;
2758 /* Workaround for errata FEr SATA#10 (part 2) */
2760 const unsigned long *timing =
2761 sata_ehc_deb_timing(&link->eh_context);
2763 rc = sata_link_hardreset(link, timing, deadline + extra,
2765 rc = online ? -EAGAIN : rc;
2768 sata_scr_read(link, SCR_STATUS, &sstatus);
2769 if (!IS_GEN_I(hpriv) && ++attempts >= 5 && sstatus == 0x121) {
2770 /* Force 1.5gb/s link speed and try again */
2771 mv_setup_ifcfg(mv_ap_base(ap), 0);
2772 if (time_after(jiffies + HZ, deadline))
2773 extra = HZ; /* only extend it once, max */
2775 } while (sstatus != 0x0 && sstatus != 0x113 && sstatus != 0x123);
2780 static void mv_eh_freeze(struct ata_port *ap)
2783 mv_enable_port_irqs(ap, 0);
2786 static void mv_eh_thaw(struct ata_port *ap)
2788 struct mv_host_priv *hpriv = ap->host->private_data;
2789 unsigned int port = ap->port_no;
2790 unsigned int hardport = mv_hardport_from_port(port);
2791 void __iomem *hc_mmio = mv_hc_base_from_port(hpriv->base, port);
2792 void __iomem *port_mmio = mv_ap_base(ap);
2795 /* clear EDMA errors on this port */
2796 writel(0, port_mmio + EDMA_ERR_IRQ_CAUSE_OFS);
2798 /* clear pending irq events */
2799 hc_irq_cause = readl(hc_mmio + HC_IRQ_CAUSE_OFS);
2800 hc_irq_cause &= ~((DEV_IRQ | DMA_IRQ) << hardport);
2801 writelfl(hc_irq_cause, hc_mmio + HC_IRQ_CAUSE_OFS);
2803 mv_enable_port_irqs(ap, DONE_IRQ | ERR_IRQ);
2807 * mv_port_init - Perform some early initialization on a single port.
2808 * @port: libata data structure storing shadow register addresses
2809 * @port_mmio: base address of the port
2811 * Initialize shadow register mmio addresses, clear outstanding
2812 * interrupts on the port, and unmask interrupts for the future
2813 * start of the port.
2816 * Inherited from caller.
2818 static void mv_port_init(struct ata_ioports *port, void __iomem *port_mmio)
2820 void __iomem *shd_base = port_mmio + SHD_BLK_OFS;
2823 /* PIO related setup
2825 port->data_addr = shd_base + (sizeof(u32) * ATA_REG_DATA);
2827 port->feature_addr = shd_base + (sizeof(u32) * ATA_REG_ERR);
2828 port->nsect_addr = shd_base + (sizeof(u32) * ATA_REG_NSECT);
2829 port->lbal_addr = shd_base + (sizeof(u32) * ATA_REG_LBAL);
2830 port->lbam_addr = shd_base + (sizeof(u32) * ATA_REG_LBAM);
2831 port->lbah_addr = shd_base + (sizeof(u32) * ATA_REG_LBAH);
2832 port->device_addr = shd_base + (sizeof(u32) * ATA_REG_DEVICE);
2834 port->command_addr = shd_base + (sizeof(u32) * ATA_REG_STATUS);
2835 /* special case: control/altstatus doesn't have ATA_REG_ address */
2836 port->altstatus_addr = port->ctl_addr = shd_base + SHD_CTL_AST_OFS;
2839 port->cmd_addr = port->bmdma_addr = port->scr_addr = NULL;
2841 /* Clear any currently outstanding port interrupt conditions */
2842 serr_ofs = mv_scr_offset(SCR_ERROR);
2843 writelfl(readl(port_mmio + serr_ofs), port_mmio + serr_ofs);
2844 writelfl(0, port_mmio + EDMA_ERR_IRQ_CAUSE_OFS);
2846 /* unmask all non-transient EDMA error interrupts */
2847 writelfl(~EDMA_ERR_IRQ_TRANSIENT, port_mmio + EDMA_ERR_IRQ_MASK_OFS);
2849 VPRINTK("EDMA cfg=0x%08x EDMA IRQ err cause/mask=0x%08x/0x%08x\n",
2850 readl(port_mmio + EDMA_CFG_OFS),
2851 readl(port_mmio + EDMA_ERR_IRQ_CAUSE_OFS),
2852 readl(port_mmio + EDMA_ERR_IRQ_MASK_OFS));
2855 static unsigned int mv_in_pcix_mode(struct ata_host *host)
2857 struct mv_host_priv *hpriv = host->private_data;
2858 void __iomem *mmio = hpriv->base;
2861 if (!HAS_PCI(host) || !IS_PCIE(hpriv))
2862 return 0; /* not PCI-X capable */
2863 reg = readl(mmio + MV_PCI_MODE_OFS);
2864 if ((reg & MV_PCI_MODE_MASK) == 0)
2865 return 0; /* conventional PCI mode */
2866 return 1; /* chip is in PCI-X mode */
2869 static int mv_pci_cut_through_okay(struct ata_host *host)
2871 struct mv_host_priv *hpriv = host->private_data;
2872 void __iomem *mmio = hpriv->base;
2875 if (!mv_in_pcix_mode(host)) {
2876 reg = readl(mmio + PCI_COMMAND_OFS);
2877 if (reg & PCI_COMMAND_MRDTRIG)
2878 return 0; /* not okay */
2880 return 1; /* okay */
2883 static int mv_chip_id(struct ata_host *host, unsigned int board_idx)
2885 struct pci_dev *pdev = to_pci_dev(host->dev);
2886 struct mv_host_priv *hpriv = host->private_data;
2887 u32 hp_flags = hpriv->hp_flags;
2889 switch (board_idx) {
2891 hpriv->ops = &mv5xxx_ops;
2892 hp_flags |= MV_HP_GEN_I;
2894 switch (pdev->revision) {
2896 hp_flags |= MV_HP_ERRATA_50XXB0;
2899 hp_flags |= MV_HP_ERRATA_50XXB2;
2902 dev_printk(KERN_WARNING, &pdev->dev,
2903 "Applying 50XXB2 workarounds to unknown rev\n");
2904 hp_flags |= MV_HP_ERRATA_50XXB2;
2911 hpriv->ops = &mv5xxx_ops;
2912 hp_flags |= MV_HP_GEN_I;
2914 switch (pdev->revision) {
2916 hp_flags |= MV_HP_ERRATA_50XXB0;
2919 hp_flags |= MV_HP_ERRATA_50XXB2;
2922 dev_printk(KERN_WARNING, &pdev->dev,
2923 "Applying B2 workarounds to unknown rev\n");
2924 hp_flags |= MV_HP_ERRATA_50XXB2;
2931 hpriv->ops = &mv6xxx_ops;
2932 hp_flags |= MV_HP_GEN_II;
2934 switch (pdev->revision) {
2936 hp_flags |= MV_HP_ERRATA_60X1B2;
2939 hp_flags |= MV_HP_ERRATA_60X1C0;
2942 dev_printk(KERN_WARNING, &pdev->dev,
2943 "Applying B2 workarounds to unknown rev\n");
2944 hp_flags |= MV_HP_ERRATA_60X1B2;
2950 hp_flags |= MV_HP_PCIE | MV_HP_CUT_THROUGH;
2951 if (pdev->vendor == PCI_VENDOR_ID_TTI &&
2952 (pdev->device == 0x2300 || pdev->device == 0x2310))
2955 * Highpoint RocketRAID PCIe 23xx series cards:
2957 * Unconfigured drives are treated as "Legacy"
2958 * by the BIOS, and it overwrites sector 8 with
2959 * a "Lgcy" metadata block prior to Linux boot.
2961 * Configured drives (RAID or JBOD) leave sector 8
2962 * alone, but instead overwrite a high numbered
2963 * sector for the RAID metadata. This sector can
2964 * be determined exactly, by truncating the physical
2965 * drive capacity to a nice even GB value.
2967 * RAID metadata is at: (dev->n_sectors & ~0xfffff)
2969 * Warn the user, lest they think we're just buggy.
2971 printk(KERN_WARNING DRV_NAME ": Highpoint RocketRAID"
2972 " BIOS CORRUPTS DATA on all attached drives,"
2973 " regardless of if/how they are configured."
2975 printk(KERN_WARNING DRV_NAME ": For data safety, do not"
2976 " use sectors 8-9 on \"Legacy\" drives,"
2977 " and avoid the final two gigabytes on"
2978 " all RocketRAID BIOS initialized drives.\n");
2982 hpriv->ops = &mv6xxx_ops;
2983 hp_flags |= MV_HP_GEN_IIE;
2984 if (board_idx == chip_6042 && mv_pci_cut_through_okay(host))
2985 hp_flags |= MV_HP_CUT_THROUGH;
2987 switch (pdev->revision) {
2989 hp_flags |= MV_HP_ERRATA_XX42A0;
2992 hp_flags |= MV_HP_ERRATA_60X1C0;
2995 dev_printk(KERN_WARNING, &pdev->dev,
2996 "Applying 60X1C0 workarounds to unknown rev\n");
2997 hp_flags |= MV_HP_ERRATA_60X1C0;
3002 hpriv->ops = &mv_soc_ops;
3003 hp_flags |= MV_HP_ERRATA_60X1C0;
3007 dev_printk(KERN_ERR, host->dev,
3008 "BUG: invalid board index %u\n", board_idx);
3012 hpriv->hp_flags = hp_flags;
3013 if (hp_flags & MV_HP_PCIE) {
3014 hpriv->irq_cause_ofs = PCIE_IRQ_CAUSE_OFS;
3015 hpriv->irq_mask_ofs = PCIE_IRQ_MASK_OFS;
3016 hpriv->unmask_all_irqs = PCIE_UNMASK_ALL_IRQS;
3018 hpriv->irq_cause_ofs = PCI_IRQ_CAUSE_OFS;
3019 hpriv->irq_mask_ofs = PCI_IRQ_MASK_OFS;
3020 hpriv->unmask_all_irqs = PCI_UNMASK_ALL_IRQS;
3027 * mv_init_host - Perform some early initialization of the host.
3028 * @host: ATA host to initialize
3029 * @board_idx: controller index
3031 * If possible, do an early global reset of the host. Then do
3032 * our port init and clear/unmask all/relevant host interrupts.
3035 * Inherited from caller.
3037 static int mv_init_host(struct ata_host *host, unsigned int board_idx)
3039 int rc = 0, n_hc, port, hc;
3040 struct mv_host_priv *hpriv = host->private_data;
3041 void __iomem *mmio = hpriv->base;
3043 rc = mv_chip_id(host, board_idx);
3047 if (HAS_PCI(host)) {
3048 hpriv->main_irq_cause_addr = mmio + PCI_HC_MAIN_IRQ_CAUSE_OFS;
3049 hpriv->main_irq_mask_addr = mmio + PCI_HC_MAIN_IRQ_MASK_OFS;
3051 hpriv->main_irq_cause_addr = mmio + SOC_HC_MAIN_IRQ_CAUSE_OFS;
3052 hpriv->main_irq_mask_addr = mmio + SOC_HC_MAIN_IRQ_MASK_OFS;
3055 /* global interrupt mask: 0 == mask everything */
3056 mv_set_main_irq_mask(host, ~0, 0);
3058 n_hc = mv_get_hc_count(host->ports[0]->flags);
3060 for (port = 0; port < host->n_ports; port++)
3061 hpriv->ops->read_preamp(hpriv, port, mmio);
3063 rc = hpriv->ops->reset_hc(hpriv, mmio, n_hc);
3067 hpriv->ops->reset_flash(hpriv, mmio);
3068 hpriv->ops->reset_bus(host, mmio);
3069 hpriv->ops->enable_leds(hpriv, mmio);
3071 for (port = 0; port < host->n_ports; port++) {
3072 struct ata_port *ap = host->ports[port];
3073 void __iomem *port_mmio = mv_port_base(mmio, port);
3075 mv_port_init(&ap->ioaddr, port_mmio);
3078 if (HAS_PCI(host)) {
3079 unsigned int offset = port_mmio - mmio;
3080 ata_port_pbar_desc(ap, MV_PRIMARY_BAR, -1, "mmio");
3081 ata_port_pbar_desc(ap, MV_PRIMARY_BAR, offset, "port");
3086 for (hc = 0; hc < n_hc; hc++) {
3087 void __iomem *hc_mmio = mv_hc_base(mmio, hc);
3089 VPRINTK("HC%i: HC config=0x%08x HC IRQ cause "
3090 "(before clear)=0x%08x\n", hc,
3091 readl(hc_mmio + HC_CFG_OFS),
3092 readl(hc_mmio + HC_IRQ_CAUSE_OFS));
3094 /* Clear any currently outstanding hc interrupt conditions */
3095 writelfl(0, hc_mmio + HC_IRQ_CAUSE_OFS);
3098 if (HAS_PCI(host)) {
3099 /* Clear any currently outstanding host interrupt conditions */
3100 writelfl(0, mmio + hpriv->irq_cause_ofs);
3102 /* and unmask interrupt generation for host regs */
3103 writelfl(hpriv->unmask_all_irqs, mmio + hpriv->irq_mask_ofs);
3106 * enable only global host interrupts for now.
3107 * The per-port interrupts get done later as ports are set up.
3109 mv_set_main_irq_mask(host, 0, PCI_ERR);
3115 static int mv_create_dma_pools(struct mv_host_priv *hpriv, struct device *dev)
3117 hpriv->crqb_pool = dmam_pool_create("crqb_q", dev, MV_CRQB_Q_SZ,
3119 if (!hpriv->crqb_pool)
3122 hpriv->crpb_pool = dmam_pool_create("crpb_q", dev, MV_CRPB_Q_SZ,
3124 if (!hpriv->crpb_pool)
3127 hpriv->sg_tbl_pool = dmam_pool_create("sg_tbl", dev, MV_SG_TBL_SZ,
3129 if (!hpriv->sg_tbl_pool)
3135 static void mv_conf_mbus_windows(struct mv_host_priv *hpriv,
3136 struct mbus_dram_target_info *dram)
3140 for (i = 0; i < 4; i++) {
3141 writel(0, hpriv->base + WINDOW_CTRL(i));
3142 writel(0, hpriv->base + WINDOW_BASE(i));
3145 for (i = 0; i < dram->num_cs; i++) {
3146 struct mbus_dram_window *cs = dram->cs + i;
3148 writel(((cs->size - 1) & 0xffff0000) |
3149 (cs->mbus_attr << 8) |
3150 (dram->mbus_dram_target_id << 4) | 1,
3151 hpriv->base + WINDOW_CTRL(i));
3152 writel(cs->base, hpriv->base + WINDOW_BASE(i));
3157 * mv_platform_probe - handle a positive probe of an soc Marvell
3159 * @pdev: platform device found
3162 * Inherited from caller.
3164 static int mv_platform_probe(struct platform_device *pdev)
3166 static int printed_version;
3167 const struct mv_sata_platform_data *mv_platform_data;
3168 const struct ata_port_info *ppi[] =
3169 { &mv_port_info[chip_soc], NULL };
3170 struct ata_host *host;
3171 struct mv_host_priv *hpriv;
3172 struct resource *res;
3175 if (!printed_version++)
3176 dev_printk(KERN_INFO, &pdev->dev, "version " DRV_VERSION "\n");
3179 * Simple resource validation ..
3181 if (unlikely(pdev->num_resources != 2)) {
3182 dev_err(&pdev->dev, "invalid number of resources\n");
3187 * Get the register base first
3189 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
3194 mv_platform_data = pdev->dev.platform_data;
3195 n_ports = mv_platform_data->n_ports;
3197 host = ata_host_alloc_pinfo(&pdev->dev, ppi, n_ports);
3198 hpriv = devm_kzalloc(&pdev->dev, sizeof(*hpriv), GFP_KERNEL);
3200 if (!host || !hpriv)
3202 host->private_data = hpriv;
3203 hpriv->n_ports = n_ports;
3206 hpriv->base = devm_ioremap(&pdev->dev, res->start,
3207 res->end - res->start + 1);
3208 hpriv->base -= MV_SATAHC0_REG_BASE;
3211 * (Re-)program MBUS remapping windows if we are asked to.
3213 if (mv_platform_data->dram != NULL)
3214 mv_conf_mbus_windows(hpriv, mv_platform_data->dram);
3216 rc = mv_create_dma_pools(hpriv, &pdev->dev);
3220 /* initialize adapter */
3221 rc = mv_init_host(host, chip_soc);
3225 dev_printk(KERN_INFO, &pdev->dev,
3226 "slots %u ports %d\n", (unsigned)MV_MAX_Q_DEPTH,
3229 return ata_host_activate(host, platform_get_irq(pdev, 0), mv_interrupt,
3230 IRQF_SHARED, &mv6_sht);
3235 * mv_platform_remove - unplug a platform interface
3236 * @pdev: platform device
3238 * A platform bus SATA device has been unplugged. Perform the needed
3239 * cleanup. Also called on module unload for any active devices.
3241 static int __devexit mv_platform_remove(struct platform_device *pdev)
3243 struct device *dev = &pdev->dev;
3244 struct ata_host *host = dev_get_drvdata(dev);
3246 ata_host_detach(host);
3250 static struct platform_driver mv_platform_driver = {
3251 .probe = mv_platform_probe,
3252 .remove = __devexit_p(mv_platform_remove),
3255 .owner = THIS_MODULE,
3261 static int mv_pci_init_one(struct pci_dev *pdev,
3262 const struct pci_device_id *ent);
3265 static struct pci_driver mv_pci_driver = {
3267 .id_table = mv_pci_tbl,
3268 .probe = mv_pci_init_one,
3269 .remove = ata_pci_remove_one,
3275 static int msi; /* Use PCI msi; either zero (off, default) or non-zero */
3278 /* move to PCI layer or libata core? */
3279 static int pci_go_64(struct pci_dev *pdev)
3283 if (!pci_set_dma_mask(pdev, DMA_64BIT_MASK)) {
3284 rc = pci_set_consistent_dma_mask(pdev, DMA_64BIT_MASK);
3286 rc = pci_set_consistent_dma_mask(pdev, DMA_32BIT_MASK);
3288 dev_printk(KERN_ERR, &pdev->dev,
3289 "64-bit DMA enable failed\n");
3294 rc = pci_set_dma_mask(pdev, DMA_32BIT_MASK);
3296 dev_printk(KERN_ERR, &pdev->dev,
3297 "32-bit DMA enable failed\n");
3300 rc = pci_set_consistent_dma_mask(pdev, DMA_32BIT_MASK);
3302 dev_printk(KERN_ERR, &pdev->dev,
3303 "32-bit consistent DMA enable failed\n");
3312 * mv_print_info - Dump key info to kernel log for perusal.
3313 * @host: ATA host to print info about
3315 * FIXME: complete this.
3318 * Inherited from caller.
3320 static void mv_print_info(struct ata_host *host)
3322 struct pci_dev *pdev = to_pci_dev(host->dev);
3323 struct mv_host_priv *hpriv = host->private_data;
3325 const char *scc_s, *gen;
3327 /* Use this to determine the HW stepping of the chip so we know
3328 * what errata to workaround
3330 pci_read_config_byte(pdev, PCI_CLASS_DEVICE, &scc);
3333 else if (scc == 0x01)
3338 if (IS_GEN_I(hpriv))
3340 else if (IS_GEN_II(hpriv))
3342 else if (IS_GEN_IIE(hpriv))
3347 dev_printk(KERN_INFO, &pdev->dev,
3348 "Gen-%s %u slots %u ports %s mode IRQ via %s\n",
3349 gen, (unsigned)MV_MAX_Q_DEPTH, host->n_ports,
3350 scc_s, (MV_HP_FLAG_MSI & hpriv->hp_flags) ? "MSI" : "INTx");
3354 * mv_pci_init_one - handle a positive probe of a PCI Marvell host
3355 * @pdev: PCI device found
3356 * @ent: PCI device ID entry for the matched host
3359 * Inherited from caller.
3361 static int mv_pci_init_one(struct pci_dev *pdev,
3362 const struct pci_device_id *ent)
3364 static int printed_version;
3365 unsigned int board_idx = (unsigned int)ent->driver_data;
3366 const struct ata_port_info *ppi[] = { &mv_port_info[board_idx], NULL };
3367 struct ata_host *host;
3368 struct mv_host_priv *hpriv;
3371 if (!printed_version++)
3372 dev_printk(KERN_INFO, &pdev->dev, "version " DRV_VERSION "\n");
3375 n_ports = mv_get_hc_count(ppi[0]->flags) * MV_PORTS_PER_HC;
3377 host = ata_host_alloc_pinfo(&pdev->dev, ppi, n_ports);
3378 hpriv = devm_kzalloc(&pdev->dev, sizeof(*hpriv), GFP_KERNEL);
3379 if (!host || !hpriv)
3381 host->private_data = hpriv;
3382 hpriv->n_ports = n_ports;
3384 /* acquire resources */
3385 rc = pcim_enable_device(pdev);
3389 rc = pcim_iomap_regions(pdev, 1 << MV_PRIMARY_BAR, DRV_NAME);
3391 pcim_pin_device(pdev);
3394 host->iomap = pcim_iomap_table(pdev);
3395 hpriv->base = host->iomap[MV_PRIMARY_BAR];
3397 rc = pci_go_64(pdev);
3401 rc = mv_create_dma_pools(hpriv, &pdev->dev);
3405 /* initialize adapter */
3406 rc = mv_init_host(host, board_idx);
3410 /* Enable interrupts */
3411 if (msi && pci_enable_msi(pdev))
3414 mv_dump_pci_cfg(pdev, 0x68);
3415 mv_print_info(host);
3417 pci_set_master(pdev);
3418 pci_try_set_mwi(pdev);
3419 return ata_host_activate(host, pdev->irq, mv_interrupt, IRQF_SHARED,
3420 IS_GEN_I(hpriv) ? &mv5_sht : &mv6_sht);
3424 static int mv_platform_probe(struct platform_device *pdev);
3425 static int __devexit mv_platform_remove(struct platform_device *pdev);
3427 static int __init mv_init(void)
3431 rc = pci_register_driver(&mv_pci_driver);
3435 rc = platform_driver_register(&mv_platform_driver);
3439 pci_unregister_driver(&mv_pci_driver);
3444 static void __exit mv_exit(void)
3447 pci_unregister_driver(&mv_pci_driver);
3449 platform_driver_unregister(&mv_platform_driver);
3452 MODULE_AUTHOR("Brett Russ");
3453 MODULE_DESCRIPTION("SCSI low-level driver for Marvell SATA controllers");
3454 MODULE_LICENSE("GPL");
3455 MODULE_DEVICE_TABLE(pci, mv_pci_tbl);
3456 MODULE_VERSION(DRV_VERSION);
3457 MODULE_ALIAS("platform:" DRV_NAME);
3460 module_param(msi, int, 0444);
3461 MODULE_PARM_DESC(msi, "Enable use of PCI MSI (0=off, 1=on)");
3464 module_init(mv_init);
3465 module_exit(mv_exit);