2 * sata_mv.c - Marvell SATA support
4 * Copyright 2005: EMC Corporation, all rights reserved.
5 * Copyright 2005 Red Hat, Inc. All rights reserved.
7 * Please ALWAYS copy linux-ide@vger.kernel.org on emails.
9 * This program is free software; you can redistribute it and/or modify
10 * it under the terms of the GNU General Public License as published by
11 * the Free Software Foundation; version 2 of the License.
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
18 * You should have received a copy of the GNU General Public License
19 * along with this program; if not, write to the Free Software
20 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
24 #include <linux/kernel.h>
25 #include <linux/module.h>
26 #include <linux/pci.h>
27 #include <linux/init.h>
28 #include <linux/blkdev.h>
29 #include <linux/delay.h>
30 #include <linux/interrupt.h>
31 #include <linux/dma-mapping.h>
32 #include <linux/device.h>
33 #include <scsi/scsi_host.h>
34 #include <scsi/scsi_cmnd.h>
35 #include <linux/libata.h>
37 #define DRV_NAME "sata_mv"
38 #define DRV_VERSION "0.8"
41 /* BAR's are enumerated in terms of pci_resource_start() terms */
42 MV_PRIMARY_BAR = 0, /* offset 0x10: memory space */
43 MV_IO_BAR = 2, /* offset 0x18: IO space */
44 MV_MISC_BAR = 3, /* offset 0x1c: FLASH, NVRAM, SRAM */
46 MV_MAJOR_REG_AREA_SZ = 0x10000, /* 64KB */
47 MV_MINOR_REG_AREA_SZ = 0x2000, /* 8KB */
50 MV_IRQ_COAL_REG_BASE = 0x18000, /* 6xxx part only */
51 MV_IRQ_COAL_CAUSE = (MV_IRQ_COAL_REG_BASE + 0x08),
52 MV_IRQ_COAL_CAUSE_LO = (MV_IRQ_COAL_REG_BASE + 0x88),
53 MV_IRQ_COAL_CAUSE_HI = (MV_IRQ_COAL_REG_BASE + 0x8c),
54 MV_IRQ_COAL_THRESHOLD = (MV_IRQ_COAL_REG_BASE + 0xcc),
55 MV_IRQ_COAL_TIME_THRESHOLD = (MV_IRQ_COAL_REG_BASE + 0xd0),
57 MV_SATAHC0_REG_BASE = 0x20000,
58 MV_FLASH_CTL = 0x1046c,
59 MV_GPIO_PORT_CTL = 0x104f0,
60 MV_RESET_CFG = 0x180d8,
62 MV_PCI_REG_SZ = MV_MAJOR_REG_AREA_SZ,
63 MV_SATAHC_REG_SZ = MV_MAJOR_REG_AREA_SZ,
64 MV_SATAHC_ARBTR_REG_SZ = MV_MINOR_REG_AREA_SZ, /* arbiter */
65 MV_PORT_REG_SZ = MV_MINOR_REG_AREA_SZ,
67 MV_USE_Q_DEPTH = ATA_DEF_QUEUE,
70 MV_MAX_Q_DEPTH_MASK = MV_MAX_Q_DEPTH - 1,
72 /* CRQB needs alignment on a 1KB boundary. Size == 1KB
73 * CRPB needs alignment on a 256B boundary. Size == 256B
74 * SG count of 176 leads to MV_PORT_PRIV_DMA_SZ == 4KB
75 * ePRD (SG) entries need alignment on a 16B boundary. Size == 16B
77 MV_CRQB_Q_SZ = (32 * MV_MAX_Q_DEPTH),
78 MV_CRPB_Q_SZ = (8 * MV_MAX_Q_DEPTH),
80 MV_SG_TBL_SZ = (16 * MV_MAX_SG_CT),
81 MV_PORT_PRIV_DMA_SZ = (MV_CRQB_Q_SZ + MV_CRPB_Q_SZ + MV_SG_TBL_SZ),
84 /* == (port / MV_PORTS_PER_HC) to determine HC from 0-7 port */
86 /* == (port % MV_PORTS_PER_HC) to determine hard port from 0-7 port */
90 MV_FLAG_DUAL_HC = (1 << 30), /* two SATA Host Controllers */
91 MV_FLAG_IRQ_COALESCE = (1 << 29), /* IRQ coalescing capability */
92 MV_COMMON_FLAGS = (ATA_FLAG_SATA | ATA_FLAG_NO_LEGACY |
93 ATA_FLAG_SATA_RESET | ATA_FLAG_MMIO |
94 ATA_FLAG_NO_ATAPI | ATA_FLAG_PIO_POLLING),
95 MV_6XXX_FLAGS = MV_FLAG_IRQ_COALESCE,
97 CRQB_FLAG_READ = (1 << 0),
99 CRQB_CMD_ADDR_SHIFT = 8,
100 CRQB_CMD_CS = (0x2 << 11),
101 CRQB_CMD_LAST = (1 << 15),
103 CRPB_FLAG_STATUS_SHIFT = 8,
105 EPRD_FLAG_END_OF_TBL = (1 << 31),
107 /* PCI interface registers */
109 PCI_COMMAND_OFS = 0xc00,
111 PCI_MAIN_CMD_STS_OFS = 0xd30,
112 STOP_PCI_MASTER = (1 << 2),
113 PCI_MASTER_EMPTY = (1 << 3),
114 GLOB_SFT_RST = (1 << 4),
117 MV_PCI_EXP_ROM_BAR_CTL = 0xd2c,
118 MV_PCI_DISC_TIMER = 0xd04,
119 MV_PCI_MSI_TRIGGER = 0xc38,
120 MV_PCI_SERR_MASK = 0xc28,
121 MV_PCI_XBAR_TMOUT = 0x1d04,
122 MV_PCI_ERR_LOW_ADDRESS = 0x1d40,
123 MV_PCI_ERR_HIGH_ADDRESS = 0x1d44,
124 MV_PCI_ERR_ATTRIBUTE = 0x1d48,
125 MV_PCI_ERR_COMMAND = 0x1d50,
127 PCI_IRQ_CAUSE_OFS = 0x1d58,
128 PCI_IRQ_MASK_OFS = 0x1d5c,
129 PCI_UNMASK_ALL_IRQS = 0x7fffff, /* bits 22-0 */
131 HC_MAIN_IRQ_CAUSE_OFS = 0x1d60,
132 HC_MAIN_IRQ_MASK_OFS = 0x1d64,
133 PORT0_ERR = (1 << 0), /* shift by port # */
134 PORT0_DONE = (1 << 1), /* shift by port # */
135 HC0_IRQ_PEND = 0x1ff, /* bits 0-8 = HC0's ports */
136 HC_SHIFT = 9, /* bits 9-17 = HC1's ports */
138 TRAN_LO_DONE = (1 << 19), /* 6xxx: IRQ coalescing */
139 TRAN_HI_DONE = (1 << 20), /* 6xxx: IRQ coalescing */
140 PORTS_0_3_COAL_DONE = (1 << 8),
141 PORTS_4_7_COAL_DONE = (1 << 17),
142 PORTS_0_7_COAL_DONE = (1 << 21), /* 6xxx: IRQ coalescing */
143 GPIO_INT = (1 << 22),
144 SELF_INT = (1 << 23),
145 TWSI_INT = (1 << 24),
146 HC_MAIN_RSVD = (0x7f << 25), /* bits 31-25 */
147 HC_MAIN_RSVD_5 = (0x1fff << 19), /* bits 31-19 */
148 HC_MAIN_MASKED_IRQS = (TRAN_LO_DONE | TRAN_HI_DONE |
149 PORTS_0_7_COAL_DONE | GPIO_INT | TWSI_INT |
151 HC_MAIN_MASKED_IRQS_5 = (PORTS_0_3_COAL_DONE | PORTS_4_7_COAL_DONE |
154 /* SATAHC registers */
157 HC_IRQ_CAUSE_OFS = 0x14,
158 CRPB_DMA_DONE = (1 << 0), /* shift by port # */
159 HC_IRQ_COAL = (1 << 4), /* IRQ coalescing */
160 DEV_IRQ = (1 << 8), /* shift by port # */
162 /* Shadow block registers */
164 SHD_CTL_AST_OFS = 0x20, /* ofs from SHD_BLK_OFS */
167 SATA_STATUS_OFS = 0x300, /* ctrl, err regs follow status */
168 SATA_ACTIVE_OFS = 0x350,
175 SATA_INTERFACE_CTL = 0x050,
177 MV_M2_PREAMP_MASK = 0x7e0,
181 EDMA_CFG_Q_DEPTH = 0, /* queueing disabled */
182 EDMA_CFG_NCQ = (1 << 5),
183 EDMA_CFG_NCQ_GO_ON_ERR = (1 << 14), /* continue on error */
184 EDMA_CFG_RD_BRST_EXT = (1 << 11), /* read burst 512B */
185 EDMA_CFG_WR_BUFF_LEN = (1 << 13), /* write buffer 512B */
187 EDMA_ERR_IRQ_CAUSE_OFS = 0x8,
188 EDMA_ERR_IRQ_MASK_OFS = 0xc,
189 EDMA_ERR_D_PAR = (1 << 0),
190 EDMA_ERR_PRD_PAR = (1 << 1),
191 EDMA_ERR_DEV = (1 << 2),
192 EDMA_ERR_DEV_DCON = (1 << 3),
193 EDMA_ERR_DEV_CON = (1 << 4),
194 EDMA_ERR_SERR = (1 << 5),
195 EDMA_ERR_SELF_DIS = (1 << 7),
196 EDMA_ERR_BIST_ASYNC = (1 << 8),
197 EDMA_ERR_CRBQ_PAR = (1 << 9),
198 EDMA_ERR_CRPB_PAR = (1 << 10),
199 EDMA_ERR_INTRL_PAR = (1 << 11),
200 EDMA_ERR_IORDY = (1 << 12),
201 EDMA_ERR_LNK_CTRL_RX = (0xf << 13),
202 EDMA_ERR_LNK_CTRL_RX_2 = (1 << 15),
203 EDMA_ERR_LNK_DATA_RX = (0xf << 17),
204 EDMA_ERR_LNK_CTRL_TX = (0x1f << 21),
205 EDMA_ERR_LNK_DATA_TX = (0x1f << 26),
206 EDMA_ERR_TRANS_PROTO = (1 << 31),
207 EDMA_ERR_FATAL = (EDMA_ERR_D_PAR | EDMA_ERR_PRD_PAR |
208 EDMA_ERR_DEV_DCON | EDMA_ERR_CRBQ_PAR |
209 EDMA_ERR_CRPB_PAR | EDMA_ERR_INTRL_PAR |
210 EDMA_ERR_IORDY | EDMA_ERR_LNK_CTRL_RX_2 |
211 EDMA_ERR_LNK_DATA_RX |
212 EDMA_ERR_LNK_DATA_TX |
213 EDMA_ERR_TRANS_PROTO),
215 EDMA_REQ_Q_BASE_HI_OFS = 0x10,
216 EDMA_REQ_Q_IN_PTR_OFS = 0x14, /* also contains BASE_LO */
218 EDMA_REQ_Q_OUT_PTR_OFS = 0x18,
219 EDMA_REQ_Q_PTR_SHIFT = 5,
221 EDMA_RSP_Q_BASE_HI_OFS = 0x1c,
222 EDMA_RSP_Q_IN_PTR_OFS = 0x20,
223 EDMA_RSP_Q_OUT_PTR_OFS = 0x24, /* also contains BASE_LO */
224 EDMA_RSP_Q_PTR_SHIFT = 3,
231 EDMA_IORDY_TMOUT = 0x34,
234 /* Host private flags (hp_flags) */
235 MV_HP_FLAG_MSI = (1 << 0),
236 MV_HP_ERRATA_50XXB0 = (1 << 1),
237 MV_HP_ERRATA_50XXB2 = (1 << 2),
238 MV_HP_ERRATA_60X1B2 = (1 << 3),
239 MV_HP_ERRATA_60X1C0 = (1 << 4),
240 MV_HP_ERRATA_XX42A0 = (1 << 5),
241 MV_HP_50XX = (1 << 6),
242 MV_HP_GEN_IIE = (1 << 7),
244 /* Port private flags (pp_flags) */
245 MV_PP_FLAG_EDMA_EN = (1 << 0),
246 MV_PP_FLAG_EDMA_DS_ACT = (1 << 1),
249 #define IS_50XX(hpriv) ((hpriv)->hp_flags & MV_HP_50XX)
250 #define IS_60XX(hpriv) (((hpriv)->hp_flags & MV_HP_50XX) == 0)
251 #define IS_GEN_I(hpriv) IS_50XX(hpriv)
252 #define IS_GEN_II(hpriv) IS_60XX(hpriv)
253 #define IS_GEN_IIE(hpriv) ((hpriv)->hp_flags & MV_HP_GEN_IIE)
256 MV_DMA_BOUNDARY = 0xffffffffU,
258 EDMA_REQ_Q_BASE_LO_MASK = 0xfffffc00U,
260 EDMA_RSP_Q_BASE_LO_MASK = 0xffffff00U,
273 /* Command ReQuest Block: 32B */
289 /* Command ResPonse Block: 8B */
296 /* EDMA Physical Region Descriptor (ePRD); A.K.A. SG */
304 struct mv_port_priv {
305 struct mv_crqb *crqb;
307 struct mv_crpb *crpb;
309 struct mv_sg *sg_tbl;
310 dma_addr_t sg_tbl_dma;
314 struct mv_port_signal {
321 void (*phy_errata)(struct mv_host_priv *hpriv, void __iomem *mmio,
323 void (*enable_leds)(struct mv_host_priv *hpriv, void __iomem *mmio);
324 void (*read_preamp)(struct mv_host_priv *hpriv, int idx,
326 int (*reset_hc)(struct mv_host_priv *hpriv, void __iomem *mmio,
328 void (*reset_flash)(struct mv_host_priv *hpriv, void __iomem *mmio);
329 void (*reset_bus)(struct pci_dev *pdev, void __iomem *mmio);
332 struct mv_host_priv {
334 struct mv_port_signal signal[8];
335 const struct mv_hw_ops *ops;
338 static void mv_irq_clear(struct ata_port *ap);
339 static u32 mv_scr_read(struct ata_port *ap, unsigned int sc_reg_in);
340 static void mv_scr_write(struct ata_port *ap, unsigned int sc_reg_in, u32 val);
341 static u32 mv5_scr_read(struct ata_port *ap, unsigned int sc_reg_in);
342 static void mv5_scr_write(struct ata_port *ap, unsigned int sc_reg_in, u32 val);
343 static void mv_phy_reset(struct ata_port *ap);
344 static void __mv_phy_reset(struct ata_port *ap, int can_sleep);
345 static int mv_port_start(struct ata_port *ap);
346 static void mv_port_stop(struct ata_port *ap);
347 static void mv_qc_prep(struct ata_queued_cmd *qc);
348 static void mv_qc_prep_iie(struct ata_queued_cmd *qc);
349 static unsigned int mv_qc_issue(struct ata_queued_cmd *qc);
350 static irqreturn_t mv_interrupt(int irq, void *dev_instance);
351 static void mv_eng_timeout(struct ata_port *ap);
352 static int mv_init_one(struct pci_dev *pdev, const struct pci_device_id *ent);
354 static void mv5_phy_errata(struct mv_host_priv *hpriv, void __iomem *mmio,
356 static void mv5_enable_leds(struct mv_host_priv *hpriv, void __iomem *mmio);
357 static void mv5_read_preamp(struct mv_host_priv *hpriv, int idx,
359 static int mv5_reset_hc(struct mv_host_priv *hpriv, void __iomem *mmio,
361 static void mv5_reset_flash(struct mv_host_priv *hpriv, void __iomem *mmio);
362 static void mv5_reset_bus(struct pci_dev *pdev, void __iomem *mmio);
364 static void mv6_phy_errata(struct mv_host_priv *hpriv, void __iomem *mmio,
366 static void mv6_enable_leds(struct mv_host_priv *hpriv, void __iomem *mmio);
367 static void mv6_read_preamp(struct mv_host_priv *hpriv, int idx,
369 static int mv6_reset_hc(struct mv_host_priv *hpriv, void __iomem *mmio,
371 static void mv6_reset_flash(struct mv_host_priv *hpriv, void __iomem *mmio);
372 static void mv_reset_pci_bus(struct pci_dev *pdev, void __iomem *mmio);
373 static void mv_channel_reset(struct mv_host_priv *hpriv, void __iomem *mmio,
374 unsigned int port_no);
375 static void mv_stop_and_reset(struct ata_port *ap);
377 static struct scsi_host_template mv_sht = {
378 .module = THIS_MODULE,
380 .ioctl = ata_scsi_ioctl,
381 .queuecommand = ata_scsi_queuecmd,
382 .can_queue = MV_USE_Q_DEPTH,
383 .this_id = ATA_SHT_THIS_ID,
384 .sg_tablesize = MV_MAX_SG_CT,
385 .cmd_per_lun = ATA_SHT_CMD_PER_LUN,
386 .emulated = ATA_SHT_EMULATED,
388 .proc_name = DRV_NAME,
389 .dma_boundary = MV_DMA_BOUNDARY,
390 .slave_configure = ata_scsi_slave_config,
391 .slave_destroy = ata_scsi_slave_destroy,
392 .bios_param = ata_std_bios_param,
395 static const struct ata_port_operations mv5_ops = {
396 .port_disable = ata_port_disable,
398 .tf_load = ata_tf_load,
399 .tf_read = ata_tf_read,
400 .check_status = ata_check_status,
401 .exec_command = ata_exec_command,
402 .dev_select = ata_std_dev_select,
404 .phy_reset = mv_phy_reset,
406 .qc_prep = mv_qc_prep,
407 .qc_issue = mv_qc_issue,
408 .data_xfer = ata_data_xfer,
410 .eng_timeout = mv_eng_timeout,
412 .irq_handler = mv_interrupt,
413 .irq_clear = mv_irq_clear,
414 .irq_on = ata_irq_on,
415 .irq_ack = ata_irq_ack,
417 .scr_read = mv5_scr_read,
418 .scr_write = mv5_scr_write,
420 .port_start = mv_port_start,
421 .port_stop = mv_port_stop,
424 static const struct ata_port_operations mv6_ops = {
425 .port_disable = ata_port_disable,
427 .tf_load = ata_tf_load,
428 .tf_read = ata_tf_read,
429 .check_status = ata_check_status,
430 .exec_command = ata_exec_command,
431 .dev_select = ata_std_dev_select,
433 .phy_reset = mv_phy_reset,
435 .qc_prep = mv_qc_prep,
436 .qc_issue = mv_qc_issue,
437 .data_xfer = ata_data_xfer,
439 .eng_timeout = mv_eng_timeout,
441 .irq_handler = mv_interrupt,
442 .irq_clear = mv_irq_clear,
443 .irq_on = ata_irq_on,
444 .irq_ack = ata_irq_ack,
446 .scr_read = mv_scr_read,
447 .scr_write = mv_scr_write,
449 .port_start = mv_port_start,
450 .port_stop = mv_port_stop,
453 static const struct ata_port_operations mv_iie_ops = {
454 .port_disable = ata_port_disable,
456 .tf_load = ata_tf_load,
457 .tf_read = ata_tf_read,
458 .check_status = ata_check_status,
459 .exec_command = ata_exec_command,
460 .dev_select = ata_std_dev_select,
462 .phy_reset = mv_phy_reset,
464 .qc_prep = mv_qc_prep_iie,
465 .qc_issue = mv_qc_issue,
466 .data_xfer = ata_data_xfer,
468 .eng_timeout = mv_eng_timeout,
470 .irq_handler = mv_interrupt,
471 .irq_clear = mv_irq_clear,
472 .irq_on = ata_irq_on,
473 .irq_ack = ata_irq_ack,
475 .scr_read = mv_scr_read,
476 .scr_write = mv_scr_write,
478 .port_start = mv_port_start,
479 .port_stop = mv_port_stop,
482 static const struct ata_port_info mv_port_info[] = {
485 .flags = MV_COMMON_FLAGS,
486 .pio_mask = 0x1f, /* pio0-4 */
487 .udma_mask = 0x7f, /* udma0-6 */
488 .port_ops = &mv5_ops,
492 .flags = (MV_COMMON_FLAGS | MV_FLAG_DUAL_HC),
493 .pio_mask = 0x1f, /* pio0-4 */
494 .udma_mask = 0x7f, /* udma0-6 */
495 .port_ops = &mv5_ops,
499 .flags = (MV_COMMON_FLAGS | MV_FLAG_DUAL_HC),
500 .pio_mask = 0x1f, /* pio0-4 */
501 .udma_mask = 0x7f, /* udma0-6 */
502 .port_ops = &mv5_ops,
506 .flags = (MV_COMMON_FLAGS | MV_6XXX_FLAGS),
507 .pio_mask = 0x1f, /* pio0-4 */
508 .udma_mask = 0x7f, /* udma0-6 */
509 .port_ops = &mv6_ops,
513 .flags = (MV_COMMON_FLAGS | MV_6XXX_FLAGS |
515 .pio_mask = 0x1f, /* pio0-4 */
516 .udma_mask = 0x7f, /* udma0-6 */
517 .port_ops = &mv6_ops,
521 .flags = (MV_COMMON_FLAGS | MV_6XXX_FLAGS),
522 .pio_mask = 0x1f, /* pio0-4 */
523 .udma_mask = 0x7f, /* udma0-6 */
524 .port_ops = &mv_iie_ops,
528 .flags = (MV_COMMON_FLAGS | MV_6XXX_FLAGS),
529 .pio_mask = 0x1f, /* pio0-4 */
530 .udma_mask = 0x7f, /* udma0-6 */
531 .port_ops = &mv_iie_ops,
535 static const struct pci_device_id mv_pci_tbl[] = {
536 { PCI_VDEVICE(MARVELL, 0x5040), chip_504x },
537 { PCI_VDEVICE(MARVELL, 0x5041), chip_504x },
538 { PCI_VDEVICE(MARVELL, 0x5080), chip_5080 },
539 { PCI_VDEVICE(MARVELL, 0x5081), chip_508x },
541 { PCI_VDEVICE(MARVELL, 0x6040), chip_604x },
542 { PCI_VDEVICE(MARVELL, 0x6041), chip_604x },
543 { PCI_VDEVICE(MARVELL, 0x6042), chip_6042 },
544 { PCI_VDEVICE(MARVELL, 0x6080), chip_608x },
545 { PCI_VDEVICE(MARVELL, 0x6081), chip_608x },
547 { PCI_VDEVICE(ADAPTEC2, 0x0241), chip_604x },
549 { PCI_VDEVICE(TTI, 0x2310), chip_7042 },
551 /* add Marvell 7042 support */
552 { PCI_VDEVICE(MARVELL, 0x7042), chip_7042 },
554 { } /* terminate list */
557 static struct pci_driver mv_pci_driver = {
559 .id_table = mv_pci_tbl,
560 .probe = mv_init_one,
561 .remove = ata_pci_remove_one,
564 static const struct mv_hw_ops mv5xxx_ops = {
565 .phy_errata = mv5_phy_errata,
566 .enable_leds = mv5_enable_leds,
567 .read_preamp = mv5_read_preamp,
568 .reset_hc = mv5_reset_hc,
569 .reset_flash = mv5_reset_flash,
570 .reset_bus = mv5_reset_bus,
573 static const struct mv_hw_ops mv6xxx_ops = {
574 .phy_errata = mv6_phy_errata,
575 .enable_leds = mv6_enable_leds,
576 .read_preamp = mv6_read_preamp,
577 .reset_hc = mv6_reset_hc,
578 .reset_flash = mv6_reset_flash,
579 .reset_bus = mv_reset_pci_bus,
585 static int msi; /* Use PCI msi; either zero (off, default) or non-zero */
588 /* move to PCI layer or libata core? */
589 static int pci_go_64(struct pci_dev *pdev)
593 if (!pci_set_dma_mask(pdev, DMA_64BIT_MASK)) {
594 rc = pci_set_consistent_dma_mask(pdev, DMA_64BIT_MASK);
596 rc = pci_set_consistent_dma_mask(pdev, DMA_32BIT_MASK);
598 dev_printk(KERN_ERR, &pdev->dev,
599 "64-bit DMA enable failed\n");
604 rc = pci_set_dma_mask(pdev, DMA_32BIT_MASK);
606 dev_printk(KERN_ERR, &pdev->dev,
607 "32-bit DMA enable failed\n");
610 rc = pci_set_consistent_dma_mask(pdev, DMA_32BIT_MASK);
612 dev_printk(KERN_ERR, &pdev->dev,
613 "32-bit consistent DMA enable failed\n");
625 static inline void writelfl(unsigned long data, void __iomem *addr)
628 (void) readl(addr); /* flush to avoid PCI posted write */
631 static inline void __iomem *mv_hc_base(void __iomem *base, unsigned int hc)
633 return (base + MV_SATAHC0_REG_BASE + (hc * MV_SATAHC_REG_SZ));
636 static inline unsigned int mv_hc_from_port(unsigned int port)
638 return port >> MV_PORT_HC_SHIFT;
641 static inline unsigned int mv_hardport_from_port(unsigned int port)
643 return port & MV_PORT_MASK;
646 static inline void __iomem *mv_hc_base_from_port(void __iomem *base,
649 return mv_hc_base(base, mv_hc_from_port(port));
652 static inline void __iomem *mv_port_base(void __iomem *base, unsigned int port)
654 return mv_hc_base_from_port(base, port) +
655 MV_SATAHC_ARBTR_REG_SZ +
656 (mv_hardport_from_port(port) * MV_PORT_REG_SZ);
659 static inline void __iomem *mv_ap_base(struct ata_port *ap)
661 return mv_port_base(ap->host->iomap[MV_PRIMARY_BAR], ap->port_no);
664 static inline int mv_get_hc_count(unsigned long port_flags)
666 return ((port_flags & MV_FLAG_DUAL_HC) ? 2 : 1);
669 static void mv_irq_clear(struct ata_port *ap)
674 * mv_start_dma - Enable eDMA engine
675 * @base: port base address
676 * @pp: port private data
678 * Verify the local cache of the eDMA state is accurate with a
682 * Inherited from caller.
684 static void mv_start_dma(void __iomem *base, struct mv_port_priv *pp)
686 if (!(MV_PP_FLAG_EDMA_EN & pp->pp_flags)) {
687 writelfl(EDMA_EN, base + EDMA_CMD_OFS);
688 pp->pp_flags |= MV_PP_FLAG_EDMA_EN;
690 WARN_ON(!(EDMA_EN & readl(base + EDMA_CMD_OFS)));
694 * mv_stop_dma - Disable eDMA engine
695 * @ap: ATA channel to manipulate
697 * Verify the local cache of the eDMA state is accurate with a
701 * Inherited from caller.
703 static void mv_stop_dma(struct ata_port *ap)
705 void __iomem *port_mmio = mv_ap_base(ap);
706 struct mv_port_priv *pp = ap->private_data;
710 if (MV_PP_FLAG_EDMA_EN & pp->pp_flags) {
711 /* Disable EDMA if active. The disable bit auto clears.
713 writelfl(EDMA_DS, port_mmio + EDMA_CMD_OFS);
714 pp->pp_flags &= ~MV_PP_FLAG_EDMA_EN;
716 WARN_ON(EDMA_EN & readl(port_mmio + EDMA_CMD_OFS));
719 /* now properly wait for the eDMA to stop */
720 for (i = 1000; i > 0; i--) {
721 reg = readl(port_mmio + EDMA_CMD_OFS);
722 if (!(EDMA_EN & reg)) {
729 ata_port_printk(ap, KERN_ERR, "Unable to stop eDMA\n");
730 /* FIXME: Consider doing a reset here to recover */
735 static void mv_dump_mem(void __iomem *start, unsigned bytes)
738 for (b = 0; b < bytes; ) {
739 DPRINTK("%p: ", start + b);
740 for (w = 0; b < bytes && w < 4; w++) {
741 printk("%08x ",readl(start + b));
749 static void mv_dump_pci_cfg(struct pci_dev *pdev, unsigned bytes)
754 for (b = 0; b < bytes; ) {
755 DPRINTK("%02x: ", b);
756 for (w = 0; b < bytes && w < 4; w++) {
757 (void) pci_read_config_dword(pdev,b,&dw);
765 static void mv_dump_all_regs(void __iomem *mmio_base, int port,
766 struct pci_dev *pdev)
769 void __iomem *hc_base = mv_hc_base(mmio_base,
770 port >> MV_PORT_HC_SHIFT);
771 void __iomem *port_base;
772 int start_port, num_ports, p, start_hc, num_hcs, hc;
775 start_hc = start_port = 0;
776 num_ports = 8; /* shld be benign for 4 port devs */
779 start_hc = port >> MV_PORT_HC_SHIFT;
781 num_ports = num_hcs = 1;
783 DPRINTK("All registers for port(s) %u-%u:\n", start_port,
784 num_ports > 1 ? num_ports - 1 : start_port);
787 DPRINTK("PCI config space regs:\n");
788 mv_dump_pci_cfg(pdev, 0x68);
790 DPRINTK("PCI regs:\n");
791 mv_dump_mem(mmio_base+0xc00, 0x3c);
792 mv_dump_mem(mmio_base+0xd00, 0x34);
793 mv_dump_mem(mmio_base+0xf00, 0x4);
794 mv_dump_mem(mmio_base+0x1d00, 0x6c);
795 for (hc = start_hc; hc < start_hc + num_hcs; hc++) {
796 hc_base = mv_hc_base(mmio_base, hc);
797 DPRINTK("HC regs (HC %i):\n", hc);
798 mv_dump_mem(hc_base, 0x1c);
800 for (p = start_port; p < start_port + num_ports; p++) {
801 port_base = mv_port_base(mmio_base, p);
802 DPRINTK("EDMA regs (port %i):\n",p);
803 mv_dump_mem(port_base, 0x54);
804 DPRINTK("SATA regs (port %i):\n",p);
805 mv_dump_mem(port_base+0x300, 0x60);
810 static unsigned int mv_scr_offset(unsigned int sc_reg_in)
818 ofs = SATA_STATUS_OFS + (sc_reg_in * sizeof(u32));
821 ofs = SATA_ACTIVE_OFS; /* active is not with the others */
830 static u32 mv_scr_read(struct ata_port *ap, unsigned int sc_reg_in)
832 unsigned int ofs = mv_scr_offset(sc_reg_in);
834 if (0xffffffffU != ofs)
835 return readl(mv_ap_base(ap) + ofs);
840 static void mv_scr_write(struct ata_port *ap, unsigned int sc_reg_in, u32 val)
842 unsigned int ofs = mv_scr_offset(sc_reg_in);
844 if (0xffffffffU != ofs)
845 writelfl(val, mv_ap_base(ap) + ofs);
848 static void mv_edma_cfg(struct mv_host_priv *hpriv, void __iomem *port_mmio)
850 u32 cfg = readl(port_mmio + EDMA_CFG_OFS);
852 /* set up non-NCQ EDMA configuration */
853 cfg &= ~(1 << 9); /* disable equeue */
855 if (IS_GEN_I(hpriv)) {
856 cfg &= ~0x1f; /* clear queue depth */
857 cfg |= (1 << 8); /* enab config burst size mask */
860 else if (IS_GEN_II(hpriv)) {
861 cfg &= ~0x1f; /* clear queue depth */
862 cfg |= EDMA_CFG_RD_BRST_EXT | EDMA_CFG_WR_BUFF_LEN;
863 cfg &= ~(EDMA_CFG_NCQ | EDMA_CFG_NCQ_GO_ON_ERR); /* clear NCQ */
866 else if (IS_GEN_IIE(hpriv)) {
867 cfg |= (1 << 23); /* do not mask PM field in rx'd FIS */
868 cfg |= (1 << 22); /* enab 4-entry host queue cache */
869 cfg &= ~(1 << 19); /* dis 128-entry queue (for now?) */
870 cfg |= (1 << 18); /* enab early completion */
871 cfg |= (1 << 17); /* enab cut-through (dis stor&forwrd) */
872 cfg &= ~(1 << 16); /* dis FIS-based switching (for now) */
873 cfg &= ~(EDMA_CFG_NCQ | EDMA_CFG_NCQ_GO_ON_ERR); /* clear NCQ */
876 writelfl(cfg, port_mmio + EDMA_CFG_OFS);
880 * mv_port_start - Port specific init/start routine.
881 * @ap: ATA channel to manipulate
883 * Allocate and point to DMA memory, init port private memory,
887 * Inherited from caller.
889 static int mv_port_start(struct ata_port *ap)
891 struct device *dev = ap->host->dev;
892 struct mv_host_priv *hpriv = ap->host->private_data;
893 struct mv_port_priv *pp;
894 void __iomem *port_mmio = mv_ap_base(ap);
899 pp = devm_kzalloc(dev, sizeof(*pp), GFP_KERNEL);
903 mem = dmam_alloc_coherent(dev, MV_PORT_PRIV_DMA_SZ, &mem_dma,
907 memset(mem, 0, MV_PORT_PRIV_DMA_SZ);
909 rc = ata_pad_alloc(ap, dev);
913 /* First item in chunk of DMA memory:
914 * 32-slot command request table (CRQB), 32 bytes each in size
917 pp->crqb_dma = mem_dma;
919 mem_dma += MV_CRQB_Q_SZ;
922 * 32-slot command response table (CRPB), 8 bytes each in size
925 pp->crpb_dma = mem_dma;
927 mem_dma += MV_CRPB_Q_SZ;
930 * Table of scatter-gather descriptors (ePRD), 16 bytes each
933 pp->sg_tbl_dma = mem_dma;
935 mv_edma_cfg(hpriv, port_mmio);
937 writel((pp->crqb_dma >> 16) >> 16, port_mmio + EDMA_REQ_Q_BASE_HI_OFS);
938 writelfl(pp->crqb_dma & EDMA_REQ_Q_BASE_LO_MASK,
939 port_mmio + EDMA_REQ_Q_IN_PTR_OFS);
941 if (hpriv->hp_flags & MV_HP_ERRATA_XX42A0)
942 writelfl(pp->crqb_dma & 0xffffffff,
943 port_mmio + EDMA_REQ_Q_OUT_PTR_OFS);
945 writelfl(0, port_mmio + EDMA_REQ_Q_OUT_PTR_OFS);
947 writel((pp->crpb_dma >> 16) >> 16, port_mmio + EDMA_RSP_Q_BASE_HI_OFS);
949 if (hpriv->hp_flags & MV_HP_ERRATA_XX42A0)
950 writelfl(pp->crpb_dma & 0xffffffff,
951 port_mmio + EDMA_RSP_Q_IN_PTR_OFS);
953 writelfl(0, port_mmio + EDMA_RSP_Q_IN_PTR_OFS);
955 writelfl(pp->crpb_dma & EDMA_RSP_Q_BASE_LO_MASK,
956 port_mmio + EDMA_RSP_Q_OUT_PTR_OFS);
958 /* Don't turn on EDMA here...do it before DMA commands only. Else
959 * we'll be unable to send non-data, PIO, etc due to restricted access
962 ap->private_data = pp;
967 * mv_port_stop - Port specific cleanup/stop routine.
968 * @ap: ATA channel to manipulate
970 * Stop DMA, cleanup port memory.
973 * This routine uses the host lock to protect the DMA stop.
975 static void mv_port_stop(struct ata_port *ap)
979 spin_lock_irqsave(&ap->host->lock, flags);
981 spin_unlock_irqrestore(&ap->host->lock, flags);
985 * mv_fill_sg - Fill out the Marvell ePRD (scatter gather) entries
986 * @qc: queued command whose SG list to source from
988 * Populate the SG list and mark the last entry.
991 * Inherited from caller.
993 static unsigned int mv_fill_sg(struct ata_queued_cmd *qc)
995 struct mv_port_priv *pp = qc->ap->private_data;
996 unsigned int n_sg = 0;
997 struct scatterlist *sg;
1001 ata_for_each_sg(sg, qc) {
1002 dma_addr_t addr = sg_dma_address(sg);
1003 u32 sg_len = sg_dma_len(sg);
1005 mv_sg->addr = cpu_to_le32(addr & 0xffffffff);
1006 mv_sg->addr_hi = cpu_to_le32((addr >> 16) >> 16);
1007 mv_sg->flags_size = cpu_to_le32(sg_len & 0xffff);
1009 if (ata_sg_is_last(sg, qc))
1010 mv_sg->flags_size |= cpu_to_le32(EPRD_FLAG_END_OF_TBL);
1019 static inline unsigned mv_inc_q_index(unsigned index)
1021 return (index + 1) & MV_MAX_Q_DEPTH_MASK;
1024 static inline void mv_crqb_pack_cmd(__le16 *cmdw, u8 data, u8 addr, unsigned last)
1026 u16 tmp = data | (addr << CRQB_CMD_ADDR_SHIFT) | CRQB_CMD_CS |
1027 (last ? CRQB_CMD_LAST : 0);
1028 *cmdw = cpu_to_le16(tmp);
1032 * mv_qc_prep - Host specific command preparation.
1033 * @qc: queued command to prepare
1035 * This routine simply redirects to the general purpose routine
1036 * if command is not DMA. Else, it handles prep of the CRQB
1037 * (command request block), does some sanity checking, and calls
1038 * the SG load routine.
1041 * Inherited from caller.
1043 static void mv_qc_prep(struct ata_queued_cmd *qc)
1045 struct ata_port *ap = qc->ap;
1046 struct mv_port_priv *pp = ap->private_data;
1048 struct ata_taskfile *tf;
1052 if (ATA_PROT_DMA != qc->tf.protocol)
1055 /* Fill in command request block
1057 if (!(qc->tf.flags & ATA_TFLAG_WRITE))
1058 flags |= CRQB_FLAG_READ;
1059 WARN_ON(MV_MAX_Q_DEPTH <= qc->tag);
1060 flags |= qc->tag << CRQB_TAG_SHIFT;
1062 /* get current queue index from hardware */
1063 in_index = (readl(mv_ap_base(ap) + EDMA_REQ_Q_IN_PTR_OFS)
1064 >> EDMA_REQ_Q_PTR_SHIFT) & MV_MAX_Q_DEPTH_MASK;
1066 pp->crqb[in_index].sg_addr =
1067 cpu_to_le32(pp->sg_tbl_dma & 0xffffffff);
1068 pp->crqb[in_index].sg_addr_hi =
1069 cpu_to_le32((pp->sg_tbl_dma >> 16) >> 16);
1070 pp->crqb[in_index].ctrl_flags = cpu_to_le16(flags);
1072 cw = &pp->crqb[in_index].ata_cmd[0];
1075 /* Sadly, the CRQB cannot accomodate all registers--there are
1076 * only 11 bytes...so we must pick and choose required
1077 * registers based on the command. So, we drop feature and
1078 * hob_feature for [RW] DMA commands, but they are needed for
1079 * NCQ. NCQ will drop hob_nsect.
1081 switch (tf->command) {
1083 case ATA_CMD_READ_EXT:
1085 case ATA_CMD_WRITE_EXT:
1086 case ATA_CMD_WRITE_FUA_EXT:
1087 mv_crqb_pack_cmd(cw++, tf->hob_nsect, ATA_REG_NSECT, 0);
1089 #ifdef LIBATA_NCQ /* FIXME: remove this line when NCQ added */
1090 case ATA_CMD_FPDMA_READ:
1091 case ATA_CMD_FPDMA_WRITE:
1092 mv_crqb_pack_cmd(cw++, tf->hob_feature, ATA_REG_FEATURE, 0);
1093 mv_crqb_pack_cmd(cw++, tf->feature, ATA_REG_FEATURE, 0);
1095 #endif /* FIXME: remove this line when NCQ added */
1097 /* The only other commands EDMA supports in non-queued and
1098 * non-NCQ mode are: [RW] STREAM DMA and W DMA FUA EXT, none
1099 * of which are defined/used by Linux. If we get here, this
1100 * driver needs work.
1102 * FIXME: modify libata to give qc_prep a return value and
1103 * return error here.
1105 BUG_ON(tf->command);
1108 mv_crqb_pack_cmd(cw++, tf->nsect, ATA_REG_NSECT, 0);
1109 mv_crqb_pack_cmd(cw++, tf->hob_lbal, ATA_REG_LBAL, 0);
1110 mv_crqb_pack_cmd(cw++, tf->lbal, ATA_REG_LBAL, 0);
1111 mv_crqb_pack_cmd(cw++, tf->hob_lbam, ATA_REG_LBAM, 0);
1112 mv_crqb_pack_cmd(cw++, tf->lbam, ATA_REG_LBAM, 0);
1113 mv_crqb_pack_cmd(cw++, tf->hob_lbah, ATA_REG_LBAH, 0);
1114 mv_crqb_pack_cmd(cw++, tf->lbah, ATA_REG_LBAH, 0);
1115 mv_crqb_pack_cmd(cw++, tf->device, ATA_REG_DEVICE, 0);
1116 mv_crqb_pack_cmd(cw++, tf->command, ATA_REG_CMD, 1); /* last */
1118 if (!(qc->flags & ATA_QCFLAG_DMAMAP))
1124 * mv_qc_prep_iie - Host specific command preparation.
1125 * @qc: queued command to prepare
1127 * This routine simply redirects to the general purpose routine
1128 * if command is not DMA. Else, it handles prep of the CRQB
1129 * (command request block), does some sanity checking, and calls
1130 * the SG load routine.
1133 * Inherited from caller.
1135 static void mv_qc_prep_iie(struct ata_queued_cmd *qc)
1137 struct ata_port *ap = qc->ap;
1138 struct mv_port_priv *pp = ap->private_data;
1139 struct mv_crqb_iie *crqb;
1140 struct ata_taskfile *tf;
1144 if (ATA_PROT_DMA != qc->tf.protocol)
1147 /* Fill in Gen IIE command request block
1149 if (!(qc->tf.flags & ATA_TFLAG_WRITE))
1150 flags |= CRQB_FLAG_READ;
1152 WARN_ON(MV_MAX_Q_DEPTH <= qc->tag);
1153 flags |= qc->tag << CRQB_TAG_SHIFT;
1155 /* get current queue index from hardware */
1156 in_index = (readl(mv_ap_base(ap) + EDMA_REQ_Q_IN_PTR_OFS)
1157 >> EDMA_REQ_Q_PTR_SHIFT) & MV_MAX_Q_DEPTH_MASK;
1159 crqb = (struct mv_crqb_iie *) &pp->crqb[in_index];
1160 crqb->addr = cpu_to_le32(pp->sg_tbl_dma & 0xffffffff);
1161 crqb->addr_hi = cpu_to_le32((pp->sg_tbl_dma >> 16) >> 16);
1162 crqb->flags = cpu_to_le32(flags);
1165 crqb->ata_cmd[0] = cpu_to_le32(
1166 (tf->command << 16) |
1169 crqb->ata_cmd[1] = cpu_to_le32(
1175 crqb->ata_cmd[2] = cpu_to_le32(
1176 (tf->hob_lbal << 0) |
1177 (tf->hob_lbam << 8) |
1178 (tf->hob_lbah << 16) |
1179 (tf->hob_feature << 24)
1181 crqb->ata_cmd[3] = cpu_to_le32(
1183 (tf->hob_nsect << 8)
1186 if (!(qc->flags & ATA_QCFLAG_DMAMAP))
1192 * mv_qc_issue - Initiate a command to the host
1193 * @qc: queued command to start
1195 * This routine simply redirects to the general purpose routine
1196 * if command is not DMA. Else, it sanity checks our local
1197 * caches of the request producer/consumer indices then enables
1198 * DMA and bumps the request producer index.
1201 * Inherited from caller.
1203 static unsigned int mv_qc_issue(struct ata_queued_cmd *qc)
1205 void __iomem *port_mmio = mv_ap_base(qc->ap);
1206 struct mv_port_priv *pp = qc->ap->private_data;
1210 if (ATA_PROT_DMA != qc->tf.protocol) {
1211 /* We're about to send a non-EDMA capable command to the
1212 * port. Turn off EDMA so there won't be problems accessing
1213 * shadow block, etc registers.
1215 mv_stop_dma(qc->ap);
1216 return ata_qc_issue_prot(qc);
1219 in_ptr = readl(port_mmio + EDMA_REQ_Q_IN_PTR_OFS);
1220 in_index = (in_ptr >> EDMA_REQ_Q_PTR_SHIFT) & MV_MAX_Q_DEPTH_MASK;
1222 /* until we do queuing, the queue should be empty at this point */
1223 WARN_ON(in_index != ((readl(port_mmio + EDMA_REQ_Q_OUT_PTR_OFS)
1224 >> EDMA_REQ_Q_PTR_SHIFT) & MV_MAX_Q_DEPTH_MASK));
1226 in_index = mv_inc_q_index(in_index); /* now incr producer index */
1228 mv_start_dma(port_mmio, pp);
1230 /* and write the request in pointer to kick the EDMA to life */
1231 in_ptr &= EDMA_REQ_Q_BASE_LO_MASK;
1232 in_ptr |= in_index << EDMA_REQ_Q_PTR_SHIFT;
1233 writelfl(in_ptr, port_mmio + EDMA_REQ_Q_IN_PTR_OFS);
1239 * mv_get_crpb_status - get status from most recently completed cmd
1240 * @ap: ATA channel to manipulate
1242 * This routine is for use when the port is in DMA mode, when it
1243 * will be using the CRPB (command response block) method of
1244 * returning command completion information. We check indices
1245 * are good, grab status, and bump the response consumer index to
1246 * prove that we're up to date.
1249 * Inherited from caller.
1251 static u8 mv_get_crpb_status(struct ata_port *ap)
1253 void __iomem *port_mmio = mv_ap_base(ap);
1254 struct mv_port_priv *pp = ap->private_data;
1259 out_ptr = readl(port_mmio + EDMA_RSP_Q_OUT_PTR_OFS);
1260 out_index = (out_ptr >> EDMA_RSP_Q_PTR_SHIFT) & MV_MAX_Q_DEPTH_MASK;
1262 ata_status = le16_to_cpu(pp->crpb[out_index].flags)
1263 >> CRPB_FLAG_STATUS_SHIFT;
1265 /* increment our consumer index... */
1266 out_index = mv_inc_q_index(out_index);
1268 /* and, until we do NCQ, there should only be 1 CRPB waiting */
1269 WARN_ON(out_index != ((readl(port_mmio + EDMA_RSP_Q_IN_PTR_OFS)
1270 >> EDMA_RSP_Q_PTR_SHIFT) & MV_MAX_Q_DEPTH_MASK));
1272 /* write out our inc'd consumer index so EDMA knows we're caught up */
1273 out_ptr &= EDMA_RSP_Q_BASE_LO_MASK;
1274 out_ptr |= out_index << EDMA_RSP_Q_PTR_SHIFT;
1275 writelfl(out_ptr, port_mmio + EDMA_RSP_Q_OUT_PTR_OFS);
1277 /* Return ATA status register for completed CRPB */
1282 * mv_err_intr - Handle error interrupts on the port
1283 * @ap: ATA channel to manipulate
1284 * @reset_allowed: bool: 0 == don't trigger from reset here
1286 * In most cases, just clear the interrupt and move on. However,
1287 * some cases require an eDMA reset, which is done right before
1288 * the COMRESET in mv_phy_reset(). The SERR case requires a
1289 * clear of pending errors in the SATA SERROR register. Finally,
1290 * if the port disabled DMA, update our cached copy to match.
1293 * Inherited from caller.
1295 static void mv_err_intr(struct ata_port *ap, int reset_allowed)
1297 void __iomem *port_mmio = mv_ap_base(ap);
1298 u32 edma_err_cause, serr = 0;
1300 edma_err_cause = readl(port_mmio + EDMA_ERR_IRQ_CAUSE_OFS);
1302 if (EDMA_ERR_SERR & edma_err_cause) {
1303 sata_scr_read(ap, SCR_ERROR, &serr);
1304 sata_scr_write_flush(ap, SCR_ERROR, serr);
1306 if (EDMA_ERR_SELF_DIS & edma_err_cause) {
1307 struct mv_port_priv *pp = ap->private_data;
1308 pp->pp_flags &= ~MV_PP_FLAG_EDMA_EN;
1310 DPRINTK(KERN_ERR "ata%u: port error; EDMA err cause: 0x%08x "
1311 "SERR: 0x%08x\n", ap->print_id, edma_err_cause, serr);
1313 /* Clear EDMA now that SERR cleanup done */
1314 writelfl(0, port_mmio + EDMA_ERR_IRQ_CAUSE_OFS);
1316 /* check for fatal here and recover if needed */
1317 if (reset_allowed && (EDMA_ERR_FATAL & edma_err_cause))
1318 mv_stop_and_reset(ap);
1322 * mv_host_intr - Handle all interrupts on the given host controller
1323 * @host: host specific structure
1324 * @relevant: port error bits relevant to this host controller
1325 * @hc: which host controller we're to look at
1327 * Read then write clear the HC interrupt status then walk each
1328 * port connected to the HC and see if it needs servicing. Port
1329 * success ints are reported in the HC interrupt status reg, the
1330 * port error ints are reported in the higher level main
1331 * interrupt status register and thus are passed in via the
1332 * 'relevant' argument.
1335 * Inherited from caller.
1337 static void mv_host_intr(struct ata_host *host, u32 relevant, unsigned int hc)
1339 void __iomem *mmio = host->iomap[MV_PRIMARY_BAR];
1340 void __iomem *hc_mmio = mv_hc_base(mmio, hc);
1341 struct ata_queued_cmd *qc;
1343 int shift, port, port0, hard_port, handled;
1344 unsigned int err_mask;
1349 port0 = MV_PORTS_PER_HC;
1351 /* we'll need the HC success int register in most cases */
1352 hc_irq_cause = readl(hc_mmio + HC_IRQ_CAUSE_OFS);
1354 writelfl(~hc_irq_cause, hc_mmio + HC_IRQ_CAUSE_OFS);
1356 VPRINTK("ENTER, hc%u relevant=0x%08x HC IRQ cause=0x%08x\n",
1357 hc,relevant,hc_irq_cause);
1359 for (port = port0; port < port0 + MV_PORTS_PER_HC; port++) {
1361 struct ata_port *ap = host->ports[port];
1362 struct mv_port_priv *pp = ap->private_data;
1364 hard_port = mv_hardport_from_port(port); /* range 0..3 */
1365 handled = 0; /* ensure ata_status is set if handled++ */
1367 /* Note that DEV_IRQ might happen spuriously during EDMA,
1368 * and should be ignored in such cases.
1369 * The cause of this is still under investigation.
1371 if (pp->pp_flags & MV_PP_FLAG_EDMA_EN) {
1372 /* EDMA: check for response queue interrupt */
1373 if ((CRPB_DMA_DONE << hard_port) & hc_irq_cause) {
1374 ata_status = mv_get_crpb_status(ap);
1378 /* PIO: check for device (drive) interrupt */
1379 if ((DEV_IRQ << hard_port) & hc_irq_cause) {
1380 ata_status = readb(ap->ioaddr.status_addr);
1382 /* ignore spurious intr if drive still BUSY */
1383 if (ata_status & ATA_BUSY) {
1390 if (ap && (ap->flags & ATA_FLAG_DISABLED))
1393 err_mask = ac_err_mask(ata_status);
1395 shift = port << 1; /* (port * 2) */
1396 if (port >= MV_PORTS_PER_HC) {
1397 shift++; /* skip bit 8 in the HC Main IRQ reg */
1399 if ((PORT0_ERR << shift) & relevant) {
1401 err_mask |= AC_ERR_OTHER;
1406 qc = ata_qc_from_tag(ap, ap->active_tag);
1407 if (qc && (qc->flags & ATA_QCFLAG_ACTIVE)) {
1408 VPRINTK("port %u IRQ found for qc, "
1409 "ata_status 0x%x\n", port,ata_status);
1410 /* mark qc status appropriately */
1411 if (!(qc->tf.flags & ATA_TFLAG_POLLING)) {
1412 qc->err_mask |= err_mask;
1413 ata_qc_complete(qc);
1424 * @dev_instance: private data; in this case the host structure
1427 * Read the read only register to determine if any host
1428 * controllers have pending interrupts. If so, call lower level
1429 * routine to handle. Also check for PCI errors which are only
1433 * This routine holds the host lock while processing pending
1436 static irqreturn_t mv_interrupt(int irq, void *dev_instance)
1438 struct ata_host *host = dev_instance;
1439 unsigned int hc, handled = 0, n_hcs;
1440 void __iomem *mmio = host->iomap[MV_PRIMARY_BAR];
1441 struct mv_host_priv *hpriv;
1444 irq_stat = readl(mmio + HC_MAIN_IRQ_CAUSE_OFS);
1446 /* check the cases where we either have nothing pending or have read
1447 * a bogus register value which can indicate HW removal or PCI fault
1449 if (!irq_stat || (0xffffffffU == irq_stat))
1452 n_hcs = mv_get_hc_count(host->ports[0]->flags);
1453 spin_lock(&host->lock);
1455 for (hc = 0; hc < n_hcs; hc++) {
1456 u32 relevant = irq_stat & (HC0_IRQ_PEND << (hc * HC_SHIFT));
1458 mv_host_intr(host, relevant, hc);
1463 hpriv = host->private_data;
1464 if (IS_60XX(hpriv)) {
1465 /* deal with the interrupt coalescing bits */
1466 if (irq_stat & (TRAN_LO_DONE | TRAN_HI_DONE | PORTS_0_7_COAL_DONE)) {
1467 writelfl(0, mmio + MV_IRQ_COAL_CAUSE_LO);
1468 writelfl(0, mmio + MV_IRQ_COAL_CAUSE_HI);
1469 writelfl(0, mmio + MV_IRQ_COAL_CAUSE);
1473 if (PCI_ERR & irq_stat) {
1474 printk(KERN_ERR DRV_NAME ": PCI ERROR; PCI IRQ cause=0x%08x\n",
1475 readl(mmio + PCI_IRQ_CAUSE_OFS));
1477 DPRINTK("All regs @ PCI error\n");
1478 mv_dump_all_regs(mmio, -1, to_pci_dev(host->dev));
1480 writelfl(0, mmio + PCI_IRQ_CAUSE_OFS);
1483 spin_unlock(&host->lock);
1485 return IRQ_RETVAL(handled);
1488 static void __iomem *mv5_phy_base(void __iomem *mmio, unsigned int port)
1490 void __iomem *hc_mmio = mv_hc_base_from_port(mmio, port);
1491 unsigned long ofs = (mv_hardport_from_port(port) + 1) * 0x100UL;
1493 return hc_mmio + ofs;
1496 static unsigned int mv5_scr_offset(unsigned int sc_reg_in)
1500 switch (sc_reg_in) {
1504 ofs = sc_reg_in * sizeof(u32);
1513 static u32 mv5_scr_read(struct ata_port *ap, unsigned int sc_reg_in)
1515 void __iomem *mmio = ap->host->iomap[MV_PRIMARY_BAR];
1516 void __iomem *addr = mv5_phy_base(mmio, ap->port_no);
1517 unsigned int ofs = mv5_scr_offset(sc_reg_in);
1519 if (ofs != 0xffffffffU)
1520 return readl(addr + ofs);
1525 static void mv5_scr_write(struct ata_port *ap, unsigned int sc_reg_in, u32 val)
1527 void __iomem *mmio = ap->host->iomap[MV_PRIMARY_BAR];
1528 void __iomem *addr = mv5_phy_base(mmio, ap->port_no);
1529 unsigned int ofs = mv5_scr_offset(sc_reg_in);
1531 if (ofs != 0xffffffffU)
1532 writelfl(val, addr + ofs);
1535 static void mv5_reset_bus(struct pci_dev *pdev, void __iomem *mmio)
1540 pci_read_config_byte(pdev, PCI_REVISION_ID, &rev_id);
1542 early_5080 = (pdev->device == 0x5080) && (rev_id == 0);
1545 u32 tmp = readl(mmio + MV_PCI_EXP_ROM_BAR_CTL);
1547 writel(tmp, mmio + MV_PCI_EXP_ROM_BAR_CTL);
1550 mv_reset_pci_bus(pdev, mmio);
1553 static void mv5_reset_flash(struct mv_host_priv *hpriv, void __iomem *mmio)
1555 writel(0x0fcfffff, mmio + MV_FLASH_CTL);
1558 static void mv5_read_preamp(struct mv_host_priv *hpriv, int idx,
1561 void __iomem *phy_mmio = mv5_phy_base(mmio, idx);
1564 tmp = readl(phy_mmio + MV5_PHY_MODE);
1566 hpriv->signal[idx].pre = tmp & 0x1800; /* bits 12:11 */
1567 hpriv->signal[idx].amps = tmp & 0xe0; /* bits 7:5 */
1570 static void mv5_enable_leds(struct mv_host_priv *hpriv, void __iomem *mmio)
1574 writel(0, mmio + MV_GPIO_PORT_CTL);
1576 /* FIXME: handle MV_HP_ERRATA_50XXB2 errata */
1578 tmp = readl(mmio + MV_PCI_EXP_ROM_BAR_CTL);
1580 writel(tmp, mmio + MV_PCI_EXP_ROM_BAR_CTL);
1583 static void mv5_phy_errata(struct mv_host_priv *hpriv, void __iomem *mmio,
1586 void __iomem *phy_mmio = mv5_phy_base(mmio, port);
1587 const u32 mask = (1<<12) | (1<<11) | (1<<7) | (1<<6) | (1<<5);
1589 int fix_apm_sq = (hpriv->hp_flags & MV_HP_ERRATA_50XXB0);
1592 tmp = readl(phy_mmio + MV5_LT_MODE);
1594 writel(tmp, phy_mmio + MV5_LT_MODE);
1596 tmp = readl(phy_mmio + MV5_PHY_CTL);
1599 writel(tmp, phy_mmio + MV5_PHY_CTL);
1602 tmp = readl(phy_mmio + MV5_PHY_MODE);
1604 tmp |= hpriv->signal[port].pre;
1605 tmp |= hpriv->signal[port].amps;
1606 writel(tmp, phy_mmio + MV5_PHY_MODE);
1611 #define ZERO(reg) writel(0, port_mmio + (reg))
1612 static void mv5_reset_hc_port(struct mv_host_priv *hpriv, void __iomem *mmio,
1615 void __iomem *port_mmio = mv_port_base(mmio, port);
1617 writelfl(EDMA_DS, port_mmio + EDMA_CMD_OFS);
1619 mv_channel_reset(hpriv, mmio, port);
1621 ZERO(0x028); /* command */
1622 writel(0x11f, port_mmio + EDMA_CFG_OFS);
1623 ZERO(0x004); /* timer */
1624 ZERO(0x008); /* irq err cause */
1625 ZERO(0x00c); /* irq err mask */
1626 ZERO(0x010); /* rq bah */
1627 ZERO(0x014); /* rq inp */
1628 ZERO(0x018); /* rq outp */
1629 ZERO(0x01c); /* respq bah */
1630 ZERO(0x024); /* respq outp */
1631 ZERO(0x020); /* respq inp */
1632 ZERO(0x02c); /* test control */
1633 writel(0xbc, port_mmio + EDMA_IORDY_TMOUT);
1637 #define ZERO(reg) writel(0, hc_mmio + (reg))
1638 static void mv5_reset_one_hc(struct mv_host_priv *hpriv, void __iomem *mmio,
1641 void __iomem *hc_mmio = mv_hc_base(mmio, hc);
1649 tmp = readl(hc_mmio + 0x20);
1652 writel(tmp, hc_mmio + 0x20);
1656 static int mv5_reset_hc(struct mv_host_priv *hpriv, void __iomem *mmio,
1659 unsigned int hc, port;
1661 for (hc = 0; hc < n_hc; hc++) {
1662 for (port = 0; port < MV_PORTS_PER_HC; port++)
1663 mv5_reset_hc_port(hpriv, mmio,
1664 (hc * MV_PORTS_PER_HC) + port);
1666 mv5_reset_one_hc(hpriv, mmio, hc);
1673 #define ZERO(reg) writel(0, mmio + (reg))
1674 static void mv_reset_pci_bus(struct pci_dev *pdev, void __iomem *mmio)
1678 tmp = readl(mmio + MV_PCI_MODE);
1680 writel(tmp, mmio + MV_PCI_MODE);
1682 ZERO(MV_PCI_DISC_TIMER);
1683 ZERO(MV_PCI_MSI_TRIGGER);
1684 writel(0x000100ff, mmio + MV_PCI_XBAR_TMOUT);
1685 ZERO(HC_MAIN_IRQ_MASK_OFS);
1686 ZERO(MV_PCI_SERR_MASK);
1687 ZERO(PCI_IRQ_CAUSE_OFS);
1688 ZERO(PCI_IRQ_MASK_OFS);
1689 ZERO(MV_PCI_ERR_LOW_ADDRESS);
1690 ZERO(MV_PCI_ERR_HIGH_ADDRESS);
1691 ZERO(MV_PCI_ERR_ATTRIBUTE);
1692 ZERO(MV_PCI_ERR_COMMAND);
1696 static void mv6_reset_flash(struct mv_host_priv *hpriv, void __iomem *mmio)
1700 mv5_reset_flash(hpriv, mmio);
1702 tmp = readl(mmio + MV_GPIO_PORT_CTL);
1704 tmp |= (1 << 5) | (1 << 6);
1705 writel(tmp, mmio + MV_GPIO_PORT_CTL);
1709 * mv6_reset_hc - Perform the 6xxx global soft reset
1710 * @mmio: base address of the HBA
1712 * This routine only applies to 6xxx parts.
1715 * Inherited from caller.
1717 static int mv6_reset_hc(struct mv_host_priv *hpriv, void __iomem *mmio,
1720 void __iomem *reg = mmio + PCI_MAIN_CMD_STS_OFS;
1724 /* Following procedure defined in PCI "main command and status
1728 writel(t | STOP_PCI_MASTER, reg);
1730 for (i = 0; i < 1000; i++) {
1733 if (PCI_MASTER_EMPTY & t) {
1737 if (!(PCI_MASTER_EMPTY & t)) {
1738 printk(KERN_ERR DRV_NAME ": PCI master won't flush\n");
1746 writel(t | GLOB_SFT_RST, reg);
1749 } while (!(GLOB_SFT_RST & t) && (i-- > 0));
1751 if (!(GLOB_SFT_RST & t)) {
1752 printk(KERN_ERR DRV_NAME ": can't set global reset\n");
1757 /* clear reset and *reenable the PCI master* (not mentioned in spec) */
1760 writel(t & ~(GLOB_SFT_RST | STOP_PCI_MASTER), reg);
1763 } while ((GLOB_SFT_RST & t) && (i-- > 0));
1765 if (GLOB_SFT_RST & t) {
1766 printk(KERN_ERR DRV_NAME ": can't clear global reset\n");
1773 static void mv6_read_preamp(struct mv_host_priv *hpriv, int idx,
1776 void __iomem *port_mmio;
1779 tmp = readl(mmio + MV_RESET_CFG);
1780 if ((tmp & (1 << 0)) == 0) {
1781 hpriv->signal[idx].amps = 0x7 << 8;
1782 hpriv->signal[idx].pre = 0x1 << 5;
1786 port_mmio = mv_port_base(mmio, idx);
1787 tmp = readl(port_mmio + PHY_MODE2);
1789 hpriv->signal[idx].amps = tmp & 0x700; /* bits 10:8 */
1790 hpriv->signal[idx].pre = tmp & 0xe0; /* bits 7:5 */
1793 static void mv6_enable_leds(struct mv_host_priv *hpriv, void __iomem *mmio)
1795 writel(0x00000060, mmio + MV_GPIO_PORT_CTL);
1798 static void mv6_phy_errata(struct mv_host_priv *hpriv, void __iomem *mmio,
1801 void __iomem *port_mmio = mv_port_base(mmio, port);
1803 u32 hp_flags = hpriv->hp_flags;
1805 hp_flags & (MV_HP_ERRATA_60X1B2 | MV_HP_ERRATA_60X1C0);
1807 hp_flags & (MV_HP_ERRATA_60X1B2 | MV_HP_ERRATA_60X1C0);
1810 if (fix_phy_mode2) {
1811 m2 = readl(port_mmio + PHY_MODE2);
1814 writel(m2, port_mmio + PHY_MODE2);
1818 m2 = readl(port_mmio + PHY_MODE2);
1819 m2 &= ~((1 << 16) | (1 << 31));
1820 writel(m2, port_mmio + PHY_MODE2);
1825 /* who knows what this magic does */
1826 tmp = readl(port_mmio + PHY_MODE3);
1829 writel(tmp, port_mmio + PHY_MODE3);
1831 if (fix_phy_mode4) {
1834 m4 = readl(port_mmio + PHY_MODE4);
1836 if (hp_flags & MV_HP_ERRATA_60X1B2)
1837 tmp = readl(port_mmio + 0x310);
1839 m4 = (m4 & ~(1 << 1)) | (1 << 0);
1841 writel(m4, port_mmio + PHY_MODE4);
1843 if (hp_flags & MV_HP_ERRATA_60X1B2)
1844 writel(tmp, port_mmio + 0x310);
1847 /* Revert values of pre-emphasis and signal amps to the saved ones */
1848 m2 = readl(port_mmio + PHY_MODE2);
1850 m2 &= ~MV_M2_PREAMP_MASK;
1851 m2 |= hpriv->signal[port].amps;
1852 m2 |= hpriv->signal[port].pre;
1855 /* according to mvSata 3.6.1, some IIE values are fixed */
1856 if (IS_GEN_IIE(hpriv)) {
1861 writel(m2, port_mmio + PHY_MODE2);
1864 static void mv_channel_reset(struct mv_host_priv *hpriv, void __iomem *mmio,
1865 unsigned int port_no)
1867 void __iomem *port_mmio = mv_port_base(mmio, port_no);
1869 writelfl(ATA_RST, port_mmio + EDMA_CMD_OFS);
1871 if (IS_60XX(hpriv)) {
1872 u32 ifctl = readl(port_mmio + SATA_INTERFACE_CTL);
1873 ifctl |= (1 << 7); /* enable gen2i speed */
1874 ifctl = (ifctl & 0xfff) | 0x9b1000; /* from chip spec */
1875 writelfl(ifctl, port_mmio + SATA_INTERFACE_CTL);
1878 udelay(25); /* allow reset propagation */
1880 /* Spec never mentions clearing the bit. Marvell's driver does
1881 * clear the bit, however.
1883 writelfl(0, port_mmio + EDMA_CMD_OFS);
1885 hpriv->ops->phy_errata(hpriv, mmio, port_no);
1891 static void mv_stop_and_reset(struct ata_port *ap)
1893 struct mv_host_priv *hpriv = ap->host->private_data;
1894 void __iomem *mmio = ap->host->iomap[MV_PRIMARY_BAR];
1898 mv_channel_reset(hpriv, mmio, ap->port_no);
1900 __mv_phy_reset(ap, 0);
1903 static inline void __msleep(unsigned int msec, int can_sleep)
1912 * __mv_phy_reset - Perform eDMA reset followed by COMRESET
1913 * @ap: ATA channel to manipulate
1915 * Part of this is taken from __sata_phy_reset and modified to
1916 * not sleep since this routine gets called from interrupt level.
1919 * Inherited from caller. This is coded to safe to call at
1920 * interrupt level, i.e. it does not sleep.
1922 static void __mv_phy_reset(struct ata_port *ap, int can_sleep)
1924 struct mv_port_priv *pp = ap->private_data;
1925 struct mv_host_priv *hpriv = ap->host->private_data;
1926 void __iomem *port_mmio = mv_ap_base(ap);
1927 struct ata_taskfile tf;
1928 struct ata_device *dev = &ap->device[0];
1929 unsigned long timeout;
1933 VPRINTK("ENTER, port %u, mmio 0x%p\n", ap->port_no, port_mmio);
1935 DPRINTK("S-regs after ATA_RST: SStat 0x%08x SErr 0x%08x "
1936 "SCtrl 0x%08x\n", mv_scr_read(ap, SCR_STATUS),
1937 mv_scr_read(ap, SCR_ERROR), mv_scr_read(ap, SCR_CONTROL));
1939 /* Issue COMRESET via SControl */
1941 sata_scr_write_flush(ap, SCR_CONTROL, 0x301);
1942 __msleep(1, can_sleep);
1944 sata_scr_write_flush(ap, SCR_CONTROL, 0x300);
1945 __msleep(20, can_sleep);
1947 timeout = jiffies + msecs_to_jiffies(200);
1949 sata_scr_read(ap, SCR_STATUS, &sstatus);
1950 if (((sstatus & 0x3) == 3) || ((sstatus & 0x3) == 0))
1953 __msleep(1, can_sleep);
1954 } while (time_before(jiffies, timeout));
1956 /* work around errata */
1957 if (IS_60XX(hpriv) &&
1958 (sstatus != 0x0) && (sstatus != 0x113) && (sstatus != 0x123) &&
1960 goto comreset_retry;
1962 DPRINTK("S-regs after PHY wake: SStat 0x%08x SErr 0x%08x "
1963 "SCtrl 0x%08x\n", mv_scr_read(ap, SCR_STATUS),
1964 mv_scr_read(ap, SCR_ERROR), mv_scr_read(ap, SCR_CONTROL));
1966 if (ata_port_online(ap)) {
1969 sata_scr_read(ap, SCR_STATUS, &sstatus);
1970 ata_port_printk(ap, KERN_INFO,
1971 "no device found (phy stat %08x)\n", sstatus);
1972 ata_port_disable(ap);
1975 ap->cbl = ATA_CBL_SATA;
1977 /* even after SStatus reflects that device is ready,
1978 * it seems to take a while for link to be fully
1979 * established (and thus Status no longer 0x80/0x7F),
1980 * so we poll a bit for that, here.
1984 u8 drv_stat = ata_check_status(ap);
1985 if ((drv_stat != 0x80) && (drv_stat != 0x7f))
1987 __msleep(500, can_sleep);
1992 tf.lbah = readb(ap->ioaddr.lbah_addr);
1993 tf.lbam = readb(ap->ioaddr.lbam_addr);
1994 tf.lbal = readb(ap->ioaddr.lbal_addr);
1995 tf.nsect = readb(ap->ioaddr.nsect_addr);
1997 dev->class = ata_dev_classify(&tf);
1998 if (!ata_dev_enabled(dev)) {
1999 VPRINTK("Port disabled post-sig: No device present.\n");
2000 ata_port_disable(ap);
2003 writelfl(0, port_mmio + EDMA_ERR_IRQ_CAUSE_OFS);
2005 pp->pp_flags &= ~MV_PP_FLAG_EDMA_EN;
2010 static void mv_phy_reset(struct ata_port *ap)
2012 __mv_phy_reset(ap, 1);
2016 * mv_eng_timeout - Routine called by libata when SCSI times out I/O
2017 * @ap: ATA channel to manipulate
2019 * Intent is to clear all pending error conditions, reset the
2020 * chip/bus, fail the command, and move on.
2023 * This routine holds the host lock while failing the command.
2025 static void mv_eng_timeout(struct ata_port *ap)
2027 void __iomem *mmio = ap->host->iomap[MV_PRIMARY_BAR];
2028 struct ata_queued_cmd *qc;
2029 unsigned long flags;
2031 ata_port_printk(ap, KERN_ERR, "Entering mv_eng_timeout\n");
2032 DPRINTK("All regs @ start of eng_timeout\n");
2033 mv_dump_all_regs(mmio, ap->port_no, to_pci_dev(ap->host->dev));
2035 qc = ata_qc_from_tag(ap, ap->active_tag);
2036 printk(KERN_ERR "mmio_base %p ap %p qc %p scsi_cmnd %p &cmnd %p\n",
2037 mmio, ap, qc, qc->scsicmd, &qc->scsicmd->cmnd);
2039 spin_lock_irqsave(&ap->host->lock, flags);
2041 mv_stop_and_reset(ap);
2042 spin_unlock_irqrestore(&ap->host->lock, flags);
2044 WARN_ON(!(qc->flags & ATA_QCFLAG_ACTIVE));
2045 if (qc->flags & ATA_QCFLAG_ACTIVE) {
2046 qc->err_mask |= AC_ERR_TIMEOUT;
2047 ata_eh_qc_complete(qc);
2052 * mv_port_init - Perform some early initialization on a single port.
2053 * @port: libata data structure storing shadow register addresses
2054 * @port_mmio: base address of the port
2056 * Initialize shadow register mmio addresses, clear outstanding
2057 * interrupts on the port, and unmask interrupts for the future
2058 * start of the port.
2061 * Inherited from caller.
2063 static void mv_port_init(struct ata_ioports *port, void __iomem *port_mmio)
2065 void __iomem *shd_base = port_mmio + SHD_BLK_OFS;
2068 /* PIO related setup
2070 port->data_addr = shd_base + (sizeof(u32) * ATA_REG_DATA);
2072 port->feature_addr = shd_base + (sizeof(u32) * ATA_REG_ERR);
2073 port->nsect_addr = shd_base + (sizeof(u32) * ATA_REG_NSECT);
2074 port->lbal_addr = shd_base + (sizeof(u32) * ATA_REG_LBAL);
2075 port->lbam_addr = shd_base + (sizeof(u32) * ATA_REG_LBAM);
2076 port->lbah_addr = shd_base + (sizeof(u32) * ATA_REG_LBAH);
2077 port->device_addr = shd_base + (sizeof(u32) * ATA_REG_DEVICE);
2079 port->command_addr = shd_base + (sizeof(u32) * ATA_REG_STATUS);
2080 /* special case: control/altstatus doesn't have ATA_REG_ address */
2081 port->altstatus_addr = port->ctl_addr = shd_base + SHD_CTL_AST_OFS;
2084 port->cmd_addr = port->bmdma_addr = port->scr_addr = NULL;
2086 /* Clear any currently outstanding port interrupt conditions */
2087 serr_ofs = mv_scr_offset(SCR_ERROR);
2088 writelfl(readl(port_mmio + serr_ofs), port_mmio + serr_ofs);
2089 writelfl(0, port_mmio + EDMA_ERR_IRQ_CAUSE_OFS);
2091 /* unmask all EDMA error interrupts */
2092 writelfl(~0, port_mmio + EDMA_ERR_IRQ_MASK_OFS);
2094 VPRINTK("EDMA cfg=0x%08x EDMA IRQ err cause/mask=0x%08x/0x%08x\n",
2095 readl(port_mmio + EDMA_CFG_OFS),
2096 readl(port_mmio + EDMA_ERR_IRQ_CAUSE_OFS),
2097 readl(port_mmio + EDMA_ERR_IRQ_MASK_OFS));
2100 static int mv_chip_id(struct pci_dev *pdev, struct mv_host_priv *hpriv,
2101 unsigned int board_idx)
2104 u32 hp_flags = hpriv->hp_flags;
2106 pci_read_config_byte(pdev, PCI_REVISION_ID, &rev_id);
2110 hpriv->ops = &mv5xxx_ops;
2111 hp_flags |= MV_HP_50XX;
2115 hp_flags |= MV_HP_ERRATA_50XXB0;
2118 hp_flags |= MV_HP_ERRATA_50XXB2;
2121 dev_printk(KERN_WARNING, &pdev->dev,
2122 "Applying 50XXB2 workarounds to unknown rev\n");
2123 hp_flags |= MV_HP_ERRATA_50XXB2;
2130 hpriv->ops = &mv5xxx_ops;
2131 hp_flags |= MV_HP_50XX;
2135 hp_flags |= MV_HP_ERRATA_50XXB0;
2138 hp_flags |= MV_HP_ERRATA_50XXB2;
2141 dev_printk(KERN_WARNING, &pdev->dev,
2142 "Applying B2 workarounds to unknown rev\n");
2143 hp_flags |= MV_HP_ERRATA_50XXB2;
2150 hpriv->ops = &mv6xxx_ops;
2154 hp_flags |= MV_HP_ERRATA_60X1B2;
2157 hp_flags |= MV_HP_ERRATA_60X1C0;
2160 dev_printk(KERN_WARNING, &pdev->dev,
2161 "Applying B2 workarounds to unknown rev\n");
2162 hp_flags |= MV_HP_ERRATA_60X1B2;
2169 hpriv->ops = &mv6xxx_ops;
2171 hp_flags |= MV_HP_GEN_IIE;
2175 hp_flags |= MV_HP_ERRATA_XX42A0;
2178 hp_flags |= MV_HP_ERRATA_60X1C0;
2181 dev_printk(KERN_WARNING, &pdev->dev,
2182 "Applying 60X1C0 workarounds to unknown rev\n");
2183 hp_flags |= MV_HP_ERRATA_60X1C0;
2189 printk(KERN_ERR DRV_NAME ": BUG: invalid board index %u\n", board_idx);
2193 hpriv->hp_flags = hp_flags;
2199 * mv_init_host - Perform some early initialization of the host.
2200 * @pdev: host PCI device
2201 * @probe_ent: early data struct representing the host
2203 * If possible, do an early global reset of the host. Then do
2204 * our port init and clear/unmask all/relevant host interrupts.
2207 * Inherited from caller.
2209 static int mv_init_host(struct pci_dev *pdev, struct ata_probe_ent *probe_ent,
2210 unsigned int board_idx)
2212 int rc = 0, n_hc, port, hc;
2213 void __iomem *mmio = probe_ent->iomap[MV_PRIMARY_BAR];
2214 struct mv_host_priv *hpriv = probe_ent->private_data;
2216 /* global interrupt mask */
2217 writel(0, mmio + HC_MAIN_IRQ_MASK_OFS);
2219 rc = mv_chip_id(pdev, hpriv, board_idx);
2223 n_hc = mv_get_hc_count(probe_ent->port_flags);
2224 probe_ent->n_ports = MV_PORTS_PER_HC * n_hc;
2226 for (port = 0; port < probe_ent->n_ports; port++)
2227 hpriv->ops->read_preamp(hpriv, port, mmio);
2229 rc = hpriv->ops->reset_hc(hpriv, mmio, n_hc);
2233 hpriv->ops->reset_flash(hpriv, mmio);
2234 hpriv->ops->reset_bus(pdev, mmio);
2235 hpriv->ops->enable_leds(hpriv, mmio);
2237 for (port = 0; port < probe_ent->n_ports; port++) {
2238 if (IS_60XX(hpriv)) {
2239 void __iomem *port_mmio = mv_port_base(mmio, port);
2241 u32 ifctl = readl(port_mmio + SATA_INTERFACE_CTL);
2242 ifctl |= (1 << 7); /* enable gen2i speed */
2243 ifctl = (ifctl & 0xfff) | 0x9b1000; /* from chip spec */
2244 writelfl(ifctl, port_mmio + SATA_INTERFACE_CTL);
2247 hpriv->ops->phy_errata(hpriv, mmio, port);
2250 for (port = 0; port < probe_ent->n_ports; port++) {
2251 void __iomem *port_mmio = mv_port_base(mmio, port);
2252 mv_port_init(&probe_ent->port[port], port_mmio);
2255 for (hc = 0; hc < n_hc; hc++) {
2256 void __iomem *hc_mmio = mv_hc_base(mmio, hc);
2258 VPRINTK("HC%i: HC config=0x%08x HC IRQ cause "
2259 "(before clear)=0x%08x\n", hc,
2260 readl(hc_mmio + HC_CFG_OFS),
2261 readl(hc_mmio + HC_IRQ_CAUSE_OFS));
2263 /* Clear any currently outstanding hc interrupt conditions */
2264 writelfl(0, hc_mmio + HC_IRQ_CAUSE_OFS);
2267 /* Clear any currently outstanding host interrupt conditions */
2268 writelfl(0, mmio + PCI_IRQ_CAUSE_OFS);
2270 /* and unmask interrupt generation for host regs */
2271 writelfl(PCI_UNMASK_ALL_IRQS, mmio + PCI_IRQ_MASK_OFS);
2274 writelfl(~HC_MAIN_MASKED_IRQS_5, mmio + HC_MAIN_IRQ_MASK_OFS);
2276 writelfl(~HC_MAIN_MASKED_IRQS, mmio + HC_MAIN_IRQ_MASK_OFS);
2278 VPRINTK("HC MAIN IRQ cause/mask=0x%08x/0x%08x "
2279 "PCI int cause/mask=0x%08x/0x%08x\n",
2280 readl(mmio + HC_MAIN_IRQ_CAUSE_OFS),
2281 readl(mmio + HC_MAIN_IRQ_MASK_OFS),
2282 readl(mmio + PCI_IRQ_CAUSE_OFS),
2283 readl(mmio + PCI_IRQ_MASK_OFS));
2290 * mv_print_info - Dump key info to kernel log for perusal.
2291 * @probe_ent: early data struct representing the host
2293 * FIXME: complete this.
2296 * Inherited from caller.
2298 static void mv_print_info(struct ata_probe_ent *probe_ent)
2300 struct pci_dev *pdev = to_pci_dev(probe_ent->dev);
2301 struct mv_host_priv *hpriv = probe_ent->private_data;
2305 /* Use this to determine the HW stepping of the chip so we know
2306 * what errata to workaround
2308 pci_read_config_byte(pdev, PCI_REVISION_ID, &rev_id);
2310 pci_read_config_byte(pdev, PCI_CLASS_DEVICE, &scc);
2313 else if (scc == 0x01)
2318 dev_printk(KERN_INFO, &pdev->dev,
2319 "%u slots %u ports %s mode IRQ via %s\n",
2320 (unsigned)MV_MAX_Q_DEPTH, probe_ent->n_ports,
2321 scc_s, (MV_HP_FLAG_MSI & hpriv->hp_flags) ? "MSI" : "INTx");
2325 * mv_init_one - handle a positive probe of a Marvell host
2326 * @pdev: PCI device found
2327 * @ent: PCI device ID entry for the matched host
2330 * Inherited from caller.
2332 static int mv_init_one(struct pci_dev *pdev, const struct pci_device_id *ent)
2334 static int printed_version = 0;
2335 struct device *dev = &pdev->dev;
2336 struct ata_probe_ent *probe_ent;
2337 struct mv_host_priv *hpriv;
2338 unsigned int board_idx = (unsigned int)ent->driver_data;
2341 if (!printed_version++)
2342 dev_printk(KERN_INFO, &pdev->dev, "version " DRV_VERSION "\n");
2344 rc = pcim_enable_device(pdev);
2347 pci_set_master(pdev);
2349 rc = pcim_iomap_regions(pdev, 1 << MV_PRIMARY_BAR, DRV_NAME);
2351 pcim_pin_device(pdev);
2355 rc = pci_go_64(pdev);
2359 probe_ent = devm_kzalloc(dev, sizeof(*probe_ent), GFP_KERNEL);
2360 if (probe_ent == NULL)
2363 probe_ent->dev = pci_dev_to_dev(pdev);
2364 INIT_LIST_HEAD(&probe_ent->node);
2366 hpriv = devm_kzalloc(dev, sizeof(*hpriv), GFP_KERNEL);
2370 probe_ent->sht = mv_port_info[board_idx].sht;
2371 probe_ent->port_flags = mv_port_info[board_idx].flags;
2372 probe_ent->pio_mask = mv_port_info[board_idx].pio_mask;
2373 probe_ent->udma_mask = mv_port_info[board_idx].udma_mask;
2374 probe_ent->port_ops = mv_port_info[board_idx].port_ops;
2376 probe_ent->irq = pdev->irq;
2377 probe_ent->irq_flags = IRQF_SHARED;
2378 probe_ent->iomap = pcim_iomap_table(pdev);
2379 probe_ent->private_data = hpriv;
2381 /* initialize adapter */
2382 rc = mv_init_host(pdev, probe_ent, board_idx);
2386 /* Enable interrupts */
2387 if (msi && pci_enable_msi(pdev))
2390 mv_dump_pci_cfg(pdev, 0x68);
2391 mv_print_info(probe_ent);
2393 if (ata_device_add(probe_ent) == 0)
2396 devm_kfree(dev, probe_ent);
2400 static int __init mv_init(void)
2402 return pci_register_driver(&mv_pci_driver);
2405 static void __exit mv_exit(void)
2407 pci_unregister_driver(&mv_pci_driver);
2410 MODULE_AUTHOR("Brett Russ");
2411 MODULE_DESCRIPTION("SCSI low-level driver for Marvell SATA controllers");
2412 MODULE_LICENSE("GPL");
2413 MODULE_DEVICE_TABLE(pci, mv_pci_tbl);
2414 MODULE_VERSION(DRV_VERSION);
2416 module_param(msi, int, 0444);
2417 MODULE_PARM_DESC(msi, "Enable use of PCI MSI (0=off, 1=on)");
2419 module_init(mv_init);
2420 module_exit(mv_exit);