2 * sata_inic162x.c - Driver for Initio 162x SATA controllers
4 * Copyright 2006 SUSE Linux Products GmbH
5 * Copyright 2006 Tejun Heo <teheo@novell.com>
7 * This file is released under GPL v2.
9 * This controller is eccentric and easily locks up if something isn't
10 * right. Documentation is available at initio's website but it only
11 * documents registers (not programming model).
15 * - ATAPI read works but burning doesn't. This thing is really
16 * peculiar about ATAPI and I couldn't figure out how ATAPI PIO and
17 * ATAPI DMA WRITE should be programmed. If you've got a clue, be
19 * - Both STR and STD work.
22 #include <linux/kernel.h>
23 #include <linux/module.h>
24 #include <linux/pci.h>
25 #include <scsi/scsi_host.h>
26 #include <linux/libata.h>
27 #include <linux/blkdev.h>
28 #include <scsi/scsi_device.h>
30 #define DRV_NAME "sata_inic162x"
31 #define DRV_VERSION "0.1"
45 /* registers for ATA TF operation */
52 PORT_PRD_XFERLEN = 0x10,
60 HCTL_IRQOFF = (1 << 8), /* global IRQ off */
61 HCTL_PWRDWN = (1 << 13), /* power down PHYs */
62 HCTL_SOFTRST = (1 << 13), /* global reset (no phy reset) */
63 HCTL_RPGSEL = (1 << 15), /* register page select */
65 HCTL_KNOWN_BITS = HCTL_IRQOFF | HCTL_PWRDWN | HCTL_SOFTRST |
68 /* HOST_IRQ_(STAT|MASK) bits */
69 HIRQ_PORT0 = (1 << 0),
70 HIRQ_PORT1 = (1 << 1),
71 HIRQ_SOFT = (1 << 14),
72 HIRQ_GLOBAL = (1 << 15), /* STAT only */
74 /* PORT_IRQ_(STAT|MASK) bits */
75 PIRQ_OFFLINE = (1 << 0), /* device unplugged */
76 PIRQ_ONLINE = (1 << 1), /* device plugged */
77 PIRQ_COMPLETE = (1 << 2), /* completion interrupt */
78 PIRQ_FATAL = (1 << 3), /* fatal error */
79 PIRQ_ATA = (1 << 4), /* ATA interrupt */
80 PIRQ_REPLY = (1 << 5), /* reply FIFO not empty */
81 PIRQ_PENDING = (1 << 7), /* port IRQ pending (STAT only) */
83 PIRQ_ERR = PIRQ_OFFLINE | PIRQ_ONLINE | PIRQ_FATAL,
85 PIRQ_MASK_DMA_READ = PIRQ_REPLY | PIRQ_ATA,
86 PIRQ_MASK_OTHER = PIRQ_REPLY | PIRQ_COMPLETE,
87 PIRQ_MASK_FREEZE = 0xff,
89 /* PORT_PRD_CTL bits */
90 PRD_CTL_START = (1 << 0),
91 PRD_CTL_WR = (1 << 3),
92 PRD_CTL_DMAEN = (1 << 7), /* DMA enable */
94 /* PORT_IDMA_CTL bits */
95 IDMA_CTL_RST_ATA = (1 << 2), /* hardreset ATA bus */
96 IDMA_CTL_RST_IDMA = (1 << 5), /* reset IDMA machinary */
97 IDMA_CTL_GO = (1 << 7), /* IDMA mode go */
98 IDMA_CTL_ATA_NIEN = (1 << 8), /* ATA IRQ disable */
101 struct inic_host_priv {
105 struct inic_port_priv {
111 static int inic_slave_config(struct scsi_device *sdev)
113 /* This controller is braindamaged. dma_boundary is 0xffff
114 * like others but it will lock up the whole machine HARD if
115 * 65536 byte PRD entry is fed. Reduce maximum segment size.
117 blk_queue_max_segment_size(sdev->request_queue, 65536 - 512);
119 return ata_scsi_slave_config(sdev);
122 static struct scsi_host_template inic_sht = {
123 .module = THIS_MODULE,
125 .ioctl = ata_scsi_ioctl,
126 .queuecommand = ata_scsi_queuecmd,
127 .can_queue = ATA_DEF_QUEUE,
128 .this_id = ATA_SHT_THIS_ID,
129 .sg_tablesize = LIBATA_MAX_PRD,
130 .cmd_per_lun = ATA_SHT_CMD_PER_LUN,
131 .emulated = ATA_SHT_EMULATED,
132 .use_clustering = ATA_SHT_USE_CLUSTERING,
133 .proc_name = DRV_NAME,
134 .dma_boundary = ATA_DMA_BOUNDARY,
135 .slave_configure = inic_slave_config,
136 .slave_destroy = ata_scsi_slave_destroy,
137 .bios_param = ata_std_bios_param,
138 .suspend = ata_scsi_device_suspend,
139 .resume = ata_scsi_device_resume,
142 static const int scr_map[] = {
148 static void __iomem * inic_port_base(struct ata_port *ap)
150 return ap->host->mmio_base + ap->port_no * PORT_SIZE;
153 static void __inic_set_pirq_mask(struct ata_port *ap, u8 mask)
155 void __iomem *port_base = inic_port_base(ap);
156 struct inic_port_priv *pp = ap->private_data;
158 writeb(mask, port_base + PORT_IRQ_MASK);
159 pp->cached_pirq_mask = mask;
162 static void inic_set_pirq_mask(struct ata_port *ap, u8 mask)
164 struct inic_port_priv *pp = ap->private_data;
166 if (pp->cached_pirq_mask != mask)
167 __inic_set_pirq_mask(ap, mask);
170 static void inic_reset_port(void __iomem *port_base)
172 void __iomem *idma_ctl = port_base + PORT_IDMA_CTL;
175 ctl = readw(idma_ctl);
176 ctl &= ~(IDMA_CTL_RST_IDMA | IDMA_CTL_ATA_NIEN | IDMA_CTL_GO);
178 /* mask IRQ and assert reset */
179 writew(ctl | IDMA_CTL_RST_IDMA | IDMA_CTL_ATA_NIEN, idma_ctl);
180 readw(idma_ctl); /* flush */
182 /* give it some time */
186 writew(ctl | IDMA_CTL_ATA_NIEN, idma_ctl);
189 writeb(0xff, port_base + PORT_IRQ_STAT);
191 /* reenable ATA IRQ, turn off IDMA mode */
192 writew(ctl, idma_ctl);
195 static u32 inic_scr_read(struct ata_port *ap, unsigned sc_reg)
197 void __iomem *scr_addr = (void __iomem *)ap->ioaddr.scr_addr;
201 if (unlikely(sc_reg >= ARRAY_SIZE(scr_map)))
204 addr = scr_addr + scr_map[sc_reg] * 4;
205 val = readl(scr_addr + scr_map[sc_reg] * 4);
207 /* this controller has stuck DIAG.N, ignore it */
208 if (sc_reg == SCR_ERROR)
209 val &= ~SERR_PHYRDY_CHG;
213 static void inic_scr_write(struct ata_port *ap, unsigned sc_reg, u32 val)
215 void __iomem *scr_addr = (void __iomem *)ap->ioaddr.scr_addr;
218 if (unlikely(sc_reg >= ARRAY_SIZE(scr_map)))
221 addr = scr_addr + scr_map[sc_reg] * 4;
222 writel(val, scr_addr + scr_map[sc_reg] * 4);
226 * In TF mode, inic162x is very similar to SFF device. TF registers
227 * function the same. DMA engine behaves similary using the same PRD
228 * format as BMDMA but different command register, interrupt and event
229 * notification methods are used. The following inic_bmdma_*()
230 * functions do the impedance matching.
232 static void inic_bmdma_setup(struct ata_queued_cmd *qc)
234 struct ata_port *ap = qc->ap;
235 struct inic_port_priv *pp = ap->private_data;
236 void __iomem *port_base = inic_port_base(ap);
237 int rw = qc->tf.flags & ATA_TFLAG_WRITE;
239 /* make sure device sees PRD table writes */
242 /* load transfer length */
243 writel(qc->nbytes, port_base + PORT_PRD_XFERLEN);
245 /* turn on DMA and specify data direction */
246 pp->cached_prdctl = pp->dfl_prdctl | PRD_CTL_DMAEN;
248 pp->cached_prdctl |= PRD_CTL_WR;
249 writeb(pp->cached_prdctl, port_base + PORT_PRD_CTL);
251 /* issue r/w command */
252 ap->ops->exec_command(ap, &qc->tf);
255 static void inic_bmdma_start(struct ata_queued_cmd *qc)
257 struct ata_port *ap = qc->ap;
258 struct inic_port_priv *pp = ap->private_data;
259 void __iomem *port_base = inic_port_base(ap);
261 /* start host DMA transaction */
262 pp->cached_prdctl |= PRD_CTL_START;
263 writeb(pp->cached_prdctl, port_base + PORT_PRD_CTL);
266 static void inic_bmdma_stop(struct ata_queued_cmd *qc)
268 struct ata_port *ap = qc->ap;
269 struct inic_port_priv *pp = ap->private_data;
270 void __iomem *port_base = inic_port_base(ap);
272 /* stop DMA engine */
273 writeb(pp->dfl_prdctl, port_base + PORT_PRD_CTL);
276 static u8 inic_bmdma_status(struct ata_port *ap)
278 /* event is already verified by the interrupt handler */
282 static void inic_irq_clear(struct ata_port *ap)
287 static void inic_host_intr(struct ata_port *ap)
289 void __iomem *port_base = inic_port_base(ap);
290 struct ata_eh_info *ehi = &ap->eh_info;
293 /* fetch and clear irq */
294 irq_stat = readb(port_base + PORT_IRQ_STAT);
295 writeb(irq_stat, port_base + PORT_IRQ_STAT);
297 if (likely(!(irq_stat & PIRQ_ERR))) {
298 struct ata_queued_cmd *qc = ata_qc_from_tag(ap, ap->active_tag);
300 if (unlikely(!qc || (qc->tf.flags & ATA_TFLAG_POLLING))) {
301 ata_chk_status(ap); /* clear ATA interrupt */
305 if (likely(ata_host_intr(ap, qc)))
308 ata_chk_status(ap); /* clear ATA interrupt */
309 ata_port_printk(ap, KERN_WARNING, "unhandled "
310 "interrupt, irq_stat=%x\n", irq_stat);
315 ata_ehi_push_desc(ehi, "irq_stat=0x%x", irq_stat);
317 if (irq_stat & (PIRQ_OFFLINE | PIRQ_ONLINE)) {
318 ata_ehi_hotplugged(ehi);
324 static irqreturn_t inic_interrupt(int irq, void *dev_instance)
326 struct ata_host *host = dev_instance;
327 void __iomem *mmio_base = host->mmio_base;
331 host_irq_stat = readw(mmio_base + HOST_IRQ_STAT);
333 if (unlikely(!(host_irq_stat & HIRQ_GLOBAL)))
336 spin_lock(&host->lock);
338 for (i = 0; i < NR_PORTS; i++) {
339 struct ata_port *ap = host->ports[i];
341 if (!(host_irq_stat & (HIRQ_PORT0 << i)))
344 if (likely(ap && !(ap->flags & ATA_FLAG_DISABLED))) {
349 dev_printk(KERN_ERR, host->dev, "interrupt "
350 "from disabled port %d (0x%x)\n",
355 spin_unlock(&host->lock);
358 return IRQ_RETVAL(handled);
361 static unsigned int inic_qc_issue(struct ata_queued_cmd *qc)
363 struct ata_port *ap = qc->ap;
365 /* ATA IRQ doesn't wait for DMA transfer completion and vice
366 * versa. Mask IRQ selectively to detect command completion.
367 * Without it, ATA DMA read command can cause data corruption.
369 * Something similar might be needed for ATAPI writes. I
370 * tried a lot of combinations but couldn't find the solution.
372 if (qc->tf.protocol == ATA_PROT_DMA &&
373 !(qc->tf.flags & ATA_TFLAG_WRITE))
374 inic_set_pirq_mask(ap, PIRQ_MASK_DMA_READ);
376 inic_set_pirq_mask(ap, PIRQ_MASK_OTHER);
378 /* Issuing a command to yet uninitialized port locks up the
379 * controller. Most of the time, this happens for the first
380 * command after reset which are ATA and ATAPI IDENTIFYs.
381 * Fast fail if stat is 0x7f or 0xff for those commands.
383 if (unlikely(qc->tf.command == ATA_CMD_ID_ATA ||
384 qc->tf.command == ATA_CMD_ID_ATAPI)) {
385 u8 stat = ata_chk_status(ap);
386 if (stat == 0x7f || stat == 0xff)
390 return ata_qc_issue_prot(qc);
393 static void inic_freeze(struct ata_port *ap)
395 void __iomem *port_base = inic_port_base(ap);
397 __inic_set_pirq_mask(ap, PIRQ_MASK_FREEZE);
400 writeb(0xff, port_base + PORT_IRQ_STAT);
402 readb(port_base + PORT_IRQ_STAT); /* flush */
405 static void inic_thaw(struct ata_port *ap)
407 void __iomem *port_base = inic_port_base(ap);
410 writeb(0xff, port_base + PORT_IRQ_STAT);
412 __inic_set_pirq_mask(ap, PIRQ_MASK_OTHER);
414 readb(port_base + PORT_IRQ_STAT); /* flush */
418 * SRST and SControl hardreset don't give valid signature on this
419 * controller. Only controller specific hardreset mechanism works.
421 static int inic_hardreset(struct ata_port *ap, unsigned int *class)
423 void __iomem *port_base = inic_port_base(ap);
424 void __iomem *idma_ctl = port_base + PORT_IDMA_CTL;
425 const unsigned long *timing = sata_ehc_deb_timing(&ap->eh_context);
429 /* hammer it into sane state */
430 inic_reset_port(port_base);
432 if (ata_port_offline(ap)) {
433 *class = ATA_DEV_NONE;
437 val = readw(idma_ctl);
438 writew(val | IDMA_CTL_RST_ATA, idma_ctl);
439 readw(idma_ctl); /* flush */
441 writew(val & ~IDMA_CTL_RST_ATA, idma_ctl);
443 rc = sata_phy_resume(ap, timing);
445 ata_port_printk(ap, KERN_WARNING, "failed to resume "
446 "link for reset (errno=%d)\n", rc);
452 *class = ATA_DEV_NONE;
453 if (ata_port_online(ap)) {
454 struct ata_taskfile tf;
456 if (ata_busy_sleep(ap, ATA_TMOUT_BOOT_QUICK, ATA_TMOUT_BOOT)) {
457 ata_port_printk(ap, KERN_WARNING,
458 "device busy after hardreset\n");
462 ata_tf_read(ap, &tf);
463 *class = ata_dev_classify(&tf);
464 if (*class == ATA_DEV_UNKNOWN)
465 *class = ATA_DEV_NONE;
471 static void inic_error_handler(struct ata_port *ap)
473 void __iomem *port_base = inic_port_base(ap);
474 struct inic_port_priv *pp = ap->private_data;
477 /* reset PIO HSM and stop DMA engine */
478 inic_reset_port(port_base);
480 spin_lock_irqsave(ap->lock, flags);
481 ap->hsm_task_state = HSM_ST_IDLE;
482 writeb(pp->dfl_prdctl, port_base + PORT_PRD_CTL);
483 spin_unlock_irqrestore(ap->lock, flags);
485 /* PIO and DMA engines have been stopped, perform recovery */
486 ata_do_eh(ap, ata_std_prereset, NULL, inic_hardreset,
490 static void inic_post_internal_cmd(struct ata_queued_cmd *qc)
492 /* make DMA engine forget about the failed command */
494 inic_reset_port(inic_port_base(qc->ap));
497 static void inic_dev_config(struct ata_port *ap, struct ata_device *dev)
499 /* inic can only handle upto LBA28 max sectors */
500 if (dev->max_sectors > ATA_MAX_SECTORS)
501 dev->max_sectors = ATA_MAX_SECTORS;
504 static void init_port(struct ata_port *ap)
506 void __iomem *port_base = inic_port_base(ap);
508 /* Setup PRD address */
509 writel(ap->prd_dma, port_base + PORT_PRD_ADDR);
512 static int inic_port_resume(struct ata_port *ap)
518 static int inic_port_start(struct ata_port *ap)
520 void __iomem *port_base = inic_port_base(ap);
521 struct inic_port_priv *pp;
525 /* alloc and initialize private data */
526 pp = kzalloc(sizeof(*pp), GFP_KERNEL);
529 ap->private_data = pp;
531 /* default PRD_CTL value, DMAEN, WR and START off */
532 tmp = readb(port_base + PORT_PRD_CTL);
533 tmp &= ~(PRD_CTL_DMAEN | PRD_CTL_WR | PRD_CTL_START);
534 pp->dfl_prdctl = tmp;
536 /* Alloc resources */
537 rc = ata_port_start(ap);
548 static void inic_port_stop(struct ata_port *ap)
551 kfree(ap->private_data);
554 static struct ata_port_operations inic_port_ops = {
555 .port_disable = ata_port_disable,
556 .tf_load = ata_tf_load,
557 .tf_read = ata_tf_read,
558 .check_status = ata_check_status,
559 .exec_command = ata_exec_command,
560 .dev_select = ata_std_dev_select,
562 .scr_read = inic_scr_read,
563 .scr_write = inic_scr_write,
565 .bmdma_setup = inic_bmdma_setup,
566 .bmdma_start = inic_bmdma_start,
567 .bmdma_stop = inic_bmdma_stop,
568 .bmdma_status = inic_bmdma_status,
570 .irq_handler = inic_interrupt,
571 .irq_clear = inic_irq_clear,
573 .qc_prep = ata_qc_prep,
574 .qc_issue = inic_qc_issue,
575 .data_xfer = ata_pio_data_xfer,
577 .freeze = inic_freeze,
579 .error_handler = inic_error_handler,
580 .post_internal_cmd = inic_post_internal_cmd,
581 .dev_config = inic_dev_config,
583 .port_resume = inic_port_resume,
585 .port_start = inic_port_start,
586 .port_stop = inic_port_stop,
587 .host_stop = ata_pci_host_stop
590 static struct ata_port_info inic_port_info = {
592 /* For some reason, ATA_PROT_ATAPI is broken on this
593 * controller, and no, PIO_POLLING does't fix it. It somehow
594 * manages to report the wrong ireason and ignoring ireason
595 * results in machine lock up. Tell libata to always prefer
598 .flags = ATA_FLAG_SATA | ATA_FLAG_PIO_DMA,
599 .pio_mask = 0x1f, /* pio0-4 */
600 .mwdma_mask = 0x07, /* mwdma0-2 */
601 .udma_mask = 0x7f, /* udma0-6 */
602 .port_ops = &inic_port_ops
605 static int init_controller(void __iomem *mmio_base, u16 hctl)
610 hctl &= ~HCTL_KNOWN_BITS;
612 /* Soft reset whole controller. Spec says reset duration is 3
613 * PCI clocks, be generous and give it 10ms.
615 writew(hctl | HCTL_SOFTRST, mmio_base + HOST_CTL);
616 readw(mmio_base + HOST_CTL); /* flush */
618 for (i = 0; i < 10; i++) {
620 val = readw(mmio_base + HOST_CTL);
621 if (!(val & HCTL_SOFTRST))
625 if (val & HCTL_SOFTRST)
628 /* mask all interrupts and reset ports */
629 for (i = 0; i < NR_PORTS; i++) {
630 void __iomem *port_base = mmio_base + i * PORT_SIZE;
632 writeb(0xff, port_base + PORT_IRQ_MASK);
633 inic_reset_port(port_base);
636 /* port IRQ is masked now, unmask global IRQ */
637 writew(hctl & ~HCTL_IRQOFF, mmio_base + HOST_CTL);
638 val = readw(mmio_base + HOST_IRQ_MASK);
639 val &= ~(HIRQ_PORT0 | HIRQ_PORT1);
640 writew(val, mmio_base + HOST_IRQ_MASK);
645 static int inic_pci_device_resume(struct pci_dev *pdev)
647 struct ata_host *host = dev_get_drvdata(&pdev->dev);
648 struct inic_host_priv *hpriv = host->private_data;
649 void __iomem *mmio_base = host->mmio_base;
652 ata_pci_device_do_resume(pdev);
654 if (pdev->dev.power.power_state.event == PM_EVENT_SUSPEND) {
656 rc = init_controller(mmio_base, hpriv->cached_hctl);
661 ata_host_resume(host);
666 static int inic_init_one(struct pci_dev *pdev, const struct pci_device_id *ent)
668 static int printed_version;
669 struct ata_port_info *pinfo = &inic_port_info;
670 struct ata_probe_ent *probe_ent;
671 struct inic_host_priv *hpriv;
672 void __iomem *mmio_base;
675 if (!printed_version++)
676 dev_printk(KERN_DEBUG, &pdev->dev, "version " DRV_VERSION "\n");
678 rc = pci_enable_device(pdev);
682 rc = pci_request_regions(pdev, DRV_NAME);
687 mmio_base = pci_iomap(pdev, MMIO_BAR, 0);
689 goto err_out_regions;
691 /* Set dma_mask. This devices doesn't support 64bit addressing. */
692 rc = pci_set_dma_mask(pdev, DMA_32BIT_MASK);
694 dev_printk(KERN_ERR, &pdev->dev,
695 "32-bit DMA enable failed\n");
699 rc = pci_set_consistent_dma_mask(pdev, DMA_32BIT_MASK);
701 dev_printk(KERN_ERR, &pdev->dev,
702 "32-bit consistent DMA enable failed\n");
707 probe_ent = kzalloc(sizeof(*probe_ent), GFP_KERNEL);
711 hpriv = kzalloc(sizeof(*hpriv), GFP_KERNEL);
715 probe_ent->dev = &pdev->dev;
716 INIT_LIST_HEAD(&probe_ent->node);
718 probe_ent->sht = pinfo->sht;
719 probe_ent->port_flags = pinfo->flags;
720 probe_ent->pio_mask = pinfo->pio_mask;
721 probe_ent->mwdma_mask = pinfo->mwdma_mask;
722 probe_ent->udma_mask = pinfo->udma_mask;
723 probe_ent->port_ops = pinfo->port_ops;
724 probe_ent->n_ports = NR_PORTS;
726 probe_ent->irq = pdev->irq;
727 probe_ent->irq_flags = SA_SHIRQ;
729 probe_ent->mmio_base = mmio_base;
731 for (i = 0; i < NR_PORTS; i++) {
732 struct ata_ioports *port = &probe_ent->port[i];
733 unsigned long port_base =
734 (unsigned long)mmio_base + i * PORT_SIZE;
736 port->cmd_addr = pci_resource_start(pdev, 2 * i);
737 port->altstatus_addr =
739 pci_resource_start(pdev, 2 * i + 1) | ATA_PCI_CTL_OFS;
740 port->scr_addr = port_base + PORT_SCR;
745 probe_ent->private_data = hpriv;
746 hpriv->cached_hctl = readw(mmio_base + HOST_CTL);
748 rc = init_controller(mmio_base, hpriv->cached_hctl);
750 dev_printk(KERN_ERR, &pdev->dev,
751 "failed to initialize controller\n");
755 pci_set_master(pdev);
758 if (!ata_device_add(probe_ent))
770 pci_iounmap(pdev, mmio_base);
772 pci_release_regions(pdev);
774 pci_disable_device(pdev);
778 static const struct pci_device_id inic_pci_tbl[] = {
779 { PCI_VDEVICE(INIT, 0x1622), },
783 static struct pci_driver inic_pci_driver = {
785 .id_table = inic_pci_tbl,
786 .suspend = ata_pci_device_suspend,
787 .resume = inic_pci_device_resume,
788 .probe = inic_init_one,
789 .remove = ata_pci_remove_one,
792 static int __init inic_init(void)
794 return pci_register_driver(&inic_pci_driver);
797 static void __exit inic_exit(void)
799 pci_unregister_driver(&inic_pci_driver);
802 MODULE_AUTHOR("Tejun Heo");
803 MODULE_DESCRIPTION("low-level driver for Initio 162x SATA");
804 MODULE_LICENSE("GPL v2");
805 MODULE_DEVICE_TABLE(pci, inic_pci_tbl);
806 MODULE_VERSION(DRV_VERSION);
808 module_init(inic_init);
809 module_exit(inic_exit);