2 * Support for IDE interfaces on Celleb platform
4 * (C) Copyright 2006 TOSHIBA CORPORATION
6 * This code is based on drivers/ata/ata_piix.c:
7 * Copyright 2003-2005 Red Hat Inc
8 * Copyright 2003-2005 Jeff Garzik
9 * Copyright (C) 1998-1999 Andrzej Krzysztofowicz, Author and Maintainer
10 * Copyright (C) 1998-2000 Andre Hedrick <andre@linux-ide.org>
11 * Copyright (C) 2003 Red Hat Inc <alan@redhat.com>
13 * and drivers/ata/ahci.c:
14 * Copyright 2004-2005 Red Hat, Inc.
16 * and drivers/ata/libata-core.c:
17 * Copyright 2003-2004 Red Hat, Inc. All rights reserved.
18 * Copyright 2003-2004 Jeff Garzik
20 * This program is free software; you can redistribute it and/or modify
21 * it under the terms of the GNU General Public License as published by
22 * the Free Software Foundation; either version 2 of the License, or
23 * (at your option) any later version.
25 * This program is distributed in the hope that it will be useful,
26 * but WITHOUT ANY WARRANTY; without even the implied warranty of
27 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
28 * GNU General Public License for more details.
30 * You should have received a copy of the GNU General Public License along
31 * with this program; if not, write to the Free Software Foundation, Inc.,
32 * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.
35 #include <linux/kernel.h>
36 #include <linux/module.h>
37 #include <linux/pci.h>
38 #include <linux/init.h>
39 #include <linux/blkdev.h>
40 #include <linux/delay.h>
41 #include <linux/device.h>
42 #include <scsi/scsi_host.h>
43 #include <linux/libata.h>
45 #define DRV_NAME "pata_scc"
46 #define DRV_VERSION "0.2"
48 #define PCI_DEVICE_ID_TOSHIBA_SCC_ATA 0x01b4
51 #define SCC_CTRL_BAR 0
52 #define SCC_BMID_BAR 1
54 /* offset of CTRL registers */
55 #define SCC_CTL_PIOSHT 0x000
56 #define SCC_CTL_PIOCT 0x004
57 #define SCC_CTL_MDMACT 0x008
58 #define SCC_CTL_MCRCST 0x00C
59 #define SCC_CTL_SDMACT 0x010
60 #define SCC_CTL_SCRCST 0x014
61 #define SCC_CTL_UDENVT 0x018
62 #define SCC_CTL_TDVHSEL 0x020
63 #define SCC_CTL_MODEREG 0x024
64 #define SCC_CTL_ECMODE 0xF00
65 #define SCC_CTL_MAEA0 0xF50
66 #define SCC_CTL_MAEC0 0xF54
67 #define SCC_CTL_CCKCTRL 0xFF0
69 /* offset of BMID registers */
70 #define SCC_DMA_CMD 0x000
71 #define SCC_DMA_STATUS 0x004
72 #define SCC_DMA_TABLE_OFS 0x008
73 #define SCC_DMA_INTMASK 0x010
74 #define SCC_DMA_INTST 0x014
75 #define SCC_DMA_PTERADD 0x018
76 #define SCC_REG_CMD_ADDR 0x020
77 #define SCC_REG_DATA 0x000
78 #define SCC_REG_ERR 0x004
79 #define SCC_REG_FEATURE 0x004
80 #define SCC_REG_NSECT 0x008
81 #define SCC_REG_LBAL 0x00C
82 #define SCC_REG_LBAM 0x010
83 #define SCC_REG_LBAH 0x014
84 #define SCC_REG_DEVICE 0x018
85 #define SCC_REG_STATUS 0x01C
86 #define SCC_REG_CMD 0x01C
87 #define SCC_REG_ALTSTATUS 0x020
90 #define TDVHSEL_MASTER 0x00000001
91 #define TDVHSEL_SLAVE 0x00000004
93 #define MODE_JCUSFEN 0x00000080
95 #define ECMODE_VALUE 0x01
97 #define CCKCTRL_ATARESET 0x00040000
98 #define CCKCTRL_BUFCNT 0x00020000
99 #define CCKCTRL_CRST 0x00010000
100 #define CCKCTRL_OCLKEN 0x00000100
101 #define CCKCTRL_ATACLKOEN 0x00000002
102 #define CCKCTRL_LCLKEN 0x00000001
104 #define QCHCD_IOS_SS 0x00000001
106 #define QCHSD_STPDIAG 0x00020000
108 #define INTMASK_MSK 0xD1000012
109 #define INTSTS_SERROR 0x80000000
110 #define INTSTS_PRERR 0x40000000
111 #define INTSTS_RERR 0x10000000
112 #define INTSTS_ICERR 0x01000000
113 #define INTSTS_BMSINT 0x00000010
114 #define INTSTS_BMHE 0x00000008
115 #define INTSTS_IOIRQS 0x00000004
116 #define INTSTS_INTRQ 0x00000002
117 #define INTSTS_ACTEINT 0x00000001
120 /* PIO transfer mode table */
122 static const unsigned long JCHSTtbl[2][7] = {
123 {0x0E, 0x05, 0x02, 0x03, 0x02, 0x00, 0x00}, /* 100MHz */
124 {0x13, 0x07, 0x04, 0x04, 0x03, 0x00, 0x00} /* 133MHz */
128 static const unsigned long JCHHTtbl[2][7] = {
129 {0x0E, 0x02, 0x02, 0x02, 0x02, 0x00, 0x00}, /* 100MHz */
130 {0x13, 0x03, 0x03, 0x03, 0x03, 0x00, 0x00} /* 133MHz */
134 static const unsigned long JCHCTtbl[2][7] = {
135 {0x1D, 0x1D, 0x1C, 0x0B, 0x06, 0x00, 0x00}, /* 100MHz */
136 {0x27, 0x26, 0x26, 0x0E, 0x09, 0x00, 0x00} /* 133MHz */
139 /* DMA transfer mode table */
140 /* JCHDCTM/JCHDCTS */
141 static const unsigned long JCHDCTxtbl[2][7] = {
142 {0x0A, 0x06, 0x04, 0x03, 0x01, 0x00, 0x00}, /* 100MHz */
143 {0x0E, 0x09, 0x06, 0x04, 0x02, 0x01, 0x00} /* 133MHz */
146 /* JCSTWTM/JCSTWTS */
147 static const unsigned long JCSTWTxtbl[2][7] = {
148 {0x06, 0x04, 0x03, 0x02, 0x02, 0x02, 0x00}, /* 100MHz */
149 {0x09, 0x06, 0x04, 0x02, 0x02, 0x02, 0x02} /* 133MHz */
153 static const unsigned long JCTSStbl[2][7] = {
154 {0x05, 0x05, 0x05, 0x05, 0x05, 0x05, 0x00}, /* 100MHz */
155 {0x05, 0x05, 0x05, 0x05, 0x05, 0x05, 0x05} /* 133MHz */
159 static const unsigned long JCENVTtbl[2][7] = {
160 {0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x00}, /* 100MHz */
161 {0x02, 0x02, 0x02, 0x02, 0x02, 0x02, 0x02} /* 133MHz */
164 /* JCACTSELS/JCACTSELM */
165 static const unsigned long JCACTSELtbl[2][7] = {
166 {0x00, 0x00, 0x00, 0x00, 0x01, 0x01, 0x00}, /* 100MHz */
167 {0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x01} /* 133MHz */
170 static const struct pci_device_id scc_pci_tbl[] = {
171 {PCI_VENDOR_ID_TOSHIBA_2, PCI_DEVICE_ID_TOSHIBA_SCC_ATA,
172 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
173 { } /* terminate list */
177 * scc_set_piomode - Initialize host controller PATA PIO timings
178 * @ap: Port whose timings we are configuring
181 * Set PIO mode for device.
184 * None (inherited from caller).
187 static void scc_set_piomode (struct ata_port *ap, struct ata_device *adev)
189 unsigned int pio = adev->pio_mode - XFER_PIO_0;
190 void __iomem *ctrl_base = ap->host->iomap[SCC_CTRL_BAR];
191 void __iomem *cckctrl_port = ctrl_base + SCC_CTL_CCKCTRL;
192 void __iomem *piosht_port = ctrl_base + SCC_CTL_PIOSHT;
193 void __iomem *pioct_port = ctrl_base + SCC_CTL_PIOCT;
197 reg = in_be32(cckctrl_port);
198 if (reg & CCKCTRL_ATACLKOEN)
199 offset = 1; /* 133MHz */
201 offset = 0; /* 100MHz */
203 reg = JCHSTtbl[offset][pio] << 16 | JCHHTtbl[offset][pio];
204 out_be32(piosht_port, reg);
205 reg = JCHCTtbl[offset][pio];
206 out_be32(pioct_port, reg);
210 * scc_set_dmamode - Initialize host controller PATA DMA timings
211 * @ap: Port whose timings we are configuring
213 * @udma: udma mode, 0 - 6
215 * Set UDMA mode for device.
218 * None (inherited from caller).
221 static void scc_set_dmamode (struct ata_port *ap, struct ata_device *adev)
223 unsigned int udma = adev->dma_mode;
224 unsigned int is_slave = (adev->devno != 0);
226 void __iomem *ctrl_base = ap->host->iomap[SCC_CTRL_BAR];
227 void __iomem *cckctrl_port = ctrl_base + SCC_CTL_CCKCTRL;
228 void __iomem *mdmact_port = ctrl_base + SCC_CTL_MDMACT;
229 void __iomem *mcrcst_port = ctrl_base + SCC_CTL_MCRCST;
230 void __iomem *sdmact_port = ctrl_base + SCC_CTL_SDMACT;
231 void __iomem *scrcst_port = ctrl_base + SCC_CTL_SCRCST;
232 void __iomem *udenvt_port = ctrl_base + SCC_CTL_UDENVT;
233 void __iomem *tdvhsel_port = ctrl_base + SCC_CTL_TDVHSEL;
236 if (in_be32(cckctrl_port) & CCKCTRL_ATACLKOEN)
237 offset = 1; /* 133MHz */
239 offset = 0; /* 100MHz */
241 /* errata A308 workaround: limit ATAPI UDMA mode to UDMA4 */
242 if (adev->class == ATA_DEV_ATAPI && speed > XFER_UDMA_4) {
243 printk(KERN_INFO "%s: limit ATAPI UDMA to UDMA4\n", DRV_NAME);
247 if (speed >= XFER_UDMA_0)
248 idx = speed - XFER_UDMA_0;
253 out_be32(sdmact_port, JCHDCTxtbl[offset][idx]);
254 out_be32(scrcst_port, JCSTWTxtbl[offset][idx]);
255 out_be32(tdvhsel_port,
256 (in_be32(tdvhsel_port) & ~TDVHSEL_SLAVE) | (JCACTSELtbl[offset][idx] << 2));
258 out_be32(mdmact_port, JCHDCTxtbl[offset][idx]);
259 out_be32(mcrcst_port, JCSTWTxtbl[offset][idx]);
260 out_be32(tdvhsel_port,
261 (in_be32(tdvhsel_port) & ~TDVHSEL_MASTER) | JCACTSELtbl[offset][idx]);
263 out_be32(udenvt_port,
264 JCTSStbl[offset][idx] << 16 | JCENVTtbl[offset][idx]);
268 * scc_tf_load - send taskfile registers to host controller
269 * @ap: Port to which output is sent
270 * @tf: ATA taskfile register set
272 * Note: Original code is ata_tf_load().
275 static void scc_tf_load (struct ata_port *ap, const struct ata_taskfile *tf)
277 struct ata_ioports *ioaddr = &ap->ioaddr;
278 unsigned int is_addr = tf->flags & ATA_TFLAG_ISADDR;
280 if (tf->ctl != ap->last_ctl) {
281 out_be32(ioaddr->ctl_addr, tf->ctl);
282 ap->last_ctl = tf->ctl;
286 if (is_addr && (tf->flags & ATA_TFLAG_LBA48)) {
287 out_be32(ioaddr->feature_addr, tf->hob_feature);
288 out_be32(ioaddr->nsect_addr, tf->hob_nsect);
289 out_be32(ioaddr->lbal_addr, tf->hob_lbal);
290 out_be32(ioaddr->lbam_addr, tf->hob_lbam);
291 out_be32(ioaddr->lbah_addr, tf->hob_lbah);
292 VPRINTK("hob: feat 0x%X nsect 0x%X, lba 0x%X 0x%X 0x%X\n",
301 out_be32(ioaddr->feature_addr, tf->feature);
302 out_be32(ioaddr->nsect_addr, tf->nsect);
303 out_be32(ioaddr->lbal_addr, tf->lbal);
304 out_be32(ioaddr->lbam_addr, tf->lbam);
305 out_be32(ioaddr->lbah_addr, tf->lbah);
306 VPRINTK("feat 0x%X nsect 0x%X lba 0x%X 0x%X 0x%X\n",
314 if (tf->flags & ATA_TFLAG_DEVICE) {
315 out_be32(ioaddr->device_addr, tf->device);
316 VPRINTK("device 0x%X\n", tf->device);
323 * scc_check_status - Read device status reg & clear interrupt
324 * @ap: port where the device is
326 * Note: Original code is ata_check_status().
329 static u8 scc_check_status (struct ata_port *ap)
331 return in_be32(ap->ioaddr.status_addr);
335 * scc_tf_read - input device's ATA taskfile shadow registers
336 * @ap: Port from which input is read
337 * @tf: ATA taskfile register set for storing input
339 * Note: Original code is ata_tf_read().
342 static void scc_tf_read (struct ata_port *ap, struct ata_taskfile *tf)
344 struct ata_ioports *ioaddr = &ap->ioaddr;
346 tf->command = scc_check_status(ap);
347 tf->feature = in_be32(ioaddr->error_addr);
348 tf->nsect = in_be32(ioaddr->nsect_addr);
349 tf->lbal = in_be32(ioaddr->lbal_addr);
350 tf->lbam = in_be32(ioaddr->lbam_addr);
351 tf->lbah = in_be32(ioaddr->lbah_addr);
352 tf->device = in_be32(ioaddr->device_addr);
354 if (tf->flags & ATA_TFLAG_LBA48) {
355 out_be32(ioaddr->ctl_addr, tf->ctl | ATA_HOB);
356 tf->hob_feature = in_be32(ioaddr->error_addr);
357 tf->hob_nsect = in_be32(ioaddr->nsect_addr);
358 tf->hob_lbal = in_be32(ioaddr->lbal_addr);
359 tf->hob_lbam = in_be32(ioaddr->lbam_addr);
360 tf->hob_lbah = in_be32(ioaddr->lbah_addr);
365 * scc_exec_command - issue ATA command to host controller
366 * @ap: port to which command is being issued
367 * @tf: ATA taskfile register set
369 * Note: Original code is ata_exec_command().
372 static void scc_exec_command (struct ata_port *ap,
373 const struct ata_taskfile *tf)
375 DPRINTK("ata%u: cmd 0x%X\n", ap->print_id, tf->command);
377 out_be32(ap->ioaddr.command_addr, tf->command);
382 * scc_check_altstatus - Read device alternate status reg
383 * @ap: port where the device is
386 static u8 scc_check_altstatus (struct ata_port *ap)
388 return in_be32(ap->ioaddr.altstatus_addr);
392 * scc_std_dev_select - Select device 0/1 on ATA bus
393 * @ap: ATA channel to manipulate
394 * @device: ATA device (numbered from zero) to select
396 * Note: Original code is ata_std_dev_select().
399 static void scc_std_dev_select (struct ata_port *ap, unsigned int device)
404 tmp = ATA_DEVICE_OBS;
406 tmp = ATA_DEVICE_OBS | ATA_DEV1;
408 out_be32(ap->ioaddr.device_addr, tmp);
413 * scc_bmdma_setup - Set up PCI IDE BMDMA transaction
414 * @qc: Info associated with this ATA transaction.
416 * Note: Original code is ata_bmdma_setup().
419 static void scc_bmdma_setup (struct ata_queued_cmd *qc)
421 struct ata_port *ap = qc->ap;
422 unsigned int rw = (qc->tf.flags & ATA_TFLAG_WRITE);
424 void __iomem *mmio = ap->ioaddr.bmdma_addr;
426 /* load PRD table addr */
427 out_be32(mmio + SCC_DMA_TABLE_OFS, ap->prd_dma);
429 /* specify data direction, triple-check start bit is clear */
430 dmactl = in_be32(mmio + SCC_DMA_CMD);
431 dmactl &= ~(ATA_DMA_WR | ATA_DMA_START);
433 dmactl |= ATA_DMA_WR;
434 out_be32(mmio + SCC_DMA_CMD, dmactl);
436 /* issue r/w command */
437 ap->ops->exec_command(ap, &qc->tf);
441 * scc_bmdma_start - Start a PCI IDE BMDMA transaction
442 * @qc: Info associated with this ATA transaction.
444 * Note: Original code is ata_bmdma_start().
447 static void scc_bmdma_start (struct ata_queued_cmd *qc)
449 struct ata_port *ap = qc->ap;
451 void __iomem *mmio = ap->ioaddr.bmdma_addr;
453 /* start host DMA transaction */
454 dmactl = in_be32(mmio + SCC_DMA_CMD);
455 out_be32(mmio + SCC_DMA_CMD, dmactl | ATA_DMA_START);
459 * scc_devchk - PATA device presence detection
460 * @ap: ATA channel to examine
461 * @device: Device to examine (starting at zero)
463 * Note: Original code is ata_devchk().
466 static unsigned int scc_devchk (struct ata_port *ap,
469 struct ata_ioports *ioaddr = &ap->ioaddr;
472 ap->ops->dev_select(ap, device);
474 out_be32(ioaddr->nsect_addr, 0x55);
475 out_be32(ioaddr->lbal_addr, 0xaa);
477 out_be32(ioaddr->nsect_addr, 0xaa);
478 out_be32(ioaddr->lbal_addr, 0x55);
480 out_be32(ioaddr->nsect_addr, 0x55);
481 out_be32(ioaddr->lbal_addr, 0xaa);
483 nsect = in_be32(ioaddr->nsect_addr);
484 lbal = in_be32(ioaddr->lbal_addr);
486 if ((nsect == 0x55) && (lbal == 0xaa))
487 return 1; /* we found a device */
489 return 0; /* nothing found */
493 * scc_bus_post_reset - PATA device post reset
495 * Note: Original code is ata_bus_post_reset().
498 static int scc_bus_post_reset(struct ata_port *ap, unsigned int devmask,
499 unsigned long deadline)
501 struct ata_ioports *ioaddr = &ap->ioaddr;
502 unsigned int dev0 = devmask & (1 << 0);
503 unsigned int dev1 = devmask & (1 << 1);
506 /* if device 0 was found in ata_devchk, wait for its
510 rc = ata_wait_ready(ap, deadline);
511 if (rc && rc != -ENODEV)
515 /* if device 1 was found in ata_devchk, wait for
516 * register access, then wait for BSY to clear
521 ap->ops->dev_select(ap, 1);
522 nsect = in_be32(ioaddr->nsect_addr);
523 lbal = in_be32(ioaddr->lbal_addr);
524 if ((nsect == 1) && (lbal == 1))
526 if (time_after(jiffies, deadline))
528 msleep(50); /* give drive a breather */
531 rc = ata_wait_ready(ap, deadline);
532 if (rc && rc != -ENODEV)
536 /* is all this really necessary? */
537 ap->ops->dev_select(ap, 0);
539 ap->ops->dev_select(ap, 1);
541 ap->ops->dev_select(ap, 0);
547 * scc_bus_softreset - PATA device software reset
549 * Note: Original code is ata_bus_softreset().
552 static unsigned int scc_bus_softreset(struct ata_port *ap, unsigned int devmask,
553 unsigned long deadline)
555 struct ata_ioports *ioaddr = &ap->ioaddr;
557 DPRINTK("ata%u: bus reset via SRST\n", ap->print_id);
559 /* software reset. causes dev0 to be selected */
560 out_be32(ioaddr->ctl_addr, ap->ctl);
562 out_be32(ioaddr->ctl_addr, ap->ctl | ATA_SRST);
564 out_be32(ioaddr->ctl_addr, ap->ctl);
566 /* spec mandates ">= 2ms" before checking status.
567 * We wait 150ms, because that was the magic delay used for
568 * ATAPI devices in Hale Landis's ATADRVR, for the period of time
569 * between when the ATA command register is written, and then
570 * status is checked. Because waiting for "a while" before
571 * checking status is fine, post SRST, we perform this magic
572 * delay here as well.
574 * Old drivers/ide uses the 2mS rule and then waits for ready
578 /* Before we perform post reset processing we want to see if
579 * the bus shows 0xFF because the odd clown forgets the D7
582 if (scc_check_status(ap) == 0xFF)
585 scc_bus_post_reset(ap, devmask, deadline);
591 * scc_std_softreset - reset host port via ATA SRST
593 * @classes: resulting classes of attached devices
594 * @deadline: deadline jiffies for the operation
596 * Note: Original code is ata_std_softreset().
599 static int scc_std_softreset (struct ata_port *ap, unsigned int *classes,
600 unsigned long deadline)
602 unsigned int slave_possible = ap->flags & ATA_FLAG_SLAVE_POSS;
603 unsigned int devmask = 0, err_mask;
608 if (ata_port_offline(ap)) {
609 classes[0] = ATA_DEV_NONE;
613 /* determine if device 0/1 are present */
614 if (scc_devchk(ap, 0))
616 if (slave_possible && scc_devchk(ap, 1))
619 /* select device 0 again */
620 ap->ops->dev_select(ap, 0);
622 /* issue bus reset */
623 DPRINTK("about to softreset, devmask=%x\n", devmask);
624 err_mask = scc_bus_softreset(ap, devmask, deadline);
626 ata_port_printk(ap, KERN_ERR, "SRST failed (err_mask=0x%x)\n",
631 /* determine by signature whether we have ATA or ATAPI devices */
632 classes[0] = ata_dev_try_classify(ap, 0, &err);
633 if (slave_possible && err != 0x81)
634 classes[1] = ata_dev_try_classify(ap, 1, &err);
637 DPRINTK("EXIT, classes[0]=%u [1]=%u\n", classes[0], classes[1]);
642 * scc_bmdma_stop - Stop PCI IDE BMDMA transfer
643 * @qc: Command we are ending DMA for
646 static void scc_bmdma_stop (struct ata_queued_cmd *qc)
648 struct ata_port *ap = qc->ap;
649 void __iomem *ctrl_base = ap->host->iomap[SCC_CTRL_BAR];
650 void __iomem *bmid_base = ap->host->iomap[SCC_BMID_BAR];
654 reg = in_be32(bmid_base + SCC_DMA_INTST);
656 if (reg & INTSTS_SERROR) {
657 printk(KERN_WARNING "%s: SERROR\n", DRV_NAME);
658 out_be32(bmid_base + SCC_DMA_INTST, INTSTS_SERROR|INTSTS_BMSINT);
659 out_be32(bmid_base + SCC_DMA_CMD,
660 in_be32(bmid_base + SCC_DMA_CMD) & ~ATA_DMA_START);
664 if (reg & INTSTS_PRERR) {
666 maea0 = in_be32(ctrl_base + SCC_CTL_MAEA0);
667 maec0 = in_be32(ctrl_base + SCC_CTL_MAEC0);
668 printk(KERN_WARNING "%s: PRERR [addr:%x cmd:%x]\n", DRV_NAME, maea0, maec0);
669 out_be32(bmid_base + SCC_DMA_INTST, INTSTS_PRERR|INTSTS_BMSINT);
670 out_be32(bmid_base + SCC_DMA_CMD,
671 in_be32(bmid_base + SCC_DMA_CMD) & ~ATA_DMA_START);
675 if (reg & INTSTS_RERR) {
676 printk(KERN_WARNING "%s: Response Error\n", DRV_NAME);
677 out_be32(bmid_base + SCC_DMA_INTST, INTSTS_RERR|INTSTS_BMSINT);
678 out_be32(bmid_base + SCC_DMA_CMD,
679 in_be32(bmid_base + SCC_DMA_CMD) & ~ATA_DMA_START);
683 if (reg & INTSTS_ICERR) {
684 out_be32(bmid_base + SCC_DMA_CMD,
685 in_be32(bmid_base + SCC_DMA_CMD) & ~ATA_DMA_START);
686 printk(KERN_WARNING "%s: Illegal Configuration\n", DRV_NAME);
687 out_be32(bmid_base + SCC_DMA_INTST, INTSTS_ICERR|INTSTS_BMSINT);
691 if (reg & INTSTS_BMSINT) {
692 unsigned int classes;
693 unsigned long deadline = jiffies + ATA_TMOUT_BOOT;
694 printk(KERN_WARNING "%s: Internal Bus Error\n", DRV_NAME);
695 out_be32(bmid_base + SCC_DMA_INTST, INTSTS_BMSINT);
697 scc_std_softreset(ap, &classes, deadline);
701 if (reg & INTSTS_BMHE) {
702 out_be32(bmid_base + SCC_DMA_INTST, INTSTS_BMHE);
706 if (reg & INTSTS_ACTEINT) {
707 out_be32(bmid_base + SCC_DMA_INTST, INTSTS_ACTEINT);
711 if (reg & INTSTS_IOIRQS) {
712 out_be32(bmid_base + SCC_DMA_INTST, INTSTS_IOIRQS);
718 /* clear start/stop bit */
719 out_be32(bmid_base + SCC_DMA_CMD,
720 in_be32(bmid_base + SCC_DMA_CMD) & ~ATA_DMA_START);
722 /* one-PIO-cycle guaranteed wait, per spec, for HDMA1:0 transition */
723 ata_altstatus(ap); /* dummy read */
727 * scc_bmdma_status - Read PCI IDE BMDMA status
728 * @ap: Port associated with this ATA transaction.
731 static u8 scc_bmdma_status (struct ata_port *ap)
733 void __iomem *mmio = ap->ioaddr.bmdma_addr;
734 u8 host_stat = in_be32(mmio + SCC_DMA_STATUS);
735 u32 int_status = in_be32(mmio + SCC_DMA_INTST);
736 struct ata_queued_cmd *qc = ata_qc_from_tag(ap, ap->active_tag);
737 static int retry = 0;
739 /* return if IOS_SS is cleared */
740 if (!(in_be32(mmio + SCC_DMA_CMD) & ATA_DMA_START))
743 /* errata A252,A308 workaround: Step4 */
744 if (ata_altstatus(ap) & ATA_ERR && int_status & INTSTS_INTRQ)
745 return (host_stat | ATA_DMA_INTR);
747 /* errata A308 workaround Step5 */
748 if (int_status & INTSTS_IOIRQS) {
749 host_stat |= ATA_DMA_INTR;
751 /* We don't check ATAPI DMA because it is limited to UDMA4 */
752 if ((qc->tf.protocol == ATA_PROT_DMA &&
753 qc->dev->xfer_mode > XFER_UDMA_4)) {
754 if (!(int_status & INTSTS_ACTEINT)) {
755 printk(KERN_WARNING "ata%u: data lost occurred. (ACTEINT==0, retry:%d)\n",
756 ap->print_id, retry);
757 host_stat |= ATA_DMA_ERR;
769 * scc_data_xfer - Transfer data by PIO
770 * @adev: device for this I/O
772 * @buflen: buffer length
773 * @write_data: read/write
775 * Note: Original code is ata_data_xfer().
778 static void scc_data_xfer (struct ata_device *adev, unsigned char *buf,
779 unsigned int buflen, int write_data)
781 struct ata_port *ap = adev->ap;
782 unsigned int words = buflen >> 1;
784 u16 *buf16 = (u16 *) buf;
785 void __iomem *mmio = ap->ioaddr.data_addr;
787 /* Transfer multiple of 2 bytes */
789 for (i = 0; i < words; i++)
790 out_be32(mmio, cpu_to_le16(buf16[i]));
792 for (i = 0; i < words; i++)
793 buf16[i] = le16_to_cpu(in_be32(mmio));
796 /* Transfer trailing 1 byte, if any. */
797 if (unlikely(buflen & 0x01)) {
798 u16 align_buf[1] = { 0 };
799 unsigned char *trailing_buf = buf + buflen - 1;
802 memcpy(align_buf, trailing_buf, 1);
803 out_be32(mmio, cpu_to_le16(align_buf[0]));
805 align_buf[0] = le16_to_cpu(in_be32(mmio));
806 memcpy(trailing_buf, align_buf, 1);
812 * scc_irq_on - Enable interrupts on a port.
813 * @ap: Port on which interrupts are enabled.
815 * Note: Original code is ata_irq_on().
818 static u8 scc_irq_on (struct ata_port *ap)
820 struct ata_ioports *ioaddr = &ap->ioaddr;
823 ap->ctl &= ~ATA_NIEN;
824 ap->last_ctl = ap->ctl;
826 out_be32(ioaddr->ctl_addr, ap->ctl);
827 tmp = ata_wait_idle(ap);
829 ap->ops->irq_clear(ap);
835 * scc_irq_ack - Acknowledge a device interrupt.
836 * @ap: Port on which interrupts are enabled.
838 * Note: Original code is ata_irq_ack().
841 static u8 scc_irq_ack (struct ata_port *ap, unsigned int chk_drq)
843 unsigned int bits = chk_drq ? ATA_BUSY | ATA_DRQ : ATA_BUSY;
844 u8 host_stat, post_stat, status;
846 status = ata_busy_wait(ap, bits, 1000);
849 printk(KERN_ERR "abnormal status 0x%X\n", status);
851 /* get controller status; clear intr, err bits */
852 host_stat = in_be32(ap->ioaddr.bmdma_addr + SCC_DMA_STATUS);
853 out_be32(ap->ioaddr.bmdma_addr + SCC_DMA_STATUS,
854 host_stat | ATA_DMA_INTR | ATA_DMA_ERR);
856 post_stat = in_be32(ap->ioaddr.bmdma_addr + SCC_DMA_STATUS);
858 if (ata_msg_intr(ap))
859 printk(KERN_INFO "%s: irq ack: host_stat 0x%X, new host_stat 0x%X, drv_stat 0x%X\n",
861 host_stat, post_stat, status);
867 * scc_bmdma_freeze - Freeze BMDMA controller port
868 * @ap: port to freeze
870 * Note: Original code is ata_bmdma_freeze().
873 static void scc_bmdma_freeze (struct ata_port *ap)
875 struct ata_ioports *ioaddr = &ap->ioaddr;
878 ap->last_ctl = ap->ctl;
880 out_be32(ioaddr->ctl_addr, ap->ctl);
882 /* Under certain circumstances, some controllers raise IRQ on
883 * ATA_NIEN manipulation. Also, many controllers fail to mask
884 * previously pending IRQ on ATA_NIEN assertion. Clear it.
888 ap->ops->irq_clear(ap);
892 * scc_pata_prereset - prepare for reset
893 * @ap: ATA port to be reset
894 * @deadline: deadline jiffies for the operation
897 static int scc_pata_prereset(struct ata_port *ap, unsigned long deadline)
899 ap->cbl = ATA_CBL_PATA80;
900 return ata_std_prereset(ap, deadline);
904 * scc_std_postreset - standard postreset callback
905 * @ap: the target ata_port
906 * @classes: classes of attached devices
908 * Note: Original code is ata_std_postreset().
911 static void scc_std_postreset (struct ata_port *ap, unsigned int *classes)
915 /* is double-select really necessary? */
916 if (classes[0] != ATA_DEV_NONE)
917 ap->ops->dev_select(ap, 1);
918 if (classes[1] != ATA_DEV_NONE)
919 ap->ops->dev_select(ap, 0);
921 /* bail out if no device is present */
922 if (classes[0] == ATA_DEV_NONE && classes[1] == ATA_DEV_NONE) {
923 DPRINTK("EXIT, no device\n");
927 /* set up device control */
928 if (ap->ioaddr.ctl_addr)
929 out_be32(ap->ioaddr.ctl_addr, ap->ctl);
935 * scc_error_handler - Stock error handler for BMDMA controller
936 * @ap: port to handle error for
939 static void scc_error_handler (struct ata_port *ap)
941 ata_bmdma_drive_eh(ap, scc_pata_prereset, scc_std_softreset, NULL,
946 * scc_bmdma_irq_clear - Clear PCI IDE BMDMA interrupt.
947 * @ap: Port associated with this ATA transaction.
949 * Note: Original code is ata_bmdma_irq_clear().
952 static void scc_bmdma_irq_clear (struct ata_port *ap)
954 void __iomem *mmio = ap->ioaddr.bmdma_addr;
959 out_be32(mmio + SCC_DMA_STATUS, in_be32(mmio + SCC_DMA_STATUS));
963 * scc_port_start - Set port up for dma.
964 * @ap: Port to initialize
966 * Allocate space for PRD table using ata_port_start().
967 * Set PRD table address for PTERADD. (PRD Transfer End Read)
970 static int scc_port_start (struct ata_port *ap)
972 void __iomem *mmio = ap->ioaddr.bmdma_addr;
975 rc = ata_port_start(ap);
979 out_be32(mmio + SCC_DMA_PTERADD, ap->prd_dma);
984 * scc_port_stop - Undo scc_port_start()
985 * @ap: Port to shut down
990 static void scc_port_stop (struct ata_port *ap)
992 void __iomem *mmio = ap->ioaddr.bmdma_addr;
994 out_be32(mmio + SCC_DMA_PTERADD, 0);
997 static struct scsi_host_template scc_sht = {
998 .module = THIS_MODULE,
1000 .ioctl = ata_scsi_ioctl,
1001 .queuecommand = ata_scsi_queuecmd,
1002 .can_queue = ATA_DEF_QUEUE,
1003 .this_id = ATA_SHT_THIS_ID,
1004 .sg_tablesize = LIBATA_MAX_PRD,
1005 .cmd_per_lun = ATA_SHT_CMD_PER_LUN,
1006 .emulated = ATA_SHT_EMULATED,
1007 .use_clustering = ATA_SHT_USE_CLUSTERING,
1008 .proc_name = DRV_NAME,
1009 .dma_boundary = ATA_DMA_BOUNDARY,
1010 .slave_configure = ata_scsi_slave_config,
1011 .slave_destroy = ata_scsi_slave_destroy,
1012 .bios_param = ata_std_bios_param,
1015 static const struct ata_port_operations scc_pata_ops = {
1016 .port_disable = ata_port_disable,
1017 .set_piomode = scc_set_piomode,
1018 .set_dmamode = scc_set_dmamode,
1019 .mode_filter = ata_pci_default_filter,
1021 .tf_load = scc_tf_load,
1022 .tf_read = scc_tf_read,
1023 .exec_command = scc_exec_command,
1024 .check_status = scc_check_status,
1025 .check_altstatus = scc_check_altstatus,
1026 .dev_select = scc_std_dev_select,
1028 .bmdma_setup = scc_bmdma_setup,
1029 .bmdma_start = scc_bmdma_start,
1030 .bmdma_stop = scc_bmdma_stop,
1031 .bmdma_status = scc_bmdma_status,
1032 .data_xfer = scc_data_xfer,
1034 .qc_prep = ata_qc_prep,
1035 .qc_issue = ata_qc_issue_prot,
1037 .freeze = scc_bmdma_freeze,
1038 .error_handler = scc_error_handler,
1039 .post_internal_cmd = scc_bmdma_stop,
1041 .irq_clear = scc_bmdma_irq_clear,
1042 .irq_on = scc_irq_on,
1043 .irq_ack = scc_irq_ack,
1045 .port_start = scc_port_start,
1046 .port_stop = scc_port_stop,
1049 static struct ata_port_info scc_port_info[] = {
1051 .flags = ATA_FLAG_SLAVE_POSS | ATA_FLAG_MMIO | ATA_FLAG_NO_LEGACY,
1052 .pio_mask = 0x1f, /* pio0-4 */
1054 .udma_mask = ATA_UDMA6,
1055 .port_ops = &scc_pata_ops,
1060 * scc_reset_controller - initialize SCC PATA controller.
1063 static int scc_reset_controller(struct ata_host *host)
1065 void __iomem *ctrl_base = host->iomap[SCC_CTRL_BAR];
1066 void __iomem *bmid_base = host->iomap[SCC_BMID_BAR];
1067 void __iomem *cckctrl_port = ctrl_base + SCC_CTL_CCKCTRL;
1068 void __iomem *mode_port = ctrl_base + SCC_CTL_MODEREG;
1069 void __iomem *ecmode_port = ctrl_base + SCC_CTL_ECMODE;
1070 void __iomem *intmask_port = bmid_base + SCC_DMA_INTMASK;
1071 void __iomem *dmastatus_port = bmid_base + SCC_DMA_STATUS;
1074 out_be32(cckctrl_port, reg);
1075 reg |= CCKCTRL_ATACLKOEN;
1076 out_be32(cckctrl_port, reg);
1077 reg |= CCKCTRL_LCLKEN | CCKCTRL_OCLKEN;
1078 out_be32(cckctrl_port, reg);
1079 reg |= CCKCTRL_CRST;
1080 out_be32(cckctrl_port, reg);
1083 reg = in_be32(cckctrl_port);
1084 if (reg & CCKCTRL_CRST)
1089 reg |= CCKCTRL_ATARESET;
1090 out_be32(cckctrl_port, reg);
1091 out_be32(ecmode_port, ECMODE_VALUE);
1092 out_be32(mode_port, MODE_JCUSFEN);
1093 out_be32(intmask_port, INTMASK_MSK);
1095 if (in_be32(dmastatus_port) & QCHSD_STPDIAG) {
1096 printk(KERN_WARNING "%s: failed to detect 80c cable. (PDIAG# is high)\n", DRV_NAME);
1104 * scc_setup_ports - initialize ioaddr with SCC PATA port offsets.
1105 * @ioaddr: IO address structure to be initialized
1106 * @base: base address of BMID region
1109 static void scc_setup_ports (struct ata_ioports *ioaddr, void __iomem *base)
1111 ioaddr->cmd_addr = base + SCC_REG_CMD_ADDR;
1112 ioaddr->altstatus_addr = ioaddr->cmd_addr + SCC_REG_ALTSTATUS;
1113 ioaddr->ctl_addr = ioaddr->cmd_addr + SCC_REG_ALTSTATUS;
1114 ioaddr->bmdma_addr = base;
1115 ioaddr->data_addr = ioaddr->cmd_addr + SCC_REG_DATA;
1116 ioaddr->error_addr = ioaddr->cmd_addr + SCC_REG_ERR;
1117 ioaddr->feature_addr = ioaddr->cmd_addr + SCC_REG_FEATURE;
1118 ioaddr->nsect_addr = ioaddr->cmd_addr + SCC_REG_NSECT;
1119 ioaddr->lbal_addr = ioaddr->cmd_addr + SCC_REG_LBAL;
1120 ioaddr->lbam_addr = ioaddr->cmd_addr + SCC_REG_LBAM;
1121 ioaddr->lbah_addr = ioaddr->cmd_addr + SCC_REG_LBAH;
1122 ioaddr->device_addr = ioaddr->cmd_addr + SCC_REG_DEVICE;
1123 ioaddr->status_addr = ioaddr->cmd_addr + SCC_REG_STATUS;
1124 ioaddr->command_addr = ioaddr->cmd_addr + SCC_REG_CMD;
1127 static int scc_host_init(struct ata_host *host)
1129 struct pci_dev *pdev = to_pci_dev(host->dev);
1132 rc = scc_reset_controller(host);
1136 rc = pci_set_dma_mask(pdev, ATA_DMA_MASK);
1139 rc = pci_set_consistent_dma_mask(pdev, ATA_DMA_MASK);
1143 scc_setup_ports(&host->ports[0]->ioaddr, host->iomap[SCC_BMID_BAR]);
1145 pci_set_master(pdev);
1151 * scc_init_one - Register SCC PATA device with kernel services
1152 * @pdev: PCI device to register
1153 * @ent: Entry in scc_pci_tbl matching with @pdev
1156 * Inherited from PCI layer (may sleep).
1159 * Zero on success, or -ERRNO value.
1162 static int scc_init_one (struct pci_dev *pdev, const struct pci_device_id *ent)
1164 static int printed_version;
1165 unsigned int board_idx = (unsigned int) ent->driver_data;
1166 const struct ata_port_info *ppi[] = { &scc_port_info[board_idx], NULL };
1167 struct ata_host *host;
1170 if (!printed_version++)
1171 dev_printk(KERN_DEBUG, &pdev->dev,
1172 "version " DRV_VERSION "\n");
1174 host = ata_host_alloc_pinfo(&pdev->dev, ppi, 1);
1178 rc = pcim_enable_device(pdev);
1182 rc = pcim_iomap_regions(pdev, (1 << SCC_CTRL_BAR) | (1 << SCC_BMID_BAR), DRV_NAME);
1184 pcim_pin_device(pdev);
1187 host->iomap = pcim_iomap_table(pdev);
1189 rc = scc_host_init(host);
1193 return ata_host_activate(host, pdev->irq, ata_interrupt, IRQF_SHARED,
1197 static struct pci_driver scc_pci_driver = {
1199 .id_table = scc_pci_tbl,
1200 .probe = scc_init_one,
1201 .remove = ata_pci_remove_one,
1203 .suspend = ata_pci_device_suspend,
1204 .resume = ata_pci_device_resume,
1208 static int __init scc_init (void)
1212 DPRINTK("pci_register_driver\n");
1213 rc = pci_register_driver(&scc_pci_driver);
1221 static void __exit scc_exit (void)
1223 pci_unregister_driver(&scc_pci_driver);
1226 module_init(scc_init);
1227 module_exit(scc_exit);
1229 MODULE_AUTHOR("Toshiba corp");
1230 MODULE_DESCRIPTION("SCSI low-level driver for Toshiba SCC PATA controller");
1231 MODULE_LICENSE("GPL");
1232 MODULE_DEVICE_TABLE(pci, scc_pci_tbl);
1233 MODULE_VERSION(DRV_VERSION);