2 * pata_pdc202xx_old.c - Promise PDC202xx PATA for new ATA layer
4 * Alan Cox <alan@redhat.com>
5 * (C) 2007 Bartlomiej Zolnierkiewicz
7 * Based in part on linux/drivers/ide/pci/pdc202xx_old.c
9 * First cut with LBA48/ATAPI
12 * Channel interlock/reset on both required ?
15 #include <linux/kernel.h>
16 #include <linux/module.h>
17 #include <linux/pci.h>
18 #include <linux/init.h>
19 #include <linux/blkdev.h>
20 #include <linux/delay.h>
21 #include <scsi/scsi_host.h>
22 #include <linux/libata.h>
24 #define DRV_NAME "pata_pdc202xx_old"
25 #define DRV_VERSION "0.4.3"
27 static int pdc2026x_cable_detect(struct ata_port *ap)
29 struct pci_dev *pdev = to_pci_dev(ap->host->dev);
32 pci_read_config_word(pdev, 0x50, &cis);
33 if (cis & (1 << (10 + ap->port_no)))
34 return ATA_CBL_PATA40;
35 return ATA_CBL_PATA80;
39 * pdc202xx_configure_piomode - set chip PIO timing
44 * Called to do the PIO mode setup. Our timing registers are shared
45 * so a configure_dmamode call will undo any work we do here and vice
49 static void pdc202xx_configure_piomode(struct ata_port *ap, struct ata_device *adev, int pio)
51 struct pci_dev *pdev = to_pci_dev(ap->host->dev);
52 int port = 0x60 + 8 * ap->port_no + 4 * adev->devno;
53 static u16 pio_timing[5] = {
54 0x0913, 0x050C , 0x0308, 0x0206, 0x0104
58 pci_read_config_byte(pdev, port, &r_ap);
59 pci_read_config_byte(pdev, port + 1, &r_bp);
60 r_ap &= ~0x3F; /* Preserve ERRDY_EN, SYNC_IN */
62 r_ap |= (pio_timing[pio] >> 8);
63 r_bp |= (pio_timing[pio] & 0xFF);
65 if (ata_pio_need_iordy(adev))
66 r_ap |= 0x20; /* IORDY enable */
67 if (adev->class == ATA_DEV_ATA)
68 r_ap |= 0x10; /* FIFO enable */
69 pci_write_config_byte(pdev, port, r_ap);
70 pci_write_config_byte(pdev, port + 1, r_bp);
74 * pdc202xx_set_piomode - set initial PIO mode data
78 * Called to do the PIO mode setup. Our timing registers are shared
79 * but we want to set the PIO timing by default.
82 static void pdc202xx_set_piomode(struct ata_port *ap, struct ata_device *adev)
84 pdc202xx_configure_piomode(ap, adev, adev->pio_mode - XFER_PIO_0);
88 * pdc202xx_configure_dmamode - set DMA mode in chip
92 * Load DMA cycle times into the chip ready for a DMA transfer
96 static void pdc202xx_set_dmamode(struct ata_port *ap, struct ata_device *adev)
98 struct pci_dev *pdev = to_pci_dev(ap->host->dev);
99 int port = 0x60 + 8 * ap->port_no + 4 * adev->devno;
100 static u8 udma_timing[6][2] = {
101 { 0x60, 0x03 }, /* 33 Mhz Clock */
104 { 0x40, 0x02 }, /* 66 Mhz Clock */
108 static u8 mdma_timing[3][2] = {
115 pci_read_config_byte(pdev, port + 1, &r_bp);
116 pci_read_config_byte(pdev, port + 2, &r_cp);
121 if (adev->dma_mode >= XFER_UDMA_0) {
122 int speed = adev->dma_mode - XFER_UDMA_0;
123 r_bp |= udma_timing[speed][0];
124 r_cp |= udma_timing[speed][1];
127 int speed = adev->dma_mode - XFER_MW_DMA_0;
128 r_bp |= mdma_timing[speed][0];
129 r_cp |= mdma_timing[speed][1];
131 pci_write_config_byte(pdev, port + 1, r_bp);
132 pci_write_config_byte(pdev, port + 2, r_cp);
137 * pdc2026x_bmdma_start - DMA engine begin
140 * In UDMA3 or higher we have to clock switch for the duration of the
141 * DMA transfer sequence.
143 * Note: The host lock held by the libata layer protects
144 * us from two channels both trying to set DMA bits at once
147 static void pdc2026x_bmdma_start(struct ata_queued_cmd *qc)
149 struct ata_port *ap = qc->ap;
150 struct ata_device *adev = qc->dev;
151 struct ata_taskfile *tf = &qc->tf;
152 int sel66 = ap->port_no ? 0x08: 0x02;
154 void __iomem *master = ap->host->ports[0]->ioaddr.bmdma_addr;
155 void __iomem *clock = master + 0x11;
156 void __iomem *atapi_reg = master + 0x20 + (4 * ap->port_no);
160 /* Check we keep host level locking here */
161 if (adev->dma_mode >= XFER_UDMA_2)
162 iowrite8(ioread8(clock) | sel66, clock);
164 iowrite8(ioread8(clock) & ~sel66, clock);
166 /* The DMA clocks may have been trashed by a reset. FIXME: make conditional
167 and move to qc_issue ? */
168 pdc202xx_set_dmamode(ap, qc->dev);
170 /* Cases the state machine will not complete correctly without help */
171 if ((tf->flags & ATA_TFLAG_LBA48) || tf->protocol == ATAPI_PROT_DMA) {
172 len = qc->nbytes / 2;
174 if (tf->flags & ATA_TFLAG_WRITE)
179 iowrite32(len, atapi_reg);
187 * pdc2026x_bmdma_end - DMA engine stop
190 * After a DMA completes we need to put the clock back to 33MHz for
193 * Note: The host lock held by the libata layer protects
194 * us from two channels both trying to set DMA bits at once
197 static void pdc2026x_bmdma_stop(struct ata_queued_cmd *qc)
199 struct ata_port *ap = qc->ap;
200 struct ata_device *adev = qc->dev;
201 struct ata_taskfile *tf = &qc->tf;
203 int sel66 = ap->port_no ? 0x08: 0x02;
204 /* The clock bits are in the same register for both channels */
205 void __iomem *master = ap->host->ports[0]->ioaddr.bmdma_addr;
206 void __iomem *clock = master + 0x11;
207 void __iomem *atapi_reg = master + 0x20 + (4 * ap->port_no);
209 /* Cases the state machine will not complete correctly */
210 if (tf->protocol == ATAPI_PROT_DMA || (tf->flags & ATA_TFLAG_LBA48)) {
211 iowrite32(0, atapi_reg);
212 iowrite8(ioread8(clock) & ~sel66, clock);
214 /* Flip back to 33Mhz for PIO */
215 if (adev->dma_mode >= XFER_UDMA_2)
216 iowrite8(ioread8(clock) & ~sel66, clock);
218 pdc202xx_set_piomode(ap, adev);
222 * pdc2026x_dev_config - device setup hook
223 * @adev: newly found device
225 * Perform chip specific early setup. We need to lock the transfer
226 * sizes to 8bit to avoid making the state engine on the 2026x cards
230 static void pdc2026x_dev_config(struct ata_device *adev)
232 adev->max_sectors = 256;
235 static int pdc2026x_port_start(struct ata_port *ap)
237 void __iomem *bmdma = ap->ioaddr.bmdma_addr;
239 /* Enable burst mode */
240 u8 burst = ioread8(bmdma + 0x1f);
241 iowrite8(burst | 0x01, bmdma + 0x1f);
243 return ata_sff_port_start(ap);
247 * pdc2026x_check_atapi_dma - Check whether ATAPI DMA can be supported for this command
248 * @qc: Metadata associated with taskfile to check
250 * Just say no - not supported on older Promise.
253 * None (inherited from caller).
255 * RETURNS: 0 when ATAPI DMA can be used
259 static int pdc2026x_check_atapi_dma(struct ata_queued_cmd *qc)
264 static struct scsi_host_template pdc202xx_sht = {
265 ATA_BMDMA_SHT(DRV_NAME),
268 static struct ata_port_operations pdc2024x_port_ops = {
269 .set_piomode = pdc202xx_set_piomode,
270 .set_dmamode = pdc202xx_set_dmamode,
271 .mode_filter = ata_pci_default_filter,
272 .tf_load = ata_tf_load,
273 .tf_read = ata_tf_read,
274 .check_status = ata_check_status,
275 .exec_command = ata_exec_command,
276 .dev_select = ata_std_dev_select,
278 .freeze = ata_bmdma_freeze,
279 .thaw = ata_bmdma_thaw,
280 .error_handler = ata_bmdma_error_handler,
281 .post_internal_cmd = ata_bmdma_post_internal_cmd,
282 .cable_detect = ata_cable_40wire,
284 .bmdma_setup = ata_bmdma_setup,
285 .bmdma_start = ata_bmdma_start,
286 .bmdma_stop = ata_bmdma_stop,
287 .bmdma_status = ata_bmdma_status,
289 .qc_prep = ata_qc_prep,
290 .qc_issue = ata_qc_issue_prot,
291 .data_xfer = ata_data_xfer,
293 .irq_handler = ata_interrupt,
294 .irq_clear = ata_bmdma_irq_clear,
295 .irq_on = ata_irq_on,
297 .port_start = ata_sff_port_start,
300 static struct ata_port_operations pdc2026x_port_ops = {
301 .set_piomode = pdc202xx_set_piomode,
302 .set_dmamode = pdc202xx_set_dmamode,
303 .mode_filter = ata_pci_default_filter,
304 .tf_load = ata_tf_load,
305 .tf_read = ata_tf_read,
306 .check_status = ata_check_status,
307 .exec_command = ata_exec_command,
308 .dev_select = ata_std_dev_select,
309 .dev_config = pdc2026x_dev_config,
311 .freeze = ata_bmdma_freeze,
312 .thaw = ata_bmdma_thaw,
313 .error_handler = ata_bmdma_error_handler,
314 .post_internal_cmd = ata_bmdma_post_internal_cmd,
315 .cable_detect = pdc2026x_cable_detect,
317 .check_atapi_dma= pdc2026x_check_atapi_dma,
318 .bmdma_setup = ata_bmdma_setup,
319 .bmdma_start = pdc2026x_bmdma_start,
320 .bmdma_stop = pdc2026x_bmdma_stop,
321 .bmdma_status = ata_bmdma_status,
323 .qc_prep = ata_qc_prep,
324 .qc_issue = ata_qc_issue_prot,
325 .data_xfer = ata_data_xfer,
327 .irq_handler = ata_interrupt,
328 .irq_clear = ata_bmdma_irq_clear,
329 .irq_on = ata_irq_on,
331 .port_start = pdc2026x_port_start,
334 static int pdc202xx_init_one(struct pci_dev *dev, const struct pci_device_id *id)
336 static const struct ata_port_info info[3] = {
338 .sht = &pdc202xx_sht,
339 .flags = ATA_FLAG_SLAVE_POSS,
342 .udma_mask = ATA_UDMA2,
343 .port_ops = &pdc2024x_port_ops
346 .sht = &pdc202xx_sht,
347 .flags = ATA_FLAG_SLAVE_POSS,
350 .udma_mask = ATA_UDMA4,
351 .port_ops = &pdc2026x_port_ops
354 .sht = &pdc202xx_sht,
355 .flags = ATA_FLAG_SLAVE_POSS,
358 .udma_mask = ATA_UDMA5,
359 .port_ops = &pdc2026x_port_ops
363 const struct ata_port_info *ppi[] = { &info[id->driver_data], NULL };
365 if (dev->device == PCI_DEVICE_ID_PROMISE_20265) {
366 struct pci_dev *bridge = dev->bus->self;
367 /* Don't grab anything behind a Promise I2O RAID */
368 if (bridge && bridge->vendor == PCI_VENDOR_ID_INTEL) {
369 if (bridge->device == PCI_DEVICE_ID_INTEL_I960)
371 if (bridge->device == PCI_DEVICE_ID_INTEL_I960RM)
375 return ata_pci_init_one(dev, ppi);
378 static const struct pci_device_id pdc202xx[] = {
379 { PCI_VDEVICE(PROMISE, PCI_DEVICE_ID_PROMISE_20246), 0 },
380 { PCI_VDEVICE(PROMISE, PCI_DEVICE_ID_PROMISE_20262), 1 },
381 { PCI_VDEVICE(PROMISE, PCI_DEVICE_ID_PROMISE_20263), 1 },
382 { PCI_VDEVICE(PROMISE, PCI_DEVICE_ID_PROMISE_20265), 2 },
383 { PCI_VDEVICE(PROMISE, PCI_DEVICE_ID_PROMISE_20267), 2 },
388 static struct pci_driver pdc202xx_pci_driver = {
390 .id_table = pdc202xx,
391 .probe = pdc202xx_init_one,
392 .remove = ata_pci_remove_one,
394 .suspend = ata_pci_device_suspend,
395 .resume = ata_pci_device_resume,
399 static int __init pdc202xx_init(void)
401 return pci_register_driver(&pdc202xx_pci_driver);
404 static void __exit pdc202xx_exit(void)
406 pci_unregister_driver(&pdc202xx_pci_driver);
409 MODULE_AUTHOR("Alan Cox");
410 MODULE_DESCRIPTION("low-level driver for Promise 2024x and 20262-20267");
411 MODULE_LICENSE("GPL");
412 MODULE_DEVICE_TABLE(pci, pdc202xx);
413 MODULE_VERSION(DRV_VERSION);
415 module_init(pdc202xx_init);
416 module_exit(pdc202xx_exit);