2 * pata_amd.c - AMD PATA for new ATA layer
3 * (C) 2005-2006 Red Hat Inc
4 * Alan Cox <alan@redhat.com>
6 * Based on pata-sil680. Errata information is taken from data sheets
7 * and the amd74xx.c driver by Vojtech Pavlik. Nvidia SATA devices are
8 * claimed by sata-nv.c.
11 * Variable system clock when/if it makes sense
12 * Power management on ports
15 * Documentation publically available.
18 #include <linux/kernel.h>
19 #include <linux/module.h>
20 #include <linux/pci.h>
21 #include <linux/init.h>
22 #include <linux/blkdev.h>
23 #include <linux/delay.h>
24 #include <scsi/scsi_host.h>
25 #include <linux/libata.h>
27 #define DRV_NAME "pata_amd"
28 #define DRV_VERSION "0.2.7"
31 * timing_setup - shared timing computation and load
32 * @ap: ATA port being set up
33 * @adev: drive being configured
34 * @offset: port offset
35 * @speed: target speed
36 * @clock: clock multiplier (number of times 33MHz for this part)
38 * Perform the actual timing set up for Nvidia or AMD PATA devices.
39 * The actual devices vary so they all call into this helper function
40 * providing the clock multipler and offset (because AMD and Nvidia put
41 * the ports at different locations).
44 static void timing_setup(struct ata_port *ap, struct ata_device *adev, int offset, int speed, int clock)
46 static const unsigned char amd_cyc2udma[] = {
47 6, 6, 5, 4, 0, 1, 1, 2, 2, 3, 3, 3, 3, 3, 3, 7
50 struct pci_dev *pdev = to_pci_dev(ap->host->dev);
51 struct ata_device *peer = ata_dev_pair(adev);
52 int dn = ap->port_no * 2 + adev->devno;
53 struct ata_timing at, apeer;
55 const int amd_clock = 33333; /* KHz. */
58 T = 1000000000 / amd_clock;
59 UT = T / min_t(int, max_t(int, clock, 1), 2);
61 if (ata_timing_compute(adev, speed, &at, T, UT) < 0) {
62 dev_printk(KERN_ERR, &pdev->dev, "unknown mode %d.\n", speed);
67 /* This may be over conservative */
69 ata_timing_compute(peer, peer->dma_mode, &apeer, T, UT);
70 ata_timing_merge(&apeer, &at, &at, ATA_TIMING_8BIT);
72 ata_timing_compute(peer, peer->pio_mode, &apeer, T, UT);
73 ata_timing_merge(&apeer, &at, &at, ATA_TIMING_8BIT);
76 if (speed == XFER_UDMA_5 && amd_clock <= 33333) at.udma = 1;
77 if (speed == XFER_UDMA_6 && amd_clock <= 33333) at.udma = 15;
80 * Now do the setup work
83 /* Configure the address set up timing */
84 pci_read_config_byte(pdev, offset + 0x0C, &t);
85 t = (t & ~(3 << ((3 - dn) << 1))) | ((FIT(at.setup, 1, 4) - 1) << ((3 - dn) << 1));
86 pci_write_config_byte(pdev, offset + 0x0C , t);
88 /* Configure the 8bit I/O timing */
89 pci_write_config_byte(pdev, offset + 0x0E + (1 - (dn >> 1)),
90 ((FIT(at.act8b, 1, 16) - 1) << 4) | (FIT(at.rec8b, 1, 16) - 1));
93 pci_write_config_byte(pdev, offset + 0x08 + (3 - dn),
94 ((FIT(at.active, 1, 16) - 1) << 4) | (FIT(at.recover, 1, 16) - 1));
98 t = at.udma ? (0xc0 | (FIT(at.udma, 2, 5) - 2)) : 0x03;
102 t = at.udma ? (0xc0 | amd_cyc2udma[FIT(at.udma, 2, 10)]) : 0x03;
106 t = at.udma ? (0xc0 | amd_cyc2udma[FIT(at.udma, 1, 10)]) : 0x03;
110 t = at.udma ? (0xc0 | amd_cyc2udma[FIT(at.udma, 1, 15)]) : 0x03;
118 pci_write_config_byte(pdev, offset + 0x10 + (3 - dn), t);
122 * amd_probe_init - cable detection
125 * Perform cable detection. The BIOS stores this in PCI config
129 static int amd_pre_reset(struct ata_port *ap)
131 static const u32 bitmask[2] = {0x03, 0xC0};
132 static const struct pci_bits amd_enable_bits[] = {
133 { 0x40, 1, 0x02, 0x02 },
134 { 0x40, 1, 0x01, 0x01 }
137 struct pci_dev *pdev = to_pci_dev(ap->host->dev);
140 if (!pci_test_config_bits(pdev, &amd_enable_bits[ap->port_no]))
143 pci_read_config_byte(pdev, 0x42, &ata66);
144 if (ata66 & bitmask[ap->port_no])
145 ap->cbl = ATA_CBL_PATA80;
147 ap->cbl = ATA_CBL_PATA40;
148 return ata_std_prereset(ap);
152 static void amd_error_handler(struct ata_port *ap)
154 return ata_bmdma_drive_eh(ap, amd_pre_reset,
155 ata_std_softreset, NULL,
159 static int amd_early_pre_reset(struct ata_port *ap)
161 struct pci_dev *pdev = to_pci_dev(ap->host->dev);
162 static struct pci_bits amd_enable_bits[] = {
163 { 0x40, 1, 0x02, 0x02 },
164 { 0x40, 1, 0x01, 0x01 }
167 if (!pci_test_config_bits(pdev, &amd_enable_bits[ap->port_no]))
170 /* No host side cable detection */
171 ap->cbl = ATA_CBL_PATA80;
172 return ata_std_prereset(ap);
176 static void amd_early_error_handler(struct ata_port *ap)
178 ata_bmdma_drive_eh(ap, amd_early_pre_reset,
179 ata_std_softreset, NULL,
184 * amd33_set_piomode - set initial PIO mode data
188 * Program the AMD registers for PIO mode.
191 static void amd33_set_piomode(struct ata_port *ap, struct ata_device *adev)
193 timing_setup(ap, adev, 0x40, adev->pio_mode, 1);
196 static void amd66_set_piomode(struct ata_port *ap, struct ata_device *adev)
198 timing_setup(ap, adev, 0x40, adev->pio_mode, 2);
201 static void amd100_set_piomode(struct ata_port *ap, struct ata_device *adev)
203 timing_setup(ap, adev, 0x40, adev->pio_mode, 3);
206 static void amd133_set_piomode(struct ata_port *ap, struct ata_device *adev)
208 timing_setup(ap, adev, 0x40, adev->pio_mode, 4);
212 * amd33_set_dmamode - set initial DMA mode data
216 * Program the MWDMA/UDMA modes for the AMD and Nvidia
220 static void amd33_set_dmamode(struct ata_port *ap, struct ata_device *adev)
222 timing_setup(ap, adev, 0x40, adev->dma_mode, 1);
225 static void amd66_set_dmamode(struct ata_port *ap, struct ata_device *adev)
227 timing_setup(ap, adev, 0x40, adev->dma_mode, 2);
230 static void amd100_set_dmamode(struct ata_port *ap, struct ata_device *adev)
232 timing_setup(ap, adev, 0x40, adev->dma_mode, 3);
235 static void amd133_set_dmamode(struct ata_port *ap, struct ata_device *adev)
237 timing_setup(ap, adev, 0x40, adev->dma_mode, 4);
242 * nv_probe_init - cable detection
245 * Perform cable detection. The BIOS stores this in PCI config
249 static int nv_pre_reset(struct ata_port *ap) {
250 static const u8 bitmask[2] = {0x03, 0xC0};
251 static const struct pci_bits nv_enable_bits[] = {
252 { 0x50, 1, 0x02, 0x02 },
253 { 0x50, 1, 0x01, 0x01 }
256 struct pci_dev *pdev = to_pci_dev(ap->host->dev);
260 if (!pci_test_config_bits(pdev, &nv_enable_bits[ap->port_no]))
263 pci_read_config_byte(pdev, 0x52, &ata66);
264 if (ata66 & bitmask[ap->port_no])
265 ap->cbl = ATA_CBL_PATA80;
267 ap->cbl = ATA_CBL_PATA40;
269 /* We now have to double check because the Nvidia boxes BIOS
270 doesn't always set the cable bits but does set mode bits */
272 pci_read_config_word(pdev, 0x62 - 2 * ap->port_no, &udma);
273 if ((udma & 0xC4) == 0xC4 || (udma & 0xC400) == 0xC400)
274 ap->cbl = ATA_CBL_PATA80;
275 return ata_std_prereset(ap);
278 static void nv_error_handler(struct ata_port *ap)
280 ata_bmdma_drive_eh(ap, nv_pre_reset,
281 ata_std_softreset, NULL,
285 * nv100_set_piomode - set initial PIO mode data
289 * Program the AMD registers for PIO mode.
292 static void nv100_set_piomode(struct ata_port *ap, struct ata_device *adev)
294 timing_setup(ap, adev, 0x50, adev->pio_mode, 3);
297 static void nv133_set_piomode(struct ata_port *ap, struct ata_device *adev)
299 timing_setup(ap, adev, 0x50, adev->pio_mode, 4);
303 * nv100_set_dmamode - set initial DMA mode data
307 * Program the MWDMA/UDMA modes for the AMD and Nvidia
311 static void nv100_set_dmamode(struct ata_port *ap, struct ata_device *adev)
313 timing_setup(ap, adev, 0x50, adev->dma_mode, 3);
316 static void nv133_set_dmamode(struct ata_port *ap, struct ata_device *adev)
318 timing_setup(ap, adev, 0x50, adev->dma_mode, 4);
321 static struct scsi_host_template amd_sht = {
322 .module = THIS_MODULE,
324 .ioctl = ata_scsi_ioctl,
325 .queuecommand = ata_scsi_queuecmd,
326 .can_queue = ATA_DEF_QUEUE,
327 .this_id = ATA_SHT_THIS_ID,
328 .sg_tablesize = LIBATA_MAX_PRD,
329 .max_sectors = ATA_MAX_SECTORS,
330 .cmd_per_lun = ATA_SHT_CMD_PER_LUN,
331 .emulated = ATA_SHT_EMULATED,
332 .use_clustering = ATA_SHT_USE_CLUSTERING,
333 .proc_name = DRV_NAME,
334 .dma_boundary = ATA_DMA_BOUNDARY,
335 .slave_configure = ata_scsi_slave_config,
336 .slave_destroy = ata_scsi_slave_destroy,
337 .bios_param = ata_std_bios_param,
338 .resume = ata_scsi_device_resume,
339 .suspend = ata_scsi_device_suspend,
342 static struct ata_port_operations amd33_port_ops = {
343 .port_disable = ata_port_disable,
344 .set_piomode = amd33_set_piomode,
345 .set_dmamode = amd33_set_dmamode,
346 .mode_filter = ata_pci_default_filter,
347 .tf_load = ata_tf_load,
348 .tf_read = ata_tf_read,
349 .check_status = ata_check_status,
350 .exec_command = ata_exec_command,
351 .dev_select = ata_std_dev_select,
353 .freeze = ata_bmdma_freeze,
354 .thaw = ata_bmdma_thaw,
355 .error_handler = amd_early_error_handler,
356 .post_internal_cmd = ata_bmdma_post_internal_cmd,
358 .bmdma_setup = ata_bmdma_setup,
359 .bmdma_start = ata_bmdma_start,
360 .bmdma_stop = ata_bmdma_stop,
361 .bmdma_status = ata_bmdma_status,
363 .qc_prep = ata_qc_prep,
364 .qc_issue = ata_qc_issue_prot,
366 .data_xfer = ata_pio_data_xfer,
368 .irq_handler = ata_interrupt,
369 .irq_clear = ata_bmdma_irq_clear,
371 .port_start = ata_port_start,
372 .port_stop = ata_port_stop,
373 .host_stop = ata_host_stop
376 static struct ata_port_operations amd66_port_ops = {
377 .port_disable = ata_port_disable,
378 .set_piomode = amd66_set_piomode,
379 .set_dmamode = amd66_set_dmamode,
380 .mode_filter = ata_pci_default_filter,
381 .tf_load = ata_tf_load,
382 .tf_read = ata_tf_read,
383 .check_status = ata_check_status,
384 .exec_command = ata_exec_command,
385 .dev_select = ata_std_dev_select,
387 .freeze = ata_bmdma_freeze,
388 .thaw = ata_bmdma_thaw,
389 .error_handler = amd_early_error_handler,
390 .post_internal_cmd = ata_bmdma_post_internal_cmd,
392 .bmdma_setup = ata_bmdma_setup,
393 .bmdma_start = ata_bmdma_start,
394 .bmdma_stop = ata_bmdma_stop,
395 .bmdma_status = ata_bmdma_status,
397 .qc_prep = ata_qc_prep,
398 .qc_issue = ata_qc_issue_prot,
400 .data_xfer = ata_pio_data_xfer,
402 .irq_handler = ata_interrupt,
403 .irq_clear = ata_bmdma_irq_clear,
405 .port_start = ata_port_start,
406 .port_stop = ata_port_stop,
407 .host_stop = ata_host_stop
410 static struct ata_port_operations amd100_port_ops = {
411 .port_disable = ata_port_disable,
412 .set_piomode = amd100_set_piomode,
413 .set_dmamode = amd100_set_dmamode,
414 .mode_filter = ata_pci_default_filter,
415 .tf_load = ata_tf_load,
416 .tf_read = ata_tf_read,
417 .check_status = ata_check_status,
418 .exec_command = ata_exec_command,
419 .dev_select = ata_std_dev_select,
421 .freeze = ata_bmdma_freeze,
422 .thaw = ata_bmdma_thaw,
423 .error_handler = amd_error_handler,
424 .post_internal_cmd = ata_bmdma_post_internal_cmd,
426 .bmdma_setup = ata_bmdma_setup,
427 .bmdma_start = ata_bmdma_start,
428 .bmdma_stop = ata_bmdma_stop,
429 .bmdma_status = ata_bmdma_status,
431 .qc_prep = ata_qc_prep,
432 .qc_issue = ata_qc_issue_prot,
434 .data_xfer = ata_pio_data_xfer,
436 .irq_handler = ata_interrupt,
437 .irq_clear = ata_bmdma_irq_clear,
439 .port_start = ata_port_start,
440 .port_stop = ata_port_stop,
441 .host_stop = ata_host_stop
444 static struct ata_port_operations amd133_port_ops = {
445 .port_disable = ata_port_disable,
446 .set_piomode = amd133_set_piomode,
447 .set_dmamode = amd133_set_dmamode,
448 .mode_filter = ata_pci_default_filter,
449 .tf_load = ata_tf_load,
450 .tf_read = ata_tf_read,
451 .check_status = ata_check_status,
452 .exec_command = ata_exec_command,
453 .dev_select = ata_std_dev_select,
455 .freeze = ata_bmdma_freeze,
456 .thaw = ata_bmdma_thaw,
457 .error_handler = amd_error_handler,
458 .post_internal_cmd = ata_bmdma_post_internal_cmd,
460 .bmdma_setup = ata_bmdma_setup,
461 .bmdma_start = ata_bmdma_start,
462 .bmdma_stop = ata_bmdma_stop,
463 .bmdma_status = ata_bmdma_status,
465 .qc_prep = ata_qc_prep,
466 .qc_issue = ata_qc_issue_prot,
468 .data_xfer = ata_pio_data_xfer,
470 .irq_handler = ata_interrupt,
471 .irq_clear = ata_bmdma_irq_clear,
473 .port_start = ata_port_start,
474 .port_stop = ata_port_stop,
475 .host_stop = ata_host_stop
478 static struct ata_port_operations nv100_port_ops = {
479 .port_disable = ata_port_disable,
480 .set_piomode = nv100_set_piomode,
481 .set_dmamode = nv100_set_dmamode,
482 .mode_filter = ata_pci_default_filter,
483 .tf_load = ata_tf_load,
484 .tf_read = ata_tf_read,
485 .check_status = ata_check_status,
486 .exec_command = ata_exec_command,
487 .dev_select = ata_std_dev_select,
489 .freeze = ata_bmdma_freeze,
490 .thaw = ata_bmdma_thaw,
491 .error_handler = nv_error_handler,
492 .post_internal_cmd = ata_bmdma_post_internal_cmd,
494 .bmdma_setup = ata_bmdma_setup,
495 .bmdma_start = ata_bmdma_start,
496 .bmdma_stop = ata_bmdma_stop,
497 .bmdma_status = ata_bmdma_status,
499 .qc_prep = ata_qc_prep,
500 .qc_issue = ata_qc_issue_prot,
502 .data_xfer = ata_pio_data_xfer,
504 .irq_handler = ata_interrupt,
505 .irq_clear = ata_bmdma_irq_clear,
507 .port_start = ata_port_start,
508 .port_stop = ata_port_stop,
509 .host_stop = ata_host_stop
512 static struct ata_port_operations nv133_port_ops = {
513 .port_disable = ata_port_disable,
514 .set_piomode = nv133_set_piomode,
515 .set_dmamode = nv133_set_dmamode,
516 .mode_filter = ata_pci_default_filter,
517 .tf_load = ata_tf_load,
518 .tf_read = ata_tf_read,
519 .check_status = ata_check_status,
520 .exec_command = ata_exec_command,
521 .dev_select = ata_std_dev_select,
523 .freeze = ata_bmdma_freeze,
524 .thaw = ata_bmdma_thaw,
525 .error_handler = nv_error_handler,
526 .post_internal_cmd = ata_bmdma_post_internal_cmd,
528 .bmdma_setup = ata_bmdma_setup,
529 .bmdma_start = ata_bmdma_start,
530 .bmdma_stop = ata_bmdma_stop,
531 .bmdma_status = ata_bmdma_status,
533 .qc_prep = ata_qc_prep,
534 .qc_issue = ata_qc_issue_prot,
536 .data_xfer = ata_pio_data_xfer,
538 .irq_handler = ata_interrupt,
539 .irq_clear = ata_bmdma_irq_clear,
541 .port_start = ata_port_start,
542 .port_stop = ata_port_stop,
543 .host_stop = ata_host_stop
546 static int amd_init_one(struct pci_dev *pdev, const struct pci_device_id *id)
548 static struct ata_port_info info[10] = {
551 .flags = ATA_FLAG_SLAVE_POSS | ATA_FLAG_SRST,
553 .mwdma_mask = 0x07, /* No SWDMA */
554 .udma_mask = 0x07, /* UDMA 33 */
555 .port_ops = &amd33_port_ops
557 { /* 1: Early AMD7409 - no swdma */
559 .flags = ATA_FLAG_SLAVE_POSS | ATA_FLAG_SRST,
562 .udma_mask = 0x1f, /* UDMA 66 */
563 .port_ops = &amd66_port_ops
565 { /* 2: AMD 7409, no swdma errata */
567 .flags = ATA_FLAG_SLAVE_POSS | ATA_FLAG_SRST,
570 .udma_mask = 0x1f, /* UDMA 66 */
571 .port_ops = &amd66_port_ops
575 .flags = ATA_FLAG_SLAVE_POSS | ATA_FLAG_SRST,
578 .udma_mask = 0x3f, /* UDMA 100 */
579 .port_ops = &amd100_port_ops
583 .flags = ATA_FLAG_SLAVE_POSS | ATA_FLAG_SRST,
586 .udma_mask = 0x3f, /* UDMA 100 */
587 .port_ops = &amd100_port_ops
591 .flags = ATA_FLAG_SLAVE_POSS | ATA_FLAG_SRST,
594 .udma_mask = 0x7f, /* UDMA 133, no swdma */
595 .port_ops = &amd133_port_ops
597 { /* 6: AMD 8111 UDMA 100 (Serenade) */
599 .flags = ATA_FLAG_SLAVE_POSS | ATA_FLAG_SRST,
602 .udma_mask = 0x3f, /* UDMA 100, no swdma */
603 .port_ops = &amd133_port_ops
605 { /* 7: Nvidia Nforce */
607 .flags = ATA_FLAG_SLAVE_POSS | ATA_FLAG_SRST,
610 .udma_mask = 0x3f, /* UDMA 100 */
611 .port_ops = &nv100_port_ops
613 { /* 8: Nvidia Nforce2 and later */
615 .flags = ATA_FLAG_SLAVE_POSS | ATA_FLAG_SRST,
618 .udma_mask = 0x7f, /* UDMA 133, no swdma */
619 .port_ops = &nv133_port_ops
621 { /* 9: AMD CS5536 (Geode companion) */
623 .flags = ATA_FLAG_SLAVE_POSS | ATA_FLAG_SRST,
626 .udma_mask = 0x3f, /* UDMA 100 */
627 .port_ops = &amd100_port_ops
630 static struct ata_port_info *port_info[2];
631 static int printed_version;
632 int type = id->driver_data;
636 if (!printed_version++)
637 dev_printk(KERN_DEBUG, &pdev->dev, "version " DRV_VERSION "\n");
639 pci_read_config_byte(pdev, PCI_REVISION_ID, &rev);
640 pci_read_config_byte(pdev, 0x41, &fifo);
642 /* Check for AMD7409 without swdma errata and if found adjust type */
643 if (type == 1 && rev > 0x7)
646 /* Check for AMD7411 */
649 pci_write_config_byte(pdev, 0x41, fifo & 0x0F);
651 pci_write_config_byte(pdev, 0x41, fifo | 0xF0);
654 if (type == 5 && pdev->subsystem_vendor == PCI_VENDOR_ID_AMD &&
655 pdev->subsystem_device == PCI_DEVICE_ID_AMD_SERENADE)
656 type = 6; /* UDMA 100 only */
659 ata_pci_clear_simplex(pdev);
663 port_info[0] = port_info[1] = &info[type];
664 return ata_pci_init_one(pdev, port_info, 2);
667 static int amd_reinit_one(struct pci_dev *pdev)
669 if (pdev->vendor == PCI_VENDOR_ID_AMD) {
671 pci_read_config_byte(pdev, 0x41, &fifo);
672 if (pdev->device == PCI_DEVICE_ID_AMD_VIPER_7411)
674 pci_write_config_byte(pdev, 0x41, fifo & 0x0F);
676 pci_write_config_byte(pdev, 0x41, fifo | 0xF0);
677 if (pdev->device == PCI_DEVICE_ID_AMD_VIPER_7409 ||
678 pdev->device == PCI_DEVICE_ID_AMD_COBRA_7401)
679 ata_pci_clear_simplex(pdev);
681 return ata_pci_device_resume(pdev);
684 static const struct pci_device_id amd[] = {
685 { PCI_VDEVICE(AMD, PCI_DEVICE_ID_AMD_COBRA_7401), 0 },
686 { PCI_VDEVICE(AMD, PCI_DEVICE_ID_AMD_VIPER_7409), 1 },
687 { PCI_VDEVICE(AMD, PCI_DEVICE_ID_AMD_VIPER_7411), 3 },
688 { PCI_VDEVICE(AMD, PCI_DEVICE_ID_AMD_OPUS_7441), 4 },
689 { PCI_VDEVICE(AMD, PCI_DEVICE_ID_AMD_8111_IDE), 5 },
690 { PCI_VDEVICE(NVIDIA, PCI_DEVICE_ID_NVIDIA_NFORCE_IDE), 7 },
691 { PCI_VDEVICE(NVIDIA, PCI_DEVICE_ID_NVIDIA_NFORCE2_IDE), 8 },
692 { PCI_VDEVICE(NVIDIA, PCI_DEVICE_ID_NVIDIA_NFORCE2S_IDE), 8 },
693 { PCI_VDEVICE(NVIDIA, PCI_DEVICE_ID_NVIDIA_NFORCE3_IDE), 8 },
694 { PCI_VDEVICE(NVIDIA, PCI_DEVICE_ID_NVIDIA_NFORCE3S_IDE), 8 },
695 { PCI_VDEVICE(NVIDIA, PCI_DEVICE_ID_NVIDIA_NFORCE_CK804_IDE), 8 },
696 { PCI_VDEVICE(NVIDIA, PCI_DEVICE_ID_NVIDIA_NFORCE_MCP04_IDE), 8 },
697 { PCI_VDEVICE(NVIDIA, PCI_DEVICE_ID_NVIDIA_NFORCE_MCP51_IDE), 8 },
698 { PCI_VDEVICE(NVIDIA, PCI_DEVICE_ID_NVIDIA_NFORCE_MCP55_IDE), 8 },
699 { PCI_VDEVICE(NVIDIA, PCI_DEVICE_ID_NVIDIA_NFORCE_MCP61_IDE), 8 },
700 { PCI_VDEVICE(NVIDIA, PCI_DEVICE_ID_NVIDIA_NFORCE_MCP65_IDE), 8 },
701 { PCI_VDEVICE(NVIDIA, PCI_DEVICE_ID_NVIDIA_NFORCE_MCP67_IDE), 8 },
702 { PCI_VDEVICE(AMD, PCI_DEVICE_ID_AMD_CS5536_IDE), 9 },
707 static struct pci_driver amd_pci_driver = {
710 .probe = amd_init_one,
711 .remove = ata_pci_remove_one,
712 .suspend = ata_pci_device_suspend,
713 .resume = amd_reinit_one,
716 static int __init amd_init(void)
718 return pci_register_driver(&amd_pci_driver);
721 static void __exit amd_exit(void)
723 pci_unregister_driver(&amd_pci_driver);
726 MODULE_AUTHOR("Alan Cox");
727 MODULE_DESCRIPTION("low-level driver for AMD PATA IDE");
728 MODULE_LICENSE("GPL");
729 MODULE_DEVICE_TABLE(pci, amd);
730 MODULE_VERSION(DRV_VERSION);
732 module_init(amd_init);
733 module_exit(amd_exit);