2 * ata_piix.c - Intel PATA/SATA controllers
4 * Maintained by: Jeff Garzik <jgarzik@pobox.com>
5 * Please ALWAYS copy linux-ide@vger.kernel.org
9 * Copyright 2003-2005 Red Hat Inc
10 * Copyright 2003-2005 Jeff Garzik
13 * Copyright header from piix.c:
15 * Copyright (C) 1998-1999 Andrzej Krzysztofowicz, Author and Maintainer
16 * Copyright (C) 1998-2000 Andre Hedrick <andre@linux-ide.org>
17 * Copyright (C) 2003 Red Hat Inc <alan@redhat.com>
20 * This program is free software; you can redistribute it and/or modify
21 * it under the terms of the GNU General Public License as published by
22 * the Free Software Foundation; either version 2, or (at your option)
25 * This program is distributed in the hope that it will be useful,
26 * but WITHOUT ANY WARRANTY; without even the implied warranty of
27 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
28 * GNU General Public License for more details.
30 * You should have received a copy of the GNU General Public License
31 * along with this program; see the file COPYING. If not, write to
32 * the Free Software Foundation, 675 Mass Ave, Cambridge, MA 02139, USA.
35 * libata documentation is available via 'make {ps|pdf}docs',
36 * as Documentation/DocBook/libata.*
38 * Hardware documentation available at http://developer.intel.com/
41 * Publically available from Intel web site. Errata documentation
42 * is also publically available. As an aide to anyone hacking on this
43 * driver the list of errata that are relevant is below, going back to
44 * PIIX4. Older device documentation is now a bit tricky to find.
46 * The chipsets all follow very much the same design. The orginal Triton
47 * series chipsets do _not_ support independant device timings, but this
48 * is fixed in Triton II. With the odd mobile exception the chips then
49 * change little except in gaining more modes until SATA arrives. This
50 * driver supports only the chips with independant timing (that is those
51 * with SITRE and the 0x44 timing register). See pata_oldpiix and pata_mpiix
52 * for the early chip drivers.
57 * PIIX4 errata #9 - Only on ultra obscure hw
58 * ICH3 errata #13 - Not observed to affect real hw
61 * Things we must deal with
62 * PIIX4 errata #10 - BM IDE hang with non UDMA
63 * (must stop/start dma to recover)
64 * 440MX errata #15 - As PIIX4 errata #10
65 * PIIX4 errata #15 - Must not read control registers
66 * during a PIO transfer
67 * 440MX errata #13 - As PIIX4 errata #15
68 * ICH2 errata #21 - DMA mode 0 doesn't work right
69 * ICH0/1 errata #55 - As ICH2 errata #21
70 * ICH2 spec c #9 - Extra operations needed to handle
71 * drive hotswap [NOT YET SUPPORTED]
72 * ICH2 spec c #20 - IDE PRD must not cross a 64K boundary
73 * and must be dword aligned
74 * ICH2 spec c #24 - UDMA mode 4,5 t85/86 should be 6ns not 3.3
76 * Should have been BIOS fixed:
77 * 450NX: errata #19 - DMA hangs on old 450NX
78 * 450NX: errata #20 - DMA hangs on old 450NX
79 * 450NX: errata #25 - Corruption with DMA on old 450NX
80 * ICH3 errata #15 - IDE deadlock under high load
81 * (BIOS must set dev 31 fn 0 bit 23)
82 * ICH3 errata #18 - Don't use native mode
85 #include <linux/kernel.h>
86 #include <linux/module.h>
87 #include <linux/pci.h>
88 #include <linux/init.h>
89 #include <linux/blkdev.h>
90 #include <linux/delay.h>
91 #include <linux/device.h>
92 #include <scsi/scsi_host.h>
93 #include <linux/libata.h>
94 #include <linux/dmi.h>
96 #define DRV_NAME "ata_piix"
97 #define DRV_VERSION "2.12"
100 PIIX_IOCFG = 0x54, /* IDE I/O configuration register */
101 ICH5_PMR = 0x90, /* port mapping register */
102 ICH5_PCS = 0x92, /* port control and status */
103 PIIX_SCC = 0x0A, /* sub-class code register */
105 PIIX_FLAG_SCR = (1 << 26), /* SCR available */
106 PIIX_FLAG_AHCI = (1 << 27), /* AHCI possible */
107 PIIX_FLAG_CHECKINTR = (1 << 28), /* make sure PCI INTx enabled */
109 PIIX_PATA_FLAGS = ATA_FLAG_SLAVE_POSS,
110 PIIX_SATA_FLAGS = ATA_FLAG_SATA | PIIX_FLAG_CHECKINTR,
112 /* combined mode. if set, PATA is channel 0.
113 * if clear, PATA is channel 1.
115 PIIX_PORT_ENABLED = (1 << 0),
116 PIIX_PORT_PRESENT = (1 << 4),
118 PIIX_80C_PRI = (1 << 5) | (1 << 4),
119 PIIX_80C_SEC = (1 << 7) | (1 << 6),
121 /* constants for mapping table */
127 NA = -2, /* not avaliable */
128 RV = -3, /* reserved */
130 PIIX_AHCI_DEVICE = 6,
132 /* host->flags bits */
133 PIIX_HOST_BROKEN_SUSPEND = (1 << 24),
136 enum piix_controller_ids {
138 piix_pata_mwdma, /* PIIX3 MWDMA only */
139 piix_pata_33, /* PIIX4 at 33Mhz */
140 ich_pata_33, /* ICH up to UDMA 33 only */
141 ich_pata_66, /* ICH up to 66 Mhz */
142 ich_pata_100, /* ICH up to UDMA 100 */
149 ich8m_apple_sata_ahci, /* locks up on second port enable */
151 piix_pata_vmw, /* PIIX4 for VMware, spurious DMA_ERR */
156 const u16 port_enable;
160 struct piix_host_priv {
164 static int piix_init_one(struct pci_dev *pdev,
165 const struct pci_device_id *ent);
166 static void piix_pata_error_handler(struct ata_port *ap);
167 static void piix_set_piomode(struct ata_port *ap, struct ata_device *adev);
168 static void piix_set_dmamode(struct ata_port *ap, struct ata_device *adev);
169 static void ich_set_dmamode(struct ata_port *ap, struct ata_device *adev);
170 static int ich_pata_cable_detect(struct ata_port *ap);
171 static u8 piix_vmw_bmdma_status(struct ata_port *ap);
173 static int piix_pci_device_suspend(struct pci_dev *pdev, pm_message_t mesg);
174 static int piix_pci_device_resume(struct pci_dev *pdev);
177 static unsigned int in_module_init = 1;
179 static const struct pci_device_id piix_pci_tbl[] = {
180 /* Intel PIIX3 for the 430HX etc */
181 { 0x8086, 0x7010, PCI_ANY_ID, PCI_ANY_ID, 0, 0, piix_pata_mwdma },
183 { 0x8086, 0x7111, 0x15ad, 0x1976, 0, 0, piix_pata_vmw },
184 /* Intel PIIX4 for the 430TX/440BX/MX chipset: UDMA 33 */
185 /* Also PIIX4E (fn3 rev 2) and PIIX4M (fn3 rev 3) */
186 { 0x8086, 0x7111, PCI_ANY_ID, PCI_ANY_ID, 0, 0, piix_pata_33 },
188 { 0x8086, 0x7199, PCI_ANY_ID, PCI_ANY_ID, 0, 0, piix_pata_33 },
190 { 0x8086, 0x7601, PCI_ANY_ID, PCI_ANY_ID, 0, 0, piix_pata_33 },
192 { 0x8086, 0x84CA, PCI_ANY_ID, PCI_ANY_ID, 0, 0, piix_pata_33 },
193 /* Intel ICH (i810, i815, i840) UDMA 66*/
194 { 0x8086, 0x2411, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich_pata_66 },
195 /* Intel ICH0 : UDMA 33*/
196 { 0x8086, 0x2421, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich_pata_33 },
198 { 0x8086, 0x244A, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich_pata_100 },
199 /* Intel ICH2 (i810E2, i845, 850, 860) UDMA 100 */
200 { 0x8086, 0x244B, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich_pata_100 },
202 { 0x8086, 0x248A, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich_pata_100 },
203 /* Intel ICH3 (E7500/1) UDMA 100 */
204 { 0x8086, 0x248B, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich_pata_100 },
205 /* Intel ICH4 (i845GV, i845E, i852, i855) UDMA 100 */
206 { 0x8086, 0x24CA, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich_pata_100 },
207 { 0x8086, 0x24CB, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich_pata_100 },
209 { 0x8086, 0x24DB, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich_pata_100 },
211 { 0x8086, 0x245B, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich_pata_100 },
212 /* ESB (855GME/875P + 6300ESB) UDMA 100 */
213 { 0x8086, 0x25A2, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich_pata_100 },
214 /* ICH6 (and 6) (i915) UDMA 100 */
215 { 0x8086, 0x266F, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich_pata_100 },
216 /* ICH7/7-R (i945, i975) UDMA 100*/
217 { 0x8086, 0x27DF, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich_pata_100 },
218 { 0x8086, 0x269E, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich_pata_100 },
219 /* ICH8 Mobile PATA Controller */
220 { 0x8086, 0x2850, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich_pata_100 },
222 /* NOTE: The following PCI ids must be kept in sync with the
223 * list in drivers/pci/quirks.c.
227 { 0x8086, 0x24d1, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich5_sata },
229 { 0x8086, 0x24df, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich5_sata },
230 /* 6300ESB (ICH5 variant with broken PCS present bits) */
231 { 0x8086, 0x25a3, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich5_sata },
232 /* 6300ESB pretending RAID */
233 { 0x8086, 0x25b0, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich5_sata },
234 /* 82801FB/FW (ICH6/ICH6W) */
235 { 0x8086, 0x2651, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich6_sata },
236 /* 82801FR/FRW (ICH6R/ICH6RW) */
237 { 0x8086, 0x2652, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich6_sata_ahci },
238 /* 82801FBM ICH6M (ICH6R with only port 0 and 2 implemented) */
239 { 0x8086, 0x2653, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich6m_sata_ahci },
240 /* 82801GB/GR/GH (ICH7, identical to ICH6) */
241 { 0x8086, 0x27c0, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich6_sata_ahci },
242 /* 2801GBM/GHM (ICH7M, identical to ICH6M) */
243 { 0x8086, 0x27c4, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich6m_sata_ahci },
244 /* Enterprise Southbridge 2 (631xESB/632xESB) */
245 { 0x8086, 0x2680, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich6_sata_ahci },
246 /* SATA Controller 1 IDE (ICH8) */
247 { 0x8086, 0x2820, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich8_sata_ahci },
248 /* SATA Controller 2 IDE (ICH8) */
249 { 0x8086, 0x2825, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich8_2port_sata },
250 /* Mobile SATA Controller IDE (ICH8M) */
251 { 0x8086, 0x2828, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich8_sata_ahci },
252 /* Mobile SATA Controller IDE (ICH8M), Apple */
253 { 0x8086, 0x2828, 0x106b, 0x00a0, 0, 0, ich8m_apple_sata_ahci },
254 /* SATA Controller IDE (ICH9) */
255 { 0x8086, 0x2920, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich8_sata_ahci },
256 /* SATA Controller IDE (ICH9) */
257 { 0x8086, 0x2921, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich8_2port_sata },
258 /* SATA Controller IDE (ICH9) */
259 { 0x8086, 0x2926, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich8_2port_sata },
260 /* SATA Controller IDE (ICH9M) */
261 { 0x8086, 0x2928, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich8_2port_sata },
262 /* SATA Controller IDE (ICH9M) */
263 { 0x8086, 0x292d, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich8_2port_sata },
264 /* SATA Controller IDE (ICH9M) */
265 { 0x8086, 0x292e, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich8_sata_ahci },
266 /* SATA Controller IDE (Tolapai) */
267 { 0x8086, 0x5028, PCI_ANY_ID, PCI_ANY_ID, 0, 0, tolapai_sata_ahci },
269 { } /* terminate list */
272 static struct pci_driver piix_pci_driver = {
274 .id_table = piix_pci_tbl,
275 .probe = piix_init_one,
276 .remove = ata_pci_remove_one,
278 .suspend = piix_pci_device_suspend,
279 .resume = piix_pci_device_resume,
283 static struct scsi_host_template piix_sht = {
284 .module = THIS_MODULE,
286 .ioctl = ata_scsi_ioctl,
287 .queuecommand = ata_scsi_queuecmd,
288 .can_queue = ATA_DEF_QUEUE,
289 .this_id = ATA_SHT_THIS_ID,
290 .sg_tablesize = LIBATA_MAX_PRD,
291 .cmd_per_lun = ATA_SHT_CMD_PER_LUN,
292 .emulated = ATA_SHT_EMULATED,
293 .use_clustering = ATA_SHT_USE_CLUSTERING,
294 .proc_name = DRV_NAME,
295 .dma_boundary = ATA_DMA_BOUNDARY,
296 .slave_configure = ata_scsi_slave_config,
297 .slave_destroy = ata_scsi_slave_destroy,
298 .bios_param = ata_std_bios_param,
301 static const struct ata_port_operations piix_pata_ops = {
302 .set_piomode = piix_set_piomode,
303 .set_dmamode = piix_set_dmamode,
304 .mode_filter = ata_pci_default_filter,
306 .tf_load = ata_tf_load,
307 .tf_read = ata_tf_read,
308 .check_status = ata_check_status,
309 .exec_command = ata_exec_command,
310 .dev_select = ata_std_dev_select,
312 .bmdma_setup = ata_bmdma_setup,
313 .bmdma_start = ata_bmdma_start,
314 .bmdma_stop = ata_bmdma_stop,
315 .bmdma_status = ata_bmdma_status,
316 .qc_prep = ata_qc_prep,
317 .qc_issue = ata_qc_issue_prot,
318 .data_xfer = ata_data_xfer,
320 .freeze = ata_bmdma_freeze,
321 .thaw = ata_bmdma_thaw,
322 .error_handler = piix_pata_error_handler,
323 .post_internal_cmd = ata_bmdma_post_internal_cmd,
324 .cable_detect = ata_cable_40wire,
326 .irq_handler = ata_interrupt,
327 .irq_clear = ata_bmdma_irq_clear,
328 .irq_on = ata_irq_on,
330 .port_start = ata_port_start,
333 static const struct ata_port_operations ich_pata_ops = {
334 .set_piomode = piix_set_piomode,
335 .set_dmamode = ich_set_dmamode,
336 .mode_filter = ata_pci_default_filter,
338 .tf_load = ata_tf_load,
339 .tf_read = ata_tf_read,
340 .check_status = ata_check_status,
341 .exec_command = ata_exec_command,
342 .dev_select = ata_std_dev_select,
344 .bmdma_setup = ata_bmdma_setup,
345 .bmdma_start = ata_bmdma_start,
346 .bmdma_stop = ata_bmdma_stop,
347 .bmdma_status = ata_bmdma_status,
348 .qc_prep = ata_qc_prep,
349 .qc_issue = ata_qc_issue_prot,
350 .data_xfer = ata_data_xfer,
352 .freeze = ata_bmdma_freeze,
353 .thaw = ata_bmdma_thaw,
354 .error_handler = piix_pata_error_handler,
355 .post_internal_cmd = ata_bmdma_post_internal_cmd,
356 .cable_detect = ich_pata_cable_detect,
358 .irq_handler = ata_interrupt,
359 .irq_clear = ata_bmdma_irq_clear,
360 .irq_on = ata_irq_on,
362 .port_start = ata_port_start,
365 static const struct ata_port_operations piix_sata_ops = {
366 .tf_load = ata_tf_load,
367 .tf_read = ata_tf_read,
368 .check_status = ata_check_status,
369 .exec_command = ata_exec_command,
370 .dev_select = ata_std_dev_select,
372 .bmdma_setup = ata_bmdma_setup,
373 .bmdma_start = ata_bmdma_start,
374 .bmdma_stop = ata_bmdma_stop,
375 .bmdma_status = ata_bmdma_status,
376 .qc_prep = ata_qc_prep,
377 .qc_issue = ata_qc_issue_prot,
378 .data_xfer = ata_data_xfer,
380 .freeze = ata_bmdma_freeze,
381 .thaw = ata_bmdma_thaw,
382 .error_handler = ata_bmdma_error_handler,
383 .post_internal_cmd = ata_bmdma_post_internal_cmd,
385 .irq_handler = ata_interrupt,
386 .irq_clear = ata_bmdma_irq_clear,
387 .irq_on = ata_irq_on,
389 .port_start = ata_port_start,
392 static const struct ata_port_operations piix_vmw_ops = {
393 .set_piomode = piix_set_piomode,
394 .set_dmamode = piix_set_dmamode,
395 .mode_filter = ata_pci_default_filter,
397 .tf_load = ata_tf_load,
398 .tf_read = ata_tf_read,
399 .check_status = ata_check_status,
400 .exec_command = ata_exec_command,
401 .dev_select = ata_std_dev_select,
403 .bmdma_setup = ata_bmdma_setup,
404 .bmdma_start = ata_bmdma_start,
405 .bmdma_stop = ata_bmdma_stop,
406 .bmdma_status = piix_vmw_bmdma_status,
407 .qc_prep = ata_qc_prep,
408 .qc_issue = ata_qc_issue_prot,
409 .data_xfer = ata_data_xfer,
411 .freeze = ata_bmdma_freeze,
412 .thaw = ata_bmdma_thaw,
413 .error_handler = piix_pata_error_handler,
414 .post_internal_cmd = ata_bmdma_post_internal_cmd,
415 .cable_detect = ata_cable_40wire,
417 .irq_handler = ata_interrupt,
418 .irq_clear = ata_bmdma_irq_clear,
419 .irq_on = ata_irq_on,
421 .port_start = ata_port_start,
424 static const struct piix_map_db ich5_map_db = {
428 /* PM PS SM SS MAP */
429 { P0, NA, P1, NA }, /* 000b */
430 { P1, NA, P0, NA }, /* 001b */
433 { P0, P1, IDE, IDE }, /* 100b */
434 { P1, P0, IDE, IDE }, /* 101b */
435 { IDE, IDE, P0, P1 }, /* 110b */
436 { IDE, IDE, P1, P0 }, /* 111b */
440 static const struct piix_map_db ich6_map_db = {
444 /* PM PS SM SS MAP */
445 { P0, P2, P1, P3 }, /* 00b */
446 { IDE, IDE, P1, P3 }, /* 01b */
447 { P0, P2, IDE, IDE }, /* 10b */
452 static const struct piix_map_db ich6m_map_db = {
456 /* Map 01b isn't specified in the doc but some notebooks use
457 * it anyway. MAP 01b have been spotted on both ICH6M and
461 /* PM PS SM SS MAP */
462 { P0, P2, NA, NA }, /* 00b */
463 { IDE, IDE, P1, P3 }, /* 01b */
464 { P0, P2, IDE, IDE }, /* 10b */
469 static const struct piix_map_db ich8_map_db = {
473 /* PM PS SM SS MAP */
474 { P0, P2, P1, P3 }, /* 00b (hardwired when in AHCI) */
476 { P0, P2, IDE, IDE }, /* 10b (IDE mode) */
481 static const struct piix_map_db ich8_2port_map_db = {
485 /* PM PS SM SS MAP */
486 { P0, NA, P1, NA }, /* 00b */
487 { RV, RV, RV, RV }, /* 01b */
488 { RV, RV, RV, RV }, /* 10b */
493 static const struct piix_map_db ich8m_apple_map_db = {
497 /* PM PS SM SS MAP */
498 { P0, NA, NA, NA }, /* 00b */
500 { P0, P2, IDE, IDE }, /* 10b */
505 static const struct piix_map_db tolapai_map_db = {
509 /* PM PS SM SS MAP */
510 { P0, NA, P1, NA }, /* 00b */
511 { RV, RV, RV, RV }, /* 01b */
512 { RV, RV, RV, RV }, /* 10b */
517 static const struct piix_map_db *piix_map_db_table[] = {
518 [ich5_sata] = &ich5_map_db,
519 [ich6_sata] = &ich6_map_db,
520 [ich6_sata_ahci] = &ich6_map_db,
521 [ich6m_sata_ahci] = &ich6m_map_db,
522 [ich8_sata_ahci] = &ich8_map_db,
523 [ich8_2port_sata] = &ich8_2port_map_db,
524 [ich8m_apple_sata_ahci] = &ich8m_apple_map_db,
525 [tolapai_sata_ahci] = &tolapai_map_db,
528 static struct ata_port_info piix_port_info[] = {
529 [piix_pata_mwdma] = /* PIIX3 MWDMA only */
532 .flags = PIIX_PATA_FLAGS,
533 .pio_mask = 0x1f, /* pio0-4 */
534 .mwdma_mask = 0x06, /* mwdma1-2 ?? CHECK 0 should be ok but slow */
535 .port_ops = &piix_pata_ops,
538 [piix_pata_33] = /* PIIX4 at 33MHz */
541 .flags = PIIX_PATA_FLAGS,
542 .pio_mask = 0x1f, /* pio0-4 */
543 .mwdma_mask = 0x06, /* mwdma1-2 ?? CHECK 0 should be ok but slow */
544 .udma_mask = ATA_UDMA_MASK_40C,
545 .port_ops = &piix_pata_ops,
548 [ich_pata_33] = /* ICH0 - ICH at 33Mhz*/
551 .flags = PIIX_PATA_FLAGS,
552 .pio_mask = 0x1f, /* pio 0-4 */
553 .mwdma_mask = 0x06, /* Check: maybe 0x07 */
554 .udma_mask = ATA_UDMA2, /* UDMA33 */
555 .port_ops = &ich_pata_ops,
558 [ich_pata_66] = /* ICH controllers up to 66MHz */
561 .flags = PIIX_PATA_FLAGS,
562 .pio_mask = 0x1f, /* pio 0-4 */
563 .mwdma_mask = 0x06, /* MWDMA0 is broken on chip */
564 .udma_mask = ATA_UDMA4,
565 .port_ops = &ich_pata_ops,
571 .flags = PIIX_PATA_FLAGS | PIIX_FLAG_CHECKINTR,
572 .pio_mask = 0x1f, /* pio0-4 */
573 .mwdma_mask = 0x06, /* mwdma1-2 */
574 .udma_mask = ATA_UDMA5, /* udma0-5 */
575 .port_ops = &ich_pata_ops,
581 .flags = PIIX_SATA_FLAGS,
582 .pio_mask = 0x1f, /* pio0-4 */
583 .mwdma_mask = 0x07, /* mwdma0-2 */
584 .udma_mask = ATA_UDMA6,
585 .port_ops = &piix_sata_ops,
591 .flags = PIIX_SATA_FLAGS | PIIX_FLAG_SCR,
592 .pio_mask = 0x1f, /* pio0-4 */
593 .mwdma_mask = 0x07, /* mwdma0-2 */
594 .udma_mask = ATA_UDMA6,
595 .port_ops = &piix_sata_ops,
601 .flags = PIIX_SATA_FLAGS | PIIX_FLAG_SCR |
603 .pio_mask = 0x1f, /* pio0-4 */
604 .mwdma_mask = 0x07, /* mwdma0-2 */
605 .udma_mask = ATA_UDMA6,
606 .port_ops = &piix_sata_ops,
612 .flags = PIIX_SATA_FLAGS | PIIX_FLAG_SCR |
614 .pio_mask = 0x1f, /* pio0-4 */
615 .mwdma_mask = 0x07, /* mwdma0-2 */
616 .udma_mask = ATA_UDMA6,
617 .port_ops = &piix_sata_ops,
623 .flags = PIIX_SATA_FLAGS | PIIX_FLAG_SCR |
625 .pio_mask = 0x1f, /* pio0-4 */
626 .mwdma_mask = 0x07, /* mwdma0-2 */
627 .udma_mask = ATA_UDMA6,
628 .port_ops = &piix_sata_ops,
634 .flags = PIIX_SATA_FLAGS | PIIX_FLAG_SCR |
636 .pio_mask = 0x1f, /* pio0-4 */
637 .mwdma_mask = 0x07, /* mwdma0-2 */
638 .udma_mask = ATA_UDMA6,
639 .port_ops = &piix_sata_ops,
642 [tolapai_sata_ahci] =
645 .flags = PIIX_SATA_FLAGS | PIIX_FLAG_SCR |
647 .pio_mask = 0x1f, /* pio0-4 */
648 .mwdma_mask = 0x07, /* mwdma0-2 */
649 .udma_mask = ATA_UDMA6,
650 .port_ops = &piix_sata_ops,
653 [ich8m_apple_sata_ahci] =
656 .flags = PIIX_SATA_FLAGS | PIIX_FLAG_SCR |
658 .pio_mask = 0x1f, /* pio0-4 */
659 .mwdma_mask = 0x07, /* mwdma0-2 */
660 .udma_mask = ATA_UDMA6,
661 .port_ops = &piix_sata_ops,
667 .flags = PIIX_PATA_FLAGS,
668 .pio_mask = 0x1f, /* pio0-4 */
669 .mwdma_mask = 0x06, /* mwdma1-2 ?? CHECK 0 should be ok but slow */
670 .udma_mask = ATA_UDMA_MASK_40C,
671 .port_ops = &piix_vmw_ops,
676 static struct pci_bits piix_enable_bits[] = {
677 { 0x41U, 1U, 0x80UL, 0x80UL }, /* port 0 */
678 { 0x43U, 1U, 0x80UL, 0x80UL }, /* port 1 */
681 MODULE_AUTHOR("Andre Hedrick, Alan Cox, Andrzej Krzysztofowicz, Jeff Garzik");
682 MODULE_DESCRIPTION("SCSI low-level driver for Intel PIIX/ICH ATA controllers");
683 MODULE_LICENSE("GPL");
684 MODULE_DEVICE_TABLE(pci, piix_pci_tbl);
685 MODULE_VERSION(DRV_VERSION);
694 * List of laptops that use short cables rather than 80 wire
697 static const struct ich_laptop ich_laptop[] = {
698 /* devid, subvendor, subdev */
699 { 0x27DF, 0x0005, 0x0280 }, /* ICH7 on Acer 5602WLMi */
700 { 0x27DF, 0x1025, 0x0102 }, /* ICH7 on Acer 5602aWLMi */
701 { 0x27DF, 0x1025, 0x0110 }, /* ICH7 on Acer 3682WLMi */
702 { 0x27DF, 0x1043, 0x1267 }, /* ICH7 on Asus W5F */
703 { 0x27DF, 0x103C, 0x30A1 }, /* ICH7 on HP Compaq nc2400 */
704 { 0x24CA, 0x1025, 0x0061 }, /* ICH4 on ACER Aspire 2023WLMi */
710 * ich_pata_cable_detect - Probe host controller cable detect info
711 * @ap: Port for which cable detect info is desired
713 * Read 80c cable indicator from ATA PCI device's PCI config
714 * register. This register is normally set by firmware (BIOS).
717 * None (inherited from caller).
720 static int ich_pata_cable_detect(struct ata_port *ap)
722 struct pci_dev *pdev = to_pci_dev(ap->host->dev);
723 const struct ich_laptop *lap = &ich_laptop[0];
726 /* Check for specials - Acer Aspire 5602WLMi */
727 while (lap->device) {
728 if (lap->device == pdev->device &&
729 lap->subvendor == pdev->subsystem_vendor &&
730 lap->subdevice == pdev->subsystem_device)
731 return ATA_CBL_PATA40_SHORT;
736 /* check BIOS cable detect results */
737 mask = ap->port_no == 0 ? PIIX_80C_PRI : PIIX_80C_SEC;
738 pci_read_config_byte(pdev, PIIX_IOCFG, &tmp);
739 if ((tmp & mask) == 0)
740 return ATA_CBL_PATA40;
741 return ATA_CBL_PATA80;
745 * piix_pata_prereset - prereset for PATA host controller
747 * @deadline: deadline jiffies for the operation
750 * None (inherited from caller).
752 static int piix_pata_prereset(struct ata_link *link, unsigned long deadline)
754 struct ata_port *ap = link->ap;
755 struct pci_dev *pdev = to_pci_dev(ap->host->dev);
757 if (!pci_test_config_bits(pdev, &piix_enable_bits[ap->port_no]))
759 return ata_std_prereset(link, deadline);
762 static void piix_pata_error_handler(struct ata_port *ap)
764 ata_bmdma_drive_eh(ap, piix_pata_prereset, ata_std_softreset, NULL,
769 * piix_set_piomode - Initialize host controller PATA PIO timings
770 * @ap: Port whose timings we are configuring
773 * Set PIO mode for device, in host controller PCI config space.
776 * None (inherited from caller).
779 static void piix_set_piomode(struct ata_port *ap, struct ata_device *adev)
781 unsigned int pio = adev->pio_mode - XFER_PIO_0;
782 struct pci_dev *dev = to_pci_dev(ap->host->dev);
783 unsigned int is_slave = (adev->devno != 0);
784 unsigned int master_port= ap->port_no ? 0x42 : 0x40;
785 unsigned int slave_port = 0x44;
792 * See Intel Document 298600-004 for the timing programing rules
793 * for ICH controllers.
796 static const /* ISP RTC */
797 u8 timings[][2] = { { 0, 0 },
804 control |= 1; /* TIME1 enable */
805 if (ata_pio_need_iordy(adev))
806 control |= 2; /* IE enable */
808 /* Intel specifies that the PPE functionality is for disk only */
809 if (adev->class == ATA_DEV_ATA)
810 control |= 4; /* PPE enable */
812 /* PIO configuration clears DTE unconditionally. It will be
813 * programmed in set_dmamode which is guaranteed to be called
814 * after set_piomode if any DMA mode is available.
816 pci_read_config_word(dev, master_port, &master_data);
818 /* clear TIME1|IE1|PPE1|DTE1 */
819 master_data &= 0xff0f;
820 /* Enable SITRE (seperate slave timing register) */
821 master_data |= 0x4000;
822 /* enable PPE1, IE1 and TIME1 as needed */
823 master_data |= (control << 4);
824 pci_read_config_byte(dev, slave_port, &slave_data);
825 slave_data &= (ap->port_no ? 0x0f : 0xf0);
826 /* Load the timing nibble for this slave */
827 slave_data |= ((timings[pio][0] << 2) | timings[pio][1])
828 << (ap->port_no ? 4 : 0);
830 /* clear ISP|RCT|TIME0|IE0|PPE0|DTE0 */
831 master_data &= 0xccf0;
832 /* Enable PPE, IE and TIME as appropriate */
833 master_data |= control;
834 /* load ISP and RCT */
836 (timings[pio][0] << 12) |
837 (timings[pio][1] << 8);
839 pci_write_config_word(dev, master_port, master_data);
841 pci_write_config_byte(dev, slave_port, slave_data);
843 /* Ensure the UDMA bit is off - it will be turned back on if
847 pci_read_config_byte(dev, 0x48, &udma_enable);
848 udma_enable &= ~(1 << (2 * ap->port_no + adev->devno));
849 pci_write_config_byte(dev, 0x48, udma_enable);
854 * do_pata_set_dmamode - Initialize host controller PATA PIO timings
855 * @ap: Port whose timings we are configuring
856 * @adev: Drive in question
857 * @udma: udma mode, 0 - 6
858 * @isich: set if the chip is an ICH device
860 * Set UDMA mode for device, in host controller PCI config space.
863 * None (inherited from caller).
866 static void do_pata_set_dmamode(struct ata_port *ap, struct ata_device *adev, int isich)
868 struct pci_dev *dev = to_pci_dev(ap->host->dev);
869 u8 master_port = ap->port_no ? 0x42 : 0x40;
871 u8 speed = adev->dma_mode;
872 int devid = adev->devno + 2 * ap->port_no;
875 static const /* ISP RTC */
876 u8 timings[][2] = { { 0, 0 },
882 pci_read_config_word(dev, master_port, &master_data);
884 pci_read_config_byte(dev, 0x48, &udma_enable);
886 if (speed >= XFER_UDMA_0) {
887 unsigned int udma = adev->dma_mode - XFER_UDMA_0;
890 int u_clock, u_speed;
893 * UDMA is handled by a combination of clock switching and
894 * selection of dividers
896 * Handy rule: Odd modes are UDMATIMx 01, even are 02
897 * except UDMA0 which is 00
899 u_speed = min(2 - (udma & 1), udma);
901 u_clock = 0x1000; /* 100Mhz */
903 u_clock = 1; /* 66Mhz */
905 u_clock = 0; /* 33Mhz */
907 udma_enable |= (1 << devid);
909 /* Load the CT/RP selection */
910 pci_read_config_word(dev, 0x4A, &udma_timing);
911 udma_timing &= ~(3 << (4 * devid));
912 udma_timing |= u_speed << (4 * devid);
913 pci_write_config_word(dev, 0x4A, udma_timing);
916 /* Select a 33/66/100Mhz clock */
917 pci_read_config_word(dev, 0x54, &ideconf);
918 ideconf &= ~(0x1001 << devid);
919 ideconf |= u_clock << devid;
920 /* For ICH or later we should set bit 10 for better
921 performance (WR_PingPong_En) */
922 pci_write_config_word(dev, 0x54, ideconf);
926 * MWDMA is driven by the PIO timings. We must also enable
927 * IORDY unconditionally along with TIME1. PPE has already
928 * been set when the PIO timing was set.
930 unsigned int mwdma = adev->dma_mode - XFER_MW_DMA_0;
931 unsigned int control;
933 const unsigned int needed_pio[3] = {
934 XFER_PIO_0, XFER_PIO_3, XFER_PIO_4
936 int pio = needed_pio[mwdma] - XFER_PIO_0;
938 control = 3; /* IORDY|TIME1 */
940 /* If the drive MWDMA is faster than it can do PIO then
941 we must force PIO into PIO0 */
943 if (adev->pio_mode < needed_pio[mwdma])
944 /* Enable DMA timing only */
945 control |= 8; /* PIO cycles in PIO0 */
947 if (adev->devno) { /* Slave */
948 master_data &= 0xFF4F; /* Mask out IORDY|TIME1|DMAONLY */
949 master_data |= control << 4;
950 pci_read_config_byte(dev, 0x44, &slave_data);
951 slave_data &= (ap->port_no ? 0x0f : 0xf0);
952 /* Load the matching timing */
953 slave_data |= ((timings[pio][0] << 2) | timings[pio][1]) << (ap->port_no ? 4 : 0);
954 pci_write_config_byte(dev, 0x44, slave_data);
955 } else { /* Master */
956 master_data &= 0xCCF4; /* Mask out IORDY|TIME1|DMAONLY
957 and master timing bits */
958 master_data |= control;
960 (timings[pio][0] << 12) |
961 (timings[pio][1] << 8);
965 udma_enable &= ~(1 << devid);
966 pci_write_config_word(dev, master_port, master_data);
969 /* Don't scribble on 0x48 if the controller does not support UDMA */
971 pci_write_config_byte(dev, 0x48, udma_enable);
975 * piix_set_dmamode - Initialize host controller PATA DMA timings
976 * @ap: Port whose timings we are configuring
979 * Set MW/UDMA mode for device, in host controller PCI config space.
982 * None (inherited from caller).
985 static void piix_set_dmamode(struct ata_port *ap, struct ata_device *adev)
987 do_pata_set_dmamode(ap, adev, 0);
991 * ich_set_dmamode - Initialize host controller PATA DMA timings
992 * @ap: Port whose timings we are configuring
995 * Set MW/UDMA mode for device, in host controller PCI config space.
998 * None (inherited from caller).
1001 static void ich_set_dmamode(struct ata_port *ap, struct ata_device *adev)
1003 do_pata_set_dmamode(ap, adev, 1);
1007 static int piix_broken_suspend(void)
1009 static const struct dmi_system_id sysids[] = {
1011 .ident = "TECRA M3",
1013 DMI_MATCH(DMI_SYS_VENDOR, "TOSHIBA"),
1014 DMI_MATCH(DMI_PRODUCT_NAME, "TECRA M3"),
1018 .ident = "TECRA M3",
1020 DMI_MATCH(DMI_SYS_VENDOR, "TOSHIBA"),
1021 DMI_MATCH(DMI_PRODUCT_NAME, "Tecra M3"),
1025 .ident = "TECRA M4",
1027 DMI_MATCH(DMI_SYS_VENDOR, "TOSHIBA"),
1028 DMI_MATCH(DMI_PRODUCT_NAME, "Tecra M4"),
1032 .ident = "TECRA M5",
1034 DMI_MATCH(DMI_SYS_VENDOR, "TOSHIBA"),
1035 DMI_MATCH(DMI_PRODUCT_NAME, "TECRA M5"),
1039 .ident = "TECRA M6",
1041 DMI_MATCH(DMI_SYS_VENDOR, "TOSHIBA"),
1042 DMI_MATCH(DMI_PRODUCT_NAME, "TECRA M6"),
1046 .ident = "TECRA M7",
1048 DMI_MATCH(DMI_SYS_VENDOR, "TOSHIBA"),
1049 DMI_MATCH(DMI_PRODUCT_NAME, "TECRA M7"),
1053 .ident = "TECRA A8",
1055 DMI_MATCH(DMI_SYS_VENDOR, "TOSHIBA"),
1056 DMI_MATCH(DMI_PRODUCT_NAME, "TECRA A8"),
1060 .ident = "Satellite R20",
1062 DMI_MATCH(DMI_SYS_VENDOR, "TOSHIBA"),
1063 DMI_MATCH(DMI_PRODUCT_NAME, "Satellite R20"),
1067 .ident = "Satellite R25",
1069 DMI_MATCH(DMI_SYS_VENDOR, "TOSHIBA"),
1070 DMI_MATCH(DMI_PRODUCT_NAME, "Satellite R25"),
1074 .ident = "Satellite U200",
1076 DMI_MATCH(DMI_SYS_VENDOR, "TOSHIBA"),
1077 DMI_MATCH(DMI_PRODUCT_NAME, "Satellite U200"),
1081 .ident = "Satellite U200",
1083 DMI_MATCH(DMI_SYS_VENDOR, "TOSHIBA"),
1084 DMI_MATCH(DMI_PRODUCT_NAME, "SATELLITE U200"),
1088 .ident = "Satellite Pro U200",
1090 DMI_MATCH(DMI_SYS_VENDOR, "TOSHIBA"),
1091 DMI_MATCH(DMI_PRODUCT_NAME, "SATELLITE PRO U200"),
1095 .ident = "Satellite U205",
1097 DMI_MATCH(DMI_SYS_VENDOR, "TOSHIBA"),
1098 DMI_MATCH(DMI_PRODUCT_NAME, "Satellite U205"),
1102 .ident = "SATELLITE U205",
1104 DMI_MATCH(DMI_SYS_VENDOR, "TOSHIBA"),
1105 DMI_MATCH(DMI_PRODUCT_NAME, "SATELLITE U205"),
1109 .ident = "Portege M500",
1111 DMI_MATCH(DMI_SYS_VENDOR, "TOSHIBA"),
1112 DMI_MATCH(DMI_PRODUCT_NAME, "PORTEGE M500"),
1116 { } /* terminate list */
1118 static const char *oemstrs[] = {
1123 if (dmi_check_system(sysids))
1126 for (i = 0; i < ARRAY_SIZE(oemstrs); i++)
1127 if (dmi_find_device(DMI_DEV_TYPE_OEM_STRING, oemstrs[i], NULL))
1133 static int piix_pci_device_suspend(struct pci_dev *pdev, pm_message_t mesg)
1135 struct ata_host *host = dev_get_drvdata(&pdev->dev);
1136 unsigned long flags;
1139 rc = ata_host_suspend(host, mesg);
1143 /* Some braindamaged ACPI suspend implementations expect the
1144 * controller to be awake on entry; otherwise, it burns cpu
1145 * cycles and power trying to do something to the sleeping
1148 if (piix_broken_suspend() && mesg.event == PM_EVENT_SUSPEND) {
1149 pci_save_state(pdev);
1151 /* mark its power state as "unknown", since we don't
1152 * know if e.g. the BIOS will change its device state
1155 if (pdev->current_state == PCI_D0)
1156 pdev->current_state = PCI_UNKNOWN;
1158 /* tell resume that it's waking up from broken suspend */
1159 spin_lock_irqsave(&host->lock, flags);
1160 host->flags |= PIIX_HOST_BROKEN_SUSPEND;
1161 spin_unlock_irqrestore(&host->lock, flags);
1163 ata_pci_device_do_suspend(pdev, mesg);
1168 static int piix_pci_device_resume(struct pci_dev *pdev)
1170 struct ata_host *host = dev_get_drvdata(&pdev->dev);
1171 unsigned long flags;
1174 if (host->flags & PIIX_HOST_BROKEN_SUSPEND) {
1175 spin_lock_irqsave(&host->lock, flags);
1176 host->flags &= ~PIIX_HOST_BROKEN_SUSPEND;
1177 spin_unlock_irqrestore(&host->lock, flags);
1179 pci_set_power_state(pdev, PCI_D0);
1180 pci_restore_state(pdev);
1182 /* PCI device wasn't disabled during suspend. Use
1183 * pci_reenable_device() to avoid affecting the enable
1186 rc = pci_reenable_device(pdev);
1188 dev_printk(KERN_ERR, &pdev->dev, "failed to enable "
1189 "device after resume (%d)\n", rc);
1191 rc = ata_pci_device_do_resume(pdev);
1194 ata_host_resume(host);
1200 static u8 piix_vmw_bmdma_status(struct ata_port *ap)
1202 return ata_bmdma_status(ap) & ~ATA_DMA_ERR;
1205 #define AHCI_PCI_BAR 5
1206 #define AHCI_GLOBAL_CTL 0x04
1207 #define AHCI_ENABLE (1 << 31)
1208 static int piix_disable_ahci(struct pci_dev *pdev)
1214 /* BUG: pci_enable_device has not yet been called. This
1215 * works because this device is usually set up by BIOS.
1218 if (!pci_resource_start(pdev, AHCI_PCI_BAR) ||
1219 !pci_resource_len(pdev, AHCI_PCI_BAR))
1222 mmio = pci_iomap(pdev, AHCI_PCI_BAR, 64);
1226 tmp = ioread32(mmio + AHCI_GLOBAL_CTL);
1227 if (tmp & AHCI_ENABLE) {
1228 tmp &= ~AHCI_ENABLE;
1229 iowrite32(tmp, mmio + AHCI_GLOBAL_CTL);
1231 tmp = ioread32(mmio + AHCI_GLOBAL_CTL);
1232 if (tmp & AHCI_ENABLE)
1236 pci_iounmap(pdev, mmio);
1241 * piix_check_450nx_errata - Check for problem 450NX setup
1242 * @ata_dev: the PCI device to check
1244 * Check for the present of 450NX errata #19 and errata #25. If
1245 * they are found return an error code so we can turn off DMA
1248 static int __devinit piix_check_450nx_errata(struct pci_dev *ata_dev)
1250 struct pci_dev *pdev = NULL;
1252 int no_piix_dma = 0;
1254 while ((pdev = pci_get_device(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82454NX, pdev)) != NULL) {
1255 /* Look for 450NX PXB. Check for problem configurations
1256 A PCI quirk checks bit 6 already */
1257 pci_read_config_word(pdev, 0x41, &cfg);
1258 /* Only on the original revision: IDE DMA can hang */
1259 if (pdev->revision == 0x00)
1261 /* On all revisions below 5 PXB bus lock must be disabled for IDE */
1262 else if (cfg & (1<<14) && pdev->revision < 5)
1266 dev_printk(KERN_WARNING, &ata_dev->dev, "450NX errata present, disabling IDE DMA.\n");
1267 if (no_piix_dma == 2)
1268 dev_printk(KERN_WARNING, &ata_dev->dev, "A BIOS update may resolve this.\n");
1272 static void __devinit piix_init_pcs(struct pci_dev *pdev,
1273 struct ata_port_info *pinfo,
1274 const struct piix_map_db *map_db)
1278 pci_read_config_word(pdev, ICH5_PCS, &pcs);
1280 new_pcs = pcs | map_db->port_enable;
1282 if (new_pcs != pcs) {
1283 DPRINTK("updating PCS from 0x%x to 0x%x\n", pcs, new_pcs);
1284 pci_write_config_word(pdev, ICH5_PCS, new_pcs);
1289 static void __devinit piix_init_sata_map(struct pci_dev *pdev,
1290 struct ata_port_info *pinfo,
1291 const struct piix_map_db *map_db)
1293 struct piix_host_priv *hpriv = pinfo[0].private_data;
1295 int i, invalid_map = 0;
1298 pci_read_config_byte(pdev, ICH5_PMR, &map_value);
1300 map = map_db->map[map_value & map_db->mask];
1302 dev_printk(KERN_INFO, &pdev->dev, "MAP [");
1303 for (i = 0; i < 4; i++) {
1315 WARN_ON((i & 1) || map[i + 1] != IDE);
1316 pinfo[i / 2] = piix_port_info[ich_pata_100];
1317 pinfo[i / 2].private_data = hpriv;
1323 printk(" P%d", map[i]);
1325 pinfo[i / 2].flags |= ATA_FLAG_SLAVE_POSS;
1332 dev_printk(KERN_ERR, &pdev->dev,
1333 "invalid MAP value %u\n", map_value);
1338 static void piix_iocfg_bit18_quirk(struct pci_dev *pdev)
1340 static const struct dmi_system_id sysids[] = {
1342 /* Clevo M570U sets IOCFG bit 18 if the cdrom
1343 * isn't used to boot the system which
1344 * disables the channel.
1348 DMI_MATCH(DMI_SYS_VENDOR, "Clevo Co."),
1349 DMI_MATCH(DMI_PRODUCT_NAME, "M570U"),
1353 { } /* terminate list */
1357 if (!dmi_check_system(sysids))
1360 /* The datasheet says that bit 18 is NOOP but certain systems
1361 * seem to use it to disable a channel. Clear the bit on the
1364 pci_read_config_dword(pdev, PIIX_IOCFG, &iocfg);
1365 if (iocfg & (1 << 18)) {
1366 dev_printk(KERN_INFO, &pdev->dev,
1367 "applying IOCFG bit18 quirk\n");
1368 iocfg &= ~(1 << 18);
1369 pci_write_config_dword(pdev, PIIX_IOCFG, iocfg);
1374 * piix_init_one - Register PIIX ATA PCI device with kernel services
1375 * @pdev: PCI device to register
1376 * @ent: Entry in piix_pci_tbl matching with @pdev
1378 * Called from kernel PCI layer. We probe for combined mode (sigh),
1379 * and then hand over control to libata, for it to do the rest.
1382 * Inherited from PCI layer (may sleep).
1385 * Zero on success, or -ERRNO value.
1388 static int piix_init_one(struct pci_dev *pdev, const struct pci_device_id *ent)
1390 static int printed_version;
1391 struct device *dev = &pdev->dev;
1392 struct ata_port_info port_info[2];
1393 const struct ata_port_info *ppi[] = { &port_info[0], &port_info[1] };
1394 struct piix_host_priv *hpriv;
1395 unsigned long port_flags;
1397 if (!printed_version++)
1398 dev_printk(KERN_DEBUG, &pdev->dev,
1399 "version " DRV_VERSION "\n");
1401 /* no hotplugging support (FIXME) */
1402 if (!in_module_init)
1405 hpriv = devm_kzalloc(dev, sizeof(*hpriv), GFP_KERNEL);
1409 port_info[0] = piix_port_info[ent->driver_data];
1410 port_info[1] = piix_port_info[ent->driver_data];
1411 port_info[0].private_data = hpriv;
1412 port_info[1].private_data = hpriv;
1414 port_flags = port_info[0].flags;
1416 if (port_flags & PIIX_FLAG_AHCI) {
1418 pci_read_config_byte(pdev, PIIX_SCC, &tmp);
1419 if (tmp == PIIX_AHCI_DEVICE) {
1420 int rc = piix_disable_ahci(pdev);
1426 /* Initialize SATA map */
1427 if (port_flags & ATA_FLAG_SATA) {
1428 piix_init_sata_map(pdev, port_info,
1429 piix_map_db_table[ent->driver_data]);
1430 piix_init_pcs(pdev, port_info,
1431 piix_map_db_table[ent->driver_data]);
1434 /* apply IOCFG bit18 quirk */
1435 piix_iocfg_bit18_quirk(pdev);
1437 /* On ICH5, some BIOSen disable the interrupt using the
1438 * PCI_COMMAND_INTX_DISABLE bit added in PCI 2.3.
1439 * On ICH6, this bit has the same effect, but only when
1440 * MSI is disabled (and it is disabled, as we don't use
1441 * message-signalled interrupts currently).
1443 if (port_flags & PIIX_FLAG_CHECKINTR)
1446 if (piix_check_450nx_errata(pdev)) {
1447 /* This writes into the master table but it does not
1448 really matter for this errata as we will apply it to
1449 all the PIIX devices on the board */
1450 port_info[0].mwdma_mask = 0;
1451 port_info[0].udma_mask = 0;
1452 port_info[1].mwdma_mask = 0;
1453 port_info[1].udma_mask = 0;
1455 return ata_pci_init_one(pdev, ppi);
1458 static int __init piix_init(void)
1462 DPRINTK("pci_register_driver\n");
1463 rc = pci_register_driver(&piix_pci_driver);
1473 static void __exit piix_exit(void)
1475 pci_unregister_driver(&piix_pci_driver);
1478 module_init(piix_init);
1479 module_exit(piix_exit);