2 * ahci.c - AHCI SATA support
4 * Maintained by: Jeff Garzik <jgarzik@pobox.com>
5 * Please ALWAYS copy linux-ide@vger.kernel.org
8 * Copyright 2004-2005 Red Hat, Inc.
11 * This program is free software; you can redistribute it and/or modify
12 * it under the terms of the GNU General Public License as published by
13 * the Free Software Foundation; either version 2, or (at your option)
16 * This program is distributed in the hope that it will be useful,
17 * but WITHOUT ANY WARRANTY; without even the implied warranty of
18 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
19 * GNU General Public License for more details.
21 * You should have received a copy of the GNU General Public License
22 * along with this program; see the file COPYING. If not, write to
23 * the Free Software Foundation, 675 Mass Ave, Cambridge, MA 02139, USA.
26 * libata documentation is available via 'make {ps|pdf}docs',
27 * as Documentation/DocBook/libata.*
29 * AHCI hardware documentation:
30 * http://www.intel.com/technology/serialata/pdf/rev1_0.pdf
31 * http://www.intel.com/technology/serialata/pdf/rev1_1.pdf
35 #include <linux/kernel.h>
36 #include <linux/module.h>
37 #include <linux/pci.h>
38 #include <linux/init.h>
39 #include <linux/blkdev.h>
40 #include <linux/delay.h>
41 #include <linux/interrupt.h>
42 #include <linux/dma-mapping.h>
43 #include <linux/device.h>
44 #include <scsi/scsi_host.h>
45 #include <scsi/scsi_cmnd.h>
46 #include <linux/libata.h>
48 #define DRV_NAME "ahci"
49 #define DRV_VERSION "2.3"
55 AHCI_MAX_SG = 168, /* hardware max is 64K */
56 AHCI_DMA_BOUNDARY = 0xffffffff,
57 AHCI_USE_CLUSTERING = 1,
60 AHCI_CMD_SLOT_SZ = AHCI_MAX_CMDS * AHCI_CMD_SZ,
62 AHCI_CMD_TBL_CDB = 0x40,
63 AHCI_CMD_TBL_HDR_SZ = 0x80,
64 AHCI_CMD_TBL_SZ = AHCI_CMD_TBL_HDR_SZ + (AHCI_MAX_SG * 16),
65 AHCI_CMD_TBL_AR_SZ = AHCI_CMD_TBL_SZ * AHCI_MAX_CMDS,
66 AHCI_PORT_PRIV_DMA_SZ = AHCI_CMD_SLOT_SZ + AHCI_CMD_TBL_AR_SZ +
68 AHCI_IRQ_ON_SG = (1 << 31),
69 AHCI_CMD_ATAPI = (1 << 5),
70 AHCI_CMD_WRITE = (1 << 6),
71 AHCI_CMD_PREFETCH = (1 << 7),
72 AHCI_CMD_RESET = (1 << 8),
73 AHCI_CMD_CLR_BUSY = (1 << 10),
75 RX_FIS_D2H_REG = 0x40, /* offset of D2H Register FIS data */
76 RX_FIS_SDB = 0x58, /* offset of SDB FIS data */
77 RX_FIS_UNK = 0x60, /* offset of Unknown FIS data */
81 board_ahci_vt8251 = 2,
82 board_ahci_ign_iferr = 3,
86 /* global controller registers */
87 HOST_CAP = 0x00, /* host capabilities */
88 HOST_CTL = 0x04, /* global host control */
89 HOST_IRQ_STAT = 0x08, /* interrupt status */
90 HOST_PORTS_IMPL = 0x0c, /* bitmap of implemented ports */
91 HOST_VERSION = 0x10, /* AHCI spec. version compliancy */
94 HOST_RESET = (1 << 0), /* reset controller; self-clear */
95 HOST_IRQ_EN = (1 << 1), /* global IRQ enable */
96 HOST_AHCI_EN = (1 << 31), /* AHCI enabled */
99 HOST_CAP_SSC = (1 << 14), /* Slumber capable */
100 HOST_CAP_CLO = (1 << 24), /* Command List Override support */
101 HOST_CAP_SSS = (1 << 27), /* Staggered Spin-up */
102 HOST_CAP_NCQ = (1 << 30), /* Native Command Queueing */
103 HOST_CAP_64 = (1 << 31), /* PCI DAC (64-bit DMA) support */
105 /* registers for each SATA port */
106 PORT_LST_ADDR = 0x00, /* command list DMA addr */
107 PORT_LST_ADDR_HI = 0x04, /* command list DMA addr hi */
108 PORT_FIS_ADDR = 0x08, /* FIS rx buf addr */
109 PORT_FIS_ADDR_HI = 0x0c, /* FIS rx buf addr hi */
110 PORT_IRQ_STAT = 0x10, /* interrupt status */
111 PORT_IRQ_MASK = 0x14, /* interrupt enable/disable mask */
112 PORT_CMD = 0x18, /* port command */
113 PORT_TFDATA = 0x20, /* taskfile data */
114 PORT_SIG = 0x24, /* device TF signature */
115 PORT_CMD_ISSUE = 0x38, /* command issue */
116 PORT_SCR = 0x28, /* SATA phy register block */
117 PORT_SCR_STAT = 0x28, /* SATA phy register: SStatus */
118 PORT_SCR_CTL = 0x2c, /* SATA phy register: SControl */
119 PORT_SCR_ERR = 0x30, /* SATA phy register: SError */
120 PORT_SCR_ACT = 0x34, /* SATA phy register: SActive */
122 /* PORT_IRQ_{STAT,MASK} bits */
123 PORT_IRQ_COLD_PRES = (1 << 31), /* cold presence detect */
124 PORT_IRQ_TF_ERR = (1 << 30), /* task file error */
125 PORT_IRQ_HBUS_ERR = (1 << 29), /* host bus fatal error */
126 PORT_IRQ_HBUS_DATA_ERR = (1 << 28), /* host bus data error */
127 PORT_IRQ_IF_ERR = (1 << 27), /* interface fatal error */
128 PORT_IRQ_IF_NONFATAL = (1 << 26), /* interface non-fatal error */
129 PORT_IRQ_OVERFLOW = (1 << 24), /* xfer exhausted available S/G */
130 PORT_IRQ_BAD_PMP = (1 << 23), /* incorrect port multiplier */
132 PORT_IRQ_PHYRDY = (1 << 22), /* PhyRdy changed */
133 PORT_IRQ_DEV_ILCK = (1 << 7), /* device interlock */
134 PORT_IRQ_CONNECT = (1 << 6), /* port connect change status */
135 PORT_IRQ_SG_DONE = (1 << 5), /* descriptor processed */
136 PORT_IRQ_UNK_FIS = (1 << 4), /* unknown FIS rx'd */
137 PORT_IRQ_SDB_FIS = (1 << 3), /* Set Device Bits FIS rx'd */
138 PORT_IRQ_DMAS_FIS = (1 << 2), /* DMA Setup FIS rx'd */
139 PORT_IRQ_PIOS_FIS = (1 << 1), /* PIO Setup FIS rx'd */
140 PORT_IRQ_D2H_REG_FIS = (1 << 0), /* D2H Register FIS rx'd */
142 PORT_IRQ_FREEZE = PORT_IRQ_HBUS_ERR |
147 PORT_IRQ_ERROR = PORT_IRQ_FREEZE |
149 PORT_IRQ_HBUS_DATA_ERR,
150 DEF_PORT_IRQ = PORT_IRQ_ERROR | PORT_IRQ_SG_DONE |
151 PORT_IRQ_SDB_FIS | PORT_IRQ_DMAS_FIS |
152 PORT_IRQ_PIOS_FIS | PORT_IRQ_D2H_REG_FIS,
155 PORT_CMD_ATAPI = (1 << 24), /* Device is ATAPI */
156 PORT_CMD_LIST_ON = (1 << 15), /* cmd list DMA engine running */
157 PORT_CMD_FIS_ON = (1 << 14), /* FIS DMA engine running */
158 PORT_CMD_FIS_RX = (1 << 4), /* Enable FIS receive DMA engine */
159 PORT_CMD_CLO = (1 << 3), /* Command list override */
160 PORT_CMD_POWER_ON = (1 << 2), /* Power up device */
161 PORT_CMD_SPIN_UP = (1 << 1), /* Spin up device */
162 PORT_CMD_START = (1 << 0), /* Enable port DMA engine */
164 PORT_CMD_ICC_MASK = (0xf << 28), /* i/f ICC state mask */
165 PORT_CMD_ICC_ACTIVE = (0x1 << 28), /* Put i/f in active state */
166 PORT_CMD_ICC_PARTIAL = (0x2 << 28), /* Put i/f in partial state */
167 PORT_CMD_ICC_SLUMBER = (0x6 << 28), /* Put i/f in slumber state */
170 AHCI_FLAG_NO_NCQ = (1 << 24),
171 AHCI_FLAG_IGN_IRQ_IF_ERR = (1 << 25), /* ignore IRQ_IF_ERR */
172 AHCI_FLAG_HONOR_PI = (1 << 26), /* honor PORTS_IMPL */
173 AHCI_FLAG_IGN_SERR_INTERNAL = (1 << 27), /* ignore SERR_INTERNAL */
174 AHCI_FLAG_32BIT_ONLY = (1 << 28), /* force 32bit */
175 AHCI_FLAG_MV_PATA = (1 << 29), /* PATA port */
176 AHCI_FLAG_NO_MSI = (1 << 30), /* no PCI MSI */
178 AHCI_FLAG_COMMON = ATA_FLAG_SATA | ATA_FLAG_NO_LEGACY |
179 ATA_FLAG_MMIO | ATA_FLAG_PIO_DMA |
180 ATA_FLAG_SKIP_D2H_BSY |
184 struct ahci_cmd_hdr {
199 struct ahci_host_priv {
200 u32 cap; /* cap to use */
201 u32 port_map; /* port map to use */
202 u32 saved_cap; /* saved initial cap */
203 u32 saved_port_map; /* saved initial port_map */
206 struct ahci_port_priv {
207 struct ahci_cmd_hdr *cmd_slot;
208 dma_addr_t cmd_slot_dma;
210 dma_addr_t cmd_tbl_dma;
212 dma_addr_t rx_fis_dma;
213 /* for NCQ spurious interrupt analysis */
214 unsigned int ncq_saw_d2h:1;
215 unsigned int ncq_saw_dmas:1;
216 unsigned int ncq_saw_sdb:1;
219 static int ahci_scr_read(struct ata_port *ap, unsigned int sc_reg, u32 *val);
220 static int ahci_scr_write(struct ata_port *ap, unsigned int sc_reg, u32 val);
221 static int ahci_init_one (struct pci_dev *pdev, const struct pci_device_id *ent);
222 static unsigned int ahci_qc_issue(struct ata_queued_cmd *qc);
223 static void ahci_irq_clear(struct ata_port *ap);
224 static int ahci_port_start(struct ata_port *ap);
225 static void ahci_port_stop(struct ata_port *ap);
226 static void ahci_tf_read(struct ata_port *ap, struct ata_taskfile *tf);
227 static void ahci_qc_prep(struct ata_queued_cmd *qc);
228 static u8 ahci_check_status(struct ata_port *ap);
229 static void ahci_freeze(struct ata_port *ap);
230 static void ahci_thaw(struct ata_port *ap);
231 static void ahci_error_handler(struct ata_port *ap);
232 static void ahci_vt8251_error_handler(struct ata_port *ap);
233 static void ahci_post_internal_cmd(struct ata_queued_cmd *qc);
234 static int ahci_port_resume(struct ata_port *ap);
235 static unsigned int ahci_fill_sg(struct ata_queued_cmd *qc, void *cmd_tbl);
236 static void ahci_fill_cmd_slot(struct ahci_port_priv *pp, unsigned int tag,
239 static int ahci_port_suspend(struct ata_port *ap, pm_message_t mesg);
240 static int ahci_pci_device_suspend(struct pci_dev *pdev, pm_message_t mesg);
241 static int ahci_pci_device_resume(struct pci_dev *pdev);
244 static struct scsi_host_template ahci_sht = {
245 .module = THIS_MODULE,
247 .ioctl = ata_scsi_ioctl,
248 .queuecommand = ata_scsi_queuecmd,
249 .change_queue_depth = ata_scsi_change_queue_depth,
250 .can_queue = AHCI_MAX_CMDS - 1,
251 .this_id = ATA_SHT_THIS_ID,
252 .sg_tablesize = AHCI_MAX_SG,
253 .cmd_per_lun = ATA_SHT_CMD_PER_LUN,
254 .emulated = ATA_SHT_EMULATED,
255 .use_clustering = AHCI_USE_CLUSTERING,
256 .proc_name = DRV_NAME,
257 .dma_boundary = AHCI_DMA_BOUNDARY,
258 .slave_configure = ata_scsi_slave_config,
259 .slave_destroy = ata_scsi_slave_destroy,
260 .bios_param = ata_std_bios_param,
263 static const struct ata_port_operations ahci_ops = {
264 .port_disable = ata_port_disable,
266 .check_status = ahci_check_status,
267 .check_altstatus = ahci_check_status,
268 .dev_select = ata_noop_dev_select,
270 .tf_read = ahci_tf_read,
272 .qc_prep = ahci_qc_prep,
273 .qc_issue = ahci_qc_issue,
275 .irq_clear = ahci_irq_clear,
276 .irq_on = ata_dummy_irq_on,
277 .irq_ack = ata_dummy_irq_ack,
279 .scr_read = ahci_scr_read,
280 .scr_write = ahci_scr_write,
282 .freeze = ahci_freeze,
285 .error_handler = ahci_error_handler,
286 .post_internal_cmd = ahci_post_internal_cmd,
289 .port_suspend = ahci_port_suspend,
290 .port_resume = ahci_port_resume,
293 .port_start = ahci_port_start,
294 .port_stop = ahci_port_stop,
297 static const struct ata_port_operations ahci_vt8251_ops = {
298 .port_disable = ata_port_disable,
300 .check_status = ahci_check_status,
301 .check_altstatus = ahci_check_status,
302 .dev_select = ata_noop_dev_select,
304 .tf_read = ahci_tf_read,
306 .qc_prep = ahci_qc_prep,
307 .qc_issue = ahci_qc_issue,
309 .irq_clear = ahci_irq_clear,
310 .irq_on = ata_dummy_irq_on,
311 .irq_ack = ata_dummy_irq_ack,
313 .scr_read = ahci_scr_read,
314 .scr_write = ahci_scr_write,
316 .freeze = ahci_freeze,
319 .error_handler = ahci_vt8251_error_handler,
320 .post_internal_cmd = ahci_post_internal_cmd,
323 .port_suspend = ahci_port_suspend,
324 .port_resume = ahci_port_resume,
327 .port_start = ahci_port_start,
328 .port_stop = ahci_port_stop,
331 static const struct ata_port_info ahci_port_info[] = {
334 .flags = AHCI_FLAG_COMMON,
335 .pio_mask = 0x1f, /* pio0-4 */
336 .udma_mask = ATA_UDMA6,
337 .port_ops = &ahci_ops,
341 .flags = AHCI_FLAG_COMMON | AHCI_FLAG_HONOR_PI,
342 .pio_mask = 0x1f, /* pio0-4 */
343 .udma_mask = ATA_UDMA6,
344 .port_ops = &ahci_ops,
346 /* board_ahci_vt8251 */
348 .flags = AHCI_FLAG_COMMON | ATA_FLAG_HRST_TO_RESUME |
350 .pio_mask = 0x1f, /* pio0-4 */
351 .udma_mask = ATA_UDMA6,
352 .port_ops = &ahci_vt8251_ops,
354 /* board_ahci_ign_iferr */
356 .flags = AHCI_FLAG_COMMON | AHCI_FLAG_IGN_IRQ_IF_ERR,
357 .pio_mask = 0x1f, /* pio0-4 */
358 .udma_mask = ATA_UDMA6,
359 .port_ops = &ahci_ops,
361 /* board_ahci_sb600 */
363 .flags = AHCI_FLAG_COMMON |
364 AHCI_FLAG_IGN_SERR_INTERNAL |
365 AHCI_FLAG_32BIT_ONLY,
366 .pio_mask = 0x1f, /* pio0-4 */
367 .udma_mask = ATA_UDMA6,
368 .port_ops = &ahci_ops,
373 .flags = ATA_FLAG_SATA | ATA_FLAG_NO_LEGACY |
374 ATA_FLAG_MMIO | ATA_FLAG_PIO_DMA |
375 ATA_FLAG_SKIP_D2H_BSY | AHCI_FLAG_HONOR_PI |
376 AHCI_FLAG_NO_NCQ | AHCI_FLAG_NO_MSI |
378 .pio_mask = 0x1f, /* pio0-4 */
379 .udma_mask = ATA_UDMA6,
380 .port_ops = &ahci_ops,
384 static const struct pci_device_id ahci_pci_tbl[] = {
386 { PCI_VDEVICE(INTEL, 0x2652), board_ahci }, /* ICH6 */
387 { PCI_VDEVICE(INTEL, 0x2653), board_ahci }, /* ICH6M */
388 { PCI_VDEVICE(INTEL, 0x27c1), board_ahci }, /* ICH7 */
389 { PCI_VDEVICE(INTEL, 0x27c5), board_ahci }, /* ICH7M */
390 { PCI_VDEVICE(INTEL, 0x27c3), board_ahci }, /* ICH7R */
391 { PCI_VDEVICE(AL, 0x5288), board_ahci_ign_iferr }, /* ULi M5288 */
392 { PCI_VDEVICE(INTEL, 0x2681), board_ahci }, /* ESB2 */
393 { PCI_VDEVICE(INTEL, 0x2682), board_ahci }, /* ESB2 */
394 { PCI_VDEVICE(INTEL, 0x2683), board_ahci }, /* ESB2 */
395 { PCI_VDEVICE(INTEL, 0x27c6), board_ahci }, /* ICH7-M DH */
396 { PCI_VDEVICE(INTEL, 0x2821), board_ahci_pi }, /* ICH8 */
397 { PCI_VDEVICE(INTEL, 0x2822), board_ahci_pi }, /* ICH8 */
398 { PCI_VDEVICE(INTEL, 0x2824), board_ahci_pi }, /* ICH8 */
399 { PCI_VDEVICE(INTEL, 0x2829), board_ahci_pi }, /* ICH8M */
400 { PCI_VDEVICE(INTEL, 0x282a), board_ahci_pi }, /* ICH8M */
401 { PCI_VDEVICE(INTEL, 0x2922), board_ahci_pi }, /* ICH9 */
402 { PCI_VDEVICE(INTEL, 0x2923), board_ahci_pi }, /* ICH9 */
403 { PCI_VDEVICE(INTEL, 0x2924), board_ahci_pi }, /* ICH9 */
404 { PCI_VDEVICE(INTEL, 0x2925), board_ahci_pi }, /* ICH9 */
405 { PCI_VDEVICE(INTEL, 0x2927), board_ahci_pi }, /* ICH9 */
406 { PCI_VDEVICE(INTEL, 0x2929), board_ahci_pi }, /* ICH9M */
407 { PCI_VDEVICE(INTEL, 0x292a), board_ahci_pi }, /* ICH9M */
408 { PCI_VDEVICE(INTEL, 0x292b), board_ahci_pi }, /* ICH9M */
409 { PCI_VDEVICE(INTEL, 0x292c), board_ahci_pi }, /* ICH9M */
410 { PCI_VDEVICE(INTEL, 0x292f), board_ahci_pi }, /* ICH9M */
411 { PCI_VDEVICE(INTEL, 0x294d), board_ahci_pi }, /* ICH9 */
412 { PCI_VDEVICE(INTEL, 0x294e), board_ahci_pi }, /* ICH9M */
414 /* JMicron 360/1/3/5/6, match class to avoid IDE function */
415 { PCI_VENDOR_ID_JMICRON, PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID,
416 PCI_CLASS_STORAGE_SATA_AHCI, 0xffffff, board_ahci_ign_iferr },
419 { PCI_VDEVICE(ATI, 0x4380), board_ahci_sb600 }, /* ATI SB600 */
420 { PCI_VDEVICE(ATI, 0x4390), board_ahci_sb600 }, /* ATI SB700 */
423 { PCI_VDEVICE(VIA, 0x3349), board_ahci_vt8251 }, /* VIA VT8251 */
424 { PCI_VDEVICE(VIA, 0x6287), board_ahci_vt8251 }, /* VIA VT8251 */
427 { PCI_VDEVICE(NVIDIA, 0x044c), board_ahci }, /* MCP65 */
428 { PCI_VDEVICE(NVIDIA, 0x044d), board_ahci }, /* MCP65 */
429 { PCI_VDEVICE(NVIDIA, 0x044e), board_ahci }, /* MCP65 */
430 { PCI_VDEVICE(NVIDIA, 0x044f), board_ahci }, /* MCP65 */
431 { PCI_VDEVICE(NVIDIA, 0x045c), board_ahci }, /* MCP65 */
432 { PCI_VDEVICE(NVIDIA, 0x045d), board_ahci }, /* MCP65 */
433 { PCI_VDEVICE(NVIDIA, 0x045e), board_ahci }, /* MCP65 */
434 { PCI_VDEVICE(NVIDIA, 0x045f), board_ahci }, /* MCP65 */
435 { PCI_VDEVICE(NVIDIA, 0x0550), board_ahci }, /* MCP67 */
436 { PCI_VDEVICE(NVIDIA, 0x0551), board_ahci }, /* MCP67 */
437 { PCI_VDEVICE(NVIDIA, 0x0552), board_ahci }, /* MCP67 */
438 { PCI_VDEVICE(NVIDIA, 0x0553), board_ahci }, /* MCP67 */
439 { PCI_VDEVICE(NVIDIA, 0x0554), board_ahci }, /* MCP67 */
440 { PCI_VDEVICE(NVIDIA, 0x0555), board_ahci }, /* MCP67 */
441 { PCI_VDEVICE(NVIDIA, 0x0556), board_ahci }, /* MCP67 */
442 { PCI_VDEVICE(NVIDIA, 0x0557), board_ahci }, /* MCP67 */
443 { PCI_VDEVICE(NVIDIA, 0x0558), board_ahci }, /* MCP67 */
444 { PCI_VDEVICE(NVIDIA, 0x0559), board_ahci }, /* MCP67 */
445 { PCI_VDEVICE(NVIDIA, 0x055a), board_ahci }, /* MCP67 */
446 { PCI_VDEVICE(NVIDIA, 0x055b), board_ahci }, /* MCP67 */
447 { PCI_VDEVICE(NVIDIA, 0x07f0), board_ahci }, /* MCP73 */
448 { PCI_VDEVICE(NVIDIA, 0x07f1), board_ahci }, /* MCP73 */
449 { PCI_VDEVICE(NVIDIA, 0x07f2), board_ahci }, /* MCP73 */
450 { PCI_VDEVICE(NVIDIA, 0x07f3), board_ahci }, /* MCP73 */
451 { PCI_VDEVICE(NVIDIA, 0x07f4), board_ahci }, /* MCP73 */
452 { PCI_VDEVICE(NVIDIA, 0x07f5), board_ahci }, /* MCP73 */
453 { PCI_VDEVICE(NVIDIA, 0x07f6), board_ahci }, /* MCP73 */
454 { PCI_VDEVICE(NVIDIA, 0x07f7), board_ahci }, /* MCP73 */
455 { PCI_VDEVICE(NVIDIA, 0x07f8), board_ahci }, /* MCP73 */
456 { PCI_VDEVICE(NVIDIA, 0x07f9), board_ahci }, /* MCP73 */
457 { PCI_VDEVICE(NVIDIA, 0x07fa), board_ahci }, /* MCP73 */
458 { PCI_VDEVICE(NVIDIA, 0x07fb), board_ahci }, /* MCP73 */
459 { PCI_VDEVICE(NVIDIA, 0x0ad0), board_ahci }, /* MCP77 */
460 { PCI_VDEVICE(NVIDIA, 0x0ad1), board_ahci }, /* MCP77 */
461 { PCI_VDEVICE(NVIDIA, 0x0ad2), board_ahci }, /* MCP77 */
462 { PCI_VDEVICE(NVIDIA, 0x0ad3), board_ahci }, /* MCP77 */
463 { PCI_VDEVICE(NVIDIA, 0x0ad4), board_ahci }, /* MCP77 */
464 { PCI_VDEVICE(NVIDIA, 0x0ad5), board_ahci }, /* MCP77 */
465 { PCI_VDEVICE(NVIDIA, 0x0ad6), board_ahci }, /* MCP77 */
466 { PCI_VDEVICE(NVIDIA, 0x0ad7), board_ahci }, /* MCP77 */
467 { PCI_VDEVICE(NVIDIA, 0x0ad8), board_ahci }, /* MCP77 */
468 { PCI_VDEVICE(NVIDIA, 0x0ad9), board_ahci }, /* MCP77 */
469 { PCI_VDEVICE(NVIDIA, 0x0ada), board_ahci }, /* MCP77 */
470 { PCI_VDEVICE(NVIDIA, 0x0adb), board_ahci }, /* MCP77 */
473 { PCI_VDEVICE(SI, 0x1184), board_ahci }, /* SiS 966 */
474 { PCI_VDEVICE(SI, 0x1185), board_ahci }, /* SiS 966 */
475 { PCI_VDEVICE(SI, 0x0186), board_ahci }, /* SiS 968 */
478 { PCI_VDEVICE(MARVELL, 0x6145), board_ahci_mv }, /* 6145 */
480 /* Generic, PCI class code for AHCI */
481 { PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID,
482 PCI_CLASS_STORAGE_SATA_AHCI, 0xffffff, board_ahci },
484 { } /* terminate list */
488 static struct pci_driver ahci_pci_driver = {
490 .id_table = ahci_pci_tbl,
491 .probe = ahci_init_one,
492 .remove = ata_pci_remove_one,
494 .suspend = ahci_pci_device_suspend,
495 .resume = ahci_pci_device_resume,
500 static inline int ahci_nr_ports(u32 cap)
502 return (cap & 0x1f) + 1;
505 static inline void __iomem *__ahci_port_base(struct ata_host *host,
506 unsigned int port_no)
508 void __iomem *mmio = host->iomap[AHCI_PCI_BAR];
510 return mmio + 0x100 + (port_no * 0x80);
513 static inline void __iomem *ahci_port_base(struct ata_port *ap)
515 return __ahci_port_base(ap->host, ap->port_no);
519 * ahci_save_initial_config - Save and fixup initial config values
520 * @pdev: target PCI device
521 * @pi: associated ATA port info
522 * @hpriv: host private area to store config values
524 * Some registers containing configuration info might be setup by
525 * BIOS and might be cleared on reset. This function saves the
526 * initial values of those registers into @hpriv such that they
527 * can be restored after controller reset.
529 * If inconsistent, config values are fixed up by this function.
534 static void ahci_save_initial_config(struct pci_dev *pdev,
535 const struct ata_port_info *pi,
536 struct ahci_host_priv *hpriv)
538 void __iomem *mmio = pcim_iomap_table(pdev)[AHCI_PCI_BAR];
542 /* Values prefixed with saved_ are written back to host after
543 * reset. Values without are used for driver operation.
545 hpriv->saved_cap = cap = readl(mmio + HOST_CAP);
546 hpriv->saved_port_map = port_map = readl(mmio + HOST_PORTS_IMPL);
548 /* some chips lie about 64bit support */
549 if ((cap & HOST_CAP_64) && (pi->flags & AHCI_FLAG_32BIT_ONLY)) {
550 dev_printk(KERN_INFO, &pdev->dev,
551 "controller can't do 64bit DMA, forcing 32bit\n");
555 /* fixup zero port_map */
557 port_map = (1 << ahci_nr_ports(cap)) - 1;
558 dev_printk(KERN_WARNING, &pdev->dev,
559 "PORTS_IMPL is zero, forcing 0x%x\n", port_map);
561 /* write the fixed up value to the PI register */
562 hpriv->saved_port_map = port_map;
566 * Temporary Marvell 6145 hack: PATA port presence
567 * is asserted through the standard AHCI port
568 * presence register, as bit 4 (counting from 0)
570 if (pi->flags & AHCI_FLAG_MV_PATA) {
571 dev_printk(KERN_ERR, &pdev->dev,
572 "MV_AHCI HACK: port_map %x -> %x\n",
574 hpriv->port_map & 0xf);
579 /* cross check port_map and cap.n_ports */
580 if (pi->flags & AHCI_FLAG_HONOR_PI) {
581 u32 tmp_port_map = port_map;
582 int n_ports = ahci_nr_ports(cap);
584 for (i = 0; i < AHCI_MAX_PORTS && n_ports; i++) {
585 if (tmp_port_map & (1 << i)) {
587 tmp_port_map &= ~(1 << i);
591 /* Whine if inconsistent. No need to update cap.
592 * port_map is used to determine number of ports.
594 if (n_ports || tmp_port_map)
595 dev_printk(KERN_WARNING, &pdev->dev,
596 "nr_ports (%u) and implemented port map "
597 "(0x%x) don't match\n",
598 ahci_nr_ports(cap), port_map);
600 /* fabricate port_map from cap.nr_ports */
601 port_map = (1 << ahci_nr_ports(cap)) - 1;
604 /* record values to use during operation */
606 hpriv->port_map = port_map;
610 * ahci_restore_initial_config - Restore initial config
611 * @host: target ATA host
613 * Restore initial config stored by ahci_save_initial_config().
618 static void ahci_restore_initial_config(struct ata_host *host)
620 struct ahci_host_priv *hpriv = host->private_data;
621 void __iomem *mmio = host->iomap[AHCI_PCI_BAR];
623 writel(hpriv->saved_cap, mmio + HOST_CAP);
624 writel(hpriv->saved_port_map, mmio + HOST_PORTS_IMPL);
625 (void) readl(mmio + HOST_PORTS_IMPL); /* flush */
628 static int ahci_scr_read(struct ata_port *ap, unsigned int sc_reg_in, u32 *val)
633 case SCR_STATUS: sc_reg = 0; break;
634 case SCR_CONTROL: sc_reg = 1; break;
635 case SCR_ERROR: sc_reg = 2; break;
636 case SCR_ACTIVE: sc_reg = 3; break;
641 *val = readl(ap->ioaddr.scr_addr + (sc_reg * 4));
646 static int ahci_scr_write(struct ata_port *ap, unsigned int sc_reg_in, u32 val)
651 case SCR_STATUS: sc_reg = 0; break;
652 case SCR_CONTROL: sc_reg = 1; break;
653 case SCR_ERROR: sc_reg = 2; break;
654 case SCR_ACTIVE: sc_reg = 3; break;
659 writel(val, ap->ioaddr.scr_addr + (sc_reg * 4));
663 static void ahci_start_engine(struct ata_port *ap)
665 void __iomem *port_mmio = ahci_port_base(ap);
669 tmp = readl(port_mmio + PORT_CMD);
670 tmp |= PORT_CMD_START;
671 writel(tmp, port_mmio + PORT_CMD);
672 readl(port_mmio + PORT_CMD); /* flush */
675 static int ahci_stop_engine(struct ata_port *ap)
677 void __iomem *port_mmio = ahci_port_base(ap);
680 tmp = readl(port_mmio + PORT_CMD);
682 /* check if the HBA is idle */
683 if ((tmp & (PORT_CMD_START | PORT_CMD_LIST_ON)) == 0)
686 /* setting HBA to idle */
687 tmp &= ~PORT_CMD_START;
688 writel(tmp, port_mmio + PORT_CMD);
690 /* wait for engine to stop. This could be as long as 500 msec */
691 tmp = ata_wait_register(port_mmio + PORT_CMD,
692 PORT_CMD_LIST_ON, PORT_CMD_LIST_ON, 1, 500);
693 if (tmp & PORT_CMD_LIST_ON)
699 static void ahci_start_fis_rx(struct ata_port *ap)
701 void __iomem *port_mmio = ahci_port_base(ap);
702 struct ahci_host_priv *hpriv = ap->host->private_data;
703 struct ahci_port_priv *pp = ap->private_data;
706 /* set FIS registers */
707 if (hpriv->cap & HOST_CAP_64)
708 writel((pp->cmd_slot_dma >> 16) >> 16,
709 port_mmio + PORT_LST_ADDR_HI);
710 writel(pp->cmd_slot_dma & 0xffffffff, port_mmio + PORT_LST_ADDR);
712 if (hpriv->cap & HOST_CAP_64)
713 writel((pp->rx_fis_dma >> 16) >> 16,
714 port_mmio + PORT_FIS_ADDR_HI);
715 writel(pp->rx_fis_dma & 0xffffffff, port_mmio + PORT_FIS_ADDR);
717 /* enable FIS reception */
718 tmp = readl(port_mmio + PORT_CMD);
719 tmp |= PORT_CMD_FIS_RX;
720 writel(tmp, port_mmio + PORT_CMD);
723 readl(port_mmio + PORT_CMD);
726 static int ahci_stop_fis_rx(struct ata_port *ap)
728 void __iomem *port_mmio = ahci_port_base(ap);
731 /* disable FIS reception */
732 tmp = readl(port_mmio + PORT_CMD);
733 tmp &= ~PORT_CMD_FIS_RX;
734 writel(tmp, port_mmio + PORT_CMD);
736 /* wait for completion, spec says 500ms, give it 1000 */
737 tmp = ata_wait_register(port_mmio + PORT_CMD, PORT_CMD_FIS_ON,
738 PORT_CMD_FIS_ON, 10, 1000);
739 if (tmp & PORT_CMD_FIS_ON)
745 static void ahci_power_up(struct ata_port *ap)
747 struct ahci_host_priv *hpriv = ap->host->private_data;
748 void __iomem *port_mmio = ahci_port_base(ap);
751 cmd = readl(port_mmio + PORT_CMD) & ~PORT_CMD_ICC_MASK;
754 if (hpriv->cap & HOST_CAP_SSS) {
755 cmd |= PORT_CMD_SPIN_UP;
756 writel(cmd, port_mmio + PORT_CMD);
760 writel(cmd | PORT_CMD_ICC_ACTIVE, port_mmio + PORT_CMD);
764 static void ahci_power_down(struct ata_port *ap)
766 struct ahci_host_priv *hpriv = ap->host->private_data;
767 void __iomem *port_mmio = ahci_port_base(ap);
770 if (!(hpriv->cap & HOST_CAP_SSS))
773 /* put device into listen mode, first set PxSCTL.DET to 0 */
774 scontrol = readl(port_mmio + PORT_SCR_CTL);
776 writel(scontrol, port_mmio + PORT_SCR_CTL);
778 /* then set PxCMD.SUD to 0 */
779 cmd = readl(port_mmio + PORT_CMD) & ~PORT_CMD_ICC_MASK;
780 cmd &= ~PORT_CMD_SPIN_UP;
781 writel(cmd, port_mmio + PORT_CMD);
785 static void ahci_start_port(struct ata_port *ap)
787 /* enable FIS reception */
788 ahci_start_fis_rx(ap);
791 ahci_start_engine(ap);
794 static int ahci_deinit_port(struct ata_port *ap, const char **emsg)
799 rc = ahci_stop_engine(ap);
801 *emsg = "failed to stop engine";
805 /* disable FIS reception */
806 rc = ahci_stop_fis_rx(ap);
808 *emsg = "failed stop FIS RX";
815 static int ahci_reset_controller(struct ata_host *host)
817 struct pci_dev *pdev = to_pci_dev(host->dev);
818 void __iomem *mmio = host->iomap[AHCI_PCI_BAR];
821 /* global controller reset */
822 tmp = readl(mmio + HOST_CTL);
823 if ((tmp & HOST_RESET) == 0) {
824 writel(tmp | HOST_RESET, mmio + HOST_CTL);
825 readl(mmio + HOST_CTL); /* flush */
828 /* reset must complete within 1 second, or
829 * the hardware should be considered fried.
833 tmp = readl(mmio + HOST_CTL);
834 if (tmp & HOST_RESET) {
835 dev_printk(KERN_ERR, host->dev,
836 "controller reset failed (0x%x)\n", tmp);
840 /* turn on AHCI mode */
841 writel(HOST_AHCI_EN, mmio + HOST_CTL);
842 (void) readl(mmio + HOST_CTL); /* flush */
844 /* some registers might be cleared on reset. restore initial values */
845 ahci_restore_initial_config(host);
847 if (pdev->vendor == PCI_VENDOR_ID_INTEL) {
851 pci_read_config_word(pdev, 0x92, &tmp16);
853 pci_write_config_word(pdev, 0x92, tmp16);
859 static void ahci_port_init(struct pci_dev *pdev, struct ata_port *ap,
860 int port_no, void __iomem *mmio,
861 void __iomem *port_mmio)
863 const char *emsg = NULL;
867 /* make sure port is not active */
868 rc = ahci_deinit_port(ap, &emsg);
870 dev_printk(KERN_WARNING, &pdev->dev,
871 "%s (%d)\n", emsg, rc);
874 tmp = readl(port_mmio + PORT_SCR_ERR);
875 VPRINTK("PORT_SCR_ERR 0x%x\n", tmp);
876 writel(tmp, port_mmio + PORT_SCR_ERR);
879 tmp = readl(port_mmio + PORT_IRQ_STAT);
880 VPRINTK("PORT_IRQ_STAT 0x%x\n", tmp);
882 writel(tmp, port_mmio + PORT_IRQ_STAT);
884 writel(1 << port_no, mmio + HOST_IRQ_STAT);
887 static void ahci_init_controller(struct ata_host *host)
889 struct pci_dev *pdev = to_pci_dev(host->dev);
890 void __iomem *mmio = host->iomap[AHCI_PCI_BAR];
892 void __iomem *port_mmio;
895 if (host->ports[0]->flags & AHCI_FLAG_MV_PATA) {
896 port_mmio = __ahci_port_base(host, 4);
898 writel(0, port_mmio + PORT_IRQ_MASK);
901 tmp = readl(port_mmio + PORT_IRQ_STAT);
902 VPRINTK("PORT_IRQ_STAT 0x%x\n", tmp);
904 writel(tmp, port_mmio + PORT_IRQ_STAT);
907 for (i = 0; i < host->n_ports; i++) {
908 struct ata_port *ap = host->ports[i];
910 port_mmio = ahci_port_base(ap);
911 if (ata_port_is_dummy(ap))
914 ahci_port_init(pdev, ap, i, mmio, port_mmio);
917 tmp = readl(mmio + HOST_CTL);
918 VPRINTK("HOST_CTL 0x%x\n", tmp);
919 writel(tmp | HOST_IRQ_EN, mmio + HOST_CTL);
920 tmp = readl(mmio + HOST_CTL);
921 VPRINTK("HOST_CTL 0x%x\n", tmp);
924 static unsigned int ahci_dev_classify(struct ata_port *ap)
926 void __iomem *port_mmio = ahci_port_base(ap);
927 struct ata_taskfile tf;
930 tmp = readl(port_mmio + PORT_SIG);
931 tf.lbah = (tmp >> 24) & 0xff;
932 tf.lbam = (tmp >> 16) & 0xff;
933 tf.lbal = (tmp >> 8) & 0xff;
934 tf.nsect = (tmp) & 0xff;
936 return ata_dev_classify(&tf);
939 static void ahci_fill_cmd_slot(struct ahci_port_priv *pp, unsigned int tag,
942 dma_addr_t cmd_tbl_dma;
944 cmd_tbl_dma = pp->cmd_tbl_dma + tag * AHCI_CMD_TBL_SZ;
946 pp->cmd_slot[tag].opts = cpu_to_le32(opts);
947 pp->cmd_slot[tag].status = 0;
948 pp->cmd_slot[tag].tbl_addr = cpu_to_le32(cmd_tbl_dma & 0xffffffff);
949 pp->cmd_slot[tag].tbl_addr_hi = cpu_to_le32((cmd_tbl_dma >> 16) >> 16);
952 static int ahci_kick_engine(struct ata_port *ap, int force_restart)
954 void __iomem *port_mmio = ap->ioaddr.cmd_addr;
955 struct ahci_host_priv *hpriv = ap->host->private_data;
959 /* do we need to kick the port? */
960 busy = ahci_check_status(ap) & (ATA_BUSY | ATA_DRQ);
961 if (!busy && !force_restart)
965 rc = ahci_stop_engine(ap);
969 /* need to do CLO? */
975 if (!(hpriv->cap & HOST_CAP_CLO)) {
981 tmp = readl(port_mmio + PORT_CMD);
983 writel(tmp, port_mmio + PORT_CMD);
986 tmp = ata_wait_register(port_mmio + PORT_CMD,
987 PORT_CMD_CLO, PORT_CMD_CLO, 1, 500);
988 if (tmp & PORT_CMD_CLO)
993 ahci_start_engine(ap);
997 static int ahci_exec_polled_cmd(struct ata_port *ap, int pmp,
998 struct ata_taskfile *tf, int is_cmd, u16 flags,
999 unsigned long timeout_msec)
1001 const u32 cmd_fis_len = 5; /* five dwords */
1002 struct ahci_port_priv *pp = ap->private_data;
1003 void __iomem *port_mmio = ahci_port_base(ap);
1004 u8 *fis = pp->cmd_tbl;
1007 /* prep the command */
1008 ata_tf_to_fis(tf, pmp, is_cmd, fis);
1009 ahci_fill_cmd_slot(pp, 0, cmd_fis_len | flags | (pmp << 12));
1012 writel(1, port_mmio + PORT_CMD_ISSUE);
1015 tmp = ata_wait_register(port_mmio + PORT_CMD_ISSUE, 0x1, 0x1,
1018 ahci_kick_engine(ap, 1);
1022 readl(port_mmio + PORT_CMD_ISSUE); /* flush */
1027 static int ahci_do_softreset(struct ata_port *ap, unsigned int *class,
1028 int pmp, unsigned long deadline)
1030 const char *reason = NULL;
1031 unsigned long now, msecs;
1032 struct ata_taskfile tf;
1037 if (ata_port_offline(ap)) {
1038 DPRINTK("PHY reports no device\n");
1039 *class = ATA_DEV_NONE;
1043 /* prepare for SRST (AHCI-1.1 10.4.1) */
1044 rc = ahci_kick_engine(ap, 1);
1046 ata_port_printk(ap, KERN_WARNING,
1047 "failed to reset engine (errno=%d)", rc);
1049 ata_tf_init(ap->device, &tf);
1051 /* issue the first D2H Register FIS */
1054 if (time_after(now, deadline))
1055 msecs = jiffies_to_msecs(deadline - now);
1058 if (ahci_exec_polled_cmd(ap, pmp, &tf, 0,
1059 AHCI_CMD_RESET | AHCI_CMD_CLR_BUSY, msecs)) {
1061 reason = "1st FIS failed";
1065 /* spec says at least 5us, but be generous and sleep for 1ms */
1068 /* issue the second D2H Register FIS */
1069 tf.ctl &= ~ATA_SRST;
1070 ahci_exec_polled_cmd(ap, pmp, &tf, 0, 0, 0);
1072 /* spec mandates ">= 2ms" before checking status.
1073 * We wait 150ms, because that was the magic delay used for
1074 * ATAPI devices in Hale Landis's ATADRVR, for the period of time
1075 * between when the ATA command register is written, and then
1076 * status is checked. Because waiting for "a while" before
1077 * checking status is fine, post SRST, we perform this magic
1078 * delay here as well.
1082 rc = ata_wait_ready(ap, deadline);
1083 /* link occupied, -ENODEV too is an error */
1085 reason = "device not ready";
1088 *class = ahci_dev_classify(ap);
1090 DPRINTK("EXIT, class=%u\n", *class);
1094 ata_port_printk(ap, KERN_ERR, "softreset failed (%s)\n", reason);
1098 static int ahci_softreset(struct ata_port *ap, unsigned int *class,
1099 unsigned long deadline)
1101 return ahci_do_softreset(ap, class, 0, deadline);
1104 static int ahci_hardreset(struct ata_port *ap, unsigned int *class,
1105 unsigned long deadline)
1107 struct ahci_port_priv *pp = ap->private_data;
1108 u8 *d2h_fis = pp->rx_fis + RX_FIS_D2H_REG;
1109 struct ata_taskfile tf;
1114 ahci_stop_engine(ap);
1116 /* clear D2H reception area to properly wait for D2H FIS */
1117 ata_tf_init(ap->device, &tf);
1119 ata_tf_to_fis(&tf, 0, 0, d2h_fis);
1121 rc = sata_std_hardreset(ap, class, deadline);
1123 ahci_start_engine(ap);
1125 if (rc == 0 && ata_port_online(ap))
1126 *class = ahci_dev_classify(ap);
1127 if (*class == ATA_DEV_UNKNOWN)
1128 *class = ATA_DEV_NONE;
1130 DPRINTK("EXIT, rc=%d, class=%u\n", rc, *class);
1134 static int ahci_vt8251_hardreset(struct ata_port *ap, unsigned int *class,
1135 unsigned long deadline)
1142 ahci_stop_engine(ap);
1144 rc = sata_port_hardreset(ap, sata_ehc_deb_timing(&ap->eh_context),
1147 /* vt8251 needs SError cleared for the port to operate */
1148 ahci_scr_read(ap, SCR_ERROR, &serror);
1149 ahci_scr_write(ap, SCR_ERROR, serror);
1151 ahci_start_engine(ap);
1153 DPRINTK("EXIT, rc=%d, class=%u\n", rc, *class);
1155 /* vt8251 doesn't clear BSY on signature FIS reception,
1156 * request follow-up softreset.
1158 return rc ?: -EAGAIN;
1161 static void ahci_postreset(struct ata_port *ap, unsigned int *class)
1163 void __iomem *port_mmio = ahci_port_base(ap);
1166 ata_std_postreset(ap, class);
1168 /* Make sure port's ATAPI bit is set appropriately */
1169 new_tmp = tmp = readl(port_mmio + PORT_CMD);
1170 if (*class == ATA_DEV_ATAPI)
1171 new_tmp |= PORT_CMD_ATAPI;
1173 new_tmp &= ~PORT_CMD_ATAPI;
1174 if (new_tmp != tmp) {
1175 writel(new_tmp, port_mmio + PORT_CMD);
1176 readl(port_mmio + PORT_CMD); /* flush */
1180 static u8 ahci_check_status(struct ata_port *ap)
1182 void __iomem *mmio = ap->ioaddr.cmd_addr;
1184 return readl(mmio + PORT_TFDATA) & 0xFF;
1187 static void ahci_tf_read(struct ata_port *ap, struct ata_taskfile *tf)
1189 struct ahci_port_priv *pp = ap->private_data;
1190 u8 *d2h_fis = pp->rx_fis + RX_FIS_D2H_REG;
1192 ata_tf_from_fis(d2h_fis, tf);
1195 static unsigned int ahci_fill_sg(struct ata_queued_cmd *qc, void *cmd_tbl)
1197 struct scatterlist *sg;
1198 struct ahci_sg *ahci_sg;
1199 unsigned int n_sg = 0;
1204 * Next, the S/G list.
1206 ahci_sg = cmd_tbl + AHCI_CMD_TBL_HDR_SZ;
1207 ata_for_each_sg(sg, qc) {
1208 dma_addr_t addr = sg_dma_address(sg);
1209 u32 sg_len = sg_dma_len(sg);
1211 ahci_sg->addr = cpu_to_le32(addr & 0xffffffff);
1212 ahci_sg->addr_hi = cpu_to_le32((addr >> 16) >> 16);
1213 ahci_sg->flags_size = cpu_to_le32(sg_len - 1);
1222 static void ahci_qc_prep(struct ata_queued_cmd *qc)
1224 struct ata_port *ap = qc->ap;
1225 struct ahci_port_priv *pp = ap->private_data;
1226 int is_atapi = is_atapi_taskfile(&qc->tf);
1229 const u32 cmd_fis_len = 5; /* five dwords */
1230 unsigned int n_elem;
1233 * Fill in command table information. First, the header,
1234 * a SATA Register - Host to Device command FIS.
1236 cmd_tbl = pp->cmd_tbl + qc->tag * AHCI_CMD_TBL_SZ;
1238 ata_tf_to_fis(&qc->tf, 0, 1, cmd_tbl);
1240 memset(cmd_tbl + AHCI_CMD_TBL_CDB, 0, 32);
1241 memcpy(cmd_tbl + AHCI_CMD_TBL_CDB, qc->cdb, qc->dev->cdb_len);
1245 if (qc->flags & ATA_QCFLAG_DMAMAP)
1246 n_elem = ahci_fill_sg(qc, cmd_tbl);
1249 * Fill in command slot information.
1251 opts = cmd_fis_len | n_elem << 16;
1252 if (qc->tf.flags & ATA_TFLAG_WRITE)
1253 opts |= AHCI_CMD_WRITE;
1255 opts |= AHCI_CMD_ATAPI | AHCI_CMD_PREFETCH;
1257 ahci_fill_cmd_slot(pp, qc->tag, opts);
1260 static void ahci_error_intr(struct ata_port *ap, u32 irq_stat)
1262 struct ahci_port_priv *pp = ap->private_data;
1263 struct ata_eh_info *ehi = &ap->eh_info;
1264 unsigned int err_mask = 0, action = 0;
1265 struct ata_queued_cmd *qc;
1268 ata_ehi_clear_desc(ehi);
1270 /* AHCI needs SError cleared; otherwise, it might lock up */
1271 ahci_scr_read(ap, SCR_ERROR, &serror);
1272 ahci_scr_write(ap, SCR_ERROR, serror);
1274 /* analyze @irq_stat */
1275 ata_ehi_push_desc(ehi, "irq_stat 0x%08x", irq_stat);
1277 /* some controllers set IRQ_IF_ERR on device errors, ignore it */
1278 if (ap->flags & AHCI_FLAG_IGN_IRQ_IF_ERR)
1279 irq_stat &= ~PORT_IRQ_IF_ERR;
1281 if (irq_stat & PORT_IRQ_TF_ERR) {
1282 err_mask |= AC_ERR_DEV;
1283 if (ap->flags & AHCI_FLAG_IGN_SERR_INTERNAL)
1284 serror &= ~SERR_INTERNAL;
1287 if (irq_stat & (PORT_IRQ_HBUS_ERR | PORT_IRQ_HBUS_DATA_ERR)) {
1288 err_mask |= AC_ERR_HOST_BUS;
1289 action |= ATA_EH_SOFTRESET;
1292 if (irq_stat & PORT_IRQ_IF_ERR) {
1293 err_mask |= AC_ERR_ATA_BUS;
1294 action |= ATA_EH_SOFTRESET;
1295 ata_ehi_push_desc(ehi, "interface fatal error");
1298 if (irq_stat & (PORT_IRQ_CONNECT | PORT_IRQ_PHYRDY)) {
1299 ata_ehi_hotplugged(ehi);
1300 ata_ehi_push_desc(ehi, "%s", irq_stat & PORT_IRQ_CONNECT ?
1301 "connection status changed" : "PHY RDY changed");
1304 if (irq_stat & PORT_IRQ_UNK_FIS) {
1305 u32 *unk = (u32 *)(pp->rx_fis + RX_FIS_UNK);
1307 err_mask |= AC_ERR_HSM;
1308 action |= ATA_EH_SOFTRESET;
1309 ata_ehi_push_desc(ehi, "unknown FIS %08x %08x %08x %08x",
1310 unk[0], unk[1], unk[2], unk[3]);
1313 /* okay, let's hand over to EH */
1314 ehi->serror |= serror;
1315 ehi->action |= action;
1317 qc = ata_qc_from_tag(ap, ap->active_tag);
1319 qc->err_mask |= err_mask;
1321 ehi->err_mask |= err_mask;
1323 if (irq_stat & PORT_IRQ_FREEZE)
1324 ata_port_freeze(ap);
1329 static void ahci_port_intr(struct ata_port *ap)
1331 void __iomem *port_mmio = ap->ioaddr.cmd_addr;
1332 struct ata_eh_info *ehi = &ap->eh_info;
1333 struct ahci_port_priv *pp = ap->private_data;
1334 u32 status, qc_active;
1335 int rc, known_irq = 0;
1337 status = readl(port_mmio + PORT_IRQ_STAT);
1338 writel(status, port_mmio + PORT_IRQ_STAT);
1340 if (unlikely(status & PORT_IRQ_ERROR)) {
1341 ahci_error_intr(ap, status);
1346 qc_active = readl(port_mmio + PORT_SCR_ACT);
1348 qc_active = readl(port_mmio + PORT_CMD_ISSUE);
1350 rc = ata_qc_complete_multiple(ap, qc_active, NULL);
1354 ehi->err_mask |= AC_ERR_HSM;
1355 ehi->action |= ATA_EH_SOFTRESET;
1356 ata_port_freeze(ap);
1360 /* hmmm... a spurious interupt */
1362 /* if !NCQ, ignore. No modern ATA device has broken HSM
1363 * implementation for non-NCQ commands.
1368 if (status & PORT_IRQ_D2H_REG_FIS) {
1369 if (!pp->ncq_saw_d2h)
1370 ata_port_printk(ap, KERN_INFO,
1371 "D2H reg with I during NCQ, "
1372 "this message won't be printed again\n");
1373 pp->ncq_saw_d2h = 1;
1377 if (status & PORT_IRQ_DMAS_FIS) {
1378 if (!pp->ncq_saw_dmas)
1379 ata_port_printk(ap, KERN_INFO,
1380 "DMAS FIS during NCQ, "
1381 "this message won't be printed again\n");
1382 pp->ncq_saw_dmas = 1;
1386 if (status & PORT_IRQ_SDB_FIS) {
1387 const __le32 *f = pp->rx_fis + RX_FIS_SDB;
1389 if (le32_to_cpu(f[1])) {
1390 /* SDB FIS containing spurious completions
1391 * might be dangerous, whine and fail commands
1392 * with HSM violation. EH will turn off NCQ
1393 * after several such failures.
1395 ata_ehi_push_desc(ehi,
1396 "spurious completions during NCQ "
1397 "issue=0x%x SAct=0x%x FIS=%08x:%08x",
1398 readl(port_mmio + PORT_CMD_ISSUE),
1399 readl(port_mmio + PORT_SCR_ACT),
1400 le32_to_cpu(f[0]), le32_to_cpu(f[1]));
1401 ehi->err_mask |= AC_ERR_HSM;
1402 ehi->action |= ATA_EH_SOFTRESET;
1403 ata_port_freeze(ap);
1405 if (!pp->ncq_saw_sdb)
1406 ata_port_printk(ap, KERN_INFO,
1407 "spurious SDB FIS %08x:%08x during NCQ, "
1408 "this message won't be printed again\n",
1409 le32_to_cpu(f[0]), le32_to_cpu(f[1]));
1410 pp->ncq_saw_sdb = 1;
1416 ata_port_printk(ap, KERN_INFO, "spurious interrupt "
1417 "(irq_stat 0x%x active_tag 0x%x sactive 0x%x)\n",
1418 status, ap->active_tag, ap->sactive);
1421 static void ahci_irq_clear(struct ata_port *ap)
1426 static irqreturn_t ahci_interrupt(int irq, void *dev_instance)
1428 struct ata_host *host = dev_instance;
1429 struct ahci_host_priv *hpriv;
1430 unsigned int i, handled = 0;
1432 u32 irq_stat, irq_ack = 0;
1436 hpriv = host->private_data;
1437 mmio = host->iomap[AHCI_PCI_BAR];
1439 /* sigh. 0xffffffff is a valid return from h/w */
1440 irq_stat = readl(mmio + HOST_IRQ_STAT);
1441 irq_stat &= hpriv->port_map;
1445 spin_lock(&host->lock);
1447 for (i = 0; i < host->n_ports; i++) {
1448 struct ata_port *ap;
1450 if (!(irq_stat & (1 << i)))
1453 ap = host->ports[i];
1456 VPRINTK("port %u\n", i);
1458 VPRINTK("port %u (no irq)\n", i);
1459 if (ata_ratelimit())
1460 dev_printk(KERN_WARNING, host->dev,
1461 "interrupt on disabled port %u\n", i);
1464 irq_ack |= (1 << i);
1468 writel(irq_ack, mmio + HOST_IRQ_STAT);
1472 spin_unlock(&host->lock);
1476 return IRQ_RETVAL(handled);
1479 static unsigned int ahci_qc_issue(struct ata_queued_cmd *qc)
1481 struct ata_port *ap = qc->ap;
1482 void __iomem *port_mmio = ahci_port_base(ap);
1484 if (qc->tf.protocol == ATA_PROT_NCQ)
1485 writel(1 << qc->tag, port_mmio + PORT_SCR_ACT);
1486 writel(1 << qc->tag, port_mmio + PORT_CMD_ISSUE);
1487 readl(port_mmio + PORT_CMD_ISSUE); /* flush */
1492 static void ahci_freeze(struct ata_port *ap)
1494 void __iomem *port_mmio = ahci_port_base(ap);
1497 writel(0, port_mmio + PORT_IRQ_MASK);
1500 static void ahci_thaw(struct ata_port *ap)
1502 void __iomem *mmio = ap->host->iomap[AHCI_PCI_BAR];
1503 void __iomem *port_mmio = ahci_port_base(ap);
1507 tmp = readl(port_mmio + PORT_IRQ_STAT);
1508 writel(tmp, port_mmio + PORT_IRQ_STAT);
1509 writel(1 << ap->port_no, mmio + HOST_IRQ_STAT);
1511 /* turn IRQ back on */
1512 writel(DEF_PORT_IRQ, port_mmio + PORT_IRQ_MASK);
1515 static void ahci_error_handler(struct ata_port *ap)
1517 if (!(ap->pflags & ATA_PFLAG_FROZEN)) {
1518 /* restart engine */
1519 ahci_stop_engine(ap);
1520 ahci_start_engine(ap);
1523 /* perform recovery */
1524 ata_do_eh(ap, ata_std_prereset, ahci_softreset, ahci_hardreset,
1528 static void ahci_vt8251_error_handler(struct ata_port *ap)
1530 if (!(ap->pflags & ATA_PFLAG_FROZEN)) {
1531 /* restart engine */
1532 ahci_stop_engine(ap);
1533 ahci_start_engine(ap);
1536 /* perform recovery */
1537 ata_do_eh(ap, ata_std_prereset, ahci_softreset, ahci_vt8251_hardreset,
1541 static void ahci_post_internal_cmd(struct ata_queued_cmd *qc)
1543 struct ata_port *ap = qc->ap;
1545 /* make DMA engine forget about the failed command */
1546 if (qc->flags & ATA_QCFLAG_FAILED)
1547 ahci_kick_engine(ap, 1);
1550 static int ahci_port_resume(struct ata_port *ap)
1553 ahci_start_port(ap);
1559 static int ahci_port_suspend(struct ata_port *ap, pm_message_t mesg)
1561 const char *emsg = NULL;
1564 rc = ahci_deinit_port(ap, &emsg);
1566 ahci_power_down(ap);
1568 ata_port_printk(ap, KERN_ERR, "%s (%d)\n", emsg, rc);
1569 ahci_start_port(ap);
1575 static int ahci_pci_device_suspend(struct pci_dev *pdev, pm_message_t mesg)
1577 struct ata_host *host = dev_get_drvdata(&pdev->dev);
1578 void __iomem *mmio = host->iomap[AHCI_PCI_BAR];
1581 if (mesg.event == PM_EVENT_SUSPEND) {
1582 /* AHCI spec rev1.1 section 8.3.3:
1583 * Software must disable interrupts prior to requesting a
1584 * transition of the HBA to D3 state.
1586 ctl = readl(mmio + HOST_CTL);
1587 ctl &= ~HOST_IRQ_EN;
1588 writel(ctl, mmio + HOST_CTL);
1589 readl(mmio + HOST_CTL); /* flush */
1592 return ata_pci_device_suspend(pdev, mesg);
1595 static int ahci_pci_device_resume(struct pci_dev *pdev)
1597 struct ata_host *host = dev_get_drvdata(&pdev->dev);
1600 rc = ata_pci_device_do_resume(pdev);
1604 if (pdev->dev.power.power_state.event == PM_EVENT_SUSPEND) {
1605 rc = ahci_reset_controller(host);
1609 ahci_init_controller(host);
1612 ata_host_resume(host);
1618 static int ahci_port_start(struct ata_port *ap)
1620 struct device *dev = ap->host->dev;
1621 struct ahci_port_priv *pp;
1626 pp = devm_kzalloc(dev, sizeof(*pp), GFP_KERNEL);
1630 rc = ata_pad_alloc(ap, dev);
1634 mem = dmam_alloc_coherent(dev, AHCI_PORT_PRIV_DMA_SZ, &mem_dma,
1638 memset(mem, 0, AHCI_PORT_PRIV_DMA_SZ);
1641 * First item in chunk of DMA memory: 32-slot command table,
1642 * 32 bytes each in size
1645 pp->cmd_slot_dma = mem_dma;
1647 mem += AHCI_CMD_SLOT_SZ;
1648 mem_dma += AHCI_CMD_SLOT_SZ;
1651 * Second item: Received-FIS area
1654 pp->rx_fis_dma = mem_dma;
1656 mem += AHCI_RX_FIS_SZ;
1657 mem_dma += AHCI_RX_FIS_SZ;
1660 * Third item: data area for storing a single command
1661 * and its scatter-gather table
1664 pp->cmd_tbl_dma = mem_dma;
1666 ap->private_data = pp;
1668 /* engage engines, captain */
1669 return ahci_port_resume(ap);
1672 static void ahci_port_stop(struct ata_port *ap)
1674 const char *emsg = NULL;
1677 /* de-initialize port */
1678 rc = ahci_deinit_port(ap, &emsg);
1680 ata_port_printk(ap, KERN_WARNING, "%s (%d)\n", emsg, rc);
1683 static int ahci_configure_dma_masks(struct pci_dev *pdev, int using_dac)
1688 !pci_set_dma_mask(pdev, DMA_64BIT_MASK)) {
1689 rc = pci_set_consistent_dma_mask(pdev, DMA_64BIT_MASK);
1691 rc = pci_set_consistent_dma_mask(pdev, DMA_32BIT_MASK);
1693 dev_printk(KERN_ERR, &pdev->dev,
1694 "64-bit DMA enable failed\n");
1699 rc = pci_set_dma_mask(pdev, DMA_32BIT_MASK);
1701 dev_printk(KERN_ERR, &pdev->dev,
1702 "32-bit DMA enable failed\n");
1705 rc = pci_set_consistent_dma_mask(pdev, DMA_32BIT_MASK);
1707 dev_printk(KERN_ERR, &pdev->dev,
1708 "32-bit consistent DMA enable failed\n");
1715 static void ahci_print_info(struct ata_host *host)
1717 struct ahci_host_priv *hpriv = host->private_data;
1718 struct pci_dev *pdev = to_pci_dev(host->dev);
1719 void __iomem *mmio = host->iomap[AHCI_PCI_BAR];
1720 u32 vers, cap, impl, speed;
1721 const char *speed_s;
1725 vers = readl(mmio + HOST_VERSION);
1727 impl = hpriv->port_map;
1729 speed = (cap >> 20) & 0xf;
1732 else if (speed == 2)
1737 pci_read_config_word(pdev, 0x0a, &cc);
1738 if (cc == PCI_CLASS_STORAGE_IDE)
1740 else if (cc == PCI_CLASS_STORAGE_SATA)
1742 else if (cc == PCI_CLASS_STORAGE_RAID)
1747 dev_printk(KERN_INFO, &pdev->dev,
1748 "AHCI %02x%02x.%02x%02x "
1749 "%u slots %u ports %s Gbps 0x%x impl %s mode\n"
1752 (vers >> 24) & 0xff,
1753 (vers >> 16) & 0xff,
1757 ((cap >> 8) & 0x1f) + 1,
1763 dev_printk(KERN_INFO, &pdev->dev,
1769 cap & (1 << 31) ? "64bit " : "",
1770 cap & (1 << 30) ? "ncq " : "",
1771 cap & (1 << 28) ? "ilck " : "",
1772 cap & (1 << 27) ? "stag " : "",
1773 cap & (1 << 26) ? "pm " : "",
1774 cap & (1 << 25) ? "led " : "",
1776 cap & (1 << 24) ? "clo " : "",
1777 cap & (1 << 19) ? "nz " : "",
1778 cap & (1 << 18) ? "only " : "",
1779 cap & (1 << 17) ? "pmp " : "",
1780 cap & (1 << 15) ? "pio " : "",
1781 cap & (1 << 14) ? "slum " : "",
1782 cap & (1 << 13) ? "part " : ""
1786 static int ahci_init_one(struct pci_dev *pdev, const struct pci_device_id *ent)
1788 static int printed_version;
1789 struct ata_port_info pi = ahci_port_info[ent->driver_data];
1790 const struct ata_port_info *ppi[] = { &pi, NULL };
1791 struct device *dev = &pdev->dev;
1792 struct ahci_host_priv *hpriv;
1793 struct ata_host *host;
1798 WARN_ON(ATA_MAX_QUEUE > AHCI_MAX_CMDS);
1800 if (!printed_version++)
1801 dev_printk(KERN_DEBUG, &pdev->dev, "version " DRV_VERSION "\n");
1803 /* acquire resources */
1804 rc = pcim_enable_device(pdev);
1808 rc = pcim_iomap_regions(pdev, 1 << AHCI_PCI_BAR, DRV_NAME);
1810 pcim_pin_device(pdev);
1814 if ((pi.flags & AHCI_FLAG_NO_MSI) || pci_enable_msi(pdev))
1817 hpriv = devm_kzalloc(dev, sizeof(*hpriv), GFP_KERNEL);
1821 /* save initial config */
1822 ahci_save_initial_config(pdev, &pi, hpriv);
1825 if (!(pi.flags & AHCI_FLAG_NO_NCQ) && (hpriv->cap & HOST_CAP_NCQ))
1826 pi.flags |= ATA_FLAG_NCQ;
1828 host = ata_host_alloc_pinfo(&pdev->dev, ppi, fls(hpriv->port_map));
1831 host->iomap = pcim_iomap_table(pdev);
1832 host->private_data = hpriv;
1834 for (i = 0; i < host->n_ports; i++) {
1835 struct ata_port *ap = host->ports[i];
1836 void __iomem *port_mmio = ahci_port_base(ap);
1838 /* standard SATA port setup */
1839 if (hpriv->port_map & (1 << i)) {
1840 ap->ioaddr.cmd_addr = port_mmio;
1841 ap->ioaddr.scr_addr = port_mmio + PORT_SCR;
1844 /* disabled/not-implemented port */
1846 ap->ops = &ata_dummy_port_ops;
1849 /* initialize adapter */
1850 rc = ahci_configure_dma_masks(pdev, hpriv->cap & HOST_CAP_64);
1854 rc = ahci_reset_controller(host);
1858 ahci_init_controller(host);
1859 ahci_print_info(host);
1861 pci_set_master(pdev);
1862 return ata_host_activate(host, pdev->irq, ahci_interrupt, IRQF_SHARED,
1866 static int __init ahci_init(void)
1868 return pci_register_driver(&ahci_pci_driver);
1871 static void __exit ahci_exit(void)
1873 pci_unregister_driver(&ahci_pci_driver);
1877 MODULE_AUTHOR("Jeff Garzik");
1878 MODULE_DESCRIPTION("AHCI SATA low-level driver");
1879 MODULE_LICENSE("GPL");
1880 MODULE_DEVICE_TABLE(pci, ahci_pci_tbl);
1881 MODULE_VERSION(DRV_VERSION);
1883 module_init(ahci_init);
1884 module_exit(ahci_exit);