2 * ahci.c - AHCI SATA support
4 * Maintained by: Jeff Garzik <jgarzik@pobox.com>
5 * Please ALWAYS copy linux-ide@vger.kernel.org
8 * Copyright 2004-2005 Red Hat, Inc.
11 * This program is free software; you can redistribute it and/or modify
12 * it under the terms of the GNU General Public License as published by
13 * the Free Software Foundation; either version 2, or (at your option)
16 * This program is distributed in the hope that it will be useful,
17 * but WITHOUT ANY WARRANTY; without even the implied warranty of
18 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
19 * GNU General Public License for more details.
21 * You should have received a copy of the GNU General Public License
22 * along with this program; see the file COPYING. If not, write to
23 * the Free Software Foundation, 675 Mass Ave, Cambridge, MA 02139, USA.
26 * libata documentation is available via 'make {ps|pdf}docs',
27 * as Documentation/DocBook/libata.*
29 * AHCI hardware documentation:
30 * http://www.intel.com/technology/serialata/pdf/rev1_0.pdf
31 * http://www.intel.com/technology/serialata/pdf/rev1_1.pdf
35 #include <linux/kernel.h>
36 #include <linux/module.h>
37 #include <linux/pci.h>
38 #include <linux/init.h>
39 #include <linux/blkdev.h>
40 #include <linux/delay.h>
41 #include <linux/interrupt.h>
42 #include <linux/sched.h>
43 #include <linux/dma-mapping.h>
44 #include <linux/device.h>
45 #include <scsi/scsi_host.h>
46 #include <scsi/scsi_cmnd.h>
47 #include <linux/libata.h>
50 #define DRV_NAME "ahci"
51 #define DRV_VERSION "2.0"
57 AHCI_MAX_SG = 168, /* hardware max is 64K */
58 AHCI_DMA_BOUNDARY = 0xffffffff,
59 AHCI_USE_CLUSTERING = 0,
62 AHCI_CMD_SLOT_SZ = AHCI_MAX_CMDS * AHCI_CMD_SZ,
64 AHCI_CMD_TBL_CDB = 0x40,
65 AHCI_CMD_TBL_HDR_SZ = 0x80,
66 AHCI_CMD_TBL_SZ = AHCI_CMD_TBL_HDR_SZ + (AHCI_MAX_SG * 16),
67 AHCI_CMD_TBL_AR_SZ = AHCI_CMD_TBL_SZ * AHCI_MAX_CMDS,
68 AHCI_PORT_PRIV_DMA_SZ = AHCI_CMD_SLOT_SZ + AHCI_CMD_TBL_AR_SZ +
70 AHCI_IRQ_ON_SG = (1 << 31),
71 AHCI_CMD_ATAPI = (1 << 5),
72 AHCI_CMD_WRITE = (1 << 6),
73 AHCI_CMD_PREFETCH = (1 << 7),
74 AHCI_CMD_RESET = (1 << 8),
75 AHCI_CMD_CLR_BUSY = (1 << 10),
77 RX_FIS_D2H_REG = 0x40, /* offset of D2H Register FIS data */
78 RX_FIS_UNK = 0x60, /* offset of Unknown FIS data */
82 board_ahci_vt8251 = 2,
83 board_ahci_ign_iferr = 3,
85 /* global controller registers */
86 HOST_CAP = 0x00, /* host capabilities */
87 HOST_CTL = 0x04, /* global host control */
88 HOST_IRQ_STAT = 0x08, /* interrupt status */
89 HOST_PORTS_IMPL = 0x0c, /* bitmap of implemented ports */
90 HOST_VERSION = 0x10, /* AHCI spec. version compliancy */
93 HOST_RESET = (1 << 0), /* reset controller; self-clear */
94 HOST_IRQ_EN = (1 << 1), /* global IRQ enable */
95 HOST_AHCI_EN = (1 << 31), /* AHCI enabled */
98 HOST_CAP_SSC = (1 << 14), /* Slumber capable */
99 HOST_CAP_CLO = (1 << 24), /* Command List Override support */
100 HOST_CAP_SSS = (1 << 27), /* Staggered Spin-up */
101 HOST_CAP_NCQ = (1 << 30), /* Native Command Queueing */
102 HOST_CAP_64 = (1 << 31), /* PCI DAC (64-bit DMA) support */
104 /* registers for each SATA port */
105 PORT_LST_ADDR = 0x00, /* command list DMA addr */
106 PORT_LST_ADDR_HI = 0x04, /* command list DMA addr hi */
107 PORT_FIS_ADDR = 0x08, /* FIS rx buf addr */
108 PORT_FIS_ADDR_HI = 0x0c, /* FIS rx buf addr hi */
109 PORT_IRQ_STAT = 0x10, /* interrupt status */
110 PORT_IRQ_MASK = 0x14, /* interrupt enable/disable mask */
111 PORT_CMD = 0x18, /* port command */
112 PORT_TFDATA = 0x20, /* taskfile data */
113 PORT_SIG = 0x24, /* device TF signature */
114 PORT_CMD_ISSUE = 0x38, /* command issue */
115 PORT_SCR = 0x28, /* SATA phy register block */
116 PORT_SCR_STAT = 0x28, /* SATA phy register: SStatus */
117 PORT_SCR_CTL = 0x2c, /* SATA phy register: SControl */
118 PORT_SCR_ERR = 0x30, /* SATA phy register: SError */
119 PORT_SCR_ACT = 0x34, /* SATA phy register: SActive */
121 /* PORT_IRQ_{STAT,MASK} bits */
122 PORT_IRQ_COLD_PRES = (1 << 31), /* cold presence detect */
123 PORT_IRQ_TF_ERR = (1 << 30), /* task file error */
124 PORT_IRQ_HBUS_ERR = (1 << 29), /* host bus fatal error */
125 PORT_IRQ_HBUS_DATA_ERR = (1 << 28), /* host bus data error */
126 PORT_IRQ_IF_ERR = (1 << 27), /* interface fatal error */
127 PORT_IRQ_IF_NONFATAL = (1 << 26), /* interface non-fatal error */
128 PORT_IRQ_OVERFLOW = (1 << 24), /* xfer exhausted available S/G */
129 PORT_IRQ_BAD_PMP = (1 << 23), /* incorrect port multiplier */
131 PORT_IRQ_PHYRDY = (1 << 22), /* PhyRdy changed */
132 PORT_IRQ_DEV_ILCK = (1 << 7), /* device interlock */
133 PORT_IRQ_CONNECT = (1 << 6), /* port connect change status */
134 PORT_IRQ_SG_DONE = (1 << 5), /* descriptor processed */
135 PORT_IRQ_UNK_FIS = (1 << 4), /* unknown FIS rx'd */
136 PORT_IRQ_SDB_FIS = (1 << 3), /* Set Device Bits FIS rx'd */
137 PORT_IRQ_DMAS_FIS = (1 << 2), /* DMA Setup FIS rx'd */
138 PORT_IRQ_PIOS_FIS = (1 << 1), /* PIO Setup FIS rx'd */
139 PORT_IRQ_D2H_REG_FIS = (1 << 0), /* D2H Register FIS rx'd */
141 PORT_IRQ_FREEZE = PORT_IRQ_HBUS_ERR |
146 PORT_IRQ_ERROR = PORT_IRQ_FREEZE |
148 PORT_IRQ_HBUS_DATA_ERR,
149 DEF_PORT_IRQ = PORT_IRQ_ERROR | PORT_IRQ_SG_DONE |
150 PORT_IRQ_SDB_FIS | PORT_IRQ_DMAS_FIS |
151 PORT_IRQ_PIOS_FIS | PORT_IRQ_D2H_REG_FIS,
154 PORT_CMD_ATAPI = (1 << 24), /* Device is ATAPI */
155 PORT_CMD_LIST_ON = (1 << 15), /* cmd list DMA engine running */
156 PORT_CMD_FIS_ON = (1 << 14), /* FIS DMA engine running */
157 PORT_CMD_FIS_RX = (1 << 4), /* Enable FIS receive DMA engine */
158 PORT_CMD_CLO = (1 << 3), /* Command list override */
159 PORT_CMD_POWER_ON = (1 << 2), /* Power up device */
160 PORT_CMD_SPIN_UP = (1 << 1), /* Spin up device */
161 PORT_CMD_START = (1 << 0), /* Enable port DMA engine */
163 PORT_CMD_ICC_MASK = (0xf << 28), /* i/f ICC state mask */
164 PORT_CMD_ICC_ACTIVE = (0x1 << 28), /* Put i/f in active state */
165 PORT_CMD_ICC_PARTIAL = (0x2 << 28), /* Put i/f in partial state */
166 PORT_CMD_ICC_SLUMBER = (0x6 << 28), /* Put i/f in slumber state */
168 /* hpriv->flags bits */
169 AHCI_FLAG_MSI = (1 << 0),
172 AHCI_FLAG_NO_NCQ = (1 << 24),
173 AHCI_FLAG_IGN_IRQ_IF_ERR = (1 << 25), /* ignore IRQ_IF_ERR */
174 AHCI_FLAG_HONOR_PI = (1 << 26), /* honor PORTS_IMPL */
177 struct ahci_cmd_hdr {
192 struct ahci_host_priv {
194 u32 cap; /* cache of HOST_CAP register */
195 u32 port_map; /* cache of HOST_PORTS_IMPL reg */
198 struct ahci_port_priv {
199 struct ahci_cmd_hdr *cmd_slot;
200 dma_addr_t cmd_slot_dma;
202 dma_addr_t cmd_tbl_dma;
204 dma_addr_t rx_fis_dma;
207 static u32 ahci_scr_read (struct ata_port *ap, unsigned int sc_reg);
208 static void ahci_scr_write (struct ata_port *ap, unsigned int sc_reg, u32 val);
209 static int ahci_init_one (struct pci_dev *pdev, const struct pci_device_id *ent);
210 static unsigned int ahci_qc_issue(struct ata_queued_cmd *qc);
211 static irqreturn_t ahci_interrupt (int irq, void *dev_instance);
212 static void ahci_irq_clear(struct ata_port *ap);
213 static int ahci_port_start(struct ata_port *ap);
214 static void ahci_port_stop(struct ata_port *ap);
215 static void ahci_tf_read(struct ata_port *ap, struct ata_taskfile *tf);
216 static void ahci_qc_prep(struct ata_queued_cmd *qc);
217 static u8 ahci_check_status(struct ata_port *ap);
218 static void ahci_freeze(struct ata_port *ap);
219 static void ahci_thaw(struct ata_port *ap);
220 static void ahci_error_handler(struct ata_port *ap);
221 static void ahci_vt8251_error_handler(struct ata_port *ap);
222 static void ahci_post_internal_cmd(struct ata_queued_cmd *qc);
223 static int ahci_port_suspend(struct ata_port *ap, pm_message_t mesg);
224 static int ahci_port_resume(struct ata_port *ap);
225 static int ahci_pci_device_suspend(struct pci_dev *pdev, pm_message_t mesg);
226 static int ahci_pci_device_resume(struct pci_dev *pdev);
227 static void ahci_remove_one (struct pci_dev *pdev);
229 static struct scsi_host_template ahci_sht = {
230 .module = THIS_MODULE,
232 .ioctl = ata_scsi_ioctl,
233 .queuecommand = ata_scsi_queuecmd,
234 .change_queue_depth = ata_scsi_change_queue_depth,
235 .can_queue = AHCI_MAX_CMDS - 1,
236 .this_id = ATA_SHT_THIS_ID,
237 .sg_tablesize = AHCI_MAX_SG,
238 .cmd_per_lun = ATA_SHT_CMD_PER_LUN,
239 .emulated = ATA_SHT_EMULATED,
240 .use_clustering = AHCI_USE_CLUSTERING,
241 .proc_name = DRV_NAME,
242 .dma_boundary = AHCI_DMA_BOUNDARY,
243 .slave_configure = ata_scsi_slave_config,
244 .slave_destroy = ata_scsi_slave_destroy,
245 .bios_param = ata_std_bios_param,
246 .suspend = ata_scsi_device_suspend,
247 .resume = ata_scsi_device_resume,
250 static const struct ata_port_operations ahci_ops = {
251 .port_disable = ata_port_disable,
253 .check_status = ahci_check_status,
254 .check_altstatus = ahci_check_status,
255 .dev_select = ata_noop_dev_select,
257 .tf_read = ahci_tf_read,
259 .qc_prep = ahci_qc_prep,
260 .qc_issue = ahci_qc_issue,
262 .irq_handler = ahci_interrupt,
263 .irq_clear = ahci_irq_clear,
265 .scr_read = ahci_scr_read,
266 .scr_write = ahci_scr_write,
268 .freeze = ahci_freeze,
271 .error_handler = ahci_error_handler,
272 .post_internal_cmd = ahci_post_internal_cmd,
274 .port_suspend = ahci_port_suspend,
275 .port_resume = ahci_port_resume,
277 .port_start = ahci_port_start,
278 .port_stop = ahci_port_stop,
281 static const struct ata_port_operations ahci_vt8251_ops = {
282 .port_disable = ata_port_disable,
284 .check_status = ahci_check_status,
285 .check_altstatus = ahci_check_status,
286 .dev_select = ata_noop_dev_select,
288 .tf_read = ahci_tf_read,
290 .qc_prep = ahci_qc_prep,
291 .qc_issue = ahci_qc_issue,
293 .irq_handler = ahci_interrupt,
294 .irq_clear = ahci_irq_clear,
296 .scr_read = ahci_scr_read,
297 .scr_write = ahci_scr_write,
299 .freeze = ahci_freeze,
302 .error_handler = ahci_vt8251_error_handler,
303 .post_internal_cmd = ahci_post_internal_cmd,
305 .port_suspend = ahci_port_suspend,
306 .port_resume = ahci_port_resume,
308 .port_start = ahci_port_start,
309 .port_stop = ahci_port_stop,
312 static const struct ata_port_info ahci_port_info[] = {
316 .flags = ATA_FLAG_SATA | ATA_FLAG_NO_LEGACY |
317 ATA_FLAG_MMIO | ATA_FLAG_PIO_DMA |
318 ATA_FLAG_SKIP_D2H_BSY,
319 .pio_mask = 0x1f, /* pio0-4 */
320 .udma_mask = 0x7f, /* udma0-6 ; FIXME */
321 .port_ops = &ahci_ops,
326 .flags = ATA_FLAG_SATA | ATA_FLAG_NO_LEGACY |
327 ATA_FLAG_MMIO | ATA_FLAG_PIO_DMA |
328 ATA_FLAG_SKIP_D2H_BSY | AHCI_FLAG_HONOR_PI,
329 .pio_mask = 0x1f, /* pio0-4 */
330 .udma_mask = 0x7f, /* udma0-6 ; FIXME */
331 .port_ops = &ahci_ops,
333 /* board_ahci_vt8251 */
336 .flags = ATA_FLAG_SATA | ATA_FLAG_NO_LEGACY |
337 ATA_FLAG_MMIO | ATA_FLAG_PIO_DMA |
338 ATA_FLAG_SKIP_D2H_BSY |
339 ATA_FLAG_HRST_TO_RESUME | AHCI_FLAG_NO_NCQ,
340 .pio_mask = 0x1f, /* pio0-4 */
341 .udma_mask = 0x7f, /* udma0-6 ; FIXME */
342 .port_ops = &ahci_vt8251_ops,
344 /* board_ahci_ign_iferr */
347 .flags = ATA_FLAG_SATA | ATA_FLAG_NO_LEGACY |
348 ATA_FLAG_MMIO | ATA_FLAG_PIO_DMA |
349 ATA_FLAG_SKIP_D2H_BSY |
350 AHCI_FLAG_IGN_IRQ_IF_ERR,
351 .pio_mask = 0x1f, /* pio0-4 */
352 .udma_mask = 0x7f, /* udma0-6 ; FIXME */
353 .port_ops = &ahci_ops,
357 static const struct pci_device_id ahci_pci_tbl[] = {
359 { PCI_VDEVICE(INTEL, 0x2652), board_ahci }, /* ICH6 */
360 { PCI_VDEVICE(INTEL, 0x2653), board_ahci }, /* ICH6M */
361 { PCI_VDEVICE(INTEL, 0x27c1), board_ahci }, /* ICH7 */
362 { PCI_VDEVICE(INTEL, 0x27c5), board_ahci }, /* ICH7M */
363 { PCI_VDEVICE(INTEL, 0x27c3), board_ahci }, /* ICH7R */
364 { PCI_VDEVICE(AL, 0x5288), board_ahci_ign_iferr }, /* ULi M5288 */
365 { PCI_VDEVICE(INTEL, 0x2681), board_ahci }, /* ESB2 */
366 { PCI_VDEVICE(INTEL, 0x2682), board_ahci }, /* ESB2 */
367 { PCI_VDEVICE(INTEL, 0x2683), board_ahci }, /* ESB2 */
368 { PCI_VDEVICE(INTEL, 0x27c6), board_ahci }, /* ICH7-M DH */
369 { PCI_VDEVICE(INTEL, 0x2821), board_ahci_pi }, /* ICH8 */
370 { PCI_VDEVICE(INTEL, 0x2822), board_ahci_pi }, /* ICH8 */
371 { PCI_VDEVICE(INTEL, 0x2824), board_ahci_pi }, /* ICH8 */
372 { PCI_VDEVICE(INTEL, 0x2829), board_ahci_pi }, /* ICH8M */
373 { PCI_VDEVICE(INTEL, 0x282a), board_ahci_pi }, /* ICH8M */
374 { PCI_VDEVICE(INTEL, 0x2922), board_ahci_pi }, /* ICH9 */
375 { PCI_VDEVICE(INTEL, 0x2923), board_ahci_pi }, /* ICH9 */
376 { PCI_VDEVICE(INTEL, 0x2924), board_ahci_pi }, /* ICH9 */
377 { PCI_VDEVICE(INTEL, 0x2925), board_ahci_pi }, /* ICH9 */
378 { PCI_VDEVICE(INTEL, 0x2927), board_ahci_pi }, /* ICH9 */
379 { PCI_VDEVICE(INTEL, 0x2929), board_ahci_pi }, /* ICH9M */
380 { PCI_VDEVICE(INTEL, 0x292a), board_ahci_pi }, /* ICH9M */
381 { PCI_VDEVICE(INTEL, 0x292b), board_ahci_pi }, /* ICH9M */
382 { PCI_VDEVICE(INTEL, 0x292f), board_ahci_pi }, /* ICH9M */
383 { PCI_VDEVICE(INTEL, 0x294d), board_ahci_pi }, /* ICH9 */
384 { PCI_VDEVICE(INTEL, 0x294e), board_ahci_pi }, /* ICH9M */
387 { PCI_VDEVICE(JMICRON, 0x2360), board_ahci_ign_iferr }, /* JMB360 */
388 { PCI_VDEVICE(JMICRON, 0x2361), board_ahci_ign_iferr }, /* JMB361 */
389 { PCI_VDEVICE(JMICRON, 0x2363), board_ahci_ign_iferr }, /* JMB363 */
390 { PCI_VDEVICE(JMICRON, 0x2365), board_ahci_ign_iferr }, /* JMB365 */
391 { PCI_VDEVICE(JMICRON, 0x2366), board_ahci_ign_iferr }, /* JMB366 */
394 { PCI_VDEVICE(ATI, 0x4380), board_ahci }, /* ATI SB600 non-raid */
395 { PCI_VDEVICE(ATI, 0x4381), board_ahci }, /* ATI SB600 raid */
398 { PCI_VDEVICE(VIA, 0x3349), board_ahci_vt8251 }, /* VIA VT8251 */
401 { PCI_VDEVICE(NVIDIA, 0x044c), board_ahci }, /* MCP65 */
402 { PCI_VDEVICE(NVIDIA, 0x044d), board_ahci }, /* MCP65 */
403 { PCI_VDEVICE(NVIDIA, 0x044e), board_ahci }, /* MCP65 */
404 { PCI_VDEVICE(NVIDIA, 0x044f), board_ahci }, /* MCP65 */
405 { PCI_VDEVICE(NVIDIA, 0x045c), board_ahci }, /* MCP65 */
406 { PCI_VDEVICE(NVIDIA, 0x045d), board_ahci }, /* MCP65 */
407 { PCI_VDEVICE(NVIDIA, 0x045e), board_ahci }, /* MCP65 */
408 { PCI_VDEVICE(NVIDIA, 0x045f), board_ahci }, /* MCP65 */
409 { PCI_VDEVICE(NVIDIA, 0x0550), board_ahci }, /* MCP67 */
410 { PCI_VDEVICE(NVIDIA, 0x0551), board_ahci }, /* MCP67 */
411 { PCI_VDEVICE(NVIDIA, 0x0552), board_ahci }, /* MCP67 */
412 { PCI_VDEVICE(NVIDIA, 0x0553), board_ahci }, /* MCP67 */
413 { PCI_VDEVICE(NVIDIA, 0x0554), board_ahci }, /* MCP67 */
414 { PCI_VDEVICE(NVIDIA, 0x0555), board_ahci }, /* MCP67 */
415 { PCI_VDEVICE(NVIDIA, 0x0556), board_ahci }, /* MCP67 */
416 { PCI_VDEVICE(NVIDIA, 0x0557), board_ahci }, /* MCP67 */
417 { PCI_VDEVICE(NVIDIA, 0x0558), board_ahci }, /* MCP67 */
418 { PCI_VDEVICE(NVIDIA, 0x0559), board_ahci }, /* MCP67 */
419 { PCI_VDEVICE(NVIDIA, 0x055a), board_ahci }, /* MCP67 */
420 { PCI_VDEVICE(NVIDIA, 0x055b), board_ahci }, /* MCP67 */
423 { PCI_VDEVICE(SI, 0x1184), board_ahci }, /* SiS 966 */
424 { PCI_VDEVICE(SI, 0x1185), board_ahci }, /* SiS 966 */
425 { PCI_VDEVICE(SI, 0x0186), board_ahci }, /* SiS 968 */
427 /* Generic, PCI class code for AHCI */
428 { PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID,
429 0x010601, 0xffffff, board_ahci },
431 { } /* terminate list */
435 static struct pci_driver ahci_pci_driver = {
437 .id_table = ahci_pci_tbl,
438 .probe = ahci_init_one,
439 .suspend = ahci_pci_device_suspend,
440 .resume = ahci_pci_device_resume,
441 .remove = ahci_remove_one,
445 static inline int ahci_nr_ports(u32 cap)
447 return (cap & 0x1f) + 1;
450 static inline unsigned long ahci_port_base_ul (unsigned long base, unsigned int port)
452 return base + 0x100 + (port * 0x80);
455 static inline void __iomem *ahci_port_base (void __iomem *base, unsigned int port)
457 return (void __iomem *) ahci_port_base_ul((unsigned long)base, port);
460 static u32 ahci_scr_read (struct ata_port *ap, unsigned int sc_reg_in)
465 case SCR_STATUS: sc_reg = 0; break;
466 case SCR_CONTROL: sc_reg = 1; break;
467 case SCR_ERROR: sc_reg = 2; break;
468 case SCR_ACTIVE: sc_reg = 3; break;
473 return readl((void __iomem *) ap->ioaddr.scr_addr + (sc_reg * 4));
477 static void ahci_scr_write (struct ata_port *ap, unsigned int sc_reg_in,
483 case SCR_STATUS: sc_reg = 0; break;
484 case SCR_CONTROL: sc_reg = 1; break;
485 case SCR_ERROR: sc_reg = 2; break;
486 case SCR_ACTIVE: sc_reg = 3; break;
491 writel(val, (void __iomem *) ap->ioaddr.scr_addr + (sc_reg * 4));
494 static void ahci_start_engine(void __iomem *port_mmio)
499 tmp = readl(port_mmio + PORT_CMD);
500 tmp |= PORT_CMD_START;
501 writel(tmp, port_mmio + PORT_CMD);
502 readl(port_mmio + PORT_CMD); /* flush */
505 static int ahci_stop_engine(void __iomem *port_mmio)
509 tmp = readl(port_mmio + PORT_CMD);
511 /* check if the HBA is idle */
512 if ((tmp & (PORT_CMD_START | PORT_CMD_LIST_ON)) == 0)
515 /* setting HBA to idle */
516 tmp &= ~PORT_CMD_START;
517 writel(tmp, port_mmio + PORT_CMD);
519 /* wait for engine to stop. This could be as long as 500 msec */
520 tmp = ata_wait_register(port_mmio + PORT_CMD,
521 PORT_CMD_LIST_ON, PORT_CMD_LIST_ON, 1, 500);
522 if (tmp & PORT_CMD_LIST_ON)
528 static void ahci_start_fis_rx(void __iomem *port_mmio, u32 cap,
529 dma_addr_t cmd_slot_dma, dma_addr_t rx_fis_dma)
533 /* set FIS registers */
534 if (cap & HOST_CAP_64)
535 writel((cmd_slot_dma >> 16) >> 16, port_mmio + PORT_LST_ADDR_HI);
536 writel(cmd_slot_dma & 0xffffffff, port_mmio + PORT_LST_ADDR);
538 if (cap & HOST_CAP_64)
539 writel((rx_fis_dma >> 16) >> 16, port_mmio + PORT_FIS_ADDR_HI);
540 writel(rx_fis_dma & 0xffffffff, port_mmio + PORT_FIS_ADDR);
542 /* enable FIS reception */
543 tmp = readl(port_mmio + PORT_CMD);
544 tmp |= PORT_CMD_FIS_RX;
545 writel(tmp, port_mmio + PORT_CMD);
548 readl(port_mmio + PORT_CMD);
551 static int ahci_stop_fis_rx(void __iomem *port_mmio)
555 /* disable FIS reception */
556 tmp = readl(port_mmio + PORT_CMD);
557 tmp &= ~PORT_CMD_FIS_RX;
558 writel(tmp, port_mmio + PORT_CMD);
560 /* wait for completion, spec says 500ms, give it 1000 */
561 tmp = ata_wait_register(port_mmio + PORT_CMD, PORT_CMD_FIS_ON,
562 PORT_CMD_FIS_ON, 10, 1000);
563 if (tmp & PORT_CMD_FIS_ON)
569 static void ahci_power_up(void __iomem *port_mmio, u32 cap)
573 cmd = readl(port_mmio + PORT_CMD) & ~PORT_CMD_ICC_MASK;
576 if (cap & HOST_CAP_SSS) {
577 cmd |= PORT_CMD_SPIN_UP;
578 writel(cmd, port_mmio + PORT_CMD);
582 writel(cmd | PORT_CMD_ICC_ACTIVE, port_mmio + PORT_CMD);
585 static void ahci_power_down(void __iomem *port_mmio, u32 cap)
589 if (!(cap & HOST_CAP_SSS))
592 /* put device into listen mode, first set PxSCTL.DET to 0 */
593 scontrol = readl(port_mmio + PORT_SCR_CTL);
595 writel(scontrol, port_mmio + PORT_SCR_CTL);
597 /* then set PxCMD.SUD to 0 */
598 cmd = readl(port_mmio + PORT_CMD) & ~PORT_CMD_ICC_MASK;
599 cmd &= ~PORT_CMD_SPIN_UP;
600 writel(cmd, port_mmio + PORT_CMD);
603 static void ahci_init_port(void __iomem *port_mmio, u32 cap,
604 dma_addr_t cmd_slot_dma, dma_addr_t rx_fis_dma)
606 /* enable FIS reception */
607 ahci_start_fis_rx(port_mmio, cap, cmd_slot_dma, rx_fis_dma);
610 ahci_start_engine(port_mmio);
613 static int ahci_deinit_port(void __iomem *port_mmio, u32 cap, const char **emsg)
618 rc = ahci_stop_engine(port_mmio);
620 *emsg = "failed to stop engine";
624 /* disable FIS reception */
625 rc = ahci_stop_fis_rx(port_mmio);
627 *emsg = "failed stop FIS RX";
634 static int ahci_reset_controller(void __iomem *mmio, struct pci_dev *pdev)
636 u32 cap_save, impl_save, tmp;
638 cap_save = readl(mmio + HOST_CAP);
639 impl_save = readl(mmio + HOST_PORTS_IMPL);
641 /* global controller reset */
642 tmp = readl(mmio + HOST_CTL);
643 if ((tmp & HOST_RESET) == 0) {
644 writel(tmp | HOST_RESET, mmio + HOST_CTL);
645 readl(mmio + HOST_CTL); /* flush */
648 /* reset must complete within 1 second, or
649 * the hardware should be considered fried.
653 tmp = readl(mmio + HOST_CTL);
654 if (tmp & HOST_RESET) {
655 dev_printk(KERN_ERR, &pdev->dev,
656 "controller reset failed (0x%x)\n", tmp);
660 /* turn on AHCI mode */
661 writel(HOST_AHCI_EN, mmio + HOST_CTL);
662 (void) readl(mmio + HOST_CTL); /* flush */
664 /* These write-once registers are normally cleared on reset.
665 * Restore BIOS values... which we HOPE were present before
669 impl_save = (1 << ahci_nr_ports(cap_save)) - 1;
670 dev_printk(KERN_WARNING, &pdev->dev,
671 "PORTS_IMPL is zero, forcing 0x%x\n", impl_save);
673 writel(cap_save, mmio + HOST_CAP);
674 writel(impl_save, mmio + HOST_PORTS_IMPL);
675 (void) readl(mmio + HOST_PORTS_IMPL); /* flush */
677 if (pdev->vendor == PCI_VENDOR_ID_INTEL) {
681 pci_read_config_word(pdev, 0x92, &tmp16);
683 pci_write_config_word(pdev, 0x92, tmp16);
689 static void ahci_init_controller(void __iomem *mmio, struct pci_dev *pdev,
690 int n_ports, unsigned int port_flags,
691 struct ahci_host_priv *hpriv)
696 for (i = 0; i < n_ports; i++) {
697 void __iomem *port_mmio = ahci_port_base(mmio, i);
698 const char *emsg = NULL;
700 if ((port_flags & AHCI_FLAG_HONOR_PI) &&
701 !(hpriv->port_map & (1 << i)))
704 /* make sure port is not active */
705 rc = ahci_deinit_port(port_mmio, hpriv->cap, &emsg);
707 dev_printk(KERN_WARNING, &pdev->dev,
708 "%s (%d)\n", emsg, rc);
711 tmp = readl(port_mmio + PORT_SCR_ERR);
712 VPRINTK("PORT_SCR_ERR 0x%x\n", tmp);
713 writel(tmp, port_mmio + PORT_SCR_ERR);
716 tmp = readl(port_mmio + PORT_IRQ_STAT);
717 VPRINTK("PORT_IRQ_STAT 0x%x\n", tmp);
719 writel(tmp, port_mmio + PORT_IRQ_STAT);
721 writel(1 << i, mmio + HOST_IRQ_STAT);
724 tmp = readl(mmio + HOST_CTL);
725 VPRINTK("HOST_CTL 0x%x\n", tmp);
726 writel(tmp | HOST_IRQ_EN, mmio + HOST_CTL);
727 tmp = readl(mmio + HOST_CTL);
728 VPRINTK("HOST_CTL 0x%x\n", tmp);
731 static unsigned int ahci_dev_classify(struct ata_port *ap)
733 void __iomem *port_mmio = (void __iomem *) ap->ioaddr.cmd_addr;
734 struct ata_taskfile tf;
737 tmp = readl(port_mmio + PORT_SIG);
738 tf.lbah = (tmp >> 24) & 0xff;
739 tf.lbam = (tmp >> 16) & 0xff;
740 tf.lbal = (tmp >> 8) & 0xff;
741 tf.nsect = (tmp) & 0xff;
743 return ata_dev_classify(&tf);
746 static void ahci_fill_cmd_slot(struct ahci_port_priv *pp, unsigned int tag,
749 dma_addr_t cmd_tbl_dma;
751 cmd_tbl_dma = pp->cmd_tbl_dma + tag * AHCI_CMD_TBL_SZ;
753 pp->cmd_slot[tag].opts = cpu_to_le32(opts);
754 pp->cmd_slot[tag].status = 0;
755 pp->cmd_slot[tag].tbl_addr = cpu_to_le32(cmd_tbl_dma & 0xffffffff);
756 pp->cmd_slot[tag].tbl_addr_hi = cpu_to_le32((cmd_tbl_dma >> 16) >> 16);
759 static int ahci_clo(struct ata_port *ap)
761 void __iomem *port_mmio = (void __iomem *) ap->ioaddr.cmd_addr;
762 struct ahci_host_priv *hpriv = ap->host->private_data;
765 if (!(hpriv->cap & HOST_CAP_CLO))
768 tmp = readl(port_mmio + PORT_CMD);
770 writel(tmp, port_mmio + PORT_CMD);
772 tmp = ata_wait_register(port_mmio + PORT_CMD,
773 PORT_CMD_CLO, PORT_CMD_CLO, 1, 500);
774 if (tmp & PORT_CMD_CLO)
780 static int ahci_softreset(struct ata_port *ap, unsigned int *class)
782 struct ahci_port_priv *pp = ap->private_data;
783 void __iomem *mmio = ap->host->mmio_base;
784 void __iomem *port_mmio = ahci_port_base(mmio, ap->port_no);
785 const u32 cmd_fis_len = 5; /* five dwords */
786 const char *reason = NULL;
787 struct ata_taskfile tf;
794 if (ata_port_offline(ap)) {
795 DPRINTK("PHY reports no device\n");
796 *class = ATA_DEV_NONE;
800 /* prepare for SRST (AHCI-1.1 10.4.1) */
801 rc = ahci_stop_engine(port_mmio);
803 reason = "failed to stop engine";
807 /* check BUSY/DRQ, perform Command List Override if necessary */
808 if (ahci_check_status(ap) & (ATA_BUSY | ATA_DRQ)) {
811 if (rc == -EOPNOTSUPP) {
812 reason = "port busy but CLO unavailable";
815 reason = "port busy but CLO failed";
821 ahci_start_engine(port_mmio);
823 ata_tf_init(ap->device, &tf);
826 /* issue the first D2H Register FIS */
827 ahci_fill_cmd_slot(pp, 0,
828 cmd_fis_len | AHCI_CMD_RESET | AHCI_CMD_CLR_BUSY);
831 ata_tf_to_fis(&tf, fis, 0);
832 fis[1] &= ~(1 << 7); /* turn off Command FIS bit */
834 writel(1, port_mmio + PORT_CMD_ISSUE);
836 tmp = ata_wait_register(port_mmio + PORT_CMD_ISSUE, 0x1, 0x1, 1, 500);
839 reason = "1st FIS failed";
843 /* spec says at least 5us, but be generous and sleep for 1ms */
846 /* issue the second D2H Register FIS */
847 ahci_fill_cmd_slot(pp, 0, cmd_fis_len);
850 ata_tf_to_fis(&tf, fis, 0);
851 fis[1] &= ~(1 << 7); /* turn off Command FIS bit */
853 writel(1, port_mmio + PORT_CMD_ISSUE);
854 readl(port_mmio + PORT_CMD_ISSUE); /* flush */
856 /* spec mandates ">= 2ms" before checking status.
857 * We wait 150ms, because that was the magic delay used for
858 * ATAPI devices in Hale Landis's ATADRVR, for the period of time
859 * between when the ATA command register is written, and then
860 * status is checked. Because waiting for "a while" before
861 * checking status is fine, post SRST, we perform this magic
862 * delay here as well.
866 *class = ATA_DEV_NONE;
867 if (ata_port_online(ap)) {
868 if (ata_busy_sleep(ap, ATA_TMOUT_BOOT_QUICK, ATA_TMOUT_BOOT)) {
870 reason = "device not ready";
873 *class = ahci_dev_classify(ap);
876 DPRINTK("EXIT, class=%u\n", *class);
880 ahci_start_engine(port_mmio);
882 ata_port_printk(ap, KERN_ERR, "softreset failed (%s)\n", reason);
886 static int ahci_hardreset(struct ata_port *ap, unsigned int *class)
888 struct ahci_port_priv *pp = ap->private_data;
889 u8 *d2h_fis = pp->rx_fis + RX_FIS_D2H_REG;
890 struct ata_taskfile tf;
891 void __iomem *mmio = ap->host->mmio_base;
892 void __iomem *port_mmio = ahci_port_base(mmio, ap->port_no);
897 ahci_stop_engine(port_mmio);
899 /* clear D2H reception area to properly wait for D2H FIS */
900 ata_tf_init(ap->device, &tf);
902 ata_tf_to_fis(&tf, d2h_fis, 0);
904 rc = sata_std_hardreset(ap, class);
906 ahci_start_engine(port_mmio);
908 if (rc == 0 && ata_port_online(ap))
909 *class = ahci_dev_classify(ap);
910 if (*class == ATA_DEV_UNKNOWN)
911 *class = ATA_DEV_NONE;
913 DPRINTK("EXIT, rc=%d, class=%u\n", rc, *class);
917 static int ahci_vt8251_hardreset(struct ata_port *ap, unsigned int *class)
919 void __iomem *mmio = ap->host->mmio_base;
920 void __iomem *port_mmio = ahci_port_base(mmio, ap->port_no);
925 ahci_stop_engine(port_mmio);
927 rc = sata_port_hardreset(ap, sata_ehc_deb_timing(&ap->eh_context));
929 /* vt8251 needs SError cleared for the port to operate */
930 ahci_scr_write(ap, SCR_ERROR, ahci_scr_read(ap, SCR_ERROR));
932 ahci_start_engine(port_mmio);
934 DPRINTK("EXIT, rc=%d, class=%u\n", rc, *class);
936 /* vt8251 doesn't clear BSY on signature FIS reception,
937 * request follow-up softreset.
939 return rc ?: -EAGAIN;
942 static void ahci_postreset(struct ata_port *ap, unsigned int *class)
944 void __iomem *port_mmio = (void __iomem *) ap->ioaddr.cmd_addr;
947 ata_std_postreset(ap, class);
949 /* Make sure port's ATAPI bit is set appropriately */
950 new_tmp = tmp = readl(port_mmio + PORT_CMD);
951 if (*class == ATA_DEV_ATAPI)
952 new_tmp |= PORT_CMD_ATAPI;
954 new_tmp &= ~PORT_CMD_ATAPI;
955 if (new_tmp != tmp) {
956 writel(new_tmp, port_mmio + PORT_CMD);
957 readl(port_mmio + PORT_CMD); /* flush */
961 static u8 ahci_check_status(struct ata_port *ap)
963 void __iomem *mmio = (void __iomem *) ap->ioaddr.cmd_addr;
965 return readl(mmio + PORT_TFDATA) & 0xFF;
968 static void ahci_tf_read(struct ata_port *ap, struct ata_taskfile *tf)
970 struct ahci_port_priv *pp = ap->private_data;
971 u8 *d2h_fis = pp->rx_fis + RX_FIS_D2H_REG;
973 ata_tf_from_fis(d2h_fis, tf);
976 static unsigned int ahci_fill_sg(struct ata_queued_cmd *qc, void *cmd_tbl)
978 struct scatterlist *sg;
979 struct ahci_sg *ahci_sg;
980 unsigned int n_sg = 0;
985 * Next, the S/G list.
987 ahci_sg = cmd_tbl + AHCI_CMD_TBL_HDR_SZ;
988 ata_for_each_sg(sg, qc) {
989 dma_addr_t addr = sg_dma_address(sg);
990 u32 sg_len = sg_dma_len(sg);
992 ahci_sg->addr = cpu_to_le32(addr & 0xffffffff);
993 ahci_sg->addr_hi = cpu_to_le32((addr >> 16) >> 16);
994 ahci_sg->flags_size = cpu_to_le32(sg_len - 1);
1003 static void ahci_qc_prep(struct ata_queued_cmd *qc)
1005 struct ata_port *ap = qc->ap;
1006 struct ahci_port_priv *pp = ap->private_data;
1007 int is_atapi = is_atapi_taskfile(&qc->tf);
1010 const u32 cmd_fis_len = 5; /* five dwords */
1011 unsigned int n_elem;
1014 * Fill in command table information. First, the header,
1015 * a SATA Register - Host to Device command FIS.
1017 cmd_tbl = pp->cmd_tbl + qc->tag * AHCI_CMD_TBL_SZ;
1019 ata_tf_to_fis(&qc->tf, cmd_tbl, 0);
1021 memset(cmd_tbl + AHCI_CMD_TBL_CDB, 0, 32);
1022 memcpy(cmd_tbl + AHCI_CMD_TBL_CDB, qc->cdb, qc->dev->cdb_len);
1026 if (qc->flags & ATA_QCFLAG_DMAMAP)
1027 n_elem = ahci_fill_sg(qc, cmd_tbl);
1030 * Fill in command slot information.
1032 opts = cmd_fis_len | n_elem << 16;
1033 if (qc->tf.flags & ATA_TFLAG_WRITE)
1034 opts |= AHCI_CMD_WRITE;
1036 opts |= AHCI_CMD_ATAPI | AHCI_CMD_PREFETCH;
1038 ahci_fill_cmd_slot(pp, qc->tag, opts);
1041 static void ahci_error_intr(struct ata_port *ap, u32 irq_stat)
1043 struct ahci_port_priv *pp = ap->private_data;
1044 struct ata_eh_info *ehi = &ap->eh_info;
1045 unsigned int err_mask = 0, action = 0;
1046 struct ata_queued_cmd *qc;
1049 ata_ehi_clear_desc(ehi);
1051 /* AHCI needs SError cleared; otherwise, it might lock up */
1052 serror = ahci_scr_read(ap, SCR_ERROR);
1053 ahci_scr_write(ap, SCR_ERROR, serror);
1055 /* analyze @irq_stat */
1056 ata_ehi_push_desc(ehi, "irq_stat 0x%08x", irq_stat);
1058 /* some controllers set IRQ_IF_ERR on device errors, ignore it */
1059 if (ap->flags & AHCI_FLAG_IGN_IRQ_IF_ERR)
1060 irq_stat &= ~PORT_IRQ_IF_ERR;
1062 if (irq_stat & PORT_IRQ_TF_ERR)
1063 err_mask |= AC_ERR_DEV;
1065 if (irq_stat & (PORT_IRQ_HBUS_ERR | PORT_IRQ_HBUS_DATA_ERR)) {
1066 err_mask |= AC_ERR_HOST_BUS;
1067 action |= ATA_EH_SOFTRESET;
1070 if (irq_stat & PORT_IRQ_IF_ERR) {
1071 err_mask |= AC_ERR_ATA_BUS;
1072 action |= ATA_EH_SOFTRESET;
1073 ata_ehi_push_desc(ehi, ", interface fatal error");
1076 if (irq_stat & (PORT_IRQ_CONNECT | PORT_IRQ_PHYRDY)) {
1077 ata_ehi_hotplugged(ehi);
1078 ata_ehi_push_desc(ehi, ", %s", irq_stat & PORT_IRQ_CONNECT ?
1079 "connection status changed" : "PHY RDY changed");
1082 if (irq_stat & PORT_IRQ_UNK_FIS) {
1083 u32 *unk = (u32 *)(pp->rx_fis + RX_FIS_UNK);
1085 err_mask |= AC_ERR_HSM;
1086 action |= ATA_EH_SOFTRESET;
1087 ata_ehi_push_desc(ehi, ", unknown FIS %08x %08x %08x %08x",
1088 unk[0], unk[1], unk[2], unk[3]);
1091 /* okay, let's hand over to EH */
1092 ehi->serror |= serror;
1093 ehi->action |= action;
1095 qc = ata_qc_from_tag(ap, ap->active_tag);
1097 qc->err_mask |= err_mask;
1099 ehi->err_mask |= err_mask;
1101 if (irq_stat & PORT_IRQ_FREEZE)
1102 ata_port_freeze(ap);
1107 static void ahci_host_intr(struct ata_port *ap)
1109 void __iomem *mmio = ap->host->mmio_base;
1110 void __iomem *port_mmio = ahci_port_base(mmio, ap->port_no);
1111 struct ata_eh_info *ehi = &ap->eh_info;
1112 u32 status, qc_active;
1115 status = readl(port_mmio + PORT_IRQ_STAT);
1116 writel(status, port_mmio + PORT_IRQ_STAT);
1118 if (unlikely(status & PORT_IRQ_ERROR)) {
1119 ahci_error_intr(ap, status);
1124 qc_active = readl(port_mmio + PORT_SCR_ACT);
1126 qc_active = readl(port_mmio + PORT_CMD_ISSUE);
1128 rc = ata_qc_complete_multiple(ap, qc_active, NULL);
1132 ehi->err_mask |= AC_ERR_HSM;
1133 ehi->action |= ATA_EH_SOFTRESET;
1134 ata_port_freeze(ap);
1138 /* hmmm... a spurious interupt */
1140 /* some devices send D2H reg with I bit set during NCQ command phase */
1141 if (ap->sactive && (status & PORT_IRQ_D2H_REG_FIS))
1144 /* ignore interim PIO setup fis interrupts */
1145 if (ata_tag_valid(ap->active_tag) && (status & PORT_IRQ_PIOS_FIS))
1148 if (ata_ratelimit())
1149 ata_port_printk(ap, KERN_INFO, "spurious interrupt "
1150 "(irq_stat 0x%x active_tag %d sactive 0x%x)\n",
1151 status, ap->active_tag, ap->sactive);
1154 static void ahci_irq_clear(struct ata_port *ap)
1159 static irqreturn_t ahci_interrupt(int irq, void *dev_instance)
1161 struct ata_host *host = dev_instance;
1162 struct ahci_host_priv *hpriv;
1163 unsigned int i, handled = 0;
1165 u32 irq_stat, irq_ack = 0;
1169 hpriv = host->private_data;
1170 mmio = host->mmio_base;
1172 /* sigh. 0xffffffff is a valid return from h/w */
1173 irq_stat = readl(mmio + HOST_IRQ_STAT);
1174 irq_stat &= hpriv->port_map;
1178 spin_lock(&host->lock);
1180 for (i = 0; i < host->n_ports; i++) {
1181 struct ata_port *ap;
1183 if (!(irq_stat & (1 << i)))
1186 ap = host->ports[i];
1189 VPRINTK("port %u\n", i);
1191 VPRINTK("port %u (no irq)\n", i);
1192 if (ata_ratelimit())
1193 dev_printk(KERN_WARNING, host->dev,
1194 "interrupt on disabled port %u\n", i);
1197 irq_ack |= (1 << i);
1201 writel(irq_ack, mmio + HOST_IRQ_STAT);
1205 spin_unlock(&host->lock);
1209 return IRQ_RETVAL(handled);
1212 static unsigned int ahci_qc_issue(struct ata_queued_cmd *qc)
1214 struct ata_port *ap = qc->ap;
1215 void __iomem *port_mmio = (void __iomem *) ap->ioaddr.cmd_addr;
1217 if (qc->tf.protocol == ATA_PROT_NCQ)
1218 writel(1 << qc->tag, port_mmio + PORT_SCR_ACT);
1219 writel(1 << qc->tag, port_mmio + PORT_CMD_ISSUE);
1220 readl(port_mmio + PORT_CMD_ISSUE); /* flush */
1225 static void ahci_freeze(struct ata_port *ap)
1227 void __iomem *mmio = ap->host->mmio_base;
1228 void __iomem *port_mmio = ahci_port_base(mmio, ap->port_no);
1231 writel(0, port_mmio + PORT_IRQ_MASK);
1234 static void ahci_thaw(struct ata_port *ap)
1236 void __iomem *mmio = ap->host->mmio_base;
1237 void __iomem *port_mmio = ahci_port_base(mmio, ap->port_no);
1241 tmp = readl(port_mmio + PORT_IRQ_STAT);
1242 writel(tmp, port_mmio + PORT_IRQ_STAT);
1243 writel(1 << ap->id, mmio + HOST_IRQ_STAT);
1245 /* turn IRQ back on */
1246 writel(DEF_PORT_IRQ, port_mmio + PORT_IRQ_MASK);
1249 static void ahci_error_handler(struct ata_port *ap)
1251 void __iomem *mmio = ap->host->mmio_base;
1252 void __iomem *port_mmio = ahci_port_base(mmio, ap->port_no);
1254 if (!(ap->pflags & ATA_PFLAG_FROZEN)) {
1255 /* restart engine */
1256 ahci_stop_engine(port_mmio);
1257 ahci_start_engine(port_mmio);
1260 /* perform recovery */
1261 ata_do_eh(ap, ata_std_prereset, ahci_softreset, ahci_hardreset,
1265 static void ahci_vt8251_error_handler(struct ata_port *ap)
1267 void __iomem *mmio = ap->host->mmio_base;
1268 void __iomem *port_mmio = ahci_port_base(mmio, ap->port_no);
1270 if (!(ap->pflags & ATA_PFLAG_FROZEN)) {
1271 /* restart engine */
1272 ahci_stop_engine(port_mmio);
1273 ahci_start_engine(port_mmio);
1276 /* perform recovery */
1277 ata_do_eh(ap, ata_std_prereset, ahci_softreset, ahci_vt8251_hardreset,
1281 static void ahci_post_internal_cmd(struct ata_queued_cmd *qc)
1283 struct ata_port *ap = qc->ap;
1284 void __iomem *mmio = ap->host->mmio_base;
1285 void __iomem *port_mmio = ahci_port_base(mmio, ap->port_no);
1287 if (qc->flags & ATA_QCFLAG_FAILED)
1288 qc->err_mask |= AC_ERR_OTHER;
1291 /* make DMA engine forget about the failed command */
1292 ahci_stop_engine(port_mmio);
1293 ahci_start_engine(port_mmio);
1297 static int ahci_port_suspend(struct ata_port *ap, pm_message_t mesg)
1299 struct ahci_host_priv *hpriv = ap->host->private_data;
1300 struct ahci_port_priv *pp = ap->private_data;
1301 void __iomem *mmio = ap->host->mmio_base;
1302 void __iomem *port_mmio = ahci_port_base(mmio, ap->port_no);
1303 const char *emsg = NULL;
1306 rc = ahci_deinit_port(port_mmio, hpriv->cap, &emsg);
1308 ahci_power_down(port_mmio, hpriv->cap);
1310 ata_port_printk(ap, KERN_ERR, "%s (%d)\n", emsg, rc);
1311 ahci_init_port(port_mmio, hpriv->cap,
1312 pp->cmd_slot_dma, pp->rx_fis_dma);
1318 static int ahci_port_resume(struct ata_port *ap)
1320 struct ahci_port_priv *pp = ap->private_data;
1321 struct ahci_host_priv *hpriv = ap->host->private_data;
1322 void __iomem *mmio = ap->host->mmio_base;
1323 void __iomem *port_mmio = ahci_port_base(mmio, ap->port_no);
1325 ahci_power_up(port_mmio, hpriv->cap);
1326 ahci_init_port(port_mmio, hpriv->cap, pp->cmd_slot_dma, pp->rx_fis_dma);
1331 static int ahci_pci_device_suspend(struct pci_dev *pdev, pm_message_t mesg)
1333 struct ata_host *host = dev_get_drvdata(&pdev->dev);
1334 void __iomem *mmio = host->mmio_base;
1337 if (mesg.event == PM_EVENT_SUSPEND) {
1338 /* AHCI spec rev1.1 section 8.3.3:
1339 * Software must disable interrupts prior to requesting a
1340 * transition of the HBA to D3 state.
1342 ctl = readl(mmio + HOST_CTL);
1343 ctl &= ~HOST_IRQ_EN;
1344 writel(ctl, mmio + HOST_CTL);
1345 readl(mmio + HOST_CTL); /* flush */
1348 return ata_pci_device_suspend(pdev, mesg);
1351 static int ahci_pci_device_resume(struct pci_dev *pdev)
1353 struct ata_host *host = dev_get_drvdata(&pdev->dev);
1354 struct ahci_host_priv *hpriv = host->private_data;
1355 void __iomem *mmio = host->mmio_base;
1358 ata_pci_device_do_resume(pdev);
1360 if (pdev->dev.power.power_state.event == PM_EVENT_SUSPEND) {
1361 rc = ahci_reset_controller(mmio, pdev);
1365 ahci_init_controller(mmio, pdev, host->n_ports,
1366 host->ports[0]->flags, hpriv);
1369 ata_host_resume(host);
1374 static int ahci_port_start(struct ata_port *ap)
1376 struct device *dev = ap->host->dev;
1377 struct ahci_host_priv *hpriv = ap->host->private_data;
1378 struct ahci_port_priv *pp;
1379 void __iomem *mmio = ap->host->mmio_base;
1380 void __iomem *port_mmio = ahci_port_base(mmio, ap->port_no);
1385 pp = kmalloc(sizeof(*pp), GFP_KERNEL);
1388 memset(pp, 0, sizeof(*pp));
1390 rc = ata_pad_alloc(ap, dev);
1396 mem = dma_alloc_coherent(dev, AHCI_PORT_PRIV_DMA_SZ, &mem_dma, GFP_KERNEL);
1398 ata_pad_free(ap, dev);
1402 memset(mem, 0, AHCI_PORT_PRIV_DMA_SZ);
1405 * First item in chunk of DMA memory: 32-slot command table,
1406 * 32 bytes each in size
1409 pp->cmd_slot_dma = mem_dma;
1411 mem += AHCI_CMD_SLOT_SZ;
1412 mem_dma += AHCI_CMD_SLOT_SZ;
1415 * Second item: Received-FIS area
1418 pp->rx_fis_dma = mem_dma;
1420 mem += AHCI_RX_FIS_SZ;
1421 mem_dma += AHCI_RX_FIS_SZ;
1424 * Third item: data area for storing a single command
1425 * and its scatter-gather table
1428 pp->cmd_tbl_dma = mem_dma;
1430 ap->private_data = pp;
1433 ahci_power_up(port_mmio, hpriv->cap);
1435 /* initialize port */
1436 ahci_init_port(port_mmio, hpriv->cap, pp->cmd_slot_dma, pp->rx_fis_dma);
1441 static void ahci_port_stop(struct ata_port *ap)
1443 struct device *dev = ap->host->dev;
1444 struct ahci_host_priv *hpriv = ap->host->private_data;
1445 struct ahci_port_priv *pp = ap->private_data;
1446 void __iomem *mmio = ap->host->mmio_base;
1447 void __iomem *port_mmio = ahci_port_base(mmio, ap->port_no);
1448 const char *emsg = NULL;
1451 /* de-initialize port */
1452 rc = ahci_deinit_port(port_mmio, hpriv->cap, &emsg);
1454 ata_port_printk(ap, KERN_WARNING, "%s (%d)\n", emsg, rc);
1456 ap->private_data = NULL;
1457 dma_free_coherent(dev, AHCI_PORT_PRIV_DMA_SZ,
1458 pp->cmd_slot, pp->cmd_slot_dma);
1459 ata_pad_free(ap, dev);
1463 static void ahci_setup_port(struct ata_ioports *port, unsigned long base,
1464 unsigned int port_idx)
1466 VPRINTK("ENTER, base==0x%lx, port_idx %u\n", base, port_idx);
1467 base = ahci_port_base_ul(base, port_idx);
1468 VPRINTK("base now==0x%lx\n", base);
1470 port->cmd_addr = base;
1471 port->scr_addr = base + PORT_SCR;
1476 static int ahci_host_init(struct ata_probe_ent *probe_ent)
1478 struct ahci_host_priv *hpriv = probe_ent->private_data;
1479 struct pci_dev *pdev = to_pci_dev(probe_ent->dev);
1480 void __iomem *mmio = probe_ent->mmio_base;
1481 unsigned int i, cap_n_ports, using_dac;
1484 rc = ahci_reset_controller(mmio, pdev);
1488 hpriv->cap = readl(mmio + HOST_CAP);
1489 hpriv->port_map = readl(mmio + HOST_PORTS_IMPL);
1490 cap_n_ports = ahci_nr_ports(hpriv->cap);
1492 VPRINTK("cap 0x%x port_map 0x%x n_ports %d\n",
1493 hpriv->cap, hpriv->port_map, cap_n_ports);
1495 if (probe_ent->port_flags & AHCI_FLAG_HONOR_PI) {
1496 unsigned int n_ports = cap_n_ports;
1497 u32 port_map = hpriv->port_map;
1500 for (i = 0; i < AHCI_MAX_PORTS && n_ports; i++) {
1501 if (port_map & (1 << i)) {
1503 port_map &= ~(1 << i);
1506 probe_ent->dummy_port_mask |= 1 << i;
1509 if (n_ports || port_map)
1510 dev_printk(KERN_WARNING, &pdev->dev,
1511 "nr_ports (%u) and implemented port map "
1512 "(0x%x) don't match\n",
1513 cap_n_ports, hpriv->port_map);
1515 probe_ent->n_ports = max_port + 1;
1517 probe_ent->n_ports = cap_n_ports;
1519 using_dac = hpriv->cap & HOST_CAP_64;
1521 !pci_set_dma_mask(pdev, DMA_64BIT_MASK)) {
1522 rc = pci_set_consistent_dma_mask(pdev, DMA_64BIT_MASK);
1524 rc = pci_set_consistent_dma_mask(pdev, DMA_32BIT_MASK);
1526 dev_printk(KERN_ERR, &pdev->dev,
1527 "64-bit DMA enable failed\n");
1532 rc = pci_set_dma_mask(pdev, DMA_32BIT_MASK);
1534 dev_printk(KERN_ERR, &pdev->dev,
1535 "32-bit DMA enable failed\n");
1538 rc = pci_set_consistent_dma_mask(pdev, DMA_32BIT_MASK);
1540 dev_printk(KERN_ERR, &pdev->dev,
1541 "32-bit consistent DMA enable failed\n");
1546 for (i = 0; i < probe_ent->n_ports; i++)
1547 ahci_setup_port(&probe_ent->port[i], (unsigned long) mmio, i);
1549 ahci_init_controller(mmio, pdev, probe_ent->n_ports,
1550 probe_ent->port_flags, hpriv);
1552 pci_set_master(pdev);
1557 static void ahci_print_info(struct ata_probe_ent *probe_ent)
1559 struct ahci_host_priv *hpriv = probe_ent->private_data;
1560 struct pci_dev *pdev = to_pci_dev(probe_ent->dev);
1561 void __iomem *mmio = probe_ent->mmio_base;
1562 u32 vers, cap, impl, speed;
1563 const char *speed_s;
1567 vers = readl(mmio + HOST_VERSION);
1569 impl = hpriv->port_map;
1571 speed = (cap >> 20) & 0xf;
1574 else if (speed == 2)
1579 pci_read_config_word(pdev, 0x0a, &cc);
1582 else if (cc == 0x0106)
1584 else if (cc == 0x0104)
1589 dev_printk(KERN_INFO, &pdev->dev,
1590 "AHCI %02x%02x.%02x%02x "
1591 "%u slots %u ports %s Gbps 0x%x impl %s mode\n"
1594 (vers >> 24) & 0xff,
1595 (vers >> 16) & 0xff,
1599 ((cap >> 8) & 0x1f) + 1,
1605 dev_printk(KERN_INFO, &pdev->dev,
1611 cap & (1 << 31) ? "64bit " : "",
1612 cap & (1 << 30) ? "ncq " : "",
1613 cap & (1 << 28) ? "ilck " : "",
1614 cap & (1 << 27) ? "stag " : "",
1615 cap & (1 << 26) ? "pm " : "",
1616 cap & (1 << 25) ? "led " : "",
1618 cap & (1 << 24) ? "clo " : "",
1619 cap & (1 << 19) ? "nz " : "",
1620 cap & (1 << 18) ? "only " : "",
1621 cap & (1 << 17) ? "pmp " : "",
1622 cap & (1 << 15) ? "pio " : "",
1623 cap & (1 << 14) ? "slum " : "",
1624 cap & (1 << 13) ? "part " : ""
1628 static int ahci_init_one (struct pci_dev *pdev, const struct pci_device_id *ent)
1630 static int printed_version;
1631 struct ata_probe_ent *probe_ent = NULL;
1632 struct ahci_host_priv *hpriv;
1634 void __iomem *mmio_base;
1635 unsigned int board_idx = (unsigned int) ent->driver_data;
1636 int have_msi, pci_dev_busy = 0;
1641 WARN_ON(ATA_MAX_QUEUE > AHCI_MAX_CMDS);
1643 if (!printed_version++)
1644 dev_printk(KERN_DEBUG, &pdev->dev, "version " DRV_VERSION "\n");
1646 /* JMicron-specific fixup: make sure we're in AHCI mode */
1647 /* This is protected from races with ata_jmicron by the pci probe
1649 if (pdev->vendor == PCI_VENDOR_ID_JMICRON) {
1650 /* AHCI enable, AHCI on function 0 */
1651 pci_write_config_byte(pdev, 0x41, 0xa1);
1652 /* Function 1 is the PATA controller */
1653 if (PCI_FUNC(pdev->devfn))
1657 rc = pci_enable_device(pdev);
1661 rc = pci_request_regions(pdev, DRV_NAME);
1667 if (pci_enable_msi(pdev) == 0)
1674 probe_ent = kmalloc(sizeof(*probe_ent), GFP_KERNEL);
1675 if (probe_ent == NULL) {
1680 memset(probe_ent, 0, sizeof(*probe_ent));
1681 probe_ent->dev = pci_dev_to_dev(pdev);
1682 INIT_LIST_HEAD(&probe_ent->node);
1684 mmio_base = pci_iomap(pdev, AHCI_PCI_BAR, 0);
1685 if (mmio_base == NULL) {
1687 goto err_out_free_ent;
1689 base = (unsigned long) mmio_base;
1691 hpriv = kmalloc(sizeof(*hpriv), GFP_KERNEL);
1694 goto err_out_iounmap;
1696 memset(hpriv, 0, sizeof(*hpriv));
1698 probe_ent->sht = ahci_port_info[board_idx].sht;
1699 probe_ent->port_flags = ahci_port_info[board_idx].flags;
1700 probe_ent->pio_mask = ahci_port_info[board_idx].pio_mask;
1701 probe_ent->udma_mask = ahci_port_info[board_idx].udma_mask;
1702 probe_ent->port_ops = ahci_port_info[board_idx].port_ops;
1704 probe_ent->irq = pdev->irq;
1705 probe_ent->irq_flags = IRQF_SHARED;
1706 probe_ent->mmio_base = mmio_base;
1707 probe_ent->private_data = hpriv;
1710 hpriv->flags |= AHCI_FLAG_MSI;
1712 /* initialize adapter */
1713 rc = ahci_host_init(probe_ent);
1717 if (!(probe_ent->port_flags & AHCI_FLAG_NO_NCQ) &&
1718 (hpriv->cap & HOST_CAP_NCQ))
1719 probe_ent->port_flags |= ATA_FLAG_NCQ;
1721 ahci_print_info(probe_ent);
1723 /* FIXME: check ata_device_add return value */
1724 ata_device_add(probe_ent);
1732 pci_iounmap(pdev, mmio_base);
1737 pci_disable_msi(pdev);
1740 pci_release_regions(pdev);
1743 pci_disable_device(pdev);
1747 static void ahci_remove_one (struct pci_dev *pdev)
1749 struct device *dev = pci_dev_to_dev(pdev);
1750 struct ata_host *host = dev_get_drvdata(dev);
1751 struct ahci_host_priv *hpriv = host->private_data;
1755 for (i = 0; i < host->n_ports; i++)
1756 ata_port_detach(host->ports[i]);
1758 have_msi = hpriv->flags & AHCI_FLAG_MSI;
1759 free_irq(host->irq, host);
1761 for (i = 0; i < host->n_ports; i++) {
1762 struct ata_port *ap = host->ports[i];
1764 ata_scsi_release(ap->scsi_host);
1765 scsi_host_put(ap->scsi_host);
1769 pci_iounmap(pdev, host->mmio_base);
1773 pci_disable_msi(pdev);
1776 pci_release_regions(pdev);
1777 pci_disable_device(pdev);
1778 dev_set_drvdata(dev, NULL);
1781 static int __init ahci_init(void)
1783 return pci_register_driver(&ahci_pci_driver);
1786 static void __exit ahci_exit(void)
1788 pci_unregister_driver(&ahci_pci_driver);
1792 MODULE_AUTHOR("Jeff Garzik");
1793 MODULE_DESCRIPTION("AHCI SATA low-level driver");
1794 MODULE_LICENSE("GPL");
1795 MODULE_DEVICE_TABLE(pci, ahci_pci_tbl);
1796 MODULE_VERSION(DRV_VERSION);
1798 module_init(ahci_init);
1799 module_exit(ahci_exit);