2 * processor_idle - idle state submodule to the ACPI processor driver
4 * Copyright (C) 2001, 2002 Andy Grover <andrew.grover@intel.com>
5 * Copyright (C) 2001, 2002 Paul Diefenbaugh <paul.s.diefenbaugh@intel.com>
6 * Copyright (C) 2004, 2005 Dominik Brodowski <linux@brodo.de>
7 * Copyright (C) 2004 Anil S Keshavamurthy <anil.s.keshavamurthy@intel.com>
8 * - Added processor hotplug support
9 * Copyright (C) 2005 Venkatesh Pallipadi <venkatesh.pallipadi@intel.com>
10 * - Added support for C3 on SMP
12 * ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
14 * This program is free software; you can redistribute it and/or modify
15 * it under the terms of the GNU General Public License as published by
16 * the Free Software Foundation; either version 2 of the License, or (at
17 * your option) any later version.
19 * This program is distributed in the hope that it will be useful, but
20 * WITHOUT ANY WARRANTY; without even the implied warranty of
21 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
22 * General Public License for more details.
24 * You should have received a copy of the GNU General Public License along
25 * with this program; if not, write to the Free Software Foundation, Inc.,
26 * 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA.
28 * ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
31 #include <linux/kernel.h>
32 #include <linux/module.h>
33 #include <linux/init.h>
34 #include <linux/cpufreq.h>
35 #include <linux/proc_fs.h>
36 #include <linux/seq_file.h>
37 #include <linux/acpi.h>
38 #include <linux/dmi.h>
39 #include <linux/moduleparam.h>
40 #include <linux/sched.h> /* need_resched() */
41 #include <linux/latency.h>
42 #include <linux/clockchips.h>
43 #include <linux/cpuidle.h>
46 * Include the apic definitions for x86 to have the APIC timer related defines
47 * available also for UP (on SMP it gets magically included via linux/smp.h).
48 * asm/acpi.h is not an option, as it would require more include magic. Also
49 * creating an empty asm-ia64/apic.h would just trade pest vs. cholera.
56 #include <asm/uaccess.h>
58 #include <acpi/acpi_bus.h>
59 #include <acpi/processor.h>
61 #define ACPI_PROCESSOR_COMPONENT 0x01000000
62 #define ACPI_PROCESSOR_CLASS "processor"
63 #define _COMPONENT ACPI_PROCESSOR_COMPONENT
64 ACPI_MODULE_NAME("processor_idle");
65 #define ACPI_PROCESSOR_FILE_POWER "power"
66 #define US_TO_PM_TIMER_TICKS(t) ((t * (PM_TIMER_FREQUENCY/1000)) / 1000)
67 #define PM_TIMER_TICK_NS (1000000000ULL/PM_TIMER_FREQUENCY)
68 #ifndef CONFIG_CPU_IDLE
69 #define C2_OVERHEAD 4 /* 1us (3.579 ticks per us) */
70 #define C3_OVERHEAD 4 /* 1us (3.579 ticks per us) */
71 static void (*pm_idle_save) (void) __read_mostly;
73 #define C2_OVERHEAD 1 /* 1us */
74 #define C3_OVERHEAD 1 /* 1us */
76 #define PM_TIMER_TICKS_TO_US(p) (((p) * 1000)/(PM_TIMER_FREQUENCY/1000))
78 static unsigned int max_cstate __read_mostly = ACPI_PROCESSOR_MAX_POWER;
79 #ifdef CONFIG_CPU_IDLE
80 module_param(max_cstate, uint, 0000);
82 module_param(max_cstate, uint, 0644);
84 static unsigned int nocst __read_mostly;
85 module_param(nocst, uint, 0000);
87 #ifndef CONFIG_CPU_IDLE
89 * bm_history -- bit-mask with a bit per jiffy of bus-master activity
90 * 1000 HZ: 0xFFFFFFFF: 32 jiffies = 32ms
91 * 800 HZ: 0xFFFFFFFF: 32 jiffies = 40ms
92 * 100 HZ: 0x0000000F: 4 jiffies = 40ms
93 * reduce history for more aggressive entry into C3
95 static unsigned int bm_history __read_mostly =
96 (HZ >= 800 ? 0xFFFFFFFF : ((1U << (HZ / 25)) - 1));
97 module_param(bm_history, uint, 0644);
99 static int acpi_processor_set_power_policy(struct acpi_processor *pr);
104 * IBM ThinkPad R40e crashes mysteriously when going into C2 or C3.
105 * For now disable this. Probably a bug somewhere else.
107 * To skip this limit, boot/load with a large max_cstate limit.
109 static int set_max_cstate(const struct dmi_system_id *id)
111 if (max_cstate > ACPI_PROCESSOR_MAX_POWER)
114 printk(KERN_NOTICE PREFIX "%s detected - limiting to C%ld max_cstate."
115 " Override with \"processor.max_cstate=%d\"\n", id->ident,
116 (long)id->driver_data, ACPI_PROCESSOR_MAX_POWER + 1);
118 max_cstate = (long)id->driver_data;
123 /* Actually this shouldn't be __cpuinitdata, would be better to fix the
124 callers to only run once -AK */
125 static struct dmi_system_id __cpuinitdata processor_power_dmi_table[] = {
126 { set_max_cstate, "IBM ThinkPad R40e", {
127 DMI_MATCH(DMI_BIOS_VENDOR,"IBM"),
128 DMI_MATCH(DMI_BIOS_VERSION,"1SET70WW")}, (void *)1},
129 { set_max_cstate, "IBM ThinkPad R40e", {
130 DMI_MATCH(DMI_BIOS_VENDOR,"IBM"),
131 DMI_MATCH(DMI_BIOS_VERSION,"1SET60WW")}, (void *)1},
132 { set_max_cstate, "IBM ThinkPad R40e", {
133 DMI_MATCH(DMI_BIOS_VENDOR,"IBM"),
134 DMI_MATCH(DMI_BIOS_VERSION,"1SET43WW") }, (void*)1},
135 { set_max_cstate, "IBM ThinkPad R40e", {
136 DMI_MATCH(DMI_BIOS_VENDOR,"IBM"),
137 DMI_MATCH(DMI_BIOS_VERSION,"1SET45WW") }, (void*)1},
138 { set_max_cstate, "IBM ThinkPad R40e", {
139 DMI_MATCH(DMI_BIOS_VENDOR,"IBM"),
140 DMI_MATCH(DMI_BIOS_VERSION,"1SET47WW") }, (void*)1},
141 { set_max_cstate, "IBM ThinkPad R40e", {
142 DMI_MATCH(DMI_BIOS_VENDOR,"IBM"),
143 DMI_MATCH(DMI_BIOS_VERSION,"1SET50WW") }, (void*)1},
144 { set_max_cstate, "IBM ThinkPad R40e", {
145 DMI_MATCH(DMI_BIOS_VENDOR,"IBM"),
146 DMI_MATCH(DMI_BIOS_VERSION,"1SET52WW") }, (void*)1},
147 { set_max_cstate, "IBM ThinkPad R40e", {
148 DMI_MATCH(DMI_BIOS_VENDOR,"IBM"),
149 DMI_MATCH(DMI_BIOS_VERSION,"1SET55WW") }, (void*)1},
150 { set_max_cstate, "IBM ThinkPad R40e", {
151 DMI_MATCH(DMI_BIOS_VENDOR,"IBM"),
152 DMI_MATCH(DMI_BIOS_VERSION,"1SET56WW") }, (void*)1},
153 { set_max_cstate, "IBM ThinkPad R40e", {
154 DMI_MATCH(DMI_BIOS_VENDOR,"IBM"),
155 DMI_MATCH(DMI_BIOS_VERSION,"1SET59WW") }, (void*)1},
156 { set_max_cstate, "IBM ThinkPad R40e", {
157 DMI_MATCH(DMI_BIOS_VENDOR,"IBM"),
158 DMI_MATCH(DMI_BIOS_VERSION,"1SET60WW") }, (void*)1},
159 { set_max_cstate, "IBM ThinkPad R40e", {
160 DMI_MATCH(DMI_BIOS_VENDOR,"IBM"),
161 DMI_MATCH(DMI_BIOS_VERSION,"1SET61WW") }, (void*)1},
162 { set_max_cstate, "IBM ThinkPad R40e", {
163 DMI_MATCH(DMI_BIOS_VENDOR,"IBM"),
164 DMI_MATCH(DMI_BIOS_VERSION,"1SET62WW") }, (void*)1},
165 { set_max_cstate, "IBM ThinkPad R40e", {
166 DMI_MATCH(DMI_BIOS_VENDOR,"IBM"),
167 DMI_MATCH(DMI_BIOS_VERSION,"1SET64WW") }, (void*)1},
168 { set_max_cstate, "IBM ThinkPad R40e", {
169 DMI_MATCH(DMI_BIOS_VENDOR,"IBM"),
170 DMI_MATCH(DMI_BIOS_VERSION,"1SET65WW") }, (void*)1},
171 { set_max_cstate, "IBM ThinkPad R40e", {
172 DMI_MATCH(DMI_BIOS_VENDOR,"IBM"),
173 DMI_MATCH(DMI_BIOS_VERSION,"1SET68WW") }, (void*)1},
174 { set_max_cstate, "Medion 41700", {
175 DMI_MATCH(DMI_BIOS_VENDOR,"Phoenix Technologies LTD"),
176 DMI_MATCH(DMI_BIOS_VERSION,"R01-A1J")}, (void *)1},
177 { set_max_cstate, "Clevo 5600D", {
178 DMI_MATCH(DMI_BIOS_VENDOR,"Phoenix Technologies LTD"),
179 DMI_MATCH(DMI_BIOS_VERSION,"SHE845M0.86C.0013.D.0302131307")},
184 static inline u32 ticks_elapsed(u32 t1, u32 t2)
188 else if (!(acpi_gbl_FADT.flags & ACPI_FADT_32BIT_TIMER))
189 return (((0x00FFFFFF - t1) + t2) & 0x00FFFFFF);
191 return ((0xFFFFFFFF - t1) + t2);
194 static inline u32 ticks_elapsed_in_us(u32 t1, u32 t2)
197 return PM_TIMER_TICKS_TO_US(t2 - t1);
198 else if (!(acpi_gbl_FADT.flags & ACPI_FADT_32BIT_TIMER))
199 return PM_TIMER_TICKS_TO_US(((0x00FFFFFF - t1) + t2) & 0x00FFFFFF);
201 return PM_TIMER_TICKS_TO_US((0xFFFFFFFF - t1) + t2);
204 static void acpi_safe_halt(void)
206 current_thread_info()->status &= ~TS_POLLING;
208 * TS_POLLING-cleared state must be visible before we
214 current_thread_info()->status |= TS_POLLING;
217 #ifndef CONFIG_CPU_IDLE
220 acpi_processor_power_activate(struct acpi_processor *pr,
221 struct acpi_processor_cx *new)
223 struct acpi_processor_cx *old;
228 old = pr->power.state;
231 old->promotion.count = 0;
232 new->demotion.count = 0;
234 /* Cleanup from old state. */
238 /* Disable bus master reload */
239 if (new->type != ACPI_STATE_C3 && pr->flags.bm_check)
240 acpi_set_register(ACPI_BITREG_BUS_MASTER_RLD, 0);
245 /* Prepare to use new state. */
248 /* Enable bus master reload */
249 if (old->type != ACPI_STATE_C3 && pr->flags.bm_check)
250 acpi_set_register(ACPI_BITREG_BUS_MASTER_RLD, 1);
254 pr->power.state = new;
259 static atomic_t c3_cpu_count;
261 /* Common C-state entry for C2, C3, .. */
262 static void acpi_cstate_enter(struct acpi_processor_cx *cstate)
264 if (cstate->space_id == ACPI_CSTATE_FFH) {
265 /* Call into architectural FFH based C-state */
266 acpi_processor_ffh_cstate_enter(cstate);
269 /* IO port based C-state */
270 inb(cstate->address);
271 /* Dummy wait op - must do something useless after P_LVL2 read
272 because chipsets cannot guarantee that STPCLK# signal
273 gets asserted in time to freeze execution properly. */
274 unused = inl(acpi_gbl_FADT.xpm_timer_block.address);
277 #endif /* !CONFIG_CPU_IDLE */
279 #ifdef ARCH_APICTIMER_STOPS_ON_C3
282 * Some BIOS implementations switch to C3 in the published C2 state.
283 * This seems to be a common problem on AMD boxen, but other vendors
284 * are affected too. We pick the most conservative approach: we assume
285 * that the local APIC stops in both C2 and C3.
287 static void acpi_timer_check_state(int state, struct acpi_processor *pr,
288 struct acpi_processor_cx *cx)
290 struct acpi_processor_power *pwr = &pr->power;
291 u8 type = local_apic_timer_c2_ok ? ACPI_STATE_C3 : ACPI_STATE_C2;
294 * Check, if one of the previous states already marked the lapic
297 if (pwr->timer_broadcast_on_state < state)
300 if (cx->type >= type)
301 pr->power.timer_broadcast_on_state = state;
304 static void acpi_propagate_timer_broadcast(struct acpi_processor *pr)
306 unsigned long reason;
308 reason = pr->power.timer_broadcast_on_state < INT_MAX ?
309 CLOCK_EVT_NOTIFY_BROADCAST_ON : CLOCK_EVT_NOTIFY_BROADCAST_OFF;
311 clockevents_notify(reason, &pr->id);
314 /* Power(C) State timer broadcast control */
315 static void acpi_state_timer_broadcast(struct acpi_processor *pr,
316 struct acpi_processor_cx *cx,
319 int state = cx - pr->power.states;
321 if (state >= pr->power.timer_broadcast_on_state) {
322 unsigned long reason;
324 reason = broadcast ? CLOCK_EVT_NOTIFY_BROADCAST_ENTER :
325 CLOCK_EVT_NOTIFY_BROADCAST_EXIT;
326 clockevents_notify(reason, &pr->id);
332 static void acpi_timer_check_state(int state, struct acpi_processor *pr,
333 struct acpi_processor_cx *cstate) { }
334 static void acpi_propagate_timer_broadcast(struct acpi_processor *pr) { }
335 static void acpi_state_timer_broadcast(struct acpi_processor *pr,
336 struct acpi_processor_cx *cx,
344 * Suspend / resume control
346 static int acpi_idle_suspend;
348 int acpi_processor_suspend(struct acpi_device * device, pm_message_t state)
350 acpi_idle_suspend = 1;
354 int acpi_processor_resume(struct acpi_device * device)
356 acpi_idle_suspend = 0;
360 #ifndef CONFIG_CPU_IDLE
361 static void acpi_processor_idle(void)
363 struct acpi_processor *pr = NULL;
364 struct acpi_processor_cx *cx = NULL;
365 struct acpi_processor_cx *next_state = NULL;
370 * Interrupts must be disabled during bus mastering calculations and
371 * for C2/C3 transitions.
375 pr = processors[smp_processor_id()];
382 * Check whether we truly need to go idle, or should
385 if (unlikely(need_resched())) {
390 cx = pr->power.state;
391 if (!cx || acpi_idle_suspend) {
402 * Check for bus mastering activity (if required), record, and check
405 if (pr->flags.bm_check) {
407 unsigned long diff = jiffies - pr->power.bm_check_timestamp;
412 pr->power.bm_activity <<= diff;
414 acpi_get_register(ACPI_BITREG_BUS_MASTER_STATUS, &bm_status);
416 pr->power.bm_activity |= 0x1;
417 acpi_set_register(ACPI_BITREG_BUS_MASTER_STATUS, 1);
420 * PIIX4 Erratum #18: Note that BM_STS doesn't always reflect
421 * the true state of bus mastering activity; forcing us to
422 * manually check the BMIDEA bit of each IDE channel.
424 else if (errata.piix4.bmisx) {
425 if ((inb_p(errata.piix4.bmisx + 0x02) & 0x01)
426 || (inb_p(errata.piix4.bmisx + 0x0A) & 0x01))
427 pr->power.bm_activity |= 0x1;
430 pr->power.bm_check_timestamp = jiffies;
433 * If bus mastering is or was active this jiffy, demote
434 * to avoid a faulty transition. Note that the processor
435 * won't enter a low-power state during this call (to this
436 * function) but should upon the next.
438 * TBD: A better policy might be to fallback to the demotion
439 * state (use it for this quantum only) istead of
440 * demoting -- and rely on duration as our sole demotion
441 * qualification. This may, however, introduce DMA
442 * issues (e.g. floppy DMA transfer overrun/underrun).
444 if ((pr->power.bm_activity & 0x1) &&
445 cx->demotion.threshold.bm) {
447 next_state = cx->demotion.state;
452 #ifdef CONFIG_HOTPLUG_CPU
454 * Check for P_LVL2_UP flag before entering C2 and above on
455 * an SMP system. We do it here instead of doing it at _CST/P_LVL
456 * detection phase, to work cleanly with logical CPU hotplug.
458 if ((cx->type != ACPI_STATE_C1) && (num_online_cpus() > 1) &&
459 !pr->flags.has_cst && !(acpi_gbl_FADT.flags & ACPI_FADT_C2_MP_SUPPORTED))
460 cx = &pr->power.states[ACPI_STATE_C1];
466 * Invoke the current Cx state to put the processor to sleep.
468 if (cx->type == ACPI_STATE_C2 || cx->type == ACPI_STATE_C3) {
469 current_thread_info()->status &= ~TS_POLLING;
471 * TS_POLLING-cleared state must be visible before we
475 if (need_resched()) {
476 current_thread_info()->status |= TS_POLLING;
487 * Use the appropriate idle routine, the one that would
488 * be used without acpi C-states.
496 * TBD: Can't get time duration while in C1, as resumes
497 * go to an ISR rather than here. Need to instrument
498 * base interrupt handler.
500 * Note: the TSC better not stop in C1, sched_clock() will
503 sleep_ticks = 0xFFFFFFFF;
507 /* Get start time (ticks) */
508 t1 = inl(acpi_gbl_FADT.xpm_timer_block.address);
509 /* Tell the scheduler that we are going deep-idle: */
510 sched_clock_idle_sleep_event();
512 acpi_state_timer_broadcast(pr, cx, 1);
513 acpi_cstate_enter(cx);
514 /* Get end time (ticks) */
515 t2 = inl(acpi_gbl_FADT.xpm_timer_block.address);
517 #if defined (CONFIG_GENERIC_TIME) && defined (CONFIG_X86_TSC)
518 /* TSC halts in C2, so notify users */
519 mark_tsc_unstable("possible TSC halt in C2");
521 /* Compute time (ticks) that we were actually asleep */
522 sleep_ticks = ticks_elapsed(t1, t2);
524 /* Tell the scheduler how much we idled: */
525 sched_clock_idle_wakeup_event(sleep_ticks*PM_TIMER_TICK_NS);
527 /* Re-enable interrupts */
529 /* Do not account our idle-switching overhead: */
530 sleep_ticks -= cx->latency_ticks + C2_OVERHEAD;
532 current_thread_info()->status |= TS_POLLING;
533 acpi_state_timer_broadcast(pr, cx, 0);
537 acpi_unlazy_tlb(smp_processor_id());
539 * Must be done before busmaster disable as we might
540 * need to access HPET !
542 acpi_state_timer_broadcast(pr, cx, 1);
545 * bm_check implies we need ARB_DIS
546 * !bm_check implies we need cache flush
547 * bm_control implies whether we can do ARB_DIS
549 * That leaves a case where bm_check is set and bm_control is
550 * not set. In that case we cannot do much, we enter C3
551 * without doing anything.
553 if (pr->flags.bm_check && pr->flags.bm_control) {
554 if (atomic_inc_return(&c3_cpu_count) ==
557 * All CPUs are trying to go to C3
558 * Disable bus master arbitration
560 acpi_set_register(ACPI_BITREG_ARB_DISABLE, 1);
562 } else if (!pr->flags.bm_check) {
563 /* SMP with no shared cache... Invalidate cache */
564 ACPI_FLUSH_CPU_CACHE();
567 /* Get start time (ticks) */
568 t1 = inl(acpi_gbl_FADT.xpm_timer_block.address);
570 /* Tell the scheduler that we are going deep-idle: */
571 sched_clock_idle_sleep_event();
572 acpi_cstate_enter(cx);
573 /* Get end time (ticks) */
574 t2 = inl(acpi_gbl_FADT.xpm_timer_block.address);
575 if (pr->flags.bm_check && pr->flags.bm_control) {
576 /* Enable bus master arbitration */
577 atomic_dec(&c3_cpu_count);
578 acpi_set_register(ACPI_BITREG_ARB_DISABLE, 0);
581 #if defined (CONFIG_GENERIC_TIME) && defined (CONFIG_X86_TSC)
582 /* TSC halts in C3, so notify users */
583 mark_tsc_unstable("TSC halts in C3");
585 /* Compute time (ticks) that we were actually asleep */
586 sleep_ticks = ticks_elapsed(t1, t2);
587 /* Tell the scheduler how much we idled: */
588 sched_clock_idle_wakeup_event(sleep_ticks*PM_TIMER_TICK_NS);
590 /* Re-enable interrupts */
592 /* Do not account our idle-switching overhead: */
593 sleep_ticks -= cx->latency_ticks + C3_OVERHEAD;
595 current_thread_info()->status |= TS_POLLING;
596 acpi_state_timer_broadcast(pr, cx, 0);
604 if ((cx->type != ACPI_STATE_C1) && (sleep_ticks > 0))
605 cx->time += sleep_ticks;
607 next_state = pr->power.state;
609 #ifdef CONFIG_HOTPLUG_CPU
610 /* Don't do promotion/demotion */
611 if ((cx->type == ACPI_STATE_C1) && (num_online_cpus() > 1) &&
612 !pr->flags.has_cst && !(acpi_gbl_FADT.flags & ACPI_FADT_C2_MP_SUPPORTED)) {
621 * Track the number of longs (time asleep is greater than threshold)
622 * and promote when the count threshold is reached. Note that bus
623 * mastering activity may prevent promotions.
624 * Do not promote above max_cstate.
626 if (cx->promotion.state &&
627 ((cx->promotion.state - pr->power.states) <= max_cstate)) {
628 if (sleep_ticks > cx->promotion.threshold.ticks &&
629 cx->promotion.state->latency <= system_latency_constraint()) {
630 cx->promotion.count++;
631 cx->demotion.count = 0;
632 if (cx->promotion.count >=
633 cx->promotion.threshold.count) {
634 if (pr->flags.bm_check) {
636 (pr->power.bm_activity & cx->
637 promotion.threshold.bm)) {
643 next_state = cx->promotion.state;
653 * Track the number of shorts (time asleep is less than time threshold)
654 * and demote when the usage threshold is reached.
656 if (cx->demotion.state) {
657 if (sleep_ticks < cx->demotion.threshold.ticks) {
658 cx->demotion.count++;
659 cx->promotion.count = 0;
660 if (cx->demotion.count >= cx->demotion.threshold.count) {
661 next_state = cx->demotion.state;
669 * Demote if current state exceeds max_cstate
670 * or if the latency of the current state is unacceptable
672 if ((pr->power.state - pr->power.states) > max_cstate ||
673 pr->power.state->latency > system_latency_constraint()) {
674 if (cx->demotion.state)
675 next_state = cx->demotion.state;
681 * If we're going to start using a new Cx state we must clean up
682 * from the previous and prepare to use the new.
684 if (next_state != pr->power.state)
685 acpi_processor_power_activate(pr, next_state);
688 static int acpi_processor_set_power_policy(struct acpi_processor *pr)
691 unsigned int state_is_set = 0;
692 struct acpi_processor_cx *lower = NULL;
693 struct acpi_processor_cx *higher = NULL;
694 struct acpi_processor_cx *cx;
701 * This function sets the default Cx state policy (OS idle handler).
702 * Our scheme is to promote quickly to C2 but more conservatively
703 * to C3. We're favoring C2 for its characteristics of low latency
704 * (quick response), good power savings, and ability to allow bus
705 * mastering activity. Note that the Cx state policy is completely
706 * customizable and can be altered dynamically.
710 for (i = 1; i < ACPI_PROCESSOR_MAX_POWER; i++) {
711 cx = &pr->power.states[i];
716 pr->power.state = cx;
725 for (i = 1; i < ACPI_PROCESSOR_MAX_POWER; i++) {
726 cx = &pr->power.states[i];
731 cx->demotion.state = lower;
732 cx->demotion.threshold.ticks = cx->latency_ticks;
733 cx->demotion.threshold.count = 1;
734 if (cx->type == ACPI_STATE_C3)
735 cx->demotion.threshold.bm = bm_history;
742 for (i = (ACPI_PROCESSOR_MAX_POWER - 1); i > 0; i--) {
743 cx = &pr->power.states[i];
748 cx->promotion.state = higher;
749 cx->promotion.threshold.ticks = cx->latency_ticks;
750 if (cx->type >= ACPI_STATE_C2)
751 cx->promotion.threshold.count = 4;
753 cx->promotion.threshold.count = 10;
754 if (higher->type == ACPI_STATE_C3)
755 cx->promotion.threshold.bm = bm_history;
763 #endif /* !CONFIG_CPU_IDLE */
765 static int acpi_processor_get_power_info_fadt(struct acpi_processor *pr)
774 /* if info is obtained from pblk/fadt, type equals state */
775 pr->power.states[ACPI_STATE_C2].type = ACPI_STATE_C2;
776 pr->power.states[ACPI_STATE_C3].type = ACPI_STATE_C3;
778 #ifndef CONFIG_HOTPLUG_CPU
780 * Check for P_LVL2_UP flag before entering C2 and above on
783 if ((num_online_cpus() > 1) &&
784 !(acpi_gbl_FADT.flags & ACPI_FADT_C2_MP_SUPPORTED))
788 /* determine C2 and C3 address from pblk */
789 pr->power.states[ACPI_STATE_C2].address = pr->pblk + 4;
790 pr->power.states[ACPI_STATE_C3].address = pr->pblk + 5;
792 /* determine latencies from FADT */
793 pr->power.states[ACPI_STATE_C2].latency = acpi_gbl_FADT.C2latency;
794 pr->power.states[ACPI_STATE_C3].latency = acpi_gbl_FADT.C3latency;
796 ACPI_DEBUG_PRINT((ACPI_DB_INFO,
797 "lvl2[0x%08x] lvl3[0x%08x]\n",
798 pr->power.states[ACPI_STATE_C2].address,
799 pr->power.states[ACPI_STATE_C3].address));
804 static int acpi_processor_get_power_info_default(struct acpi_processor *pr)
806 if (!pr->power.states[ACPI_STATE_C1].valid) {
807 /* set the first C-State to C1 */
808 /* all processors need to support C1 */
809 pr->power.states[ACPI_STATE_C1].type = ACPI_STATE_C1;
810 pr->power.states[ACPI_STATE_C1].valid = 1;
812 /* the C0 state only exists as a filler in our array */
813 pr->power.states[ACPI_STATE_C0].valid = 1;
817 static int acpi_processor_get_power_info_cst(struct acpi_processor *pr)
819 acpi_status status = 0;
823 struct acpi_buffer buffer = { ACPI_ALLOCATE_BUFFER, NULL };
824 union acpi_object *cst;
832 status = acpi_evaluate_object(pr->handle, "_CST", NULL, &buffer);
833 if (ACPI_FAILURE(status)) {
834 ACPI_DEBUG_PRINT((ACPI_DB_INFO, "No _CST, giving up\n"));
838 cst = buffer.pointer;
840 /* There must be at least 2 elements */
841 if (!cst || (cst->type != ACPI_TYPE_PACKAGE) || cst->package.count < 2) {
842 printk(KERN_ERR PREFIX "not enough elements in _CST\n");
847 count = cst->package.elements[0].integer.value;
849 /* Validate number of power states. */
850 if (count < 1 || count != cst->package.count - 1) {
851 printk(KERN_ERR PREFIX "count given by _CST is not valid\n");
856 /* Tell driver that at least _CST is supported. */
857 pr->flags.has_cst = 1;
859 for (i = 1; i <= count; i++) {
860 union acpi_object *element;
861 union acpi_object *obj;
862 struct acpi_power_register *reg;
863 struct acpi_processor_cx cx;
865 memset(&cx, 0, sizeof(cx));
867 element = &(cst->package.elements[i]);
868 if (element->type != ACPI_TYPE_PACKAGE)
871 if (element->package.count != 4)
874 obj = &(element->package.elements[0]);
876 if (obj->type != ACPI_TYPE_BUFFER)
879 reg = (struct acpi_power_register *)obj->buffer.pointer;
881 if (reg->space_id != ACPI_ADR_SPACE_SYSTEM_IO &&
882 (reg->space_id != ACPI_ADR_SPACE_FIXED_HARDWARE))
885 /* There should be an easy way to extract an integer... */
886 obj = &(element->package.elements[1]);
887 if (obj->type != ACPI_TYPE_INTEGER)
890 cx.type = obj->integer.value;
892 * Some buggy BIOSes won't list C1 in _CST -
893 * Let acpi_processor_get_power_info_default() handle them later
895 if (i == 1 && cx.type != ACPI_STATE_C1)
898 cx.address = reg->address;
899 cx.index = current_count + 1;
901 cx.space_id = ACPI_CSTATE_SYSTEMIO;
902 if (reg->space_id == ACPI_ADR_SPACE_FIXED_HARDWARE) {
903 if (acpi_processor_ffh_cstate_probe
904 (pr->id, &cx, reg) == 0) {
905 cx.space_id = ACPI_CSTATE_FFH;
906 } else if (cx.type != ACPI_STATE_C1) {
908 * C1 is a special case where FIXED_HARDWARE
909 * can be handled in non-MWAIT way as well.
910 * In that case, save this _CST entry info.
911 * That is, we retain space_id of SYSTEM_IO for
913 * Otherwise, ignore this info and continue.
919 obj = &(element->package.elements[2]);
920 if (obj->type != ACPI_TYPE_INTEGER)
923 cx.latency = obj->integer.value;
925 obj = &(element->package.elements[3]);
926 if (obj->type != ACPI_TYPE_INTEGER)
929 cx.power = obj->integer.value;
932 memcpy(&(pr->power.states[current_count]), &cx, sizeof(cx));
935 * We support total ACPI_PROCESSOR_MAX_POWER - 1
936 * (From 1 through ACPI_PROCESSOR_MAX_POWER - 1)
938 if (current_count >= (ACPI_PROCESSOR_MAX_POWER - 1)) {
940 "Limiting number of power states to max (%d)\n",
941 ACPI_PROCESSOR_MAX_POWER);
943 "Please increase ACPI_PROCESSOR_MAX_POWER if needed.\n");
948 ACPI_DEBUG_PRINT((ACPI_DB_INFO, "Found %d power states\n",
951 /* Validate number of power states discovered */
952 if (current_count < 2)
956 kfree(buffer.pointer);
961 static void acpi_processor_power_verify_c2(struct acpi_processor_cx *cx)
968 * C2 latency must be less than or equal to 100
971 else if (cx->latency > ACPI_PROCESSOR_MAX_C2_LATENCY) {
972 ACPI_DEBUG_PRINT((ACPI_DB_INFO,
973 "latency too large [%d]\n", cx->latency));
978 * Otherwise we've met all of our C2 requirements.
979 * Normalize the C2 latency to expidite policy
983 #ifndef CONFIG_CPU_IDLE
984 cx->latency_ticks = US_TO_PM_TIMER_TICKS(cx->latency);
986 cx->latency_ticks = cx->latency;
992 static void acpi_processor_power_verify_c3(struct acpi_processor *pr,
993 struct acpi_processor_cx *cx)
995 static int bm_check_flag;
1002 * C3 latency must be less than or equal to 1000
1005 else if (cx->latency > ACPI_PROCESSOR_MAX_C3_LATENCY) {
1006 ACPI_DEBUG_PRINT((ACPI_DB_INFO,
1007 "latency too large [%d]\n", cx->latency));
1012 * PIIX4 Erratum #18: We don't support C3 when Type-F (fast)
1013 * DMA transfers are used by any ISA device to avoid livelock.
1014 * Note that we could disable Type-F DMA (as recommended by
1015 * the erratum), but this is known to disrupt certain ISA
1016 * devices thus we take the conservative approach.
1018 else if (errata.piix4.fdma) {
1019 ACPI_DEBUG_PRINT((ACPI_DB_INFO,
1020 "C3 not supported on PIIX4 with Type-F DMA\n"));
1024 /* All the logic here assumes flags.bm_check is same across all CPUs */
1025 if (!bm_check_flag) {
1026 /* Determine whether bm_check is needed based on CPU */
1027 acpi_processor_power_init_bm_check(&(pr->flags), pr->id);
1028 bm_check_flag = pr->flags.bm_check;
1030 pr->flags.bm_check = bm_check_flag;
1033 if (pr->flags.bm_check) {
1034 if (!pr->flags.bm_control) {
1035 if (pr->flags.has_cst != 1) {
1036 /* bus mastering control is necessary */
1037 ACPI_DEBUG_PRINT((ACPI_DB_INFO,
1038 "C3 support requires BM control\n"));
1041 /* Here we enter C3 without bus mastering */
1042 ACPI_DEBUG_PRINT((ACPI_DB_INFO,
1043 "C3 support without BM control\n"));
1048 * WBINVD should be set in fadt, for C3 state to be
1049 * supported on when bm_check is not required.
1051 if (!(acpi_gbl_FADT.flags & ACPI_FADT_WBINVD)) {
1052 ACPI_DEBUG_PRINT((ACPI_DB_INFO,
1053 "Cache invalidation should work properly"
1054 " for C3 to be enabled on SMP systems\n"));
1057 acpi_set_register(ACPI_BITREG_BUS_MASTER_RLD, 0);
1061 * Otherwise we've met all of our C3 requirements.
1062 * Normalize the C3 latency to expidite policy. Enable
1063 * checking of bus mastering status (bm_check) so we can
1064 * use this in our C3 policy
1068 #ifndef CONFIG_CPU_IDLE
1069 cx->latency_ticks = US_TO_PM_TIMER_TICKS(cx->latency);
1071 cx->latency_ticks = cx->latency;
1077 static int acpi_processor_power_verify(struct acpi_processor *pr)
1080 unsigned int working = 0;
1082 pr->power.timer_broadcast_on_state = INT_MAX;
1084 for (i = 1; i < ACPI_PROCESSOR_MAX_POWER; i++) {
1085 struct acpi_processor_cx *cx = &pr->power.states[i];
1093 acpi_processor_power_verify_c2(cx);
1095 acpi_timer_check_state(i, pr, cx);
1099 acpi_processor_power_verify_c3(pr, cx);
1101 acpi_timer_check_state(i, pr, cx);
1109 acpi_propagate_timer_broadcast(pr);
1114 static int acpi_processor_get_power_info(struct acpi_processor *pr)
1120 /* NOTE: the idle thread may not be running while calling
1123 /* Zero initialize all the C-states info. */
1124 memset(pr->power.states, 0, sizeof(pr->power.states));
1126 result = acpi_processor_get_power_info_cst(pr);
1127 if (result == -ENODEV)
1128 result = acpi_processor_get_power_info_fadt(pr);
1133 acpi_processor_get_power_info_default(pr);
1135 pr->power.count = acpi_processor_power_verify(pr);
1137 #ifndef CONFIG_CPU_IDLE
1139 * Set Default Policy
1140 * ------------------
1141 * Now that we know which states are supported, set the default
1142 * policy. Note that this policy can be changed dynamically
1143 * (e.g. encourage deeper sleeps to conserve battery life when
1146 result = acpi_processor_set_power_policy(pr);
1152 * if one state of type C2 or C3 is available, mark this
1153 * CPU as being "idle manageable"
1155 for (i = 1; i < ACPI_PROCESSOR_MAX_POWER; i++) {
1156 if (pr->power.states[i].valid) {
1157 pr->power.count = i;
1158 if (pr->power.states[i].type >= ACPI_STATE_C2)
1159 pr->flags.power = 1;
1166 static int acpi_processor_power_seq_show(struct seq_file *seq, void *offset)
1168 struct acpi_processor *pr = seq->private;
1175 seq_printf(seq, "active state: C%zd\n"
1177 "bus master activity: %08x\n"
1178 "maximum allowed latency: %d usec\n",
1179 pr->power.state ? pr->power.state - pr->power.states : 0,
1180 max_cstate, (unsigned)pr->power.bm_activity,
1181 system_latency_constraint());
1183 seq_puts(seq, "states:\n");
1185 for (i = 1; i <= pr->power.count; i++) {
1186 seq_printf(seq, " %cC%d: ",
1187 (&pr->power.states[i] ==
1188 pr->power.state ? '*' : ' '), i);
1190 if (!pr->power.states[i].valid) {
1191 seq_puts(seq, "<not supported>\n");
1195 switch (pr->power.states[i].type) {
1197 seq_printf(seq, "type[C1] ");
1200 seq_printf(seq, "type[C2] ");
1203 seq_printf(seq, "type[C3] ");
1206 seq_printf(seq, "type[--] ");
1210 if (pr->power.states[i].promotion.state)
1211 seq_printf(seq, "promotion[C%zd] ",
1212 (pr->power.states[i].promotion.state -
1215 seq_puts(seq, "promotion[--] ");
1217 if (pr->power.states[i].demotion.state)
1218 seq_printf(seq, "demotion[C%zd] ",
1219 (pr->power.states[i].demotion.state -
1222 seq_puts(seq, "demotion[--] ");
1224 seq_printf(seq, "latency[%03d] usage[%08d] duration[%020llu]\n",
1225 pr->power.states[i].latency,
1226 pr->power.states[i].usage,
1227 (unsigned long long)pr->power.states[i].time);
1234 static int acpi_processor_power_open_fs(struct inode *inode, struct file *file)
1236 return single_open(file, acpi_processor_power_seq_show,
1240 static const struct file_operations acpi_processor_power_fops = {
1241 .open = acpi_processor_power_open_fs,
1243 .llseek = seq_lseek,
1244 .release = single_release,
1247 #ifndef CONFIG_CPU_IDLE
1249 int acpi_processor_cst_has_changed(struct acpi_processor *pr)
1261 if (!pr->flags.power_setup_done)
1264 /* Fall back to the default idle loop */
1265 pm_idle = pm_idle_save;
1266 synchronize_sched(); /* Relies on interrupts forcing exit from idle. */
1268 pr->flags.power = 0;
1269 result = acpi_processor_get_power_info(pr);
1270 if ((pr->flags.power == 1) && (pr->flags.power_setup_done))
1271 pm_idle = acpi_processor_idle;
1277 static void smp_callback(void *v)
1279 /* we already woke the CPU up, nothing more to do */
1283 * This function gets called when a part of the kernel has a new latency
1284 * requirement. This means we need to get all processors out of their C-state,
1285 * and then recalculate a new suitable C-state. Just do a cross-cpu IPI; that
1286 * wakes them all right up.
1288 static int acpi_processor_latency_notify(struct notifier_block *b,
1289 unsigned long l, void *v)
1291 smp_call_function(smp_callback, NULL, 0, 1);
1295 static struct notifier_block acpi_processor_latency_notifier = {
1296 .notifier_call = acpi_processor_latency_notify,
1301 #else /* CONFIG_CPU_IDLE */
1304 * acpi_idle_bm_check - checks if bus master activity was detected
1306 static int acpi_idle_bm_check(void)
1310 acpi_get_register(ACPI_BITREG_BUS_MASTER_STATUS, &bm_status);
1312 acpi_set_register(ACPI_BITREG_BUS_MASTER_STATUS, 1);
1314 * PIIX4 Erratum #18: Note that BM_STS doesn't always reflect
1315 * the true state of bus mastering activity; forcing us to
1316 * manually check the BMIDEA bit of each IDE channel.
1318 else if (errata.piix4.bmisx) {
1319 if ((inb_p(errata.piix4.bmisx + 0x02) & 0x01)
1320 || (inb_p(errata.piix4.bmisx + 0x0A) & 0x01))
1327 * acpi_idle_update_bm_rld - updates the BM_RLD bit depending on target state
1328 * @pr: the processor
1329 * @target: the new target state
1331 static inline void acpi_idle_update_bm_rld(struct acpi_processor *pr,
1332 struct acpi_processor_cx *target)
1334 if (pr->flags.bm_rld_set && target->type != ACPI_STATE_C3) {
1335 acpi_set_register(ACPI_BITREG_BUS_MASTER_RLD, 0);
1336 pr->flags.bm_rld_set = 0;
1339 if (!pr->flags.bm_rld_set && target->type == ACPI_STATE_C3) {
1340 acpi_set_register(ACPI_BITREG_BUS_MASTER_RLD, 1);
1341 pr->flags.bm_rld_set = 1;
1346 * acpi_idle_do_entry - a helper function that does C2 and C3 type entry
1349 static inline void acpi_idle_do_entry(struct acpi_processor_cx *cx)
1351 if (cx->space_id == ACPI_CSTATE_FFH) {
1352 /* Call into architectural FFH based C-state */
1353 acpi_processor_ffh_cstate_enter(cx);
1356 /* IO port based C-state */
1358 /* Dummy wait op - must do something useless after P_LVL2 read
1359 because chipsets cannot guarantee that STPCLK# signal
1360 gets asserted in time to freeze execution properly. */
1361 unused = inl(acpi_gbl_FADT.xpm_timer_block.address);
1366 * acpi_idle_enter_c1 - enters an ACPI C1 state-type
1367 * @dev: the target CPU
1368 * @state: the state data
1370 * This is equivalent to the HALT instruction.
1372 static int acpi_idle_enter_c1(struct cpuidle_device *dev,
1373 struct cpuidle_state *state)
1375 struct acpi_processor *pr;
1376 struct acpi_processor_cx *cx = cpuidle_get_statedata(state);
1377 pr = processors[smp_processor_id()];
1382 if (pr->flags.bm_check)
1383 acpi_idle_update_bm_rld(pr, cx);
1393 * acpi_idle_enter_simple - enters an ACPI state without BM handling
1394 * @dev: the target CPU
1395 * @state: the state data
1397 static int acpi_idle_enter_simple(struct cpuidle_device *dev,
1398 struct cpuidle_state *state)
1400 struct acpi_processor *pr;
1401 struct acpi_processor_cx *cx = cpuidle_get_statedata(state);
1403 int sleep_ticks = 0;
1405 pr = processors[smp_processor_id()];
1410 if (acpi_idle_suspend)
1411 return(acpi_idle_enter_c1(dev, state));
1413 local_irq_disable();
1414 current_thread_info()->status &= ~TS_POLLING;
1416 * TS_POLLING-cleared state must be visible before we test
1421 if (unlikely(need_resched())) {
1422 current_thread_info()->status |= TS_POLLING;
1427 acpi_unlazy_tlb(smp_processor_id());
1429 * Must be done before busmaster disable as we might need to
1432 acpi_state_timer_broadcast(pr, cx, 1);
1434 if (pr->flags.bm_check)
1435 acpi_idle_update_bm_rld(pr, cx);
1437 if (cx->type == ACPI_STATE_C3)
1438 ACPI_FLUSH_CPU_CACHE();
1440 t1 = inl(acpi_gbl_FADT.xpm_timer_block.address);
1441 /* Tell the scheduler that we are going deep-idle: */
1442 sched_clock_idle_sleep_event();
1443 acpi_idle_do_entry(cx);
1444 t2 = inl(acpi_gbl_FADT.xpm_timer_block.address);
1446 #if defined (CONFIG_GENERIC_TIME) && defined (CONFIG_X86_TSC)
1447 /* TSC could halt in idle, so notify users */
1448 mark_tsc_unstable("TSC halts in idle");;
1450 sleep_ticks = ticks_elapsed(t1, t2);
1452 /* Tell the scheduler how much we idled: */
1453 sched_clock_idle_wakeup_event(sleep_ticks*PM_TIMER_TICK_NS);
1456 current_thread_info()->status |= TS_POLLING;
1460 acpi_state_timer_broadcast(pr, cx, 0);
1461 cx->time += sleep_ticks;
1462 return ticks_elapsed_in_us(t1, t2);
1465 static int c3_cpu_count;
1466 static DEFINE_SPINLOCK(c3_lock);
1469 * acpi_idle_enter_bm - enters C3 with proper BM handling
1470 * @dev: the target CPU
1471 * @state: the state data
1473 * If BM is detected, the deepest non-C3 idle state is entered instead.
1475 static int acpi_idle_enter_bm(struct cpuidle_device *dev,
1476 struct cpuidle_state *state)
1478 struct acpi_processor *pr;
1479 struct acpi_processor_cx *cx = cpuidle_get_statedata(state);
1481 int sleep_ticks = 0;
1483 pr = processors[smp_processor_id()];
1488 if (acpi_idle_suspend)
1489 return(acpi_idle_enter_c1(dev, state));
1491 if (acpi_idle_bm_check()) {
1492 if (dev->safe_state) {
1493 return dev->safe_state->enter(dev, dev->safe_state);
1500 local_irq_disable();
1501 current_thread_info()->status &= ~TS_POLLING;
1503 * TS_POLLING-cleared state must be visible before we test
1508 if (unlikely(need_resched())) {
1509 current_thread_info()->status |= TS_POLLING;
1514 /* Tell the scheduler that we are going deep-idle: */
1515 sched_clock_idle_sleep_event();
1517 * Must be done before busmaster disable as we might need to
1520 acpi_state_timer_broadcast(pr, cx, 1);
1522 acpi_idle_update_bm_rld(pr, cx);
1525 * disable bus master
1526 * bm_check implies we need ARB_DIS
1527 * !bm_check implies we need cache flush
1528 * bm_control implies whether we can do ARB_DIS
1530 * That leaves a case where bm_check is set and bm_control is
1531 * not set. In that case we cannot do much, we enter C3
1532 * without doing anything.
1534 if (pr->flags.bm_check && pr->flags.bm_control) {
1535 spin_lock(&c3_lock);
1537 /* Disable bus master arbitration when all CPUs are in C3 */
1538 if (c3_cpu_count == num_online_cpus())
1539 acpi_set_register(ACPI_BITREG_ARB_DISABLE, 1);
1540 spin_unlock(&c3_lock);
1541 } else if (!pr->flags.bm_check) {
1542 ACPI_FLUSH_CPU_CACHE();
1545 t1 = inl(acpi_gbl_FADT.xpm_timer_block.address);
1546 acpi_idle_do_entry(cx);
1547 t2 = inl(acpi_gbl_FADT.xpm_timer_block.address);
1549 /* Re-enable bus master arbitration */
1550 if (pr->flags.bm_check && pr->flags.bm_control) {
1551 spin_lock(&c3_lock);
1552 acpi_set_register(ACPI_BITREG_ARB_DISABLE, 0);
1554 spin_unlock(&c3_lock);
1557 #if defined (CONFIG_GENERIC_TIME) && defined (CONFIG_X86_TSC)
1558 /* TSC could halt in idle, so notify users */
1559 mark_tsc_unstable("TSC halts in idle");
1561 sleep_ticks = ticks_elapsed(t1, t2);
1562 /* Tell the scheduler how much we idled: */
1563 sched_clock_idle_wakeup_event(sleep_ticks*PM_TIMER_TICK_NS);
1566 current_thread_info()->status |= TS_POLLING;
1570 acpi_state_timer_broadcast(pr, cx, 0);
1571 cx->time += sleep_ticks;
1572 return ticks_elapsed_in_us(t1, t2);
1575 struct cpuidle_driver acpi_idle_driver = {
1576 .name = "acpi_idle",
1577 .owner = THIS_MODULE,
1581 * acpi_processor_setup_cpuidle - prepares and configures CPUIDLE
1582 * @pr: the ACPI processor
1584 static int acpi_processor_setup_cpuidle(struct acpi_processor *pr)
1587 struct acpi_processor_cx *cx;
1588 struct cpuidle_state *state;
1589 struct cpuidle_device *dev = &pr->power.dev;
1591 if (!pr->flags.power_setup_done)
1594 if (pr->flags.power == 0) {
1598 for (i = 1; i < ACPI_PROCESSOR_MAX_POWER && i <= max_cstate; i++) {
1599 cx = &pr->power.states[i];
1600 state = &dev->states[count];
1605 #ifdef CONFIG_HOTPLUG_CPU
1606 if ((cx->type != ACPI_STATE_C1) && (num_online_cpus() > 1) &&
1607 !pr->flags.has_cst &&
1608 !(acpi_gbl_FADT.flags & ACPI_FADT_C2_MP_SUPPORTED))
1611 cpuidle_set_statedata(state, cx);
1613 snprintf(state->name, CPUIDLE_NAME_LEN, "C%d", i);
1614 state->exit_latency = cx->latency;
1615 state->target_residency = cx->latency * 6;
1616 state->power_usage = cx->power;
1621 state->flags |= CPUIDLE_FLAG_SHALLOW;
1622 state->enter = acpi_idle_enter_c1;
1623 dev->safe_state = state;
1627 state->flags |= CPUIDLE_FLAG_BALANCED;
1628 state->flags |= CPUIDLE_FLAG_TIME_VALID;
1629 state->enter = acpi_idle_enter_simple;
1630 dev->safe_state = state;
1634 state->flags |= CPUIDLE_FLAG_DEEP;
1635 state->flags |= CPUIDLE_FLAG_TIME_VALID;
1636 state->flags |= CPUIDLE_FLAG_CHECK_BM;
1637 state->enter = pr->flags.bm_check ?
1638 acpi_idle_enter_bm :
1639 acpi_idle_enter_simple;
1646 dev->state_count = count;
1654 int acpi_processor_cst_has_changed(struct acpi_processor *pr)
1665 if (!pr->flags.power_setup_done)
1668 cpuidle_pause_and_lock();
1669 cpuidle_disable_device(&pr->power.dev);
1670 acpi_processor_get_power_info(pr);
1671 acpi_processor_setup_cpuidle(pr);
1672 ret = cpuidle_enable_device(&pr->power.dev);
1673 cpuidle_resume_and_unlock();
1678 #endif /* CONFIG_CPU_IDLE */
1680 int __cpuinit acpi_processor_power_init(struct acpi_processor *pr,
1681 struct acpi_device *device)
1683 acpi_status status = 0;
1684 static int first_run;
1685 struct proc_dir_entry *entry = NULL;
1690 dmi_check_system(processor_power_dmi_table);
1691 max_cstate = acpi_processor_cstate_check(max_cstate);
1692 if (max_cstate < ACPI_C_STATES_MAX)
1694 "ACPI: processor limited to max C-state %d\n",
1697 #if !defined (CONFIG_CPU_IDLE) && defined (CONFIG_SMP)
1698 register_latency_notifier(&acpi_processor_latency_notifier);
1705 if (acpi_gbl_FADT.cst_control && !nocst) {
1707 acpi_os_write_port(acpi_gbl_FADT.smi_command, acpi_gbl_FADT.cst_control, 8);
1708 if (ACPI_FAILURE(status)) {
1709 ACPI_EXCEPTION((AE_INFO, status,
1710 "Notifying BIOS of _CST ability failed"));
1714 acpi_processor_get_power_info(pr);
1715 pr->flags.power_setup_done = 1;
1718 * Install the idle handler if processor power management is supported.
1719 * Note that we use previously set idle handler will be used on
1720 * platforms that only support C1.
1722 if ((pr->flags.power) && (!boot_option_idle_override)) {
1723 #ifdef CONFIG_CPU_IDLE
1724 acpi_processor_setup_cpuidle(pr);
1725 pr->power.dev.cpu = pr->id;
1726 if (cpuidle_register_device(&pr->power.dev))
1730 printk(KERN_INFO PREFIX "CPU%d (power states:", pr->id);
1731 for (i = 1; i <= pr->power.count; i++)
1732 if (pr->power.states[i].valid)
1733 printk(" C%d[C%d]", i,
1734 pr->power.states[i].type);
1737 #ifndef CONFIG_CPU_IDLE
1739 pm_idle_save = pm_idle;
1740 pm_idle = acpi_processor_idle;
1746 entry = create_proc_entry(ACPI_PROCESSOR_FILE_POWER,
1747 S_IRUGO, acpi_device_dir(device));
1751 entry->proc_fops = &acpi_processor_power_fops;
1752 entry->data = acpi_driver_data(device);
1753 entry->owner = THIS_MODULE;
1759 int acpi_processor_power_exit(struct acpi_processor *pr,
1760 struct acpi_device *device)
1762 #ifdef CONFIG_CPU_IDLE
1763 if ((pr->flags.power) && (!boot_option_idle_override))
1764 cpuidle_unregister_device(&pr->power.dev);
1766 pr->flags.power_setup_done = 0;
1768 if (acpi_device_dir(device))
1769 remove_proc_entry(ACPI_PROCESSOR_FILE_POWER,
1770 acpi_device_dir(device));
1772 #ifndef CONFIG_CPU_IDLE
1774 /* Unregister the idle handler when processor #0 is removed. */
1776 pm_idle = pm_idle_save;
1779 * We are about to unload the current idle thread pm callback
1780 * (pm_idle), Wait for all processors to update cached/local
1781 * copies of pm_idle before proceeding.
1785 unregister_latency_notifier(&acpi_processor_latency_notifier);