2 * linux/arch/x86-64/kernel/setup.c
4 * Copyright (C) 1995 Linus Torvalds
6 * Nov 2001 Dave Jones <davej@suse.de>
7 * Forked from i386 setup code.
13 * This file handles the architecture-dependent parts of initialization
16 #include <linux/errno.h>
17 #include <linux/sched.h>
18 #include <linux/kernel.h>
20 #include <linux/stddef.h>
21 #include <linux/unistd.h>
22 #include <linux/ptrace.h>
23 #include <linux/slab.h>
24 #include <linux/user.h>
25 #include <linux/a.out.h>
26 #include <linux/tty.h>
27 #include <linux/ioport.h>
28 #include <linux/delay.h>
29 #include <linux/config.h>
30 #include <linux/init.h>
31 #include <linux/initrd.h>
32 #include <linux/highmem.h>
33 #include <linux/bootmem.h>
34 #include <linux/module.h>
35 #include <asm/processor.h>
36 #include <linux/console.h>
37 #include <linux/seq_file.h>
38 #include <linux/root_dev.h>
39 #include <linux/pci.h>
40 #include <linux/acpi.h>
41 #include <linux/kallsyms.h>
42 #include <linux/edd.h>
43 #include <linux/mmzone.h>
44 #include <linux/kexec.h>
45 #include <linux/cpufreq.h>
48 #include <asm/uaccess.h>
49 #include <asm/system.h>
54 #include <video/edid.h>
57 #include <asm/mpspec.h>
58 #include <asm/mmu_context.h>
59 #include <asm/bootsetup.h>
60 #include <asm/proto.h>
61 #include <asm/setup.h>
62 #include <asm/mach_apic.h>
64 #include <asm/sections.h>
70 struct cpuinfo_x86 boot_cpu_data __read_mostly;
72 unsigned long mmu_cr4_features;
75 EXPORT_SYMBOL(acpi_disabled);
77 extern int __initdata acpi_ht;
78 extern acpi_interrupt_flags acpi_sci_flags;
79 int __initdata acpi_force = 0;
82 int acpi_numa __initdata;
84 /* Boot loader ID as an integer, for the benefit of proc_dointvec */
87 unsigned long saved_video_mode;
91 EXPORT_SYMBOL(swiotlb);
97 struct drive_info_struct { char dummy[32]; } drive_info;
98 struct screen_info screen_info;
99 struct sys_desc_table_struct {
100 unsigned short length;
101 unsigned char table[0];
104 struct edid_info edid_info;
107 extern int root_mountflags;
109 char command_line[COMMAND_LINE_SIZE];
111 struct resource standard_io_resources[] = {
112 { .name = "dma1", .start = 0x00, .end = 0x1f,
113 .flags = IORESOURCE_BUSY | IORESOURCE_IO },
114 { .name = "pic1", .start = 0x20, .end = 0x21,
115 .flags = IORESOURCE_BUSY | IORESOURCE_IO },
116 { .name = "timer0", .start = 0x40, .end = 0x43,
117 .flags = IORESOURCE_BUSY | IORESOURCE_IO },
118 { .name = "timer1", .start = 0x50, .end = 0x53,
119 .flags = IORESOURCE_BUSY | IORESOURCE_IO },
120 { .name = "keyboard", .start = 0x60, .end = 0x6f,
121 .flags = IORESOURCE_BUSY | IORESOURCE_IO },
122 { .name = "dma page reg", .start = 0x80, .end = 0x8f,
123 .flags = IORESOURCE_BUSY | IORESOURCE_IO },
124 { .name = "pic2", .start = 0xa0, .end = 0xa1,
125 .flags = IORESOURCE_BUSY | IORESOURCE_IO },
126 { .name = "dma2", .start = 0xc0, .end = 0xdf,
127 .flags = IORESOURCE_BUSY | IORESOURCE_IO },
128 { .name = "fpu", .start = 0xf0, .end = 0xff,
129 .flags = IORESOURCE_BUSY | IORESOURCE_IO }
132 #define STANDARD_IO_RESOURCES \
133 (sizeof standard_io_resources / sizeof standard_io_resources[0])
135 #define IORESOURCE_RAM (IORESOURCE_BUSY | IORESOURCE_MEM)
137 struct resource data_resource = {
138 .name = "Kernel data",
141 .flags = IORESOURCE_RAM,
143 struct resource code_resource = {
144 .name = "Kernel code",
147 .flags = IORESOURCE_RAM,
150 #define IORESOURCE_ROM (IORESOURCE_BUSY | IORESOURCE_READONLY | IORESOURCE_MEM)
152 static struct resource system_rom_resource = {
153 .name = "System ROM",
156 .flags = IORESOURCE_ROM,
159 static struct resource extension_rom_resource = {
160 .name = "Extension ROM",
163 .flags = IORESOURCE_ROM,
166 static struct resource adapter_rom_resources[] = {
167 { .name = "Adapter ROM", .start = 0xc8000, .end = 0,
168 .flags = IORESOURCE_ROM },
169 { .name = "Adapter ROM", .start = 0, .end = 0,
170 .flags = IORESOURCE_ROM },
171 { .name = "Adapter ROM", .start = 0, .end = 0,
172 .flags = IORESOURCE_ROM },
173 { .name = "Adapter ROM", .start = 0, .end = 0,
174 .flags = IORESOURCE_ROM },
175 { .name = "Adapter ROM", .start = 0, .end = 0,
176 .flags = IORESOURCE_ROM },
177 { .name = "Adapter ROM", .start = 0, .end = 0,
178 .flags = IORESOURCE_ROM }
181 #define ADAPTER_ROM_RESOURCES \
182 (sizeof adapter_rom_resources / sizeof adapter_rom_resources[0])
184 static struct resource video_rom_resource = {
188 .flags = IORESOURCE_ROM,
191 static struct resource video_ram_resource = {
192 .name = "Video RAM area",
195 .flags = IORESOURCE_RAM,
198 #define romsignature(x) (*(unsigned short *)(x) == 0xaa55)
200 static int __init romchecksum(unsigned char *rom, unsigned long length)
202 unsigned char *p, sum = 0;
204 for (p = rom; p < rom + length; p++)
209 static void __init probe_roms(void)
211 unsigned long start, length, upper;
216 upper = adapter_rom_resources[0].start;
217 for (start = video_rom_resource.start; start < upper; start += 2048) {
218 rom = isa_bus_to_virt(start);
219 if (!romsignature(rom))
222 video_rom_resource.start = start;
224 /* 0 < length <= 0x7f * 512, historically */
225 length = rom[2] * 512;
227 /* if checksum okay, trust length byte */
228 if (length && romchecksum(rom, length))
229 video_rom_resource.end = start + length - 1;
231 request_resource(&iomem_resource, &video_rom_resource);
235 start = (video_rom_resource.end + 1 + 2047) & ~2047UL;
240 request_resource(&iomem_resource, &system_rom_resource);
241 upper = system_rom_resource.start;
243 /* check for extension rom (ignore length byte!) */
244 rom = isa_bus_to_virt(extension_rom_resource.start);
245 if (romsignature(rom)) {
246 length = extension_rom_resource.end - extension_rom_resource.start + 1;
247 if (romchecksum(rom, length)) {
248 request_resource(&iomem_resource, &extension_rom_resource);
249 upper = extension_rom_resource.start;
253 /* check for adapter roms on 2k boundaries */
254 for (i = 0; i < ADAPTER_ROM_RESOURCES && start < upper; start += 2048) {
255 rom = isa_bus_to_virt(start);
256 if (!romsignature(rom))
259 /* 0 < length <= 0x7f * 512, historically */
260 length = rom[2] * 512;
262 /* but accept any length that fits if checksum okay */
263 if (!length || start + length > upper || !romchecksum(rom, length))
266 adapter_rom_resources[i].start = start;
267 adapter_rom_resources[i].end = start + length - 1;
268 request_resource(&iomem_resource, &adapter_rom_resources[i]);
270 start = adapter_rom_resources[i++].end & ~2047UL;
274 static __init void parse_cmdline_early (char ** cmdline_p)
276 char c = ' ', *to = command_line, *from = COMMAND_LINE;
280 /* Save unparsed command line copy for /proc/cmdline */
281 memcpy(saved_command_line, COMMAND_LINE, COMMAND_LINE_SIZE);
282 saved_command_line[COMMAND_LINE_SIZE-1] = '\0';
290 * If the BIOS enumerates physical processors before logical,
291 * maxcpus=N at enumeration-time can be used to disable HT.
293 else if (!memcmp(from, "maxcpus=", 8)) {
294 extern unsigned int maxcpus;
296 maxcpus = simple_strtoul(from + 8, NULL, 0);
300 /* "acpi=off" disables both ACPI table parsing and interpreter init */
301 if (!memcmp(from, "acpi=off", 8))
304 if (!memcmp(from, "acpi=force", 10)) {
305 /* add later when we do DMI horrors: */
310 /* acpi=ht just means: do ACPI MADT parsing
311 at bootup, but don't enable the full ACPI interpreter */
312 if (!memcmp(from, "acpi=ht", 7)) {
317 else if (!memcmp(from, "pci=noacpi", 10))
319 else if (!memcmp(from, "acpi=noirq", 10))
322 else if (!memcmp(from, "acpi_sci=edge", 13))
323 acpi_sci_flags.trigger = 1;
324 else if (!memcmp(from, "acpi_sci=level", 14))
325 acpi_sci_flags.trigger = 3;
326 else if (!memcmp(from, "acpi_sci=high", 13))
327 acpi_sci_flags.polarity = 1;
328 else if (!memcmp(from, "acpi_sci=low", 12))
329 acpi_sci_flags.polarity = 3;
331 /* acpi=strict disables out-of-spec workarounds */
332 else if (!memcmp(from, "acpi=strict", 11)) {
335 #ifdef CONFIG_X86_IO_APIC
336 else if (!memcmp(from, "acpi_skip_timer_override", 24))
337 acpi_skip_timer_override = 1;
341 if (!memcmp(from, "disable_timer_pin_1", 19))
342 disable_timer_pin_1 = 1;
343 if (!memcmp(from, "enable_timer_pin_1", 18))
344 disable_timer_pin_1 = -1;
346 if (!memcmp(from, "nolapic", 7) ||
347 !memcmp(from, "disableapic", 11))
350 if (!memcmp(from, "noapic", 6))
351 skip_ioapic_setup = 1;
353 if (!memcmp(from, "apic", 4)) {
354 skip_ioapic_setup = 0;
358 if (!memcmp(from, "mem=", 4))
359 parse_memopt(from+4, &from);
361 if (!memcmp(from, "memmap=", 7)) {
362 /* exactmap option is for used defined memory */
363 if (!memcmp(from+7, "exactmap", 8)) {
364 #ifdef CONFIG_CRASH_DUMP
365 /* If we are doing a crash dump, we
366 * still need to know the real mem
367 * size before original memory map is
370 saved_max_pfn = e820_end_of_ram();
378 parse_memmapopt(from+7, &from);
384 if (!memcmp(from, "numa=", 5))
388 #ifdef CONFIG_GART_IOMMU
389 if (!memcmp(from,"iommu=",6)) {
394 if (!memcmp(from,"oops=panic", 10))
397 if (!memcmp(from, "noexec=", 7))
398 nonx_setup(from + 7);
401 /* crashkernel=size@addr specifies the location to reserve for
402 * a crash kernel. By reserving this memory we guarantee
403 * that linux never set's it up as a DMA target.
404 * Useful for holding code to do something appropriate
405 * after a kernel panic.
407 else if (!memcmp(from, "crashkernel=", 12)) {
408 unsigned long size, base;
409 size = memparse(from+12, &from);
411 base = memparse(from+1, &from);
412 /* FIXME: Do I want a sanity check
413 * to validate the memory range?
415 crashk_res.start = base;
416 crashk_res.end = base + size - 1;
425 if (COMMAND_LINE_SIZE <= ++len)
430 printk(KERN_INFO "user-defined physical RAM map:\n");
431 e820_print_map("user");
434 *cmdline_p = command_line;
439 contig_initmem_init(unsigned long start_pfn, unsigned long end_pfn)
441 unsigned long bootmap_size, bootmap;
443 bootmap_size = bootmem_bootmap_pages(end_pfn)<<PAGE_SHIFT;
444 bootmap = find_e820_area(0, end_pfn<<PAGE_SHIFT, bootmap_size);
446 panic("Cannot find bootmem map of size %ld\n",bootmap_size);
447 bootmap_size = init_bootmem(bootmap >> PAGE_SHIFT, end_pfn);
448 e820_bootmem_free(NODE_DATA(0), 0, end_pfn << PAGE_SHIFT);
449 reserve_bootmem(bootmap, bootmap_size);
453 /* Use inline assembly to define this because the nops are defined
454 as inline assembly strings in the include files and we cannot
455 get them easily into strings. */
456 asm("\t.data\nk8nops: "
457 K8_NOP1 K8_NOP2 K8_NOP3 K8_NOP4 K8_NOP5 K8_NOP6
460 extern unsigned char k8nops[];
461 static unsigned char *k8_nops[ASM_NOP_MAX+1] = {
467 k8nops + 1 + 2 + 3 + 4,
468 k8nops + 1 + 2 + 3 + 4 + 5,
469 k8nops + 1 + 2 + 3 + 4 + 5 + 6,
470 k8nops + 1 + 2 + 3 + 4 + 5 + 6 + 7,
473 /* Replace instructions with better alternatives for this CPU type.
475 This runs before SMP is initialized to avoid SMP problems with
476 self modifying code. This implies that assymetric systems where
477 APs have less capabilities than the boot processor are not handled.
478 In this case boot with "noreplacement". */
479 void apply_alternatives(void *start, void *end)
483 for (a = start; (void *)a < end; a++) {
484 if (!boot_cpu_has(a->cpuid))
487 BUG_ON(a->replacementlen > a->instrlen);
488 __inline_memcpy(a->instr, a->replacement, a->replacementlen);
489 diff = a->instrlen - a->replacementlen;
491 /* Pad the rest with nops */
492 for (i = a->replacementlen; diff > 0; diff -= k, i += k) {
496 __inline_memcpy(a->instr + i, k8_nops[k], k);
501 static int no_replacement __initdata = 0;
503 void __init alternative_instructions(void)
505 extern struct alt_instr __alt_instructions[], __alt_instructions_end[];
508 apply_alternatives(__alt_instructions, __alt_instructions_end);
511 static int __init noreplacement_setup(char *s)
517 __setup("noreplacement", noreplacement_setup);
519 #if defined(CONFIG_EDD) || defined(CONFIG_EDD_MODULE)
521 #ifdef CONFIG_EDD_MODULE
525 * copy_edd() - Copy the BIOS EDD information
526 * from boot_params into a safe place.
529 static inline void copy_edd(void)
531 memcpy(edd.mbr_signature, EDD_MBR_SIGNATURE, sizeof(edd.mbr_signature));
532 memcpy(edd.edd_info, EDD_BUF, sizeof(edd.edd_info));
533 edd.mbr_signature_nr = EDD_MBR_SIG_NR;
534 edd.edd_info_nr = EDD_NR;
537 static inline void copy_edd(void)
542 #define EBDA_ADDR_POINTER 0x40E
543 static void __init reserve_ebda_region(void)
547 * there is a real-mode segmented pointer pointing to the
548 * 4K EBDA area at 0x40E
550 addr = *(unsigned short *)phys_to_virt(EBDA_ADDR_POINTER);
553 reserve_bootmem_generic(addr, PAGE_SIZE);
556 void __init setup_arch(char **cmdline_p)
558 unsigned long kernel_end;
560 ROOT_DEV = old_decode_dev(ORIG_ROOT_DEV);
561 drive_info = DRIVE_INFO;
562 screen_info = SCREEN_INFO;
563 edid_info = EDID_INFO;
564 saved_video_mode = SAVED_VIDEO_MODE;
565 bootloader_type = LOADER_TYPE;
567 #ifdef CONFIG_BLK_DEV_RAM
568 rd_image_start = RAMDISK_FLAGS & RAMDISK_IMAGE_START_MASK;
569 rd_prompt = ((RAMDISK_FLAGS & RAMDISK_PROMPT_FLAG) != 0);
570 rd_doload = ((RAMDISK_FLAGS & RAMDISK_LOAD_FLAG) != 0);
572 setup_memory_region();
575 if (!MOUNT_ROOT_RDONLY)
576 root_mountflags &= ~MS_RDONLY;
577 init_mm.start_code = (unsigned long) &_text;
578 init_mm.end_code = (unsigned long) &_etext;
579 init_mm.end_data = (unsigned long) &_edata;
580 init_mm.brk = (unsigned long) &_end;
582 code_resource.start = virt_to_phys(&_text);
583 code_resource.end = virt_to_phys(&_etext)-1;
584 data_resource.start = virt_to_phys(&_etext);
585 data_resource.end = virt_to_phys(&_edata)-1;
587 parse_cmdline_early(cmdline_p);
589 early_identify_cpu(&boot_cpu_data);
592 * partially used pages are not usable - thus
593 * we are rounding upwards:
595 end_pfn = e820_end_of_ram();
599 init_memory_mapping(0, (end_pfn_map << PAGE_SHIFT));
605 * Initialize the ACPI boot-time table parser (gets the RSDP and SDT).
606 * Call this early for SRAT node setup.
608 acpi_boot_table_init();
611 #ifdef CONFIG_ACPI_NUMA
613 * Parse SRAT to discover nodes.
619 numa_initmem_init(0, end_pfn);
621 contig_initmem_init(0, end_pfn);
624 /* Reserve direct mapping */
625 reserve_bootmem_generic(table_start << PAGE_SHIFT,
626 (table_end - table_start) << PAGE_SHIFT);
629 kernel_end = round_up(__pa_symbol(&_end),PAGE_SIZE);
630 reserve_bootmem_generic(HIGH_MEMORY, kernel_end - HIGH_MEMORY);
633 * reserve physical page 0 - it's a special BIOS page on many boxes,
634 * enabling clean reboots, SMP operation, laptop functions.
636 reserve_bootmem_generic(0, PAGE_SIZE);
638 /* reserve ebda region */
639 reserve_ebda_region();
643 * But first pinch a few for the stack/trampoline stuff
644 * FIXME: Don't need the extra page at 4K, but need to fix
645 * trampoline before removing it. (see the GDT stuff)
647 reserve_bootmem_generic(PAGE_SIZE, PAGE_SIZE);
649 /* Reserve SMP trampoline */
650 reserve_bootmem_generic(SMP_TRAMPOLINE_BASE, PAGE_SIZE);
653 #ifdef CONFIG_ACPI_SLEEP
655 * Reserve low memory region for sleep support.
657 acpi_reserve_bootmem();
659 #ifdef CONFIG_X86_LOCAL_APIC
661 * Find and reserve possible boot-time SMP configuration:
665 #ifdef CONFIG_BLK_DEV_INITRD
666 if (LOADER_TYPE && INITRD_START) {
667 if (INITRD_START + INITRD_SIZE <= (end_pfn << PAGE_SHIFT)) {
668 reserve_bootmem_generic(INITRD_START, INITRD_SIZE);
670 INITRD_START ? INITRD_START + PAGE_OFFSET : 0;
671 initrd_end = initrd_start+INITRD_SIZE;
674 printk(KERN_ERR "initrd extends beyond end of memory "
675 "(0x%08lx > 0x%08lx)\ndisabling initrd\n",
676 (unsigned long)(INITRD_START + INITRD_SIZE),
677 (unsigned long)(end_pfn << PAGE_SHIFT));
683 if (crashk_res.start != crashk_res.end) {
684 reserve_bootmem(crashk_res.start,
685 crashk_res.end - crashk_res.start + 1);
695 * Read APIC and some other early information from ACPI tables.
700 #ifdef CONFIG_X86_LOCAL_APIC
702 * get boot-time SMP configuration:
704 if (smp_found_config)
706 init_apic_mappings();
710 * Request address space for all standard RAM and ROM resources
711 * and also for regions reported as reserved by the e820.
714 e820_reserve_resources();
716 request_resource(&iomem_resource, &video_ram_resource);
720 /* request I/O space for devices used on all i[345]86 PCs */
721 for (i = 0; i < STANDARD_IO_RESOURCES; i++)
722 request_resource(&ioport_resource, &standard_io_resources[i]);
727 #ifdef CONFIG_GART_IOMMU
732 #if defined(CONFIG_VGA_CONSOLE)
733 conswitchp = &vga_con;
734 #elif defined(CONFIG_DUMMY_CONSOLE)
735 conswitchp = &dummy_con;
740 static int __cpuinit get_model_name(struct cpuinfo_x86 *c)
744 if (c->extended_cpuid_level < 0x80000004)
747 v = (unsigned int *) c->x86_model_id;
748 cpuid(0x80000002, &v[0], &v[1], &v[2], &v[3]);
749 cpuid(0x80000003, &v[4], &v[5], &v[6], &v[7]);
750 cpuid(0x80000004, &v[8], &v[9], &v[10], &v[11]);
751 c->x86_model_id[48] = 0;
756 static void __cpuinit display_cacheinfo(struct cpuinfo_x86 *c)
758 unsigned int n, dummy, eax, ebx, ecx, edx;
760 n = c->extended_cpuid_level;
762 if (n >= 0x80000005) {
763 cpuid(0x80000005, &dummy, &ebx, &ecx, &edx);
764 printk(KERN_INFO "CPU: L1 I Cache: %dK (%d bytes/line), D cache %dK (%d bytes/line)\n",
765 edx>>24, edx&0xFF, ecx>>24, ecx&0xFF);
766 c->x86_cache_size=(ecx>>24)+(edx>>24);
767 /* On K8 L1 TLB is inclusive, so don't count it */
771 if (n >= 0x80000006) {
772 cpuid(0x80000006, &dummy, &ebx, &ecx, &edx);
773 ecx = cpuid_ecx(0x80000006);
774 c->x86_cache_size = ecx >> 16;
775 c->x86_tlbsize += ((ebx >> 16) & 0xfff) + (ebx & 0xfff);
777 printk(KERN_INFO "CPU: L2 Cache: %dK (%d bytes/line)\n",
778 c->x86_cache_size, ecx & 0xFF);
782 cpuid(0x80000007, &dummy, &dummy, &dummy, &c->x86_power);
783 if (n >= 0x80000008) {
784 cpuid(0x80000008, &eax, &dummy, &dummy, &dummy);
785 c->x86_virt_bits = (eax >> 8) & 0xff;
786 c->x86_phys_bits = eax & 0xff;
791 static int nearby_node(int apicid)
794 for (i = apicid - 1; i >= 0; i--) {
795 int node = apicid_to_node[i];
796 if (node != NUMA_NO_NODE && node_online(node))
799 for (i = apicid + 1; i < MAX_LOCAL_APIC; i++) {
800 int node = apicid_to_node[i];
801 if (node != NUMA_NO_NODE && node_online(node))
804 return first_node(node_online_map); /* Shouldn't happen */
809 * On a AMD dual core setup the lower bits of the APIC id distingush the cores.
810 * Assumes number of cores is a power of two.
812 static void __init amd_detect_cmp(struct cpuinfo_x86 *c)
815 int cpu = smp_processor_id();
819 unsigned apicid = phys_proc_id[cpu];
823 while ((1 << bits) < c->x86_max_cores)
826 /* Low order bits define the core id (index of core in socket) */
827 cpu_core_id[cpu] = phys_proc_id[cpu] & ((1 << bits)-1);
828 /* Convert the APIC ID into the socket ID */
829 phys_proc_id[cpu] >>= bits;
832 node = phys_proc_id[cpu];
833 if (apicid_to_node[apicid] != NUMA_NO_NODE)
834 node = apicid_to_node[apicid];
835 if (!node_online(node)) {
836 /* Two possibilities here:
837 - The CPU is missing memory and no node was created.
838 In that case try picking one from a nearby CPU
839 - The APIC IDs differ from the HyperTransport node IDs
840 which the K8 northbridge parsing fills in.
841 Assume they are all increased by a constant offset,
842 but in the same order as the HT nodeids.
843 If that doesn't result in a usable node fall back to the
844 path for the previous case. */
845 int ht_nodeid = apicid - (phys_proc_id[0] << bits);
846 if (ht_nodeid >= 0 &&
847 apicid_to_node[ht_nodeid] != NUMA_NO_NODE)
848 node = apicid_to_node[ht_nodeid];
849 /* Pick a nearby node */
850 if (!node_online(node))
851 node = nearby_node(apicid);
853 numa_set_node(cpu, node);
855 printk(KERN_INFO "CPU %d(%d) -> Node %d -> Core %d\n",
856 cpu, c->x86_max_cores, node, cpu_core_id[cpu]);
861 static int __init init_amd(struct cpuinfo_x86 *c)
870 * Disable TLB flush filter by setting HWCR.FFDIS on K8
871 * bit 6 of msr C001_0015
873 * Errata 63 for SH-B3 steppings
874 * Errata 122 for all steppings (F+ have it disabled by default)
877 rdmsrl(MSR_K8_HWCR, value);
879 wrmsrl(MSR_K8_HWCR, value);
883 /* Bit 31 in normal CPUID used for nonstandard 3DNow ID;
884 3DNow is IDd by bit 31 in extended CPUID (1*32+31) anyway */
885 clear_bit(0*32+31, &c->x86_capability);
888 level = cpuid_eax(1);
889 if ((level >= 0x0f48 && level < 0x0f50) || level >= 0x0f58)
890 set_bit(X86_FEATURE_K8_C, &c->x86_capability);
892 r = get_model_name(c);
896 /* Should distinguish Models here, but this is only
897 a fallback anyways. */
898 strcpy(c->x86_model_id, "Hammer");
902 display_cacheinfo(c);
904 if (c->extended_cpuid_level >= 0x80000008) {
905 c->x86_max_cores = (cpuid_ecx(0x80000008) & 0xff) + 1;
906 if (c->x86_max_cores & (c->x86_max_cores - 1))
907 c->x86_max_cores = 1;
915 static void __cpuinit detect_ht(struct cpuinfo_x86 *c)
918 u32 eax, ebx, ecx, edx;
919 int index_msb, core_bits;
920 int cpu = smp_processor_id();
922 cpuid(1, &eax, &ebx, &ecx, &edx);
924 c->apicid = phys_pkg_id(0);
926 if (!cpu_has(c, X86_FEATURE_HT) || cpu_has(c, X86_FEATURE_CMP_LEGACY))
929 smp_num_siblings = (ebx & 0xff0000) >> 16;
931 if (smp_num_siblings == 1) {
932 printk(KERN_INFO "CPU: Hyper-Threading is disabled\n");
933 } else if (smp_num_siblings > 1 ) {
935 if (smp_num_siblings > NR_CPUS) {
936 printk(KERN_WARNING "CPU: Unsupported number of the siblings %d", smp_num_siblings);
937 smp_num_siblings = 1;
941 index_msb = get_count_order(smp_num_siblings);
942 phys_proc_id[cpu] = phys_pkg_id(index_msb);
944 printk(KERN_INFO "CPU: Physical Processor ID: %d\n",
947 smp_num_siblings = smp_num_siblings / c->x86_max_cores;
949 index_msb = get_count_order(smp_num_siblings) ;
951 core_bits = get_count_order(c->x86_max_cores);
953 cpu_core_id[cpu] = phys_pkg_id(index_msb) &
954 ((1 << core_bits) - 1);
956 if (c->x86_max_cores > 1)
957 printk(KERN_INFO "CPU: Processor Core ID: %d\n",
964 * find out the number of processor cores on the die
966 static int __cpuinit intel_num_cpu_cores(struct cpuinfo_x86 *c)
970 if (c->cpuid_level < 4)
979 return ((eax >> 26) + 1);
984 static void srat_detect_node(void)
988 int cpu = smp_processor_id();
990 /* Don't do the funky fallback heuristics the AMD version employs
992 node = apicid_to_node[hard_smp_processor_id()];
993 if (node == NUMA_NO_NODE)
995 numa_set_node(cpu, node);
998 printk(KERN_INFO "CPU %d -> Node %d\n", cpu, node);
1002 static void __cpuinit init_intel(struct cpuinfo_x86 *c)
1007 init_intel_cacheinfo(c);
1008 n = c->extended_cpuid_level;
1009 if (n >= 0x80000008) {
1010 unsigned eax = cpuid_eax(0x80000008);
1011 c->x86_virt_bits = (eax >> 8) & 0xff;
1012 c->x86_phys_bits = eax & 0xff;
1013 /* CPUID workaround for Intel 0F34 CPU */
1014 if (c->x86_vendor == X86_VENDOR_INTEL &&
1015 c->x86 == 0xF && c->x86_model == 0x3 &&
1017 c->x86_phys_bits = 36;
1021 c->x86_cache_alignment = c->x86_clflush_size * 2;
1023 set_bit(X86_FEATURE_CONSTANT_TSC, &c->x86_capability);
1024 c->x86_max_cores = intel_num_cpu_cores(c);
1029 static void __cpuinit get_cpu_vendor(struct cpuinfo_x86 *c)
1031 char *v = c->x86_vendor_id;
1033 if (!strcmp(v, "AuthenticAMD"))
1034 c->x86_vendor = X86_VENDOR_AMD;
1035 else if (!strcmp(v, "GenuineIntel"))
1036 c->x86_vendor = X86_VENDOR_INTEL;
1038 c->x86_vendor = X86_VENDOR_UNKNOWN;
1041 struct cpu_model_info {
1044 char *model_names[16];
1047 /* Do some early cpuid on the boot CPU to get some parameter that are
1048 needed before check_bugs. Everything advanced is in identify_cpu
1050 void __cpuinit early_identify_cpu(struct cpuinfo_x86 *c)
1054 c->loops_per_jiffy = loops_per_jiffy;
1055 c->x86_cache_size = -1;
1056 c->x86_vendor = X86_VENDOR_UNKNOWN;
1057 c->x86_model = c->x86_mask = 0; /* So far unknown... */
1058 c->x86_vendor_id[0] = '\0'; /* Unset */
1059 c->x86_model_id[0] = '\0'; /* Unset */
1060 c->x86_clflush_size = 64;
1061 c->x86_cache_alignment = c->x86_clflush_size;
1062 c->x86_max_cores = 1;
1063 c->extended_cpuid_level = 0;
1064 memset(&c->x86_capability, 0, sizeof c->x86_capability);
1066 /* Get vendor name */
1067 cpuid(0x00000000, (unsigned int *)&c->cpuid_level,
1068 (unsigned int *)&c->x86_vendor_id[0],
1069 (unsigned int *)&c->x86_vendor_id[8],
1070 (unsigned int *)&c->x86_vendor_id[4]);
1074 /* Initialize the standard set of capabilities */
1075 /* Note that the vendor-specific code below might override */
1077 /* Intel-defined flags: level 0x00000001 */
1078 if (c->cpuid_level >= 0x00000001) {
1080 cpuid(0x00000001, &tfms, &misc, &c->x86_capability[4],
1081 &c->x86_capability[0]);
1082 c->x86 = (tfms >> 8) & 0xf;
1083 c->x86_model = (tfms >> 4) & 0xf;
1084 c->x86_mask = tfms & 0xf;
1086 c->x86 += (tfms >> 20) & 0xff;
1088 c->x86_model += ((tfms >> 16) & 0xF) << 4;
1089 if (c->x86_capability[0] & (1<<19))
1090 c->x86_clflush_size = ((misc >> 8) & 0xff) * 8;
1092 /* Have CPUID level 0 only - unheard of */
1097 phys_proc_id[smp_processor_id()] = (cpuid_ebx(1) >> 24) & 0xff;
1102 * This does the hard work of actually picking apart the CPU stuff...
1104 void __cpuinit identify_cpu(struct cpuinfo_x86 *c)
1109 early_identify_cpu(c);
1111 /* AMD-defined flags: level 0x80000001 */
1112 xlvl = cpuid_eax(0x80000000);
1113 c->extended_cpuid_level = xlvl;
1114 if ((xlvl & 0xffff0000) == 0x80000000) {
1115 if (xlvl >= 0x80000001) {
1116 c->x86_capability[1] = cpuid_edx(0x80000001);
1117 c->x86_capability[6] = cpuid_ecx(0x80000001);
1119 if (xlvl >= 0x80000004)
1120 get_model_name(c); /* Default name */
1123 /* Transmeta-defined flags: level 0x80860001 */
1124 xlvl = cpuid_eax(0x80860000);
1125 if ((xlvl & 0xffff0000) == 0x80860000) {
1126 /* Don't set x86_cpuid_level here for now to not confuse. */
1127 if (xlvl >= 0x80860001)
1128 c->x86_capability[2] = cpuid_edx(0x80860001);
1132 * Vendor-specific initialization. In this section we
1133 * canonicalize the feature flags, meaning if there are
1134 * features a certain CPU supports which CPUID doesn't
1135 * tell us, CPUID claiming incorrect flags, or other bugs,
1136 * we handle them here.
1138 * At the end of this section, c->x86_capability better
1139 * indicate the features this CPU genuinely supports!
1141 switch (c->x86_vendor) {
1142 case X86_VENDOR_AMD:
1146 case X86_VENDOR_INTEL:
1150 case X86_VENDOR_UNKNOWN:
1152 display_cacheinfo(c);
1156 select_idle_routine(c);
1160 * On SMP, boot_cpu_data holds the common feature set between
1161 * all CPUs; so make sure that we indicate which features are
1162 * common between the CPUs. The first time this routine gets
1163 * executed, c == &boot_cpu_data.
1165 if (c != &boot_cpu_data) {
1166 /* AND the already accumulated flags with these */
1167 for (i = 0 ; i < NCAPINTS ; i++)
1168 boot_cpu_data.x86_capability[i] &= c->x86_capability[i];
1171 #ifdef CONFIG_X86_MCE
1174 if (c == &boot_cpu_data)
1179 numa_add_cpu(smp_processor_id());
1184 void __cpuinit print_cpu_info(struct cpuinfo_x86 *c)
1186 if (c->x86_model_id[0])
1187 printk("%s", c->x86_model_id);
1189 if (c->x86_mask || c->cpuid_level >= 0)
1190 printk(" stepping %02x\n", c->x86_mask);
1196 * Get CPU information for use by the procfs.
1199 static int show_cpuinfo(struct seq_file *m, void *v)
1201 struct cpuinfo_x86 *c = v;
1204 * These flag bits must match the definitions in <asm/cpufeature.h>.
1205 * NULL means this bit is undefined or reserved; either way it doesn't
1206 * have meaning as far as Linux is concerned. Note that it's important
1207 * to realize there is a difference between this table and CPUID -- if
1208 * applications want to get the raw CPUID data, they should access
1209 * /dev/cpu/<cpu_nr>/cpuid instead.
1211 static char *x86_cap_flags[] = {
1213 "fpu", "vme", "de", "pse", "tsc", "msr", "pae", "mce",
1214 "cx8", "apic", NULL, "sep", "mtrr", "pge", "mca", "cmov",
1215 "pat", "pse36", "pn", "clflush", NULL, "dts", "acpi", "mmx",
1216 "fxsr", "sse", "sse2", "ss", "ht", "tm", "ia64", NULL,
1219 NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL,
1220 NULL, NULL, NULL, "syscall", NULL, NULL, NULL, NULL,
1221 NULL, NULL, NULL, NULL, "nx", NULL, "mmxext", NULL,
1222 NULL, "fxsr_opt", NULL, NULL, NULL, "lm", "3dnowext", "3dnow",
1224 /* Transmeta-defined */
1225 "recovery", "longrun", NULL, "lrti", NULL, NULL, NULL, NULL,
1226 NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL,
1227 NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL,
1228 NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL,
1230 /* Other (Linux-defined) */
1231 "cxmmx", NULL, "cyrix_arr", "centaur_mcr", NULL,
1232 "constant_tsc", NULL, NULL,
1233 NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL,
1234 NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL,
1235 NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL,
1237 /* Intel-defined (#2) */
1238 "pni", NULL, NULL, "monitor", "ds_cpl", "vmx", NULL, "est",
1239 "tm2", NULL, "cid", NULL, NULL, "cx16", "xtpr", NULL,
1240 NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL,
1241 NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL,
1243 /* VIA/Cyrix/Centaur-defined */
1244 NULL, NULL, "rng", "rng_en", NULL, NULL, "ace", "ace_en",
1245 NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL,
1246 NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL,
1247 NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL,
1249 /* AMD-defined (#2) */
1250 "lahf_lm", "cmp_legacy", NULL, NULL, NULL, NULL, NULL, NULL,
1251 NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL,
1252 NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL,
1253 NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL,
1255 static char *x86_power_flags[] = {
1256 "ts", /* temperature sensor */
1257 "fid", /* frequency id control */
1258 "vid", /* voltage id control */
1259 "ttp", /* thermal trip */
1266 if (!cpu_online(c-cpu_data))
1270 seq_printf(m,"processor\t: %u\n"
1272 "cpu family\t: %d\n"
1274 "model name\t: %s\n",
1275 (unsigned)(c-cpu_data),
1276 c->x86_vendor_id[0] ? c->x86_vendor_id : "unknown",
1279 c->x86_model_id[0] ? c->x86_model_id : "unknown");
1281 if (c->x86_mask || c->cpuid_level >= 0)
1282 seq_printf(m, "stepping\t: %d\n", c->x86_mask);
1284 seq_printf(m, "stepping\t: unknown\n");
1286 if (cpu_has(c,X86_FEATURE_TSC)) {
1287 unsigned int freq = cpufreq_quick_get((unsigned)(c-cpu_data));
1290 seq_printf(m, "cpu MHz\t\t: %u.%03u\n",
1291 freq / 1000, (freq % 1000));
1295 if (c->x86_cache_size >= 0)
1296 seq_printf(m, "cache size\t: %d KB\n", c->x86_cache_size);
1299 if (smp_num_siblings * c->x86_max_cores > 1) {
1300 int cpu = c - cpu_data;
1301 seq_printf(m, "physical id\t: %d\n", phys_proc_id[cpu]);
1302 seq_printf(m, "siblings\t: %d\n", cpus_weight(cpu_core_map[cpu]));
1303 seq_printf(m, "core id\t\t: %d\n", cpu_core_id[cpu]);
1304 seq_printf(m, "cpu cores\t: %d\n", c->booted_cores);
1310 "fpu_exception\t: yes\n"
1311 "cpuid level\t: %d\n"
1318 for ( i = 0 ; i < 32*NCAPINTS ; i++ )
1319 if ( test_bit(i, &c->x86_capability) &&
1320 x86_cap_flags[i] != NULL )
1321 seq_printf(m, " %s", x86_cap_flags[i]);
1324 seq_printf(m, "\nbogomips\t: %lu.%02lu\n",
1325 c->loops_per_jiffy/(500000/HZ),
1326 (c->loops_per_jiffy/(5000/HZ)) % 100);
1328 if (c->x86_tlbsize > 0)
1329 seq_printf(m, "TLB size\t: %d 4K pages\n", c->x86_tlbsize);
1330 seq_printf(m, "clflush size\t: %d\n", c->x86_clflush_size);
1331 seq_printf(m, "cache_alignment\t: %d\n", c->x86_cache_alignment);
1333 seq_printf(m, "address sizes\t: %u bits physical, %u bits virtual\n",
1334 c->x86_phys_bits, c->x86_virt_bits);
1336 seq_printf(m, "power management:");
1339 for (i = 0; i < 32; i++)
1340 if (c->x86_power & (1 << i)) {
1341 if (i < ARRAY_SIZE(x86_power_flags))
1342 seq_printf(m, " %s", x86_power_flags[i]);
1344 seq_printf(m, " [%d]", i);
1348 seq_printf(m, "\n\n");
1353 static void *c_start(struct seq_file *m, loff_t *pos)
1355 return *pos < NR_CPUS ? cpu_data + *pos : NULL;
1358 static void *c_next(struct seq_file *m, void *v, loff_t *pos)
1361 return c_start(m, pos);
1364 static void c_stop(struct seq_file *m, void *v)
1368 struct seq_operations cpuinfo_op = {
1372 .show = show_cpuinfo,