2 * Derived from arch/powerpc/kernel/iommu.c
4 * Copyright IBM Corporation, 2006-2007
5 * Copyright (C) 2006 Jon Mason <jdmason@kudzu.us>
7 * Author: Jon Mason <jdmason@kudzu.us>
8 * Author: Muli Ben-Yehuda <muli@il.ibm.com>
10 * This program is free software; you can redistribute it and/or modify
11 * it under the terms of the GNU General Public License as published by
12 * the Free Software Foundation; either version 2 of the License, or
13 * (at your option) any later version.
15 * This program is distributed in the hope that it will be useful,
16 * but WITHOUT ANY WARRANTY; without even the implied warranty of
17 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
18 * GNU General Public License for more details.
20 * You should have received a copy of the GNU General Public License
21 * along with this program; if not, write to the Free Software
22 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
25 #include <linux/kernel.h>
26 #include <linux/init.h>
27 #include <linux/types.h>
28 #include <linux/slab.h>
30 #include <linux/spinlock.h>
31 #include <linux/string.h>
32 #include <linux/dma-mapping.h>
33 #include <linux/init.h>
34 #include <linux/bitops.h>
35 #include <linux/pci_ids.h>
36 #include <linux/pci.h>
37 #include <linux/delay.h>
38 #include <asm/iommu.h>
39 #include <asm/calgary.h>
41 #include <asm/pci-direct.h>
42 #include <asm/system.h>
46 #ifdef CONFIG_CALGARY_IOMMU_ENABLED_BY_DEFAULT
47 int use_calgary __read_mostly = 1;
49 int use_calgary __read_mostly = 0;
50 #endif /* CONFIG_CALGARY_DEFAULT_ENABLED */
52 #define PCI_DEVICE_ID_IBM_CALGARY 0x02a1
53 #define PCI_DEVICE_ID_IBM_CALIOC2 0x0308
55 /* register offsets inside the host bridge space */
56 #define CALGARY_CONFIG_REG 0x0108
57 #define PHB_CSR_OFFSET 0x0110 /* Channel Status */
58 #define PHB_PLSSR_OFFSET 0x0120
59 #define PHB_CONFIG_RW_OFFSET 0x0160
60 #define PHB_IOBASE_BAR_LOW 0x0170
61 #define PHB_IOBASE_BAR_HIGH 0x0180
62 #define PHB_MEM_1_LOW 0x0190
63 #define PHB_MEM_1_HIGH 0x01A0
64 #define PHB_IO_ADDR_SIZE 0x01B0
65 #define PHB_MEM_1_SIZE 0x01C0
66 #define PHB_MEM_ST_OFFSET 0x01D0
67 #define PHB_AER_OFFSET 0x0200
68 #define PHB_CONFIG_0_HIGH 0x0220
69 #define PHB_CONFIG_0_LOW 0x0230
70 #define PHB_CONFIG_0_END 0x0240
71 #define PHB_MEM_2_LOW 0x02B0
72 #define PHB_MEM_2_HIGH 0x02C0
73 #define PHB_MEM_2_SIZE_HIGH 0x02D0
74 #define PHB_MEM_2_SIZE_LOW 0x02E0
75 #define PHB_DOSHOLE_OFFSET 0x08E0
77 /* CalIOC2 specific */
78 #define PHB_SAVIOR_L2 0x0DB0
79 #define PHB_PAGE_MIG_CTRL 0x0DA8
80 #define PHB_PAGE_MIG_DEBUG 0x0DA0
81 #define PHB_ROOT_COMPLEX_STATUS 0x0CB0
84 #define PHB_TCE_ENABLE 0x20000000
85 #define PHB_SLOT_DISABLE 0x1C000000
86 #define PHB_DAC_DISABLE 0x01000000
87 #define PHB_MEM2_ENABLE 0x00400000
88 #define PHB_MCSR_ENABLE 0x00100000
89 /* TAR (Table Address Register) */
90 #define TAR_SW_BITS 0x0000ffffffff800fUL
91 #define TAR_VALID 0x0000000000000008UL
92 /* CSR (Channel/DMA Status Register) */
93 #define CSR_AGENT_MASK 0xffe0ffff
94 /* CCR (Calgary Configuration Register) */
95 #define CCR_2SEC_TIMEOUT 0x000000000000000EUL
96 /* PMCR/PMDR (Page Migration Control/Debug Registers */
97 #define PMR_SOFTSTOP 0x80000000
98 #define PMR_SOFTSTOPFAULT 0x40000000
99 #define PMR_HARDSTOP 0x20000000
101 #define MAX_NUM_OF_PHBS 8 /* how many PHBs in total? */
102 #define MAX_NUM_CHASSIS 8 /* max number of chassis */
103 /* MAX_PHB_BUS_NUM is the maximal possible dev->bus->number */
104 #define MAX_PHB_BUS_NUM (MAX_NUM_OF_PHBS * MAX_NUM_CHASSIS * 2)
105 #define PHBS_PER_CALGARY 4
107 /* register offsets in Calgary's internal register space */
108 static const unsigned long tar_offsets[] = {
115 static const unsigned long split_queue_offsets[] = {
116 0x4870 /* SPLIT QUEUE 0 */,
117 0x5870 /* SPLIT QUEUE 1 */,
118 0x6870 /* SPLIT QUEUE 2 */,
119 0x7870 /* SPLIT QUEUE 3 */
122 static const unsigned long phb_offsets[] = {
129 /* PHB debug registers */
131 static const unsigned long phb_debug_offsets[] = {
132 0x4000 /* PHB 0 DEBUG */,
133 0x5000 /* PHB 1 DEBUG */,
134 0x6000 /* PHB 2 DEBUG */,
135 0x7000 /* PHB 3 DEBUG */
139 * STUFF register for each debug PHB,
140 * byte 1 = start bus number, byte 2 = end bus number
143 #define PHB_DEBUG_STUFF_OFFSET 0x0020
145 #define EMERGENCY_PAGES 32 /* = 128KB */
147 unsigned int specified_table_size = TCE_TABLE_SIZE_UNSPECIFIED;
148 static int translate_empty_slots __read_mostly = 0;
149 static int calgary_detected __read_mostly = 0;
151 static struct rio_table_hdr *rio_table_hdr __initdata;
152 static struct scal_detail *scal_devs[MAX_NUMNODES] __initdata;
153 static struct rio_detail *rio_devs[MAX_NUMNODES * 4] __initdata;
155 struct calgary_bus_info {
157 unsigned char translation_disabled;
162 static void calgary_handle_quirks(struct iommu_table *tbl, struct pci_dev *dev);
163 static void calgary_tce_cache_blast(struct iommu_table *tbl);
164 static void calgary_dump_error_regs(struct iommu_table *tbl);
165 static void calioc2_handle_quirks(struct iommu_table *tbl, struct pci_dev *dev);
166 static void calioc2_tce_cache_blast(struct iommu_table *tbl);
167 static void calioc2_dump_error_regs(struct iommu_table *tbl);
169 static struct cal_chipset_ops calgary_chip_ops = {
170 .handle_quirks = calgary_handle_quirks,
171 .tce_cache_blast = calgary_tce_cache_blast,
172 .dump_error_regs = calgary_dump_error_regs
175 static struct cal_chipset_ops calioc2_chip_ops = {
176 .handle_quirks = calioc2_handle_quirks,
177 .tce_cache_blast = calioc2_tce_cache_blast,
178 .dump_error_regs = calioc2_dump_error_regs
181 static struct calgary_bus_info bus_info[MAX_PHB_BUS_NUM] = { { NULL, 0, 0 }, };
183 /* enable this to stress test the chip's TCE cache */
184 #ifdef CONFIG_IOMMU_DEBUG
185 int debugging __read_mostly = 1;
187 static inline unsigned long verify_bit_range(unsigned long* bitmap,
188 int expected, unsigned long start, unsigned long end)
190 unsigned long idx = start;
192 BUG_ON(start >= end);
195 if (!!test_bit(idx, bitmap) != expected)
200 /* all bits have the expected value */
203 #else /* debugging is disabled */
204 int debugging __read_mostly = 0;
206 static inline unsigned long verify_bit_range(unsigned long* bitmap,
207 int expected, unsigned long start, unsigned long end)
212 #endif /* CONFIG_IOMMU_DEBUG */
214 static inline unsigned int num_dma_pages(unsigned long dma, unsigned int dmalen)
218 npages = PAGE_ALIGN(dma + dmalen) - (dma & PAGE_MASK);
219 npages >>= PAGE_SHIFT;
224 static inline int translate_phb(struct pci_dev* dev)
226 int disabled = bus_info[dev->bus->number].translation_disabled;
230 static void iommu_range_reserve(struct iommu_table *tbl,
231 unsigned long start_addr, unsigned int npages)
235 unsigned long badbit;
238 index = start_addr >> PAGE_SHIFT;
240 /* bail out if we're asked to reserve a region we don't cover */
241 if (index >= tbl->it_size)
244 end = index + npages;
245 if (end > tbl->it_size) /* don't go off the table */
248 spin_lock_irqsave(&tbl->it_lock, flags);
250 badbit = verify_bit_range(tbl->it_map, 0, index, end);
251 if (badbit != ~0UL) {
252 if (printk_ratelimit())
253 printk(KERN_ERR "Calgary: entry already allocated at "
254 "0x%lx tbl %p dma 0x%lx npages %u\n",
255 badbit, tbl, start_addr, npages);
258 set_bit_string(tbl->it_map, index, npages);
260 spin_unlock_irqrestore(&tbl->it_lock, flags);
263 static unsigned long iommu_range_alloc(struct iommu_table *tbl,
267 unsigned long offset;
271 spin_lock_irqsave(&tbl->it_lock, flags);
273 offset = find_next_zero_string(tbl->it_map, tbl->it_hint,
274 tbl->it_size, npages);
275 if (offset == ~0UL) {
276 tbl->chip_ops->tce_cache_blast(tbl);
277 offset = find_next_zero_string(tbl->it_map, 0,
278 tbl->it_size, npages);
279 if (offset == ~0UL) {
280 printk(KERN_WARNING "Calgary: IOMMU full.\n");
281 spin_unlock_irqrestore(&tbl->it_lock, flags);
282 if (panic_on_overflow)
283 panic("Calgary: fix the allocator.\n");
285 return bad_dma_address;
289 set_bit_string(tbl->it_map, offset, npages);
290 tbl->it_hint = offset + npages;
291 BUG_ON(tbl->it_hint > tbl->it_size);
293 spin_unlock_irqrestore(&tbl->it_lock, flags);
298 static dma_addr_t iommu_alloc(struct iommu_table *tbl, void *vaddr,
299 unsigned int npages, int direction)
302 dma_addr_t ret = bad_dma_address;
304 entry = iommu_range_alloc(tbl, npages);
306 if (unlikely(entry == bad_dma_address))
309 /* set the return dma address */
310 ret = (entry << PAGE_SHIFT) | ((unsigned long)vaddr & ~PAGE_MASK);
312 /* put the TCEs in the HW table */
313 tce_build(tbl, entry, npages, (unsigned long)vaddr & PAGE_MASK,
319 printk(KERN_WARNING "Calgary: failed to allocate %u pages in "
320 "iommu %p\n", npages, tbl);
321 return bad_dma_address;
324 static void iommu_free(struct iommu_table *tbl, dma_addr_t dma_addr,
328 unsigned long badbit;
329 unsigned long badend;
332 /* were we called with bad_dma_address? */
333 badend = bad_dma_address + (EMERGENCY_PAGES * PAGE_SIZE);
334 if (unlikely((dma_addr >= bad_dma_address) && (dma_addr < badend))) {
335 printk(KERN_ERR "Calgary: driver tried unmapping bad DMA "
336 "address 0x%Lx\n", dma_addr);
341 entry = dma_addr >> PAGE_SHIFT;
343 BUG_ON(entry + npages > tbl->it_size);
345 tce_free(tbl, entry, npages);
347 spin_lock_irqsave(&tbl->it_lock, flags);
349 badbit = verify_bit_range(tbl->it_map, 1, entry, entry + npages);
350 if (badbit != ~0UL) {
351 if (printk_ratelimit())
352 printk(KERN_ERR "Calgary: bit is off at 0x%lx "
353 "tbl %p dma 0x%Lx entry 0x%lx npages %u\n",
354 badbit, tbl, dma_addr, entry, npages);
357 __clear_bit_string(tbl->it_map, entry, npages);
359 spin_unlock_irqrestore(&tbl->it_lock, flags);
362 static inline struct iommu_table *find_iommu_table(struct device *dev)
364 struct pci_dev *pdev;
365 struct pci_bus *pbus;
366 struct iommu_table *tbl;
368 pdev = to_pci_dev(dev);
370 /* is the device behind a bridge? */
371 if (unlikely(pdev->bus->parent))
372 pbus = pdev->bus->parent;
376 tbl = pci_iommu(pbus);
378 BUG_ON(pdev->bus->parent &&
379 (tbl->it_busno != pdev->bus->parent->number));
384 static void calgary_unmap_sg(struct device *dev,
385 struct scatterlist *sglist, int nelems, int direction)
387 struct iommu_table *tbl = find_iommu_table(dev);
389 if (!translate_phb(to_pci_dev(dev)))
394 dma_addr_t dma = sglist->dma_address;
395 unsigned int dmalen = sglist->dma_length;
400 npages = num_dma_pages(dma, dmalen);
401 iommu_free(tbl, dma, npages);
406 static int calgary_nontranslate_map_sg(struct device* dev,
407 struct scatterlist *sg, int nelems, int direction)
411 for (i = 0; i < nelems; i++ ) {
412 struct scatterlist *s = &sg[i];
414 s->dma_address = virt_to_bus(page_address(s->page) +s->offset);
415 s->dma_length = s->length;
420 static int calgary_map_sg(struct device *dev, struct scatterlist *sg,
421 int nelems, int direction)
423 struct iommu_table *tbl = find_iommu_table(dev);
429 if (!translate_phb(to_pci_dev(dev)))
430 return calgary_nontranslate_map_sg(dev, sg, nelems, direction);
432 for (i = 0; i < nelems; i++ ) {
433 struct scatterlist *s = &sg[i];
436 vaddr = (unsigned long)page_address(s->page) + s->offset;
437 npages = num_dma_pages(vaddr, s->length);
439 entry = iommu_range_alloc(tbl, npages);
440 if (entry == bad_dma_address) {
441 /* makes sure unmap knows to stop */
446 s->dma_address = (entry << PAGE_SHIFT) | s->offset;
448 /* insert into HW table */
449 tce_build(tbl, entry, npages, vaddr & PAGE_MASK,
452 s->dma_length = s->length;
457 calgary_unmap_sg(dev, sg, nelems, direction);
458 for (i = 0; i < nelems; i++) {
459 sg[i].dma_address = bad_dma_address;
460 sg[i].dma_length = 0;
465 static dma_addr_t calgary_map_single(struct device *dev, void *vaddr,
466 size_t size, int direction)
468 dma_addr_t dma_handle = bad_dma_address;
471 struct iommu_table *tbl = find_iommu_table(dev);
473 uaddr = (unsigned long)vaddr;
474 npages = num_dma_pages(uaddr, size);
476 if (translate_phb(to_pci_dev(dev)))
477 dma_handle = iommu_alloc(tbl, vaddr, npages, direction);
479 dma_handle = virt_to_bus(vaddr);
484 static void calgary_unmap_single(struct device *dev, dma_addr_t dma_handle,
485 size_t size, int direction)
487 struct iommu_table *tbl = find_iommu_table(dev);
490 if (!translate_phb(to_pci_dev(dev)))
493 npages = num_dma_pages(dma_handle, size);
494 iommu_free(tbl, dma_handle, npages);
497 static void* calgary_alloc_coherent(struct device *dev, size_t size,
498 dma_addr_t *dma_handle, gfp_t flag)
502 unsigned int npages, order;
503 struct iommu_table *tbl = find_iommu_table(dev);
505 size = PAGE_ALIGN(size); /* size rounded up to full pages */
506 npages = size >> PAGE_SHIFT;
507 order = get_order(size);
509 /* alloc enough pages (and possibly more) */
510 ret = (void *)__get_free_pages(flag, order);
513 memset(ret, 0, size);
515 if (translate_phb(to_pci_dev(dev))) {
516 /* set up tces to cover the allocated range */
517 mapping = iommu_alloc(tbl, ret, npages, DMA_BIDIRECTIONAL);
518 if (mapping == bad_dma_address)
521 *dma_handle = mapping;
522 } else /* non translated slot */
523 *dma_handle = virt_to_bus(ret);
528 free_pages((unsigned long)ret, get_order(size));
534 static const struct dma_mapping_ops calgary_dma_ops = {
535 .alloc_coherent = calgary_alloc_coherent,
536 .map_single = calgary_map_single,
537 .unmap_single = calgary_unmap_single,
538 .map_sg = calgary_map_sg,
539 .unmap_sg = calgary_unmap_sg,
542 static inline void __iomem * busno_to_bbar(unsigned char num)
544 return bus_info[num].bbar;
547 static inline int busno_to_phbid(unsigned char num)
549 return bus_info[num].phbid;
552 static inline unsigned long split_queue_offset(unsigned char num)
554 size_t idx = busno_to_phbid(num);
556 return split_queue_offsets[idx];
559 static inline unsigned long tar_offset(unsigned char num)
561 size_t idx = busno_to_phbid(num);
563 return tar_offsets[idx];
566 static inline unsigned long phb_offset(unsigned char num)
568 size_t idx = busno_to_phbid(num);
570 return phb_offsets[idx];
573 static inline void __iomem* calgary_reg(void __iomem *bar, unsigned long offset)
575 unsigned long target = ((unsigned long)bar) | offset;
576 return (void __iomem*)target;
579 static inline int is_calioc2(unsigned short device)
581 return (device == PCI_DEVICE_ID_IBM_CALIOC2);
584 static inline int is_calgary(unsigned short device)
586 return (device == PCI_DEVICE_ID_IBM_CALGARY);
589 static inline int is_cal_pci_dev(unsigned short device)
591 return (is_calgary(device) || is_calioc2(device));
594 static void calgary_tce_cache_blast(struct iommu_table *tbl)
599 void __iomem *bbar = tbl->bbar;
600 void __iomem *target;
602 /* disable arbitration on the bus */
603 target = calgary_reg(bbar, phb_offset(tbl->it_busno) | PHB_AER_OFFSET);
607 /* read plssr to ensure it got there */
608 target = calgary_reg(bbar, phb_offset(tbl->it_busno) | PHB_PLSSR_OFFSET);
611 /* poll split queues until all DMA activity is done */
612 target = calgary_reg(bbar, split_queue_offset(tbl->it_busno));
616 } while ((val & 0xff) != 0xff && i < 100);
618 printk(KERN_WARNING "Calgary: PCI bus not quiesced, "
619 "continuing anyway\n");
621 /* invalidate TCE cache */
622 target = calgary_reg(bbar, tar_offset(tbl->it_busno));
623 writeq(tbl->tar_val, target);
625 /* enable arbitration */
626 target = calgary_reg(bbar, phb_offset(tbl->it_busno) | PHB_AER_OFFSET);
628 (void)readl(target); /* flush */
631 static void calioc2_tce_cache_blast(struct iommu_table *tbl)
633 void __iomem *bbar = tbl->bbar;
634 void __iomem *target;
639 unsigned char bus = tbl->it_busno;
642 printk(KERN_DEBUG "Calgary: CalIOC2 bus 0x%x entering tce cache blast "
643 "sequence - count %d\n", bus, count);
645 /* 1. using the Page Migration Control reg set SoftStop */
646 target = calgary_reg(bbar, phb_offset(bus) | PHB_PAGE_MIG_CTRL);
647 val = be32_to_cpu(readl(target));
648 printk(KERN_DEBUG "1a. read 0x%x [LE] from %p\n", val, target);
650 printk(KERN_DEBUG "1b. writing 0x%x [LE] to %p\n", val, target);
651 writel(cpu_to_be32(val), target);
653 /* 2. poll split queues until all DMA activity is done */
654 printk(KERN_DEBUG "2a. starting to poll split queues\n");
655 target = calgary_reg(bbar, split_queue_offset(bus));
657 val64 = readq(target);
659 } while ((val64 & 0xff) != 0xff && i < 100);
661 printk(KERN_WARNING "CalIOC2: PCI bus not quiesced, "
662 "continuing anyway\n");
664 /* 3. poll Page Migration DEBUG for SoftStopFault */
665 target = calgary_reg(bbar, phb_offset(bus) | PHB_PAGE_MIG_DEBUG);
666 val = be32_to_cpu(readl(target));
667 printk(KERN_DEBUG "3. read 0x%x [LE] from %p\n", val, target);
669 /* 4. if SoftStopFault - goto (1) */
670 if (val & PMR_SOFTSTOPFAULT) {
674 printk(KERN_WARNING "CalIOC2: too many SoftStopFaults, "
675 "aborting TCE cache flush sequence!\n");
676 return; /* pray for the best */
680 /* 5. Slam into HardStop by reading PHB_PAGE_MIG_CTRL */
681 target = calgary_reg(bbar, phb_offset(bus) | PHB_PAGE_MIG_CTRL);
682 printk(KERN_DEBUG "5a. slamming into HardStop by reading %p\n", target);
683 val = be32_to_cpu(readl(target));
684 printk(KERN_DEBUG "5b. read 0x%x [LE] from %p\n", val, target);
685 target = calgary_reg(bbar, phb_offset(bus) | PHB_PAGE_MIG_DEBUG);
686 val = be32_to_cpu(readl(target));
687 printk(KERN_DEBUG "5c. read 0x%x [LE] from %p (debug)\n", val, target);
689 /* 6. invalidate TCE cache */
690 printk(KERN_DEBUG "6. invalidating TCE cache\n");
691 target = calgary_reg(bbar, tar_offset(bus));
692 writeq(tbl->tar_val, target);
694 /* 7. Re-read PMCR */
695 printk(KERN_DEBUG "7a. Re-reading PMCR\n");
696 target = calgary_reg(bbar, phb_offset(bus) | PHB_PAGE_MIG_CTRL);
697 val = be32_to_cpu(readl(target));
698 printk(KERN_DEBUG "7b. read 0x%x [LE] from %p\n", val, target);
700 /* 8. Remove HardStop */
701 printk(KERN_DEBUG "8a. removing HardStop from PMCR\n");
702 target = calgary_reg(bbar, phb_offset(bus) | PHB_PAGE_MIG_CTRL);
704 printk(KERN_DEBUG "8b. writing 0x%x [LE] to %p\n", val, target);
705 writel(cpu_to_be32(val), target);
706 val = be32_to_cpu(readl(target));
707 printk(KERN_DEBUG "8c. read 0x%x [LE] from %p\n", val, target);
710 static void __init calgary_reserve_mem_region(struct pci_dev *dev, u64 start,
713 unsigned int numpages;
715 limit = limit | 0xfffff;
718 numpages = ((limit - start) >> PAGE_SHIFT);
719 iommu_range_reserve(pci_iommu(dev->bus), start, numpages);
722 static void __init calgary_reserve_peripheral_mem_1(struct pci_dev *dev)
724 void __iomem *target;
725 u64 low, high, sizelow;
727 struct iommu_table *tbl = pci_iommu(dev->bus);
728 unsigned char busnum = dev->bus->number;
729 void __iomem *bbar = tbl->bbar;
731 /* peripheral MEM_1 region */
732 target = calgary_reg(bbar, phb_offset(busnum) | PHB_MEM_1_LOW);
733 low = be32_to_cpu(readl(target));
734 target = calgary_reg(bbar, phb_offset(busnum) | PHB_MEM_1_HIGH);
735 high = be32_to_cpu(readl(target));
736 target = calgary_reg(bbar, phb_offset(busnum) | PHB_MEM_1_SIZE);
737 sizelow = be32_to_cpu(readl(target));
739 start = (high << 32) | low;
742 calgary_reserve_mem_region(dev, start, limit);
745 static void __init calgary_reserve_peripheral_mem_2(struct pci_dev *dev)
747 void __iomem *target;
749 u64 low, high, sizelow, sizehigh;
751 struct iommu_table *tbl = pci_iommu(dev->bus);
752 unsigned char busnum = dev->bus->number;
753 void __iomem *bbar = tbl->bbar;
756 target = calgary_reg(bbar, phb_offset(busnum) | PHB_CONFIG_RW_OFFSET);
757 val32 = be32_to_cpu(readl(target));
758 if (!(val32 & PHB_MEM2_ENABLE))
761 target = calgary_reg(bbar, phb_offset(busnum) | PHB_MEM_2_LOW);
762 low = be32_to_cpu(readl(target));
763 target = calgary_reg(bbar, phb_offset(busnum) | PHB_MEM_2_HIGH);
764 high = be32_to_cpu(readl(target));
765 target = calgary_reg(bbar, phb_offset(busnum) | PHB_MEM_2_SIZE_LOW);
766 sizelow = be32_to_cpu(readl(target));
767 target = calgary_reg(bbar, phb_offset(busnum) | PHB_MEM_2_SIZE_HIGH);
768 sizehigh = be32_to_cpu(readl(target));
770 start = (high << 32) | low;
771 limit = (sizehigh << 32) | sizelow;
773 calgary_reserve_mem_region(dev, start, limit);
777 * some regions of the IO address space do not get translated, so we
778 * must not give devices IO addresses in those regions. The regions
779 * are the 640KB-1MB region and the two PCI peripheral memory holes.
780 * Reserve all of them in the IOMMU bitmap to avoid giving them out
783 static void __init calgary_reserve_regions(struct pci_dev *dev)
787 struct iommu_table *tbl = pci_iommu(dev->bus);
789 /* reserve EMERGENCY_PAGES from bad_dma_address and up */
790 iommu_range_reserve(tbl, bad_dma_address, EMERGENCY_PAGES);
792 /* avoid the BIOS/VGA first 640KB-1MB region */
793 /* for CalIOC2 - avoid the entire first MB */
794 if (is_calgary(dev->device)) {
795 start = (640 * 1024);
796 npages = ((1024 - 640) * 1024) >> PAGE_SHIFT;
797 } else { /* calioc2 */
799 npages = (1 * 1024 * 1024) >> PAGE_SHIFT;
801 iommu_range_reserve(tbl, start, npages);
803 /* reserve the two PCI peripheral memory regions in IO space */
804 calgary_reserve_peripheral_mem_1(dev);
805 calgary_reserve_peripheral_mem_2(dev);
808 static int __init calgary_setup_tar(struct pci_dev *dev, void __iomem *bbar)
812 void __iomem *target;
814 struct iommu_table *tbl;
816 /* build TCE tables for each PHB */
817 ret = build_tce_table(dev, bbar);
821 tbl = pci_iommu(dev->bus);
822 tbl->it_base = (unsigned long)bus_info[dev->bus->number].tce_space;
823 tce_free(tbl, 0, tbl->it_size);
825 if (is_calgary(dev->device))
826 tbl->chip_ops = &calgary_chip_ops;
827 else if (is_calioc2(dev->device))
828 tbl->chip_ops = &calioc2_chip_ops;
832 calgary_reserve_regions(dev);
834 /* set TARs for each PHB */
835 target = calgary_reg(bbar, tar_offset(dev->bus->number));
836 val64 = be64_to_cpu(readq(target));
838 /* zero out all TAR bits under sw control */
839 val64 &= ~TAR_SW_BITS;
840 table_phys = (u64)__pa(tbl->it_base);
844 BUG_ON(specified_table_size > TCE_TABLE_SIZE_8M);
845 val64 |= (u64) specified_table_size;
847 tbl->tar_val = cpu_to_be64(val64);
849 writeq(tbl->tar_val, target);
850 readq(target); /* flush */
855 static void __init calgary_free_bus(struct pci_dev *dev)
858 struct iommu_table *tbl = pci_iommu(dev->bus);
859 void __iomem *target;
860 unsigned int bitmapsz;
862 target = calgary_reg(tbl->bbar, tar_offset(dev->bus->number));
863 val64 = be64_to_cpu(readq(target));
864 val64 &= ~TAR_SW_BITS;
865 writeq(cpu_to_be64(val64), target);
866 readq(target); /* flush */
868 bitmapsz = tbl->it_size / BITS_PER_BYTE;
869 free_pages((unsigned long)tbl->it_map, get_order(bitmapsz));
874 set_pci_iommu(dev->bus, NULL);
876 /* Can't free bootmem allocated memory after system is up :-( */
877 bus_info[dev->bus->number].tce_space = NULL;
880 static void calgary_dump_error_regs(struct iommu_table *tbl)
882 void __iomem *bbar = tbl->bbar;
883 void __iomem *target;
886 target = calgary_reg(bbar, phb_offset(tbl->it_busno) | PHB_CSR_OFFSET);
887 csr = be32_to_cpu(readl(target));
889 target = calgary_reg(bbar, phb_offset(tbl->it_busno) | PHB_PLSSR_OFFSET);
890 plssr = be32_to_cpu(readl(target));
892 /* If no error, the agent ID in the CSR is not valid */
893 printk(KERN_EMERG "Calgary: DMA error on Calgary PHB 0x%x, "
894 "0x%08x@CSR 0x%08x@PLSSR\n", tbl->it_busno, csr, plssr);
897 static void calioc2_dump_error_regs(struct iommu_table *tbl)
899 void __iomem *bbar = tbl->bbar;
900 u32 csr, csmr, plssr, mck, rcstat;
901 void __iomem *target;
902 unsigned long phboff = phb_offset(tbl->it_busno);
903 unsigned long erroff;
908 target = calgary_reg(bbar, phboff | PHB_CSR_OFFSET);
909 csr = be32_to_cpu(readl(target));
911 target = calgary_reg(bbar, phboff | PHB_PLSSR_OFFSET);
912 plssr = be32_to_cpu(readl(target));
914 target = calgary_reg(bbar, phboff | 0x290);
915 csmr = be32_to_cpu(readl(target));
917 target = calgary_reg(bbar, phboff | 0x800);
918 mck = be32_to_cpu(readl(target));
920 printk(KERN_EMERG "Calgary: DMA error on CalIOC2 PHB 0x%x\n",
923 printk(KERN_EMERG "Calgary: 0x%08x@CSR 0x%08x@PLSSR 0x%08x@CSMR 0x%08x@MCK\n",
924 csr, plssr, csmr, mck);
926 /* dump rest of error regs */
927 printk(KERN_EMERG "Calgary: ");
928 for (i = 0; i < ARRAY_SIZE(errregs); i++) {
929 /* err regs are at 0x810 - 0x870 */
930 erroff = (0x810 + (i * 0x10));
931 target = calgary_reg(bbar, phboff | erroff);
932 errregs[i] = be32_to_cpu(readl(target));
933 printk("0x%08x@0x%lx ", errregs[i], erroff);
937 /* root complex status */
938 target = calgary_reg(bbar, phboff | PHB_ROOT_COMPLEX_STATUS);
939 rcstat = be32_to_cpu(readl(target));
940 printk(KERN_EMERG "Calgary: 0x%08x@0x%x\n", rcstat,
941 PHB_ROOT_COMPLEX_STATUS);
944 static void calgary_watchdog(unsigned long data)
946 struct pci_dev *dev = (struct pci_dev *)data;
947 struct iommu_table *tbl = pci_iommu(dev->bus);
948 void __iomem *bbar = tbl->bbar;
950 void __iomem *target;
952 target = calgary_reg(bbar, phb_offset(tbl->it_busno) | PHB_CSR_OFFSET);
953 val32 = be32_to_cpu(readl(target));
955 /* If no error, the agent ID in the CSR is not valid */
956 if (val32 & CSR_AGENT_MASK) {
957 tbl->chip_ops->dump_error_regs(tbl);
962 /* Disable bus that caused the error */
963 target = calgary_reg(bbar, phb_offset(tbl->it_busno) |
964 PHB_CONFIG_RW_OFFSET);
965 val32 = be32_to_cpu(readl(target));
966 val32 |= PHB_SLOT_DISABLE;
967 writel(cpu_to_be32(val32), target);
968 readl(target); /* flush */
970 /* Reset the timer */
971 mod_timer(&tbl->watchdog_timer, jiffies + 2 * HZ);
975 static void __init calgary_set_split_completion_timeout(void __iomem *bbar,
976 unsigned char busnum, unsigned long timeout)
979 void __iomem *target;
980 unsigned int phb_shift = ~0; /* silence gcc */
983 switch (busno_to_phbid(busnum)) {
984 case 0: phb_shift = (63 - 19);
986 case 1: phb_shift = (63 - 23);
988 case 2: phb_shift = (63 - 27);
990 case 3: phb_shift = (63 - 35);
993 BUG_ON(busno_to_phbid(busnum));
996 target = calgary_reg(bbar, CALGARY_CONFIG_REG);
997 val64 = be64_to_cpu(readq(target));
999 /* zero out this PHB's timer bits */
1000 mask = ~(0xFUL << phb_shift);
1002 val64 |= (timeout << phb_shift);
1003 writeq(cpu_to_be64(val64), target);
1004 readq(target); /* flush */
1007 static void calioc2_handle_quirks(struct iommu_table *tbl, struct pci_dev *dev)
1009 unsigned char busnum = dev->bus->number;
1010 void __iomem *bbar = tbl->bbar;
1011 void __iomem *target;
1015 * CalIOC2 designers recommend setting bit 8 in 0xnDB0 to 1
1017 target = calgary_reg(bbar, phb_offset(busnum) | PHB_SAVIOR_L2);
1018 val = cpu_to_be32(readl(target));
1020 writel(cpu_to_be32(val), target);
1023 static void calgary_handle_quirks(struct iommu_table *tbl, struct pci_dev *dev)
1025 unsigned char busnum = dev->bus->number;
1028 * Give split completion a longer timeout on bus 1 for aic94xx
1029 * http://bugzilla.kernel.org/show_bug.cgi?id=7180
1031 if (is_calgary(dev->device) && (busnum == 1))
1032 calgary_set_split_completion_timeout(tbl->bbar, busnum,
1036 static void __init calgary_enable_translation(struct pci_dev *dev)
1039 unsigned char busnum;
1040 void __iomem *target;
1042 struct iommu_table *tbl;
1044 busnum = dev->bus->number;
1045 tbl = pci_iommu(dev->bus);
1048 /* enable TCE in PHB Config Register */
1049 target = calgary_reg(bbar, phb_offset(busnum) | PHB_CONFIG_RW_OFFSET);
1050 val32 = be32_to_cpu(readl(target));
1051 val32 |= PHB_TCE_ENABLE | PHB_DAC_DISABLE | PHB_MCSR_ENABLE;
1053 printk(KERN_INFO "Calgary: enabling translation on %s PHB %#x\n",
1054 (dev->device == PCI_DEVICE_ID_IBM_CALGARY) ?
1055 "Calgary" : "CalIOC2", busnum);
1056 printk(KERN_INFO "Calgary: errant DMAs will now be prevented on this "
1059 writel(cpu_to_be32(val32), target);
1060 readl(target); /* flush */
1062 init_timer(&tbl->watchdog_timer);
1063 tbl->watchdog_timer.function = &calgary_watchdog;
1064 tbl->watchdog_timer.data = (unsigned long)dev;
1065 mod_timer(&tbl->watchdog_timer, jiffies);
1068 static void __init calgary_disable_translation(struct pci_dev *dev)
1071 unsigned char busnum;
1072 void __iomem *target;
1074 struct iommu_table *tbl;
1076 busnum = dev->bus->number;
1077 tbl = pci_iommu(dev->bus);
1080 /* disable TCE in PHB Config Register */
1081 target = calgary_reg(bbar, phb_offset(busnum) | PHB_CONFIG_RW_OFFSET);
1082 val32 = be32_to_cpu(readl(target));
1083 val32 &= ~(PHB_TCE_ENABLE | PHB_DAC_DISABLE | PHB_MCSR_ENABLE);
1085 printk(KERN_INFO "Calgary: disabling translation on PHB %#x!\n", busnum);
1086 writel(cpu_to_be32(val32), target);
1087 readl(target); /* flush */
1089 del_timer_sync(&tbl->watchdog_timer);
1092 static void __init calgary_init_one_nontraslated(struct pci_dev *dev)
1095 set_pci_iommu(dev->bus, NULL);
1097 /* is the device behind a bridge? */
1098 if (dev->bus->parent)
1099 dev->bus->parent->self = dev;
1101 dev->bus->self = dev;
1104 static int __init calgary_init_one(struct pci_dev *dev)
1107 struct iommu_table *tbl;
1110 BUG_ON(dev->bus->number >= MAX_PHB_BUS_NUM);
1112 bbar = busno_to_bbar(dev->bus->number);
1113 ret = calgary_setup_tar(dev, bbar);
1119 if (dev->bus->parent) {
1120 if (dev->bus->parent->self)
1121 printk(KERN_WARNING "Calgary: IEEEE, dev %p has "
1122 "bus->parent->self!\n", dev);
1123 dev->bus->parent->self = dev;
1125 dev->bus->self = dev;
1127 tbl = pci_iommu(dev->bus);
1128 tbl->chip_ops->handle_quirks(tbl, dev);
1130 calgary_enable_translation(dev);
1138 static int __init calgary_locate_bbars(void)
1141 int rioidx, phb, bus;
1143 void __iomem *target;
1144 unsigned long offset;
1145 u8 start_bus, end_bus;
1149 for (rioidx = 0; rioidx < rio_table_hdr->num_rio_dev; rioidx++) {
1150 struct rio_detail *rio = rio_devs[rioidx];
1152 if ((rio->type != COMPAT_CALGARY) && (rio->type != ALT_CALGARY))
1155 /* map entire 1MB of Calgary config space */
1156 bbar = ioremap_nocache(rio->BBAR, 1024 * 1024);
1160 for (phb = 0; phb < PHBS_PER_CALGARY; phb++) {
1161 offset = phb_debug_offsets[phb] | PHB_DEBUG_STUFF_OFFSET;
1162 target = calgary_reg(bbar, offset);
1164 val = be32_to_cpu(readl(target));
1166 start_bus = (u8)((val & 0x00FF0000) >> 16);
1167 end_bus = (u8)((val & 0x0000FF00) >> 8);
1170 for (bus = start_bus; bus <= end_bus; bus++) {
1171 bus_info[bus].bbar = bbar;
1172 bus_info[bus].phbid = phb;
1175 bus_info[start_bus].bbar = bbar;
1176 bus_info[start_bus].phbid = phb;
1184 /* scan bus_info and iounmap any bbars we previously ioremap'd */
1185 for (bus = 0; bus < ARRAY_SIZE(bus_info); bus++)
1186 if (bus_info[bus].bbar)
1187 iounmap(bus_info[bus].bbar);
1192 static int __init calgary_init(void)
1195 struct pci_dev *dev = NULL;
1198 ret = calgary_locate_bbars();
1203 dev = pci_get_device(PCI_VENDOR_ID_IBM, PCI_ANY_ID, dev);
1206 if (!is_cal_pci_dev(dev->device))
1208 if (!translate_phb(dev)) {
1209 calgary_init_one_nontraslated(dev);
1212 tce_space = bus_info[dev->bus->number].tce_space;
1213 if (!tce_space && !translate_empty_slots)
1216 ret = calgary_init_one(dev);
1225 dev = pci_get_device_reverse(PCI_VENDOR_ID_IBM,
1229 if (!is_cal_pci_dev(dev->device))
1231 if (!translate_phb(dev)) {
1235 if (!bus_info[dev->bus->number].tce_space && !translate_empty_slots)
1238 calgary_disable_translation(dev);
1239 calgary_free_bus(dev);
1240 pci_dev_put(dev); /* Undo calgary_init_one()'s pci_dev_get() */
1246 static inline int __init determine_tce_table_size(u64 ram)
1250 if (specified_table_size != TCE_TABLE_SIZE_UNSPECIFIED)
1251 return specified_table_size;
1254 * Table sizes are from 0 to 7 (TCE_TABLE_SIZE_64K to
1255 * TCE_TABLE_SIZE_8M). Table size 0 has 8K entries and each
1256 * larger table size has twice as many entries, so shift the
1257 * max ram address by 13 to divide by 8K and then look at the
1258 * order of the result to choose between 0-7.
1260 ret = get_order(ram >> 13);
1261 if (ret > TCE_TABLE_SIZE_8M)
1262 ret = TCE_TABLE_SIZE_8M;
1267 static int __init build_detail_arrays(void)
1270 int i, scal_detail_size, rio_detail_size;
1272 if (rio_table_hdr->num_scal_dev > MAX_NUMNODES){
1274 "Calgary: MAX_NUMNODES too low! Defined as %d, "
1275 "but system has %d nodes.\n",
1276 MAX_NUMNODES, rio_table_hdr->num_scal_dev);
1280 switch (rio_table_hdr->version){
1282 scal_detail_size = 11;
1283 rio_detail_size = 13;
1286 scal_detail_size = 12;
1287 rio_detail_size = 15;
1291 "Calgary: Invalid Rio Grande Table Version: %d\n",
1292 rio_table_hdr->version);
1296 ptr = ((unsigned long)rio_table_hdr) + 3;
1297 for (i = 0; i < rio_table_hdr->num_scal_dev;
1298 i++, ptr += scal_detail_size)
1299 scal_devs[i] = (struct scal_detail *)ptr;
1301 for (i = 0; i < rio_table_hdr->num_rio_dev;
1302 i++, ptr += rio_detail_size)
1303 rio_devs[i] = (struct rio_detail *)ptr;
1308 static int __init calgary_bus_has_devices(int bus, unsigned short pci_dev)
1313 if (pci_dev == PCI_DEVICE_ID_IBM_CALIOC2) {
1315 * FIXME: properly scan for devices accross the
1316 * PCI-to-PCI bridge on every CalIOC2 port.
1321 for (dev = 1; dev < 8; dev++) {
1322 val = read_pci_config(bus, dev, 0, 0);
1323 if (val != 0xffffffff)
1326 return (val != 0xffffffff);
1329 void __init detect_calgary(void)
1333 int calgary_found = 0;
1335 unsigned int offset, prev_offset;
1339 * if the user specified iommu=off or iommu=soft or we found
1340 * another HW IOMMU already, bail out.
1342 if (swiotlb || no_iommu || iommu_detected)
1348 if (!early_pci_allowed())
1351 printk(KERN_DEBUG "Calgary: detecting Calgary via BIOS EBDA area\n");
1353 ptr = (unsigned long)phys_to_virt(get_bios_ebda());
1355 rio_table_hdr = NULL;
1359 * The next offset is stored in the 1st word.
1360 * Only parse up until the offset increases:
1362 while (offset > prev_offset) {
1363 /* The block id is stored in the 2nd word */
1364 if (*((unsigned short *)(ptr + offset + 2)) == 0x4752){
1365 /* set the pointer past the offset & block id */
1366 rio_table_hdr = (struct rio_table_hdr *)(ptr + offset + 4);
1369 prev_offset = offset;
1370 offset = *((unsigned short *)(ptr + offset));
1372 if (!rio_table_hdr) {
1373 printk(KERN_DEBUG "Calgary: Unable to locate Rio Grande table "
1374 "in EBDA - bailing!\n");
1378 ret = build_detail_arrays();
1380 printk(KERN_DEBUG "Calgary: build_detail_arrays ret %d\n", ret);
1384 specified_table_size = determine_tce_table_size(end_pfn * PAGE_SIZE);
1386 for (bus = 0; bus < MAX_PHB_BUS_NUM; bus++) {
1387 struct calgary_bus_info *info = &bus_info[bus];
1388 unsigned short pci_device;
1391 val = read_pci_config(bus, 0, 0, 0);
1392 pci_device = (val & 0xFFFF0000) >> 16;
1394 if (!is_cal_pci_dev(pci_device))
1397 if (info->translation_disabled)
1400 if (calgary_bus_has_devices(bus, pci_device) ||
1401 translate_empty_slots) {
1402 tbl = alloc_tce_table();
1405 info->tce_space = tbl;
1410 printk(KERN_DEBUG "Calgary: finished detection, Calgary %s\n",
1411 calgary_found ? "found" : "not found");
1413 if (calgary_found) {
1415 calgary_detected = 1;
1416 printk(KERN_INFO "PCI-DMA: Calgary IOMMU detected.\n");
1417 printk(KERN_INFO "PCI-DMA: Calgary TCE table spec is %d, "
1418 "CONFIG_IOMMU_DEBUG is %s.\n", specified_table_size,
1419 debugging ? "enabled" : "disabled");
1424 for (--bus; bus >= 0; --bus) {
1425 struct calgary_bus_info *info = &bus_info[bus];
1427 if (info->tce_space)
1428 free_tce_table(info->tce_space);
1432 int __init calgary_iommu_init(void)
1436 if (no_iommu || swiotlb)
1439 if (!calgary_detected)
1442 /* ok, we're trying to use Calgary - let's roll */
1443 printk(KERN_INFO "PCI-DMA: Using Calgary IOMMU\n");
1445 ret = calgary_init();
1447 printk(KERN_ERR "PCI-DMA: Calgary init failed %d, "
1448 "falling back to no_iommu\n", ret);
1449 if (end_pfn > MAX_DMA32_PFN)
1450 printk(KERN_ERR "WARNING more than 4GB of memory, "
1451 "32bit PCI may malfunction.\n");
1456 bad_dma_address = 0x0;
1457 dma_ops = &calgary_dma_ops;
1462 static int __init calgary_parse_options(char *p)
1464 unsigned int bridge;
1469 if (!strncmp(p, "64k", 3))
1470 specified_table_size = TCE_TABLE_SIZE_64K;
1471 else if (!strncmp(p, "128k", 4))
1472 specified_table_size = TCE_TABLE_SIZE_128K;
1473 else if (!strncmp(p, "256k", 4))
1474 specified_table_size = TCE_TABLE_SIZE_256K;
1475 else if (!strncmp(p, "512k", 4))
1476 specified_table_size = TCE_TABLE_SIZE_512K;
1477 else if (!strncmp(p, "1M", 2))
1478 specified_table_size = TCE_TABLE_SIZE_1M;
1479 else if (!strncmp(p, "2M", 2))
1480 specified_table_size = TCE_TABLE_SIZE_2M;
1481 else if (!strncmp(p, "4M", 2))
1482 specified_table_size = TCE_TABLE_SIZE_4M;
1483 else if (!strncmp(p, "8M", 2))
1484 specified_table_size = TCE_TABLE_SIZE_8M;
1486 len = strlen("translate_empty_slots");
1487 if (!strncmp(p, "translate_empty_slots", len))
1488 translate_empty_slots = 1;
1490 len = strlen("disable");
1491 if (!strncmp(p, "disable", len)) {
1497 bridge = simple_strtol(p, &endp, 0);
1501 if (bridge < MAX_PHB_BUS_NUM) {
1502 printk(KERN_INFO "Calgary: disabling "
1503 "translation for PHB %#x\n", bridge);
1504 bus_info[bridge].translation_disabled = 1;
1508 p = strpbrk(p, ",");
1516 __setup("calgary=", calgary_parse_options);
1518 static void __init calgary_fixup_one_tce_space(struct pci_dev *dev)
1520 struct iommu_table *tbl;
1521 unsigned int npages;
1524 tbl = pci_iommu(dev->bus);
1526 for (i = 0; i < 4; i++) {
1527 struct resource *r = &dev->resource[PCI_BRIDGE_RESOURCES + i];
1529 /* Don't give out TCEs that map MEM resources */
1530 if (!(r->flags & IORESOURCE_MEM))
1533 /* 0-based? we reserve the whole 1st MB anyway */
1537 /* cover the whole region */
1538 npages = (r->end - r->start) >> PAGE_SHIFT;
1541 iommu_range_reserve(tbl, r->start, npages);
1545 static int __init calgary_fixup_tce_spaces(void)
1547 struct pci_dev *dev = NULL;
1550 if (no_iommu || swiotlb || !calgary_detected)
1553 printk(KERN_DEBUG "Calgary: fixing up tce spaces\n");
1556 dev = pci_get_device(PCI_VENDOR_ID_IBM, PCI_ANY_ID, dev);
1559 if (!is_cal_pci_dev(dev->device))
1561 if (!translate_phb(dev))
1564 tce_space = bus_info[dev->bus->number].tce_space;
1568 calgary_fixup_one_tce_space(dev);
1576 * We need to be call after pcibios_assign_resources (fs_initcall level)
1577 * and before device_initcall.
1579 rootfs_initcall(calgary_fixup_tce_spaces);