2 * Intel Multiprocessor Specification 1.1 and 1.4
3 * compliant MP-table parsing routines.
5 * (c) 1995 Alan Cox, Building #3 <alan@redhat.com>
6 * (c) 1998, 1999, 2000 Ingo Molnar <mingo@redhat.com>
9 * Erich Boleyn : MP v1.4 and additional changes.
10 * Alan Cox : Added EBDA scanning
11 * Ingo Molnar : various cleanups and rewrites
12 * Maciej W. Rozycki: Bits for default MP configurations
13 * Paul Diefenbaugh: Added full ACPI support
17 #include <linux/init.h>
18 #include <linux/delay.h>
19 #include <linux/bootmem.h>
20 #include <linux/smp_lock.h>
21 #include <linux/kernel_stat.h>
22 #include <linux/mc146818rtc.h>
23 #include <linux/acpi.h>
24 #include <linux/module.h>
28 #include <asm/mpspec.h>
29 #include <asm/pgalloc.h>
30 #include <asm/io_apic.h>
31 #include <asm/proto.h>
34 /* Have we found an MP table */
36 unsigned int __initdata maxcpus = NR_CPUS;
41 * Various Linux-internal data structures created from the
44 unsigned char apic_version [MAX_APICS];
45 DECLARE_BITMAP(mp_bus_not_pci, MAX_MP_BUSSES);
46 int mp_bus_id_to_pci_bus [MAX_MP_BUSSES] = { [0 ... MAX_MP_BUSSES-1] = -1 };
48 static int mp_current_pci_id = 0;
49 /* I/O APIC entries */
50 struct mpc_config_ioapic mp_ioapics[MAX_IO_APICS];
52 /* # of MP IRQ source entries */
53 struct mpc_config_intsrc mp_irqs[MAX_IRQ_SOURCES];
55 /* MP IRQ source entries */
59 unsigned long mp_lapic_addr = 0;
63 /* Processor that is doing the boot up */
64 unsigned int boot_cpu_id = -1U;
65 /* Internal processor count */
66 unsigned int num_processors __initdata = 0;
68 unsigned disabled_cpus __initdata;
70 /* Bitmask of physically existing CPUs */
71 physid_mask_t phys_cpu_present_map = PHYSID_MASK_NONE;
73 u8 bios_cpu_apicid[NR_CPUS] = { [0 ... NR_CPUS-1] = BAD_APICID };
77 * Intel MP BIOS table parsing routines:
81 * Checksum an MP configuration block.
84 static int __init mpf_checksum(unsigned char *mp, int len)
94 static void __cpuinit MP_processor_info (struct mpc_config_processor *m)
100 if (!(m->mpc_cpuflag & CPU_ENABLED)) {
105 printk(KERN_INFO "Processor #%d %d:%d APIC version %d\n",
107 (m->mpc_cpufeature & CPU_FAMILY_MASK)>>8,
108 (m->mpc_cpufeature & CPU_MODEL_MASK)>>4,
111 if (m->mpc_cpuflag & CPU_BOOTPROCESSOR) {
112 Dprintk(" Bootup CPU\n");
113 boot_cpu_id = m->mpc_apicid;
115 if (num_processors >= NR_CPUS) {
116 printk(KERN_WARNING "WARNING: NR_CPUS limit of %i reached."
117 " Processor ignored.\n", NR_CPUS);
122 cpus_complement(tmp_map, cpu_present_map);
123 cpu = first_cpu(tmp_map);
126 if ((int)m->mpc_apicid > MAX_APICS) {
127 printk(KERN_ERR "Processor #%d INVALID. (Max ID: %d).\n",
128 m->mpc_apicid, MAX_APICS);
132 ver = m->mpc_apicver;
134 physid_set(m->mpc_apicid, phys_cpu_present_map);
139 printk(KERN_ERR "BIOS bug, APIC version is 0 for CPU#%d! fixing up to 0x10. (tell your hw vendor)\n", m->mpc_apicid);
142 apic_version[m->mpc_apicid] = ver;
143 if (m->mpc_cpuflag & CPU_BOOTPROCESSOR) {
145 * bios_cpu_apicid is required to have processors listed
146 * in same order as logical cpu numbers. Hence the first
147 * entry is BSP, and so on.
151 bios_cpu_apicid[cpu] = m->mpc_apicid;
152 x86_cpu_to_apicid[cpu] = m->mpc_apicid;
154 cpu_set(cpu, cpu_possible_map);
155 cpu_set(cpu, cpu_present_map);
158 static void __init MP_bus_info (struct mpc_config_bus *m)
162 memcpy(str, m->mpc_bustype, 6);
164 Dprintk("Bus #%d is %s\n", m->mpc_busid, str);
166 if (strncmp(str, "ISA", 3) == 0) {
167 set_bit(m->mpc_busid, mp_bus_not_pci);
168 } else if (strncmp(str, "PCI", 3) == 0) {
169 clear_bit(m->mpc_busid, mp_bus_not_pci);
170 mp_bus_id_to_pci_bus[m->mpc_busid] = mp_current_pci_id;
173 printk(KERN_ERR "Unknown bustype %s\n", str);
177 static void __init MP_ioapic_info (struct mpc_config_ioapic *m)
179 if (!(m->mpc_flags & MPC_APIC_USABLE))
182 printk("I/O APIC #%d Version %d at 0x%X.\n",
183 m->mpc_apicid, m->mpc_apicver, m->mpc_apicaddr);
184 if (nr_ioapics >= MAX_IO_APICS) {
185 printk(KERN_ERR "Max # of I/O APICs (%d) exceeded (found %d).\n",
186 MAX_IO_APICS, nr_ioapics);
187 panic("Recompile kernel with bigger MAX_IO_APICS!.\n");
189 if (!m->mpc_apicaddr) {
190 printk(KERN_ERR "WARNING: bogus zero I/O APIC address"
191 " found in MP table, skipping!\n");
194 mp_ioapics[nr_ioapics] = *m;
198 static void __init MP_intsrc_info (struct mpc_config_intsrc *m)
200 mp_irqs [mp_irq_entries] = *m;
201 Dprintk("Int: type %d, pol %d, trig %d, bus %d,"
202 " IRQ %02x, APIC ID %x, APIC INT %02x\n",
203 m->mpc_irqtype, m->mpc_irqflag & 3,
204 (m->mpc_irqflag >> 2) & 3, m->mpc_srcbus,
205 m->mpc_srcbusirq, m->mpc_dstapic, m->mpc_dstirq);
206 if (++mp_irq_entries >= MAX_IRQ_SOURCES)
207 panic("Max # of irq sources exceeded!!\n");
210 static void __init MP_lintsrc_info (struct mpc_config_lintsrc *m)
212 Dprintk("Lint: type %d, pol %d, trig %d, bus %d,"
213 " IRQ %02x, APIC ID %x, APIC LINT %02x\n",
214 m->mpc_irqtype, m->mpc_irqflag & 3,
215 (m->mpc_irqflag >> 2) &3, m->mpc_srcbusid,
216 m->mpc_srcbusirq, m->mpc_destapic, m->mpc_destapiclint);
223 static int __init smp_read_mpc(struct mp_config_table *mpc)
226 int count=sizeof(*mpc);
227 unsigned char *mpt=((unsigned char *)mpc)+count;
229 if (memcmp(mpc->mpc_signature,MPC_SIGNATURE,4)) {
230 printk("SMP mptable: bad signature [%c%c%c%c]!\n",
231 mpc->mpc_signature[0],
232 mpc->mpc_signature[1],
233 mpc->mpc_signature[2],
234 mpc->mpc_signature[3]);
237 if (mpf_checksum((unsigned char *)mpc,mpc->mpc_length)) {
238 printk("SMP mptable: checksum error!\n");
241 if (mpc->mpc_spec!=0x01 && mpc->mpc_spec!=0x04) {
242 printk(KERN_ERR "SMP mptable: bad table version (%d)!!\n",
246 if (!mpc->mpc_lapic) {
247 printk(KERN_ERR "SMP mptable: null local APIC address!\n");
250 memcpy(str,mpc->mpc_oem,8);
252 printk(KERN_INFO "OEM ID: %s ",str);
254 memcpy(str,mpc->mpc_productid,12);
256 printk("Product ID: %s ",str);
258 printk("APIC at: 0x%X\n",mpc->mpc_lapic);
260 /* save the local APIC address, it might be non-default */
262 mp_lapic_addr = mpc->mpc_lapic;
265 * Now process the configuration blocks.
267 while (count < mpc->mpc_length) {
271 struct mpc_config_processor *m=
272 (struct mpc_config_processor *)mpt;
274 MP_processor_info(m);
281 struct mpc_config_bus *m=
282 (struct mpc_config_bus *)mpt;
290 struct mpc_config_ioapic *m=
291 (struct mpc_config_ioapic *)mpt;
299 struct mpc_config_intsrc *m=
300 (struct mpc_config_intsrc *)mpt;
309 struct mpc_config_lintsrc *m=
310 (struct mpc_config_lintsrc *)mpt;
318 clustered_apic_check();
320 printk(KERN_ERR "SMP mptable: no processors registered!\n");
321 return num_processors;
324 static int __init ELCR_trigger(unsigned int irq)
328 port = 0x4d0 + (irq >> 3);
329 return (inb(port) >> (irq & 7)) & 1;
332 static void __init construct_default_ioirq_mptable(int mpc_default_type)
334 struct mpc_config_intsrc intsrc;
336 int ELCR_fallback = 0;
338 intsrc.mpc_type = MP_INTSRC;
339 intsrc.mpc_irqflag = 0; /* conforming */
340 intsrc.mpc_srcbus = 0;
341 intsrc.mpc_dstapic = mp_ioapics[0].mpc_apicid;
343 intsrc.mpc_irqtype = mp_INT;
346 * If true, we have an ISA/PCI system with no IRQ entries
347 * in the MP table. To prevent the PCI interrupts from being set up
348 * incorrectly, we try to use the ELCR. The sanity check to see if
349 * there is good ELCR data is very simple - IRQ0, 1, 2 and 13 can
350 * never be level sensitive, so we simply see if the ELCR agrees.
351 * If it does, we assume it's valid.
353 if (mpc_default_type == 5) {
354 printk(KERN_INFO "ISA/PCI bus type with no IRQ information... falling back to ELCR\n");
356 if (ELCR_trigger(0) || ELCR_trigger(1) || ELCR_trigger(2) || ELCR_trigger(13))
357 printk(KERN_ERR "ELCR contains invalid data... not using ELCR\n");
359 printk(KERN_INFO "Using ELCR to identify PCI interrupts\n");
364 for (i = 0; i < 16; i++) {
365 switch (mpc_default_type) {
367 if (i == 0 || i == 13)
368 continue; /* IRQ0 & IRQ13 not connected */
372 continue; /* IRQ2 is never connected */
377 * If the ELCR indicates a level-sensitive interrupt, we
378 * copy that information over to the MP table in the
379 * irqflag field (level sensitive, active high polarity).
382 intsrc.mpc_irqflag = 13;
384 intsrc.mpc_irqflag = 0;
387 intsrc.mpc_srcbusirq = i;
388 intsrc.mpc_dstirq = i ? i : 2; /* IRQ0 to INTIN2 */
389 MP_intsrc_info(&intsrc);
392 intsrc.mpc_irqtype = mp_ExtINT;
393 intsrc.mpc_srcbusirq = 0;
394 intsrc.mpc_dstirq = 0; /* 8259A to INTIN0 */
395 MP_intsrc_info(&intsrc);
398 static inline void __init construct_default_ISA_mptable(int mpc_default_type)
400 struct mpc_config_processor processor;
401 struct mpc_config_bus bus;
402 struct mpc_config_ioapic ioapic;
403 struct mpc_config_lintsrc lintsrc;
404 int linttypes[2] = { mp_ExtINT, mp_NMI };
408 * local APIC has default address
410 mp_lapic_addr = APIC_DEFAULT_PHYS_BASE;
413 * 2 CPUs, numbered 0 & 1.
415 processor.mpc_type = MP_PROCESSOR;
416 /* Either an integrated APIC or a discrete 82489DX. */
417 processor.mpc_apicver = mpc_default_type > 4 ? 0x10 : 0x01;
418 processor.mpc_cpuflag = CPU_ENABLED;
419 processor.mpc_cpufeature = (boot_cpu_data.x86 << 8) |
420 (boot_cpu_data.x86_model << 4) |
421 boot_cpu_data.x86_mask;
422 processor.mpc_featureflag = boot_cpu_data.x86_capability[0];
423 processor.mpc_reserved[0] = 0;
424 processor.mpc_reserved[1] = 0;
425 for (i = 0; i < 2; i++) {
426 processor.mpc_apicid = i;
427 MP_processor_info(&processor);
430 bus.mpc_type = MP_BUS;
432 switch (mpc_default_type) {
434 printk(KERN_ERR "???\nUnknown standard configuration %d\n",
439 memcpy(bus.mpc_bustype, "ISA ", 6);
443 if (mpc_default_type > 4) {
445 memcpy(bus.mpc_bustype, "PCI ", 6);
449 ioapic.mpc_type = MP_IOAPIC;
450 ioapic.mpc_apicid = 2;
451 ioapic.mpc_apicver = mpc_default_type > 4 ? 0x10 : 0x01;
452 ioapic.mpc_flags = MPC_APIC_USABLE;
453 ioapic.mpc_apicaddr = 0xFEC00000;
454 MP_ioapic_info(&ioapic);
457 * We set up most of the low 16 IO-APIC pins according to MPS rules.
459 construct_default_ioirq_mptable(mpc_default_type);
461 lintsrc.mpc_type = MP_LINTSRC;
462 lintsrc.mpc_irqflag = 0; /* conforming */
463 lintsrc.mpc_srcbusid = 0;
464 lintsrc.mpc_srcbusirq = 0;
465 lintsrc.mpc_destapic = MP_APIC_ALL;
466 for (i = 0; i < 2; i++) {
467 lintsrc.mpc_irqtype = linttypes[i];
468 lintsrc.mpc_destapiclint = i;
469 MP_lintsrc_info(&lintsrc);
473 static struct intel_mp_floating *mpf_found;
476 * Scan the memory blocks for an SMP configuration block.
478 void __init get_smp_config (void)
480 struct intel_mp_floating *mpf = mpf_found;
483 * ACPI supports both logical (e.g. Hyper-Threading) and physical
484 * processors, where MPS only supports physical.
486 if (acpi_lapic && acpi_ioapic) {
487 printk(KERN_INFO "Using ACPI (MADT) for SMP configuration information\n");
491 printk(KERN_INFO "Using ACPI for processor (LAPIC) configuration information\n");
493 printk("Intel MultiProcessor Specification v1.%d\n", mpf->mpf_specification);
496 * Now see if we need to read further.
498 if (mpf->mpf_feature1 != 0) {
500 printk(KERN_INFO "Default MP configuration #%d\n", mpf->mpf_feature1);
501 construct_default_ISA_mptable(mpf->mpf_feature1);
503 } else if (mpf->mpf_physptr) {
506 * Read the physical hardware table. Anything here will
507 * override the defaults.
509 if (!smp_read_mpc(phys_to_virt(mpf->mpf_physptr))) {
510 smp_found_config = 0;
511 printk(KERN_ERR "BIOS bug, MP table errors detected!...\n");
512 printk(KERN_ERR "... disabling SMP support. (tell your hw vendor)\n");
516 * If there are no explicit MP IRQ entries, then we are
517 * broken. We set up most of the low 16 IO-APIC pins to
518 * ISA defaults and hope it will work.
520 if (!mp_irq_entries) {
521 struct mpc_config_bus bus;
523 printk(KERN_ERR "BIOS bug, no explicit IRQ entries, using default mptable. (tell your hw vendor)\n");
525 bus.mpc_type = MP_BUS;
527 memcpy(bus.mpc_bustype, "ISA ", 6);
530 construct_default_ioirq_mptable(0);
536 printk(KERN_INFO "Processors: %d\n", num_processors);
538 * Only use the first configuration found.
542 static int __init smp_scan_config (unsigned long base, unsigned long length)
544 extern void __bad_mpf_size(void);
545 unsigned int *bp = phys_to_virt(base);
546 struct intel_mp_floating *mpf;
548 Dprintk("Scan SMP from %p for %ld bytes.\n", bp,length);
549 if (sizeof(*mpf) != 16)
553 mpf = (struct intel_mp_floating *)bp;
554 if ((*bp == SMP_MAGIC_IDENT) &&
555 (mpf->mpf_length == 1) &&
556 !mpf_checksum((unsigned char *)bp, 16) &&
557 ((mpf->mpf_specification == 1)
558 || (mpf->mpf_specification == 4)) ) {
560 smp_found_config = 1;
561 reserve_bootmem_generic(virt_to_phys(mpf), PAGE_SIZE);
562 if (mpf->mpf_physptr)
563 reserve_bootmem_generic(mpf->mpf_physptr, PAGE_SIZE);
573 void __init find_smp_config(void)
575 unsigned int address;
578 * FIXME: Linux assumes you have 640K of base ram..
579 * this continues the error...
581 * 1) Scan the bottom 1K for a signature
582 * 2) Scan the top 1K of base RAM
583 * 3) Scan the 64K of bios
585 if (smp_scan_config(0x0,0x400) ||
586 smp_scan_config(639*0x400,0x400) ||
587 smp_scan_config(0xF0000,0x10000))
590 * If it is an SMP machine we should know now.
592 * there is a real-mode segmented pointer pointing to the
593 * 4K EBDA area at 0x40E, calculate and scan it here.
595 * NOTE! There are Linux loaders that will corrupt the EBDA
596 * area, and as such this kind of SMP config may be less
597 * trustworthy, simply because the SMP table may have been
598 * stomped on during early boot. These loaders are buggy and
602 address = *(unsigned short *)phys_to_virt(0x40E);
604 if (smp_scan_config(address, 0x1000))
607 /* If we have come this far, we did not find an MP table */
608 printk(KERN_INFO "No mptable found.\n");
611 /* --------------------------------------------------------------------------
612 ACPI-based MP Configuration
613 -------------------------------------------------------------------------- */
617 void __init mp_register_lapic_address(u64 address)
619 mp_lapic_addr = (unsigned long) address;
620 set_fixmap_nocache(FIX_APIC_BASE, mp_lapic_addr);
621 if (boot_cpu_id == -1U)
622 boot_cpu_id = GET_APIC_ID(apic_read(APIC_ID));
624 Dprintk("Boot CPU = %d\n", boot_cpu_physical_apicid);
627 void __cpuinit mp_register_lapic (u8 id, u8 enabled)
629 struct mpc_config_processor processor;
632 if (id >= MAX_APICS) {
633 printk(KERN_WARNING "Processor #%d invalid (max %d)\n",
638 if (id == boot_cpu_physical_apicid)
641 processor.mpc_type = MP_PROCESSOR;
642 processor.mpc_apicid = id;
643 processor.mpc_apicver = GET_APIC_VERSION(apic_read(APIC_LVR));
644 processor.mpc_cpuflag = (enabled ? CPU_ENABLED : 0);
645 processor.mpc_cpuflag |= (boot_cpu ? CPU_BOOTPROCESSOR : 0);
646 processor.mpc_cpufeature = (boot_cpu_data.x86 << 8) |
647 (boot_cpu_data.x86_model << 4) | boot_cpu_data.x86_mask;
648 processor.mpc_featureflag = boot_cpu_data.x86_capability[0];
649 processor.mpc_reserved[0] = 0;
650 processor.mpc_reserved[1] = 0;
652 MP_processor_info(&processor);
656 #define MP_MAX_IOAPIC_PIN 127
658 static struct mp_ioapic_routing {
662 u32 pin_programmed[4];
663 } mp_ioapic_routing[MAX_IO_APICS];
665 static int mp_find_ioapic(int gsi)
669 /* Find the IOAPIC that manages this GSI. */
670 for (i = 0; i < nr_ioapics; i++) {
671 if ((gsi >= mp_ioapic_routing[i].gsi_start)
672 && (gsi <= mp_ioapic_routing[i].gsi_end))
676 printk(KERN_ERR "ERROR: Unable to locate IOAPIC for GSI %d\n", gsi);
680 void __init mp_register_ioapic(u8 id, u32 address, u32 gsi_base)
684 if (nr_ioapics >= MAX_IO_APICS) {
685 printk(KERN_ERR "ERROR: Max # of I/O APICs (%d) exceeded "
686 "(found %d)\n", MAX_IO_APICS, nr_ioapics);
687 panic("Recompile kernel with bigger MAX_IO_APICS!\n");
690 printk(KERN_ERR "WARNING: Bogus (zero) I/O APIC address"
691 " found in MADT table, skipping!\n");
697 mp_ioapics[idx].mpc_type = MP_IOAPIC;
698 mp_ioapics[idx].mpc_flags = MPC_APIC_USABLE;
699 mp_ioapics[idx].mpc_apicaddr = address;
701 set_fixmap_nocache(FIX_IO_APIC_BASE_0 + idx, address);
702 mp_ioapics[idx].mpc_apicid = id;
703 mp_ioapics[idx].mpc_apicver = io_apic_get_version(idx);
706 * Build basic IRQ lookup table to facilitate gsi->io_apic lookups
707 * and to prevent reprogramming of IOAPIC pins (PCI IRQs).
709 mp_ioapic_routing[idx].apic_id = mp_ioapics[idx].mpc_apicid;
710 mp_ioapic_routing[idx].gsi_start = gsi_base;
711 mp_ioapic_routing[idx].gsi_end = gsi_base +
712 io_apic_get_redir_entries(idx);
714 printk(KERN_INFO "IOAPIC[%d]: apic_id %d, version %d, address 0x%x, "
715 "GSI %d-%d\n", idx, mp_ioapics[idx].mpc_apicid,
716 mp_ioapics[idx].mpc_apicver, mp_ioapics[idx].mpc_apicaddr,
717 mp_ioapic_routing[idx].gsi_start,
718 mp_ioapic_routing[idx].gsi_end);
722 mp_override_legacy_irq(u8 bus_irq, u8 polarity, u8 trigger, u32 gsi)
724 struct mpc_config_intsrc intsrc;
729 * Convert 'gsi' to 'ioapic.pin'.
731 ioapic = mp_find_ioapic(gsi);
734 pin = gsi - mp_ioapic_routing[ioapic].gsi_start;
737 * TBD: This check is for faulty timer entries, where the override
738 * erroneously sets the trigger to level, resulting in a HUGE
739 * increase of timer interrupts!
741 if ((bus_irq == 0) && (trigger == 3))
744 intsrc.mpc_type = MP_INTSRC;
745 intsrc.mpc_irqtype = mp_INT;
746 intsrc.mpc_irqflag = (trigger << 2) | polarity;
747 intsrc.mpc_srcbus = MP_ISA_BUS;
748 intsrc.mpc_srcbusirq = bus_irq; /* IRQ */
749 intsrc.mpc_dstapic = mp_ioapics[ioapic].mpc_apicid; /* APIC ID */
750 intsrc.mpc_dstirq = pin; /* INTIN# */
752 Dprintk("Int: type %d, pol %d, trig %d, bus %d, irq %d, %d-%d\n",
753 intsrc.mpc_irqtype, intsrc.mpc_irqflag & 3,
754 (intsrc.mpc_irqflag >> 2) & 3, intsrc.mpc_srcbus,
755 intsrc.mpc_srcbusirq, intsrc.mpc_dstapic, intsrc.mpc_dstirq);
757 mp_irqs[mp_irq_entries] = intsrc;
758 if (++mp_irq_entries == MAX_IRQ_SOURCES)
759 panic("Max # of irq sources exceeded!\n");
762 void __init mp_config_acpi_legacy_irqs(void)
764 struct mpc_config_intsrc intsrc;
769 * Fabricate the legacy ISA bus (bus #31).
771 set_bit(MP_ISA_BUS, mp_bus_not_pci);
774 * Locate the IOAPIC that manages the ISA IRQs (0-15).
776 ioapic = mp_find_ioapic(0);
780 intsrc.mpc_type = MP_INTSRC;
781 intsrc.mpc_irqflag = 0; /* Conforming */
782 intsrc.mpc_srcbus = MP_ISA_BUS;
783 intsrc.mpc_dstapic = mp_ioapics[ioapic].mpc_apicid;
786 * Use the default configuration for the IRQs 0-15. Unless
787 * overridden by (MADT) interrupt source override entries.
789 for (i = 0; i < 16; i++) {
792 for (idx = 0; idx < mp_irq_entries; idx++) {
793 struct mpc_config_intsrc *irq = mp_irqs + idx;
795 /* Do we already have a mapping for this ISA IRQ? */
796 if (irq->mpc_srcbus == MP_ISA_BUS && irq->mpc_srcbusirq == i)
799 /* Do we already have a mapping for this IOAPIC pin */
800 if ((irq->mpc_dstapic == intsrc.mpc_dstapic) &&
801 (irq->mpc_dstirq == i))
805 if (idx != mp_irq_entries) {
806 printk(KERN_DEBUG "ACPI: IRQ%d used by override.\n", i);
807 continue; /* IRQ already used */
810 intsrc.mpc_irqtype = mp_INT;
811 intsrc.mpc_srcbusirq = i; /* Identity mapped */
812 intsrc.mpc_dstirq = i;
814 Dprintk("Int: type %d, pol %d, trig %d, bus %d, irq %d, "
815 "%d-%d\n", intsrc.mpc_irqtype, intsrc.mpc_irqflag & 3,
816 (intsrc.mpc_irqflag >> 2) & 3, intsrc.mpc_srcbus,
817 intsrc.mpc_srcbusirq, intsrc.mpc_dstapic,
820 mp_irqs[mp_irq_entries] = intsrc;
821 if (++mp_irq_entries == MAX_IRQ_SOURCES)
822 panic("Max # of irq sources exceeded!\n");
826 #define MAX_GSI_NUM 4096
828 int mp_register_gsi(u32 gsi, int triggering, int polarity)
833 static int pci_irq = 16;
835 * Mapping between Global System Interrupts, which
836 * represent all possible interrupts, to the IRQs
837 * assigned to actual devices.
839 static int gsi_to_irq[MAX_GSI_NUM];
841 if (acpi_irq_model != ACPI_IRQ_MODEL_IOAPIC)
844 /* Don't set up the ACPI SCI because it's already set up */
845 if (acpi_fadt.sci_int == gsi)
848 ioapic = mp_find_ioapic(gsi);
850 printk(KERN_WARNING "No IOAPIC for GSI %u\n", gsi);
854 ioapic_pin = gsi - mp_ioapic_routing[ioapic].gsi_start;
857 * Avoid pin reprogramming. PRTs typically include entries
858 * with redundant pin->gsi mappings (but unique PCI devices);
859 * we only program the IOAPIC on the first.
861 bit = ioapic_pin % 32;
862 idx = (ioapic_pin < 32) ? 0 : (ioapic_pin / 32);
864 printk(KERN_ERR "Invalid reference to IOAPIC pin "
865 "%d-%d\n", mp_ioapic_routing[ioapic].apic_id,
869 if ((1<<bit) & mp_ioapic_routing[ioapic].pin_programmed[idx]) {
870 Dprintk(KERN_DEBUG "Pin %d-%d already programmed\n",
871 mp_ioapic_routing[ioapic].apic_id, ioapic_pin);
872 return gsi_to_irq[gsi];
875 mp_ioapic_routing[ioapic].pin_programmed[idx] |= (1<<bit);
877 if (triggering == ACPI_LEVEL_SENSITIVE) {
879 * For PCI devices assign IRQs in order, avoiding gaps
880 * due to unused I/O APIC pins.
883 if (gsi < MAX_GSI_NUM) {
885 * Retain the VIA chipset work-around (gsi > 15), but
886 * avoid a problem where the 8254 timer (IRQ0) is setup
887 * via an override (so it's not on pin 0 of the ioapic),
888 * and at the same time, the pin 0 interrupt is a PCI
889 * type. The gsi > 15 test could cause these two pins
890 * to be shared as IRQ0, and they are not shareable.
891 * So test for this condition, and if necessary, avoid
894 if (gsi > 15 || (gsi == 0 && !timer_uses_ioapic_pin_0))
897 * Don't assign IRQ used by ACPI SCI
899 if (gsi == acpi_fadt.sci_int)
901 gsi_to_irq[irq] = gsi;
903 printk(KERN_ERR "GSI %u is too high\n", gsi);
908 io_apic_set_pci_routing(ioapic, ioapic_pin, gsi,
909 triggering == ACPI_EDGE_SENSITIVE ? 0 : 1,
910 polarity == ACPI_ACTIVE_HIGH ? 0 : 1);
913 #endif /*CONFIG_ACPI*/