2 * Intel Multiprocessor Specification 1.1 and 1.4
3 * compliant MP-table parsing routines.
5 * (c) 1995 Alan Cox, Building #3 <alan@redhat.com>
6 * (c) 1998, 1999, 2000 Ingo Molnar <mingo@redhat.com>
9 * Erich Boleyn : MP v1.4 and additional changes.
10 * Alan Cox : Added EBDA scanning
11 * Ingo Molnar : various cleanups and rewrites
12 * Maciej W. Rozycki: Bits for default MP configurations
13 * Paul Diefenbaugh: Added full ACPI support
17 #include <linux/init.h>
18 #include <linux/delay.h>
19 #include <linux/bootmem.h>
20 #include <linux/smp_lock.h>
21 #include <linux/kernel_stat.h>
22 #include <linux/mc146818rtc.h>
23 #include <linux/acpi.h>
24 #include <linux/module.h>
28 #include <asm/mpspec.h>
29 #include <asm/pgalloc.h>
30 #include <asm/io_apic.h>
31 #include <asm/proto.h>
34 /* Have we found an MP table */
36 unsigned int __initdata maxcpus = NR_CPUS;
41 * Various Linux-internal data structures created from the
44 unsigned char apic_version [MAX_APICS];
45 unsigned char mp_bus_id_to_type [MAX_MP_BUSSES] = { [0 ... MAX_MP_BUSSES-1] = -1 };
46 int mp_bus_id_to_pci_bus [MAX_MP_BUSSES] = { [0 ... MAX_MP_BUSSES-1] = -1 };
48 static int mp_current_pci_id = 0;
49 /* I/O APIC entries */
50 struct mpc_config_ioapic mp_ioapics[MAX_IO_APICS];
52 /* # of MP IRQ source entries */
53 struct mpc_config_intsrc mp_irqs[MAX_IRQ_SOURCES];
55 /* MP IRQ source entries */
60 unsigned long mp_lapic_addr = 0;
64 /* Processor that is doing the boot up */
65 unsigned int boot_cpu_id = -1U;
66 /* Internal processor count */
67 unsigned int num_processors __initdata = 0;
69 unsigned disabled_cpus __initdata;
71 /* Bitmask of physically existing CPUs */
72 physid_mask_t phys_cpu_present_map = PHYSID_MASK_NONE;
74 /* ACPI MADT entry parsing functions */
76 extern struct acpi_boot_flags acpi_boot;
77 extern int acpi_parse_lapic (acpi_table_entry_header *header);
78 extern int acpi_parse_lapic_addr_ovr (acpi_table_entry_header *header);
79 extern int acpi_parse_lapic_nmi (acpi_table_entry_header *header);
80 extern int acpi_parse_ioapic (acpi_table_entry_header *header);
81 #endif /*CONFIG_ACPI*/
83 u8 bios_cpu_apicid[NR_CPUS] = { [0 ... NR_CPUS-1] = BAD_APICID };
87 * Intel MP BIOS table parsing routines:
91 * Checksum an MP configuration block.
94 static int __init mpf_checksum(unsigned char *mp, int len)
104 static void __cpuinit MP_processor_info (struct mpc_config_processor *m)
110 if (!(m->mpc_cpuflag & CPU_ENABLED)) {
115 printk(KERN_INFO "Processor #%d %d:%d APIC version %d\n",
117 (m->mpc_cpufeature & CPU_FAMILY_MASK)>>8,
118 (m->mpc_cpufeature & CPU_MODEL_MASK)>>4,
121 if (m->mpc_cpuflag & CPU_BOOTPROCESSOR) {
122 Dprintk(" Bootup CPU\n");
123 boot_cpu_id = m->mpc_apicid;
125 if (num_processors >= NR_CPUS) {
126 printk(KERN_WARNING "WARNING: NR_CPUS limit of %i reached."
127 " Processor ignored.\n", NR_CPUS);
132 cpus_complement(tmp_map, cpu_present_map);
133 cpu = first_cpu(tmp_map);
136 if ((int)m->mpc_apicid > MAX_APICS) {
137 printk(KERN_ERR "Processor #%d INVALID. (Max ID: %d).\n",
138 m->mpc_apicid, MAX_APICS);
142 ver = m->mpc_apicver;
144 physid_set(m->mpc_apicid, phys_cpu_present_map);
149 printk(KERN_ERR "BIOS bug, APIC version is 0 for CPU#%d! fixing up to 0x10. (tell your hw vendor)\n", m->mpc_apicid);
152 apic_version[m->mpc_apicid] = ver;
153 if (m->mpc_cpuflag & CPU_BOOTPROCESSOR) {
155 * bios_cpu_apicid is required to have processors listed
156 * in same order as logical cpu numbers. Hence the first
157 * entry is BSP, and so on.
161 bios_cpu_apicid[cpu] = m->mpc_apicid;
162 x86_cpu_to_apicid[cpu] = m->mpc_apicid;
164 cpu_set(cpu, cpu_possible_map);
165 cpu_set(cpu, cpu_present_map);
168 static void __init MP_bus_info (struct mpc_config_bus *m)
172 memcpy(str, m->mpc_bustype, 6);
174 Dprintk("Bus #%d is %s\n", m->mpc_busid, str);
176 if (strncmp(str, "ISA", 3) == 0) {
177 mp_bus_id_to_type[m->mpc_busid] = MP_BUS_ISA;
178 } else if (strncmp(str, "EISA", 4) == 0) {
179 mp_bus_id_to_type[m->mpc_busid] = MP_BUS_EISA;
180 } else if (strncmp(str, "PCI", 3) == 0) {
181 mp_bus_id_to_type[m->mpc_busid] = MP_BUS_PCI;
182 mp_bus_id_to_pci_bus[m->mpc_busid] = mp_current_pci_id;
184 } else if (strncmp(str, "MCA", 3) == 0) {
185 mp_bus_id_to_type[m->mpc_busid] = MP_BUS_MCA;
187 printk(KERN_ERR "Unknown bustype %s\n", str);
191 static void __init MP_ioapic_info (struct mpc_config_ioapic *m)
193 if (!(m->mpc_flags & MPC_APIC_USABLE))
196 printk("I/O APIC #%d Version %d at 0x%X.\n",
197 m->mpc_apicid, m->mpc_apicver, m->mpc_apicaddr);
198 if (nr_ioapics >= MAX_IO_APICS) {
199 printk(KERN_ERR "Max # of I/O APICs (%d) exceeded (found %d).\n",
200 MAX_IO_APICS, nr_ioapics);
201 panic("Recompile kernel with bigger MAX_IO_APICS!.\n");
203 if (!m->mpc_apicaddr) {
204 printk(KERN_ERR "WARNING: bogus zero I/O APIC address"
205 " found in MP table, skipping!\n");
208 mp_ioapics[nr_ioapics] = *m;
212 static void __init MP_intsrc_info (struct mpc_config_intsrc *m)
214 mp_irqs [mp_irq_entries] = *m;
215 Dprintk("Int: type %d, pol %d, trig %d, bus %d,"
216 " IRQ %02x, APIC ID %x, APIC INT %02x\n",
217 m->mpc_irqtype, m->mpc_irqflag & 3,
218 (m->mpc_irqflag >> 2) & 3, m->mpc_srcbus,
219 m->mpc_srcbusirq, m->mpc_dstapic, m->mpc_dstirq);
220 if (++mp_irq_entries >= MAX_IRQ_SOURCES)
221 panic("Max # of irq sources exceeded!!\n");
224 static void __init MP_lintsrc_info (struct mpc_config_lintsrc *m)
226 Dprintk("Lint: type %d, pol %d, trig %d, bus %d,"
227 " IRQ %02x, APIC ID %x, APIC LINT %02x\n",
228 m->mpc_irqtype, m->mpc_irqflag & 3,
229 (m->mpc_irqflag >> 2) &3, m->mpc_srcbusid,
230 m->mpc_srcbusirq, m->mpc_destapic, m->mpc_destapiclint);
232 * Well it seems all SMP boards in existence
233 * use ExtINT/LVT1 == LINT0 and
234 * NMI/LVT2 == LINT1 - the following check
235 * will show us if this assumptions is false.
236 * Until then we do not have to add baggage.
238 if ((m->mpc_irqtype == mp_ExtINT) &&
239 (m->mpc_destapiclint != 0))
241 if ((m->mpc_irqtype == mp_NMI) &&
242 (m->mpc_destapiclint != 1))
250 static int __init smp_read_mpc(struct mp_config_table *mpc)
253 int count=sizeof(*mpc);
254 unsigned char *mpt=((unsigned char *)mpc)+count;
256 if (memcmp(mpc->mpc_signature,MPC_SIGNATURE,4)) {
257 printk("SMP mptable: bad signature [%c%c%c%c]!\n",
258 mpc->mpc_signature[0],
259 mpc->mpc_signature[1],
260 mpc->mpc_signature[2],
261 mpc->mpc_signature[3]);
264 if (mpf_checksum((unsigned char *)mpc,mpc->mpc_length)) {
265 printk("SMP mptable: checksum error!\n");
268 if (mpc->mpc_spec!=0x01 && mpc->mpc_spec!=0x04) {
269 printk(KERN_ERR "SMP mptable: bad table version (%d)!!\n",
273 if (!mpc->mpc_lapic) {
274 printk(KERN_ERR "SMP mptable: null local APIC address!\n");
277 memcpy(str,mpc->mpc_oem,8);
279 printk(KERN_INFO "OEM ID: %s ",str);
281 memcpy(str,mpc->mpc_productid,12);
283 printk("Product ID: %s ",str);
285 printk("APIC at: 0x%X\n",mpc->mpc_lapic);
287 /* save the local APIC address, it might be non-default */
289 mp_lapic_addr = mpc->mpc_lapic;
292 * Now process the configuration blocks.
294 while (count < mpc->mpc_length) {
298 struct mpc_config_processor *m=
299 (struct mpc_config_processor *)mpt;
301 MP_processor_info(m);
308 struct mpc_config_bus *m=
309 (struct mpc_config_bus *)mpt;
317 struct mpc_config_ioapic *m=
318 (struct mpc_config_ioapic *)mpt;
326 struct mpc_config_intsrc *m=
327 (struct mpc_config_intsrc *)mpt;
336 struct mpc_config_lintsrc *m=
337 (struct mpc_config_lintsrc *)mpt;
345 clustered_apic_check();
347 printk(KERN_ERR "SMP mptable: no processors registered!\n");
348 return num_processors;
351 static int __init ELCR_trigger(unsigned int irq)
355 port = 0x4d0 + (irq >> 3);
356 return (inb(port) >> (irq & 7)) & 1;
359 static void __init construct_default_ioirq_mptable(int mpc_default_type)
361 struct mpc_config_intsrc intsrc;
363 int ELCR_fallback = 0;
365 intsrc.mpc_type = MP_INTSRC;
366 intsrc.mpc_irqflag = 0; /* conforming */
367 intsrc.mpc_srcbus = 0;
368 intsrc.mpc_dstapic = mp_ioapics[0].mpc_apicid;
370 intsrc.mpc_irqtype = mp_INT;
373 * If true, we have an ISA/PCI system with no IRQ entries
374 * in the MP table. To prevent the PCI interrupts from being set up
375 * incorrectly, we try to use the ELCR. The sanity check to see if
376 * there is good ELCR data is very simple - IRQ0, 1, 2 and 13 can
377 * never be level sensitive, so we simply see if the ELCR agrees.
378 * If it does, we assume it's valid.
380 if (mpc_default_type == 5) {
381 printk(KERN_INFO "ISA/PCI bus type with no IRQ information... falling back to ELCR\n");
383 if (ELCR_trigger(0) || ELCR_trigger(1) || ELCR_trigger(2) || ELCR_trigger(13))
384 printk(KERN_ERR "ELCR contains invalid data... not using ELCR\n");
386 printk(KERN_INFO "Using ELCR to identify PCI interrupts\n");
391 for (i = 0; i < 16; i++) {
392 switch (mpc_default_type) {
394 if (i == 0 || i == 13)
395 continue; /* IRQ0 & IRQ13 not connected */
399 continue; /* IRQ2 is never connected */
404 * If the ELCR indicates a level-sensitive interrupt, we
405 * copy that information over to the MP table in the
406 * irqflag field (level sensitive, active high polarity).
409 intsrc.mpc_irqflag = 13;
411 intsrc.mpc_irqflag = 0;
414 intsrc.mpc_srcbusirq = i;
415 intsrc.mpc_dstirq = i ? i : 2; /* IRQ0 to INTIN2 */
416 MP_intsrc_info(&intsrc);
419 intsrc.mpc_irqtype = mp_ExtINT;
420 intsrc.mpc_srcbusirq = 0;
421 intsrc.mpc_dstirq = 0; /* 8259A to INTIN0 */
422 MP_intsrc_info(&intsrc);
425 static inline void __init construct_default_ISA_mptable(int mpc_default_type)
427 struct mpc_config_processor processor;
428 struct mpc_config_bus bus;
429 struct mpc_config_ioapic ioapic;
430 struct mpc_config_lintsrc lintsrc;
431 int linttypes[2] = { mp_ExtINT, mp_NMI };
435 * local APIC has default address
437 mp_lapic_addr = APIC_DEFAULT_PHYS_BASE;
440 * 2 CPUs, numbered 0 & 1.
442 processor.mpc_type = MP_PROCESSOR;
443 /* Either an integrated APIC or a discrete 82489DX. */
444 processor.mpc_apicver = mpc_default_type > 4 ? 0x10 : 0x01;
445 processor.mpc_cpuflag = CPU_ENABLED;
446 processor.mpc_cpufeature = (boot_cpu_data.x86 << 8) |
447 (boot_cpu_data.x86_model << 4) |
448 boot_cpu_data.x86_mask;
449 processor.mpc_featureflag = boot_cpu_data.x86_capability[0];
450 processor.mpc_reserved[0] = 0;
451 processor.mpc_reserved[1] = 0;
452 for (i = 0; i < 2; i++) {
453 processor.mpc_apicid = i;
454 MP_processor_info(&processor);
457 bus.mpc_type = MP_BUS;
459 switch (mpc_default_type) {
461 printk(KERN_ERR "???\nUnknown standard configuration %d\n",
466 memcpy(bus.mpc_bustype, "ISA ", 6);
471 memcpy(bus.mpc_bustype, "EISA ", 6);
475 memcpy(bus.mpc_bustype, "MCA ", 6);
478 if (mpc_default_type > 4) {
480 memcpy(bus.mpc_bustype, "PCI ", 6);
484 ioapic.mpc_type = MP_IOAPIC;
485 ioapic.mpc_apicid = 2;
486 ioapic.mpc_apicver = mpc_default_type > 4 ? 0x10 : 0x01;
487 ioapic.mpc_flags = MPC_APIC_USABLE;
488 ioapic.mpc_apicaddr = 0xFEC00000;
489 MP_ioapic_info(&ioapic);
492 * We set up most of the low 16 IO-APIC pins according to MPS rules.
494 construct_default_ioirq_mptable(mpc_default_type);
496 lintsrc.mpc_type = MP_LINTSRC;
497 lintsrc.mpc_irqflag = 0; /* conforming */
498 lintsrc.mpc_srcbusid = 0;
499 lintsrc.mpc_srcbusirq = 0;
500 lintsrc.mpc_destapic = MP_APIC_ALL;
501 for (i = 0; i < 2; i++) {
502 lintsrc.mpc_irqtype = linttypes[i];
503 lintsrc.mpc_destapiclint = i;
504 MP_lintsrc_info(&lintsrc);
508 static struct intel_mp_floating *mpf_found;
511 * Scan the memory blocks for an SMP configuration block.
513 void __init get_smp_config (void)
515 struct intel_mp_floating *mpf = mpf_found;
518 * ACPI supports both logical (e.g. Hyper-Threading) and physical
519 * processors, where MPS only supports physical.
521 if (acpi_lapic && acpi_ioapic) {
522 printk(KERN_INFO "Using ACPI (MADT) for SMP configuration information\n");
526 printk(KERN_INFO "Using ACPI for processor (LAPIC) configuration information\n");
528 printk("Intel MultiProcessor Specification v1.%d\n", mpf->mpf_specification);
529 if (mpf->mpf_feature2 & (1<<7)) {
530 printk(KERN_INFO " IMCR and PIC compatibility mode.\n");
533 printk(KERN_INFO " Virtual Wire compatibility mode.\n");
538 * Now see if we need to read further.
540 if (mpf->mpf_feature1 != 0) {
542 printk(KERN_INFO "Default MP configuration #%d\n", mpf->mpf_feature1);
543 construct_default_ISA_mptable(mpf->mpf_feature1);
545 } else if (mpf->mpf_physptr) {
548 * Read the physical hardware table. Anything here will
549 * override the defaults.
551 if (!smp_read_mpc(phys_to_virt(mpf->mpf_physptr))) {
552 smp_found_config = 0;
553 printk(KERN_ERR "BIOS bug, MP table errors detected!...\n");
554 printk(KERN_ERR "... disabling SMP support. (tell your hw vendor)\n");
558 * If there are no explicit MP IRQ entries, then we are
559 * broken. We set up most of the low 16 IO-APIC pins to
560 * ISA defaults and hope it will work.
562 if (!mp_irq_entries) {
563 struct mpc_config_bus bus;
565 printk(KERN_ERR "BIOS bug, no explicit IRQ entries, using default mptable. (tell your hw vendor)\n");
567 bus.mpc_type = MP_BUS;
569 memcpy(bus.mpc_bustype, "ISA ", 6);
572 construct_default_ioirq_mptable(0);
578 printk(KERN_INFO "Processors: %d\n", num_processors);
580 * Only use the first configuration found.
584 static int __init smp_scan_config (unsigned long base, unsigned long length)
586 extern void __bad_mpf_size(void);
587 unsigned int *bp = phys_to_virt(base);
588 struct intel_mp_floating *mpf;
590 Dprintk("Scan SMP from %p for %ld bytes.\n", bp,length);
591 if (sizeof(*mpf) != 16)
595 mpf = (struct intel_mp_floating *)bp;
596 if ((*bp == SMP_MAGIC_IDENT) &&
597 (mpf->mpf_length == 1) &&
598 !mpf_checksum((unsigned char *)bp, 16) &&
599 ((mpf->mpf_specification == 1)
600 || (mpf->mpf_specification == 4)) ) {
602 smp_found_config = 1;
603 reserve_bootmem_generic(virt_to_phys(mpf), PAGE_SIZE);
604 if (mpf->mpf_physptr)
605 reserve_bootmem_generic(mpf->mpf_physptr, PAGE_SIZE);
615 void __init find_intel_smp (void)
617 unsigned int address;
620 * FIXME: Linux assumes you have 640K of base ram..
621 * this continues the error...
623 * 1) Scan the bottom 1K for a signature
624 * 2) Scan the top 1K of base RAM
625 * 3) Scan the 64K of bios
627 if (smp_scan_config(0x0,0x400) ||
628 smp_scan_config(639*0x400,0x400) ||
629 smp_scan_config(0xF0000,0x10000))
632 * If it is an SMP machine we should know now, unless the
633 * configuration is in an EISA/MCA bus machine with an
634 * extended bios data area.
636 * there is a real-mode segmented pointer pointing to the
637 * 4K EBDA area at 0x40E, calculate and scan it here.
639 * NOTE! There are Linux loaders that will corrupt the EBDA
640 * area, and as such this kind of SMP config may be less
641 * trustworthy, simply because the SMP table may have been
642 * stomped on during early boot. These loaders are buggy and
646 address = *(unsigned short *)phys_to_virt(0x40E);
648 if (smp_scan_config(address, 0x1000))
651 /* If we have come this far, we did not find an MP table */
652 printk(KERN_INFO "No mptable found.\n");
656 * - Intel MP Configuration Table
658 void __init find_smp_config (void)
664 /* --------------------------------------------------------------------------
665 ACPI-based MP Configuration
666 -------------------------------------------------------------------------- */
670 void __init mp_register_lapic_address (
673 mp_lapic_addr = (unsigned long) address;
675 set_fixmap_nocache(FIX_APIC_BASE, mp_lapic_addr);
677 if (boot_cpu_id == -1U)
678 boot_cpu_id = GET_APIC_ID(apic_read(APIC_ID));
680 Dprintk("Boot CPU = %d\n", boot_cpu_physical_apicid);
684 void __cpuinit mp_register_lapic (
688 struct mpc_config_processor processor;
691 if (id >= MAX_APICS) {
692 printk(KERN_WARNING "Processor #%d invalid (max %d)\n",
697 if (id == boot_cpu_physical_apicid)
700 processor.mpc_type = MP_PROCESSOR;
701 processor.mpc_apicid = id;
702 processor.mpc_apicver = GET_APIC_VERSION(apic_read(APIC_LVR));
703 processor.mpc_cpuflag = (enabled ? CPU_ENABLED : 0);
704 processor.mpc_cpuflag |= (boot_cpu ? CPU_BOOTPROCESSOR : 0);
705 processor.mpc_cpufeature = (boot_cpu_data.x86 << 8) |
706 (boot_cpu_data.x86_model << 4) | boot_cpu_data.x86_mask;
707 processor.mpc_featureflag = boot_cpu_data.x86_capability[0];
708 processor.mpc_reserved[0] = 0;
709 processor.mpc_reserved[1] = 0;
711 MP_processor_info(&processor);
715 #define MP_MAX_IOAPIC_PIN 127
717 static struct mp_ioapic_routing {
721 u32 pin_programmed[4];
722 } mp_ioapic_routing[MAX_IO_APICS];
725 static int mp_find_ioapic (
730 /* Find the IOAPIC that manages this GSI. */
731 for (i = 0; i < nr_ioapics; i++) {
732 if ((gsi >= mp_ioapic_routing[i].gsi_start)
733 && (gsi <= mp_ioapic_routing[i].gsi_end))
737 printk(KERN_ERR "ERROR: Unable to locate IOAPIC for GSI %d\n", gsi);
743 void __init mp_register_ioapic (
750 if (nr_ioapics >= MAX_IO_APICS) {
751 printk(KERN_ERR "ERROR: Max # of I/O APICs (%d) exceeded "
752 "(found %d)\n", MAX_IO_APICS, nr_ioapics);
753 panic("Recompile kernel with bigger MAX_IO_APICS!\n");
756 printk(KERN_ERR "WARNING: Bogus (zero) I/O APIC address"
757 " found in MADT table, skipping!\n");
763 mp_ioapics[idx].mpc_type = MP_IOAPIC;
764 mp_ioapics[idx].mpc_flags = MPC_APIC_USABLE;
765 mp_ioapics[idx].mpc_apicaddr = address;
767 set_fixmap_nocache(FIX_IO_APIC_BASE_0 + idx, address);
768 mp_ioapics[idx].mpc_apicid = id;
769 mp_ioapics[idx].mpc_apicver = io_apic_get_version(idx);
772 * Build basic IRQ lookup table to facilitate gsi->io_apic lookups
773 * and to prevent reprogramming of IOAPIC pins (PCI IRQs).
775 mp_ioapic_routing[idx].apic_id = mp_ioapics[idx].mpc_apicid;
776 mp_ioapic_routing[idx].gsi_start = gsi_base;
777 mp_ioapic_routing[idx].gsi_end = gsi_base +
778 io_apic_get_redir_entries(idx);
780 printk(KERN_INFO "IOAPIC[%d]: apic_id %d, version %d, address 0x%x, "
781 "GSI %d-%d\n", idx, mp_ioapics[idx].mpc_apicid,
782 mp_ioapics[idx].mpc_apicver, mp_ioapics[idx].mpc_apicaddr,
783 mp_ioapic_routing[idx].gsi_start,
784 mp_ioapic_routing[idx].gsi_end);
790 void __init mp_override_legacy_irq (
796 struct mpc_config_intsrc intsrc;
801 * Convert 'gsi' to 'ioapic.pin'.
803 ioapic = mp_find_ioapic(gsi);
806 pin = gsi - mp_ioapic_routing[ioapic].gsi_start;
809 * TBD: This check is for faulty timer entries, where the override
810 * erroneously sets the trigger to level, resulting in a HUGE
811 * increase of timer interrupts!
813 if ((bus_irq == 0) && (trigger == 3))
816 intsrc.mpc_type = MP_INTSRC;
817 intsrc.mpc_irqtype = mp_INT;
818 intsrc.mpc_irqflag = (trigger << 2) | polarity;
819 intsrc.mpc_srcbus = MP_ISA_BUS;
820 intsrc.mpc_srcbusirq = bus_irq; /* IRQ */
821 intsrc.mpc_dstapic = mp_ioapics[ioapic].mpc_apicid; /* APIC ID */
822 intsrc.mpc_dstirq = pin; /* INTIN# */
824 Dprintk("Int: type %d, pol %d, trig %d, bus %d, irq %d, %d-%d\n",
825 intsrc.mpc_irqtype, intsrc.mpc_irqflag & 3,
826 (intsrc.mpc_irqflag >> 2) & 3, intsrc.mpc_srcbus,
827 intsrc.mpc_srcbusirq, intsrc.mpc_dstapic, intsrc.mpc_dstirq);
829 mp_irqs[mp_irq_entries] = intsrc;
830 if (++mp_irq_entries == MAX_IRQ_SOURCES)
831 panic("Max # of irq sources exceeded!\n");
837 void __init mp_config_acpi_legacy_irqs (void)
839 struct mpc_config_intsrc intsrc;
844 * Fabricate the legacy ISA bus (bus #31).
846 mp_bus_id_to_type[MP_ISA_BUS] = MP_BUS_ISA;
847 Dprintk("Bus #%d is ISA\n", MP_ISA_BUS);
850 * Locate the IOAPIC that manages the ISA IRQs (0-15).
852 ioapic = mp_find_ioapic(0);
856 intsrc.mpc_type = MP_INTSRC;
857 intsrc.mpc_irqflag = 0; /* Conforming */
858 intsrc.mpc_srcbus = MP_ISA_BUS;
859 intsrc.mpc_dstapic = mp_ioapics[ioapic].mpc_apicid;
862 * Use the default configuration for the IRQs 0-15. Unless
863 * overridden by (MADT) interrupt source override entries.
865 for (i = 0; i < 16; i++) {
868 for (idx = 0; idx < mp_irq_entries; idx++) {
869 struct mpc_config_intsrc *irq = mp_irqs + idx;
871 /* Do we already have a mapping for this ISA IRQ? */
872 if (irq->mpc_srcbus == MP_ISA_BUS && irq->mpc_srcbusirq == i)
875 /* Do we already have a mapping for this IOAPIC pin */
876 if ((irq->mpc_dstapic == intsrc.mpc_dstapic) &&
877 (irq->mpc_dstirq == i))
881 if (idx != mp_irq_entries) {
882 printk(KERN_DEBUG "ACPI: IRQ%d used by override.\n", i);
883 continue; /* IRQ already used */
886 intsrc.mpc_irqtype = mp_INT;
887 intsrc.mpc_srcbusirq = i; /* Identity mapped */
888 intsrc.mpc_dstirq = i;
890 Dprintk("Int: type %d, pol %d, trig %d, bus %d, irq %d, "
891 "%d-%d\n", intsrc.mpc_irqtype, intsrc.mpc_irqflag & 3,
892 (intsrc.mpc_irqflag >> 2) & 3, intsrc.mpc_srcbus,
893 intsrc.mpc_srcbusirq, intsrc.mpc_dstapic,
896 mp_irqs[mp_irq_entries] = intsrc;
897 if (++mp_irq_entries == MAX_IRQ_SOURCES)
898 panic("Max # of irq sources exceeded!\n");
904 #define MAX_GSI_NUM 4096
906 int mp_register_gsi(u32 gsi, int triggering, int polarity)
911 static int pci_irq = 16;
913 * Mapping between Global System Interrupts, which
914 * represent all possible interrupts, to the IRQs
915 * assigned to actual devices.
917 static int gsi_to_irq[MAX_GSI_NUM];
919 if (acpi_irq_model != ACPI_IRQ_MODEL_IOAPIC)
922 /* Don't set up the ACPI SCI because it's already set up */
923 if (acpi_fadt.sci_int == gsi)
926 ioapic = mp_find_ioapic(gsi);
928 printk(KERN_WARNING "No IOAPIC for GSI %u\n", gsi);
932 ioapic_pin = gsi - mp_ioapic_routing[ioapic].gsi_start;
935 * Avoid pin reprogramming. PRTs typically include entries
936 * with redundant pin->gsi mappings (but unique PCI devices);
937 * we only program the IOAPIC on the first.
939 bit = ioapic_pin % 32;
940 idx = (ioapic_pin < 32) ? 0 : (ioapic_pin / 32);
942 printk(KERN_ERR "Invalid reference to IOAPIC pin "
943 "%d-%d\n", mp_ioapic_routing[ioapic].apic_id,
947 if ((1<<bit) & mp_ioapic_routing[ioapic].pin_programmed[idx]) {
948 Dprintk(KERN_DEBUG "Pin %d-%d already programmed\n",
949 mp_ioapic_routing[ioapic].apic_id, ioapic_pin);
950 return gsi_to_irq[gsi];
953 mp_ioapic_routing[ioapic].pin_programmed[idx] |= (1<<bit);
955 if (triggering == ACPI_LEVEL_SENSITIVE) {
957 * For PCI devices assign IRQs in order, avoiding gaps
958 * due to unused I/O APIC pins.
961 if (gsi < MAX_GSI_NUM) {
963 * Retain the VIA chipset work-around (gsi > 15), but
964 * avoid a problem where the 8254 timer (IRQ0) is setup
965 * via an override (so it's not on pin 0 of the ioapic),
966 * and at the same time, the pin 0 interrupt is a PCI
967 * type. The gsi > 15 test could cause these two pins
968 * to be shared as IRQ0, and they are not shareable.
969 * So test for this condition, and if necessary, avoid
972 if (gsi > 15 || (gsi == 0 && !timer_uses_ioapic_pin_0))
975 * Don't assign IRQ used by ACPI SCI
977 if (gsi == acpi_fadt.sci_int)
979 gsi_to_irq[irq] = gsi;
981 printk(KERN_ERR "GSI %u is too high\n", gsi);
986 io_apic_set_pci_routing(ioapic, ioapic_pin, gsi,
987 triggering == ACPI_EDGE_SENSITIVE ? 0 : 1,
988 polarity == ACPI_ACTIVE_HIGH ? 0 : 1);
992 #endif /*CONFIG_ACPI*/