2 * Intel IO-APIC support for multi-Pentium hosts.
4 * Copyright (C) 1997, 1998, 1999, 2000 Ingo Molnar, Hajnalka Szabo
6 * Many thanks to Stig Venaas for trying out countless experimental
7 * patches and reporting/debugging problems patiently!
9 * (c) 1999, Multiple IO-APIC support, developed by
10 * Ken-ichi Yaku <yaku@css1.kbnes.nec.co.jp> and
11 * Hidemi Kishimoto <kisimoto@css1.kbnes.nec.co.jp>,
12 * further tested and cleaned up by Zach Brown <zab@redhat.com>
13 * and Ingo Molnar <mingo@redhat.com>
16 * Maciej W. Rozycki : Bits for genuine 82489DX APICs;
17 * thanks to Eric Gilmore
19 * for testing these extensively
20 * Paul Diefenbaugh : Added full ACPI support
24 #include <linux/irq.h>
25 #include <linux/interrupt.h>
26 #include <linux/init.h>
27 #include <linux/delay.h>
28 #include <linux/sched.h>
29 #include <linux/config.h>
30 #include <linux/smp_lock.h>
31 #include <linux/mc146818rtc.h>
32 #include <linux/acpi.h>
33 #include <linux/sysdev.h>
38 #include <asm/proto.h>
39 #include <asm/mach_apic.h>
41 #define __apicdebuginit __init
43 int sis_apic_bug; /* not actually supported, dummy for compile */
45 static int no_timer_check;
47 static DEFINE_SPINLOCK(ioapic_lock);
50 * # of IRQ routing registers
52 int nr_ioapic_registers[MAX_IO_APICS];
55 * Rough estimation of how many shared IRQs there are, can
58 #define MAX_PLUS_SHARED_IRQS NR_IRQS
59 #define PIN_MAP_SIZE (MAX_PLUS_SHARED_IRQS + NR_IRQS)
62 * This is performance-critical, we want to do it O(1)
64 * the indexing order of this array favors 1:1 mappings
65 * between pins and IRQs.
68 static struct irq_pin_list {
69 short apic, pin, next;
70 } irq_2_pin[PIN_MAP_SIZE];
72 int vector_irq[NR_VECTORS] = { [0 ... NR_VECTORS - 1] = -1};
74 #define vector_to_irq(vector) \
75 (platform_legacy_irq(vector) ? vector : vector_irq[vector])
77 #define vector_to_irq(vector) (vector)
81 * The common case is 1:1 IRQ<->pin mappings. Sometimes there are
82 * shared ISA-space IRQs, so we have to support them. We are super
83 * fast in the common case, and fast for shared ISA-space IRQs.
85 static void add_pin_to_irq(unsigned int irq, int apic, int pin)
87 static int first_free_entry = NR_IRQS;
88 struct irq_pin_list *entry = irq_2_pin + irq;
91 entry = irq_2_pin + entry->next;
93 if (entry->pin != -1) {
94 entry->next = first_free_entry;
95 entry = irq_2_pin + entry->next;
96 if (++first_free_entry >= PIN_MAP_SIZE)
97 panic("io_apic.c: whoops");
103 #define __DO_ACTION(R, ACTION, FINAL) \
107 struct irq_pin_list *entry = irq_2_pin + irq; \
114 reg = io_apic_read(entry->apic, 0x10 + R + pin*2); \
116 io_apic_modify(entry->apic, reg); \
119 entry = irq_2_pin + entry->next; \
124 #define DO_ACTION(name,R,ACTION, FINAL) \
126 static void name##_IO_APIC_irq (unsigned int irq) \
127 __DO_ACTION(R, ACTION, FINAL)
129 DO_ACTION( __mask, 0, |= 0x00010000, io_apic_sync(entry->apic) )
131 DO_ACTION( __unmask, 0, &= 0xfffeffff, )
134 static void mask_IO_APIC_irq (unsigned int irq)
138 spin_lock_irqsave(&ioapic_lock, flags);
139 __mask_IO_APIC_irq(irq);
140 spin_unlock_irqrestore(&ioapic_lock, flags);
143 static void unmask_IO_APIC_irq (unsigned int irq)
147 spin_lock_irqsave(&ioapic_lock, flags);
148 __unmask_IO_APIC_irq(irq);
149 spin_unlock_irqrestore(&ioapic_lock, flags);
152 static void clear_IO_APIC_pin(unsigned int apic, unsigned int pin)
154 struct IO_APIC_route_entry entry;
157 /* Check delivery_mode to be sure we're not clearing an SMI pin */
158 spin_lock_irqsave(&ioapic_lock, flags);
159 *(((int*)&entry) + 0) = io_apic_read(apic, 0x10 + 2 * pin);
160 *(((int*)&entry) + 1) = io_apic_read(apic, 0x11 + 2 * pin);
161 spin_unlock_irqrestore(&ioapic_lock, flags);
162 if (entry.delivery_mode == dest_SMI)
165 * Disable it in the IO-APIC irq-routing table:
167 memset(&entry, 0, sizeof(entry));
169 spin_lock_irqsave(&ioapic_lock, flags);
170 io_apic_write(apic, 0x10 + 2 * pin, *(((int *)&entry) + 0));
171 io_apic_write(apic, 0x11 + 2 * pin, *(((int *)&entry) + 1));
172 spin_unlock_irqrestore(&ioapic_lock, flags);
175 static void clear_IO_APIC (void)
179 for (apic = 0; apic < nr_ioapics; apic++)
180 for (pin = 0; pin < nr_ioapic_registers[apic]; pin++)
181 clear_IO_APIC_pin(apic, pin);
185 * support for broken MP BIOSs, enables hand-redirection of PIRQ0-7 to
186 * specific CPU-side IRQs.
190 static int pirq_entries [MAX_PIRQS];
191 static int pirqs_enabled;
192 int skip_ioapic_setup;
195 /* dummy parsing: see setup.c */
197 static int __init disable_ioapic_setup(char *str)
199 skip_ioapic_setup = 1;
203 static int __init enable_ioapic_setup(char *str)
206 skip_ioapic_setup = 0;
210 __setup("noapic", disable_ioapic_setup);
211 __setup("apic", enable_ioapic_setup);
213 #include <asm/pci-direct.h>
214 #include <linux/pci_ids.h>
215 #include <linux/pci.h>
217 /* Temporary Hack. Nvidia and VIA boards currently only work with IO-APIC
218 off. Check for an Nvidia or VIA PCI bridge and turn it off.
219 Use pci direct infrastructure because this runs before the PCI subsystem.
221 Can be overwritten with "apic"
223 And another hack to disable the IOMMU on VIA chipsets.
226 void __init check_ioapic(void)
232 /* Poor man's PCI discovery */
233 for (num = 0; num < 32; num++) {
234 for (slot = 0; slot < 32; slot++) {
235 for (func = 0; func < 8; func++) {
239 class = read_pci_config(num,slot,func,
241 if (class == 0xffffffff)
244 if ((class >> 16) != PCI_CLASS_BRIDGE_PCI)
247 vendor = read_pci_config(num, slot, func,
251 case PCI_VENDOR_ID_VIA:
252 #ifdef CONFIG_GART_IOMMU
253 if ((end_pfn >= (0xffffffff>>PAGE_SHIFT) ||
255 !iommu_aperture_allowed) {
257 "Looks like a VIA chipset. Disabling IOMMU. Overwrite with \"iommu=allowed\"\n");
258 iommu_aperture_disabled = 1;
262 case PCI_VENDOR_ID_NVIDIA:
264 /* All timer overrides on Nvidia
265 seem to be wrong. Skip them. */
266 acpi_skip_timer_override = 1;
268 "Nvidia board detected. Ignoring ACPI timer override.\n");
270 /* RED-PEN skip them on mptables too? */
274 /* No multi-function device? */
275 type = read_pci_config_byte(num,slot,func,
284 static int __init ioapic_pirq_setup(char *str)
287 int ints[MAX_PIRQS+1];
289 get_options(str, ARRAY_SIZE(ints), ints);
291 for (i = 0; i < MAX_PIRQS; i++)
292 pirq_entries[i] = -1;
295 apic_printk(APIC_VERBOSE, "PIRQ redirection, working around broken MP-BIOS.\n");
297 if (ints[0] < MAX_PIRQS)
300 for (i = 0; i < max; i++) {
301 apic_printk(APIC_VERBOSE, "... PIRQ%d -> IRQ %d\n", i, ints[i+1]);
303 * PIRQs are mapped upside down, usually.
305 pirq_entries[MAX_PIRQS-i-1] = ints[i+1];
310 __setup("pirq=", ioapic_pirq_setup);
313 * Find the IRQ entry number of a certain pin.
315 static int find_irq_entry(int apic, int pin, int type)
319 for (i = 0; i < mp_irq_entries; i++)
320 if (mp_irqs[i].mpc_irqtype == type &&
321 (mp_irqs[i].mpc_dstapic == mp_ioapics[apic].mpc_apicid ||
322 mp_irqs[i].mpc_dstapic == MP_APIC_ALL) &&
323 mp_irqs[i].mpc_dstirq == pin)
330 * Find the pin to which IRQ[irq] (ISA) is connected
332 static int __init find_isa_irq_pin(int irq, int type)
336 for (i = 0; i < mp_irq_entries; i++) {
337 int lbus = mp_irqs[i].mpc_srcbus;
339 if ((mp_bus_id_to_type[lbus] == MP_BUS_ISA ||
340 mp_bus_id_to_type[lbus] == MP_BUS_EISA ||
341 mp_bus_id_to_type[lbus] == MP_BUS_MCA) &&
342 (mp_irqs[i].mpc_irqtype == type) &&
343 (mp_irqs[i].mpc_srcbusirq == irq))
345 return mp_irqs[i].mpc_dstirq;
351 * Find a specific PCI IRQ entry.
352 * Not an __init, possibly needed by modules
354 static int pin_2_irq(int idx, int apic, int pin);
356 int IO_APIC_get_PCI_irq_vector(int bus, int slot, int pin)
358 int apic, i, best_guess = -1;
360 apic_printk(APIC_DEBUG, "querying PCI -> IRQ mapping bus:%d, slot:%d, pin:%d.\n",
362 if (mp_bus_id_to_pci_bus[bus] == -1) {
363 apic_printk(APIC_VERBOSE, "PCI BIOS passed nonexistent PCI bus %d!\n", bus);
366 for (i = 0; i < mp_irq_entries; i++) {
367 int lbus = mp_irqs[i].mpc_srcbus;
369 for (apic = 0; apic < nr_ioapics; apic++)
370 if (mp_ioapics[apic].mpc_apicid == mp_irqs[i].mpc_dstapic ||
371 mp_irqs[i].mpc_dstapic == MP_APIC_ALL)
374 if ((mp_bus_id_to_type[lbus] == MP_BUS_PCI) &&
375 !mp_irqs[i].mpc_irqtype &&
377 (slot == ((mp_irqs[i].mpc_srcbusirq >> 2) & 0x1f))) {
378 int irq = pin_2_irq(i,apic,mp_irqs[i].mpc_dstirq);
380 if (!(apic || IO_APIC_IRQ(irq)))
383 if (pin == (mp_irqs[i].mpc_srcbusirq & 3))
386 * Use the first all-but-pin matching entry as a
387 * best-guess fuzzy result for broken mptables.
397 * EISA Edge/Level control register, ELCR
399 static int EISA_ELCR(unsigned int irq)
402 unsigned int port = 0x4d0 + (irq >> 3);
403 return (inb(port) >> (irq & 7)) & 1;
405 apic_printk(APIC_VERBOSE, "Broken MPtable reports ISA irq %d\n", irq);
409 /* EISA interrupts are always polarity zero and can be edge or level
410 * trigger depending on the ELCR value. If an interrupt is listed as
411 * EISA conforming in the MP table, that means its trigger type must
412 * be read in from the ELCR */
414 #define default_EISA_trigger(idx) (EISA_ELCR(mp_irqs[idx].mpc_srcbusirq))
415 #define default_EISA_polarity(idx) (0)
417 /* ISA interrupts are always polarity zero edge triggered,
418 * when listed as conforming in the MP table. */
420 #define default_ISA_trigger(idx) (0)
421 #define default_ISA_polarity(idx) (0)
423 /* PCI interrupts are always polarity one level triggered,
424 * when listed as conforming in the MP table. */
426 #define default_PCI_trigger(idx) (1)
427 #define default_PCI_polarity(idx) (1)
429 /* MCA interrupts are always polarity zero level triggered,
430 * when listed as conforming in the MP table. */
432 #define default_MCA_trigger(idx) (1)
433 #define default_MCA_polarity(idx) (0)
435 static int __init MPBIOS_polarity(int idx)
437 int bus = mp_irqs[idx].mpc_srcbus;
441 * Determine IRQ line polarity (high active or low active):
443 switch (mp_irqs[idx].mpc_irqflag & 3)
445 case 0: /* conforms, ie. bus-type dependent polarity */
447 switch (mp_bus_id_to_type[bus])
449 case MP_BUS_ISA: /* ISA pin */
451 polarity = default_ISA_polarity(idx);
454 case MP_BUS_EISA: /* EISA pin */
456 polarity = default_EISA_polarity(idx);
459 case MP_BUS_PCI: /* PCI pin */
461 polarity = default_PCI_polarity(idx);
464 case MP_BUS_MCA: /* MCA pin */
466 polarity = default_MCA_polarity(idx);
471 printk(KERN_WARNING "broken BIOS!!\n");
478 case 1: /* high active */
483 case 2: /* reserved */
485 printk(KERN_WARNING "broken BIOS!!\n");
489 case 3: /* low active */
494 default: /* invalid */
496 printk(KERN_WARNING "broken BIOS!!\n");
504 static int MPBIOS_trigger(int idx)
506 int bus = mp_irqs[idx].mpc_srcbus;
510 * Determine IRQ trigger mode (edge or level sensitive):
512 switch ((mp_irqs[idx].mpc_irqflag>>2) & 3)
514 case 0: /* conforms, ie. bus-type dependent */
516 switch (mp_bus_id_to_type[bus])
518 case MP_BUS_ISA: /* ISA pin */
520 trigger = default_ISA_trigger(idx);
523 case MP_BUS_EISA: /* EISA pin */
525 trigger = default_EISA_trigger(idx);
528 case MP_BUS_PCI: /* PCI pin */
530 trigger = default_PCI_trigger(idx);
533 case MP_BUS_MCA: /* MCA pin */
535 trigger = default_MCA_trigger(idx);
540 printk(KERN_WARNING "broken BIOS!!\n");
552 case 2: /* reserved */
554 printk(KERN_WARNING "broken BIOS!!\n");
563 default: /* invalid */
565 printk(KERN_WARNING "broken BIOS!!\n");
573 static inline int irq_polarity(int idx)
575 return MPBIOS_polarity(idx);
578 static inline int irq_trigger(int idx)
580 return MPBIOS_trigger(idx);
583 static int pin_2_irq(int idx, int apic, int pin)
586 int bus = mp_irqs[idx].mpc_srcbus;
589 * Debugging check, we are in big trouble if this message pops up!
591 if (mp_irqs[idx].mpc_dstirq != pin)
592 printk(KERN_ERR "broken BIOS or MPTABLE parser, ayiee!!\n");
594 switch (mp_bus_id_to_type[bus])
596 case MP_BUS_ISA: /* ISA pin */
600 irq = mp_irqs[idx].mpc_srcbusirq;
603 case MP_BUS_PCI: /* PCI pin */
606 * PCI IRQs are mapped in order
610 irq += nr_ioapic_registers[i++];
616 printk(KERN_ERR "unknown bus type %d.\n",bus);
623 * PCI IRQ command line redirection. Yes, limits are hardcoded.
625 if ((pin >= 16) && (pin <= 23)) {
626 if (pirq_entries[pin-16] != -1) {
627 if (!pirq_entries[pin-16]) {
628 apic_printk(APIC_VERBOSE, "disabling PIRQ%d\n", pin-16);
630 irq = pirq_entries[pin-16];
631 apic_printk(APIC_VERBOSE, "using PIRQ%d -> IRQ %d\n",
639 static inline int IO_APIC_irq_trigger(int irq)
643 for (apic = 0; apic < nr_ioapics; apic++) {
644 for (pin = 0; pin < nr_ioapic_registers[apic]; pin++) {
645 idx = find_irq_entry(apic,pin,mp_INT);
646 if ((idx != -1) && (irq == pin_2_irq(idx,apic,pin)))
647 return irq_trigger(idx);
651 * nonexistent IRQs are edge default
656 /* irq_vectors is indexed by the sum of all RTEs in all I/O APICs. */
657 u8 irq_vector[NR_IRQ_VECTORS] = { FIRST_DEVICE_VECTOR , 0 };
659 int assign_irq_vector(int irq)
661 static int current_vector = FIRST_DEVICE_VECTOR, offset = 0;
663 BUG_ON(irq >= NR_IRQ_VECTORS);
664 if (IO_APIC_VECTOR(irq) > 0)
665 return IO_APIC_VECTOR(irq);
668 if (current_vector == IA32_SYSCALL_VECTOR)
671 if (current_vector >= FIRST_SYSTEM_VECTOR) {
675 current_vector = FIRST_DEVICE_VECTOR + offset;
678 vector_irq[current_vector] = irq;
679 if (irq != AUTO_ASSIGN)
680 IO_APIC_VECTOR(irq) = current_vector;
682 return current_vector;
685 extern void (*interrupt[NR_IRQS])(void);
686 static struct hw_interrupt_type ioapic_level_type;
687 static struct hw_interrupt_type ioapic_edge_type;
689 #define IOAPIC_AUTO -1
690 #define IOAPIC_EDGE 0
691 #define IOAPIC_LEVEL 1
693 static inline void ioapic_register_intr(int irq, int vector, unsigned long trigger)
695 if (use_pci_vector() && !platform_legacy_irq(irq)) {
696 if ((trigger == IOAPIC_AUTO && IO_APIC_irq_trigger(irq)) ||
697 trigger == IOAPIC_LEVEL)
698 irq_desc[vector].handler = &ioapic_level_type;
700 irq_desc[vector].handler = &ioapic_edge_type;
701 set_intr_gate(vector, interrupt[vector]);
703 if ((trigger == IOAPIC_AUTO && IO_APIC_irq_trigger(irq)) ||
704 trigger == IOAPIC_LEVEL)
705 irq_desc[irq].handler = &ioapic_level_type;
707 irq_desc[irq].handler = &ioapic_edge_type;
708 set_intr_gate(vector, interrupt[irq]);
712 static void __init setup_IO_APIC_irqs(void)
714 struct IO_APIC_route_entry entry;
715 int apic, pin, idx, irq, first_notcon = 1, vector;
718 apic_printk(APIC_VERBOSE, KERN_DEBUG "init IO_APIC IRQs\n");
720 for (apic = 0; apic < nr_ioapics; apic++) {
721 for (pin = 0; pin < nr_ioapic_registers[apic]; pin++) {
724 * add it to the IO-APIC irq-routing table:
726 memset(&entry,0,sizeof(entry));
728 entry.delivery_mode = INT_DELIVERY_MODE;
729 entry.dest_mode = INT_DEST_MODE;
730 entry.mask = 0; /* enable IRQ */
731 entry.dest.logical.logical_dest = cpu_mask_to_apicid(TARGET_CPUS);
733 idx = find_irq_entry(apic,pin,mp_INT);
736 apic_printk(APIC_VERBOSE, KERN_DEBUG " IO-APIC (apicid-pin) %d-%d", mp_ioapics[apic].mpc_apicid, pin);
739 apic_printk(APIC_VERBOSE, ", %d-%d", mp_ioapics[apic].mpc_apicid, pin);
743 entry.trigger = irq_trigger(idx);
744 entry.polarity = irq_polarity(idx);
746 if (irq_trigger(idx)) {
749 entry.dest.logical.logical_dest = cpu_mask_to_apicid(TARGET_CPUS);
752 irq = pin_2_irq(idx, apic, pin);
753 add_pin_to_irq(irq, apic, pin);
755 if (!apic && !IO_APIC_IRQ(irq))
758 if (IO_APIC_IRQ(irq)) {
759 vector = assign_irq_vector(irq);
760 entry.vector = vector;
762 ioapic_register_intr(irq, vector, IOAPIC_AUTO);
763 if (!apic && (irq < 16))
764 disable_8259A_irq(irq);
766 spin_lock_irqsave(&ioapic_lock, flags);
767 io_apic_write(apic, 0x11+2*pin, *(((int *)&entry)+1));
768 io_apic_write(apic, 0x10+2*pin, *(((int *)&entry)+0));
769 spin_unlock_irqrestore(&ioapic_lock, flags);
774 apic_printk(APIC_VERBOSE," not connected.\n");
778 * Set up the 8259A-master output pin as broadcast to all
781 static void __init setup_ExtINT_IRQ0_pin(unsigned int pin, int vector)
783 struct IO_APIC_route_entry entry;
786 memset(&entry,0,sizeof(entry));
788 disable_8259A_irq(0);
791 apic_write_around(APIC_LVT0, APIC_LVT_MASKED | APIC_DM_EXTINT);
794 * We use logical delivery to get the timer IRQ
797 entry.dest_mode = INT_DEST_MODE;
798 entry.mask = 0; /* unmask IRQ now */
799 entry.dest.logical.logical_dest = cpu_mask_to_apicid(TARGET_CPUS);
800 entry.delivery_mode = INT_DELIVERY_MODE;
803 entry.vector = vector;
806 * The timer IRQ doesn't have to know that behind the
807 * scene we have a 8259A-master in AEOI mode ...
809 irq_desc[0].handler = &ioapic_edge_type;
812 * Add it to the IO-APIC irq-routing table:
814 spin_lock_irqsave(&ioapic_lock, flags);
815 io_apic_write(0, 0x11+2*pin, *(((int *)&entry)+1));
816 io_apic_write(0, 0x10+2*pin, *(((int *)&entry)+0));
817 spin_unlock_irqrestore(&ioapic_lock, flags);
822 void __init UNEXPECTED_IO_APIC(void)
826 void __apicdebuginit print_IO_APIC(void)
829 union IO_APIC_reg_00 reg_00;
830 union IO_APIC_reg_01 reg_01;
831 union IO_APIC_reg_02 reg_02;
834 if (apic_verbosity == APIC_QUIET)
837 printk(KERN_DEBUG "number of MP IRQ sources: %d.\n", mp_irq_entries);
838 for (i = 0; i < nr_ioapics; i++)
839 printk(KERN_DEBUG "number of IO-APIC #%d registers: %d.\n",
840 mp_ioapics[i].mpc_apicid, nr_ioapic_registers[i]);
843 * We are a bit conservative about what we expect. We have to
844 * know about every hardware change ASAP.
846 printk(KERN_INFO "testing the IO APIC.......................\n");
848 for (apic = 0; apic < nr_ioapics; apic++) {
850 spin_lock_irqsave(&ioapic_lock, flags);
851 reg_00.raw = io_apic_read(apic, 0);
852 reg_01.raw = io_apic_read(apic, 1);
853 if (reg_01.bits.version >= 0x10)
854 reg_02.raw = io_apic_read(apic, 2);
855 spin_unlock_irqrestore(&ioapic_lock, flags);
858 printk(KERN_DEBUG "IO APIC #%d......\n", mp_ioapics[apic].mpc_apicid);
859 printk(KERN_DEBUG ".... register #00: %08X\n", reg_00.raw);
860 printk(KERN_DEBUG "....... : physical APIC id: %02X\n", reg_00.bits.ID);
861 if (reg_00.bits.__reserved_1 || reg_00.bits.__reserved_2)
862 UNEXPECTED_IO_APIC();
864 printk(KERN_DEBUG ".... register #01: %08X\n", *(int *)®_01);
865 printk(KERN_DEBUG "....... : max redirection entries: %04X\n", reg_01.bits.entries);
866 if ( (reg_01.bits.entries != 0x0f) && /* older (Neptune) boards */
867 (reg_01.bits.entries != 0x17) && /* typical ISA+PCI boards */
868 (reg_01.bits.entries != 0x1b) && /* Compaq Proliant boards */
869 (reg_01.bits.entries != 0x1f) && /* dual Xeon boards */
870 (reg_01.bits.entries != 0x22) && /* bigger Xeon boards */
871 (reg_01.bits.entries != 0x2E) &&
872 (reg_01.bits.entries != 0x3F) &&
873 (reg_01.bits.entries != 0x03)
875 UNEXPECTED_IO_APIC();
877 printk(KERN_DEBUG "....... : PRQ implemented: %X\n", reg_01.bits.PRQ);
878 printk(KERN_DEBUG "....... : IO APIC version: %04X\n", reg_01.bits.version);
879 if ( (reg_01.bits.version != 0x01) && /* 82489DX IO-APICs */
880 (reg_01.bits.version != 0x02) && /* 82801BA IO-APICs (ICH2) */
881 (reg_01.bits.version != 0x10) && /* oldest IO-APICs */
882 (reg_01.bits.version != 0x11) && /* Pentium/Pro IO-APICs */
883 (reg_01.bits.version != 0x13) && /* Xeon IO-APICs */
884 (reg_01.bits.version != 0x20) /* Intel P64H (82806 AA) */
886 UNEXPECTED_IO_APIC();
887 if (reg_01.bits.__reserved_1 || reg_01.bits.__reserved_2)
888 UNEXPECTED_IO_APIC();
890 if (reg_01.bits.version >= 0x10) {
891 printk(KERN_DEBUG ".... register #02: %08X\n", reg_02.raw);
892 printk(KERN_DEBUG "....... : arbitration: %02X\n", reg_02.bits.arbitration);
893 if (reg_02.bits.__reserved_1 || reg_02.bits.__reserved_2)
894 UNEXPECTED_IO_APIC();
897 printk(KERN_DEBUG ".... IRQ redirection table:\n");
899 printk(KERN_DEBUG " NR Log Phy Mask Trig IRR Pol"
900 " Stat Dest Deli Vect: \n");
902 for (i = 0; i <= reg_01.bits.entries; i++) {
903 struct IO_APIC_route_entry entry;
905 spin_lock_irqsave(&ioapic_lock, flags);
906 *(((int *)&entry)+0) = io_apic_read(apic, 0x10+i*2);
907 *(((int *)&entry)+1) = io_apic_read(apic, 0x11+i*2);
908 spin_unlock_irqrestore(&ioapic_lock, flags);
910 printk(KERN_DEBUG " %02x %03X %02X ",
912 entry.dest.logical.logical_dest,
913 entry.dest.physical.physical_dest
916 printk("%1d %1d %1d %1d %1d %1d %1d %02X\n",
921 entry.delivery_status,
928 if (use_pci_vector())
929 printk(KERN_INFO "Using vector-based indexing\n");
930 printk(KERN_DEBUG "IRQ to pin mappings:\n");
931 for (i = 0; i < NR_IRQS; i++) {
932 struct irq_pin_list *entry = irq_2_pin + i;
935 if (use_pci_vector() && !platform_legacy_irq(i))
936 printk(KERN_DEBUG "IRQ%d ", IO_APIC_VECTOR(i));
938 printk(KERN_DEBUG "IRQ%d ", i);
940 printk("-> %d:%d", entry->apic, entry->pin);
943 entry = irq_2_pin + entry->next;
948 printk(KERN_INFO ".................................... done.\n");
955 static __apicdebuginit void print_APIC_bitfield (int base)
960 if (apic_verbosity == APIC_QUIET)
963 printk(KERN_DEBUG "0123456789abcdef0123456789abcdef\n" KERN_DEBUG);
964 for (i = 0; i < 8; i++) {
965 v = apic_read(base + i*0x10);
966 for (j = 0; j < 32; j++) {
976 void __apicdebuginit print_local_APIC(void * dummy)
978 unsigned int v, ver, maxlvt;
980 if (apic_verbosity == APIC_QUIET)
983 printk("\n" KERN_DEBUG "printing local APIC contents on CPU#%d/%d:\n",
984 smp_processor_id(), hard_smp_processor_id());
985 v = apic_read(APIC_ID);
986 printk(KERN_INFO "... APIC ID: %08x (%01x)\n", v, GET_APIC_ID(v));
987 v = apic_read(APIC_LVR);
988 printk(KERN_INFO "... APIC VERSION: %08x\n", v);
989 ver = GET_APIC_VERSION(v);
990 maxlvt = get_maxlvt();
992 v = apic_read(APIC_TASKPRI);
993 printk(KERN_DEBUG "... APIC TASKPRI: %08x (%02x)\n", v, v & APIC_TPRI_MASK);
995 if (APIC_INTEGRATED(ver)) { /* !82489DX */
996 v = apic_read(APIC_ARBPRI);
997 printk(KERN_DEBUG "... APIC ARBPRI: %08x (%02x)\n", v,
998 v & APIC_ARBPRI_MASK);
999 v = apic_read(APIC_PROCPRI);
1000 printk(KERN_DEBUG "... APIC PROCPRI: %08x\n", v);
1003 v = apic_read(APIC_EOI);
1004 printk(KERN_DEBUG "... APIC EOI: %08x\n", v);
1005 v = apic_read(APIC_RRR);
1006 printk(KERN_DEBUG "... APIC RRR: %08x\n", v);
1007 v = apic_read(APIC_LDR);
1008 printk(KERN_DEBUG "... APIC LDR: %08x\n", v);
1009 v = apic_read(APIC_DFR);
1010 printk(KERN_DEBUG "... APIC DFR: %08x\n", v);
1011 v = apic_read(APIC_SPIV);
1012 printk(KERN_DEBUG "... APIC SPIV: %08x\n", v);
1014 printk(KERN_DEBUG "... APIC ISR field:\n");
1015 print_APIC_bitfield(APIC_ISR);
1016 printk(KERN_DEBUG "... APIC TMR field:\n");
1017 print_APIC_bitfield(APIC_TMR);
1018 printk(KERN_DEBUG "... APIC IRR field:\n");
1019 print_APIC_bitfield(APIC_IRR);
1021 if (APIC_INTEGRATED(ver)) { /* !82489DX */
1022 if (maxlvt > 3) /* Due to the Pentium erratum 3AP. */
1023 apic_write(APIC_ESR, 0);
1024 v = apic_read(APIC_ESR);
1025 printk(KERN_DEBUG "... APIC ESR: %08x\n", v);
1028 v = apic_read(APIC_ICR);
1029 printk(KERN_DEBUG "... APIC ICR: %08x\n", v);
1030 v = apic_read(APIC_ICR2);
1031 printk(KERN_DEBUG "... APIC ICR2: %08x\n", v);
1033 v = apic_read(APIC_LVTT);
1034 printk(KERN_DEBUG "... APIC LVTT: %08x\n", v);
1036 if (maxlvt > 3) { /* PC is LVT#4. */
1037 v = apic_read(APIC_LVTPC);
1038 printk(KERN_DEBUG "... APIC LVTPC: %08x\n", v);
1040 v = apic_read(APIC_LVT0);
1041 printk(KERN_DEBUG "... APIC LVT0: %08x\n", v);
1042 v = apic_read(APIC_LVT1);
1043 printk(KERN_DEBUG "... APIC LVT1: %08x\n", v);
1045 if (maxlvt > 2) { /* ERR is LVT#3. */
1046 v = apic_read(APIC_LVTERR);
1047 printk(KERN_DEBUG "... APIC LVTERR: %08x\n", v);
1050 v = apic_read(APIC_TMICT);
1051 printk(KERN_DEBUG "... APIC TMICT: %08x\n", v);
1052 v = apic_read(APIC_TMCCT);
1053 printk(KERN_DEBUG "... APIC TMCCT: %08x\n", v);
1054 v = apic_read(APIC_TDCR);
1055 printk(KERN_DEBUG "... APIC TDCR: %08x\n", v);
1059 void print_all_local_APICs (void)
1061 on_each_cpu(print_local_APIC, NULL, 1, 1);
1064 void __apicdebuginit print_PIC(void)
1066 extern spinlock_t i8259A_lock;
1068 unsigned long flags;
1070 if (apic_verbosity == APIC_QUIET)
1073 printk(KERN_DEBUG "\nprinting PIC contents\n");
1075 spin_lock_irqsave(&i8259A_lock, flags);
1077 v = inb(0xa1) << 8 | inb(0x21);
1078 printk(KERN_DEBUG "... PIC IMR: %04x\n", v);
1080 v = inb(0xa0) << 8 | inb(0x20);
1081 printk(KERN_DEBUG "... PIC IRR: %04x\n", v);
1085 v = inb(0xa0) << 8 | inb(0x20);
1089 spin_unlock_irqrestore(&i8259A_lock, flags);
1091 printk(KERN_DEBUG "... PIC ISR: %04x\n", v);
1093 v = inb(0x4d1) << 8 | inb(0x4d0);
1094 printk(KERN_DEBUG "... PIC ELCR: %04x\n", v);
1099 static void __init enable_IO_APIC(void)
1101 union IO_APIC_reg_01 reg_01;
1103 unsigned long flags;
1105 for (i = 0; i < PIN_MAP_SIZE; i++) {
1106 irq_2_pin[i].pin = -1;
1107 irq_2_pin[i].next = 0;
1110 for (i = 0; i < MAX_PIRQS; i++)
1111 pirq_entries[i] = -1;
1114 * The number of IO-APIC IRQ registers (== #pins):
1116 for (i = 0; i < nr_ioapics; i++) {
1117 spin_lock_irqsave(&ioapic_lock, flags);
1118 reg_01.raw = io_apic_read(i, 1);
1119 spin_unlock_irqrestore(&ioapic_lock, flags);
1120 nr_ioapic_registers[i] = reg_01.bits.entries+1;
1124 * Do not trust the IO-APIC being empty at bootup
1130 * Not an __init, needed by the reboot code
1132 void disable_IO_APIC(void)
1135 * Clear the IO-APIC before rebooting:
1139 disconnect_bsp_APIC();
1143 * function to set the IO-APIC physical IDs based on the
1144 * values stored in the MPC table.
1146 * by Matt Domsch <Matt_Domsch@dell.com> Tue Dec 21 12:25:05 CST 1999
1149 static void __init setup_ioapic_ids_from_mpc (void)
1151 union IO_APIC_reg_00 reg_00;
1154 unsigned char old_id;
1155 unsigned long flags;
1158 * Set the IOAPIC ID to the value stored in the MPC table.
1160 for (apic = 0; apic < nr_ioapics; apic++) {
1162 /* Read the register 0 value */
1163 spin_lock_irqsave(&ioapic_lock, flags);
1164 reg_00.raw = io_apic_read(apic, 0);
1165 spin_unlock_irqrestore(&ioapic_lock, flags);
1167 old_id = mp_ioapics[apic].mpc_apicid;
1170 printk(KERN_INFO "Using IO-APIC %d\n", mp_ioapics[apic].mpc_apicid);
1174 * We need to adjust the IRQ routing table
1175 * if the ID changed.
1177 if (old_id != mp_ioapics[apic].mpc_apicid)
1178 for (i = 0; i < mp_irq_entries; i++)
1179 if (mp_irqs[i].mpc_dstapic == old_id)
1180 mp_irqs[i].mpc_dstapic
1181 = mp_ioapics[apic].mpc_apicid;
1184 * Read the right value from the MPC table and
1185 * write it into the ID register.
1187 apic_printk(APIC_VERBOSE,KERN_INFO "...changing IO-APIC physical APIC ID to %d ...",
1188 mp_ioapics[apic].mpc_apicid);
1190 reg_00.bits.ID = mp_ioapics[apic].mpc_apicid;
1191 spin_lock_irqsave(&ioapic_lock, flags);
1192 io_apic_write(apic, 0, reg_00.raw);
1193 spin_unlock_irqrestore(&ioapic_lock, flags);
1198 spin_lock_irqsave(&ioapic_lock, flags);
1199 reg_00.raw = io_apic_read(apic, 0);
1200 spin_unlock_irqrestore(&ioapic_lock, flags);
1201 if (reg_00.bits.ID != mp_ioapics[apic].mpc_apicid)
1202 printk("could not set ID!\n");
1204 apic_printk(APIC_VERBOSE," ok.\n");
1209 * There is a nasty bug in some older SMP boards, their mptable lies
1210 * about the timer IRQ. We do the following to work around the situation:
1212 * - timer IRQ defaults to IO-APIC IRQ
1213 * - if this function detects that timer IRQs are defunct, then we fall
1214 * back to ISA timer IRQs
1216 static int __init timer_irq_works(void)
1218 unsigned long t1 = jiffies;
1221 /* Let ten ticks pass... */
1222 mdelay((10 * 1000) / HZ);
1225 * Expect a few ticks at least, to be sure some possible
1226 * glue logic does not lock up after one or two first
1227 * ticks in a non-ExtINT mode. Also the local APIC
1228 * might have cached one ExtINT interrupt. Finally, at
1229 * least one tick may be lost due to delays.
1233 if (jiffies - t1 > 4)
1239 * In the SMP+IOAPIC case it might happen that there are an unspecified
1240 * number of pending IRQ events unhandled. These cases are very rare,
1241 * so we 'resend' these IRQs via IPIs, to the same CPU. It's much
1242 * better to do it this way as thus we do not have to be aware of
1243 * 'pending' interrupts in the IRQ path, except at this point.
1246 * Edge triggered needs to resend any interrupt
1247 * that was delayed but this is now handled in the device
1252 * Starting up a edge-triggered IO-APIC interrupt is
1253 * nasty - we need to make sure that we get the edge.
1254 * If it is already asserted for some reason, we need
1255 * return 1 to indicate that is was pending.
1257 * This is not complete - we should be able to fake
1258 * an edge even if it isn't on the 8259A...
1261 static unsigned int startup_edge_ioapic_irq(unsigned int irq)
1263 int was_pending = 0;
1264 unsigned long flags;
1266 spin_lock_irqsave(&ioapic_lock, flags);
1268 disable_8259A_irq(irq);
1269 if (i8259A_irq_pending(irq))
1272 __unmask_IO_APIC_irq(irq);
1273 spin_unlock_irqrestore(&ioapic_lock, flags);
1279 * Once we have recorded IRQ_PENDING already, we can mask the
1280 * interrupt for real. This prevents IRQ storms from unhandled
1283 static void ack_edge_ioapic_irq(unsigned int irq)
1285 if ((irq_desc[irq].status & (IRQ_PENDING | IRQ_DISABLED))
1286 == (IRQ_PENDING | IRQ_DISABLED))
1287 mask_IO_APIC_irq(irq);
1292 * Level triggered interrupts can just be masked,
1293 * and shutting down and starting up the interrupt
1294 * is the same as enabling and disabling them -- except
1295 * with a startup need to return a "was pending" value.
1297 * Level triggered interrupts are special because we
1298 * do not touch any IO-APIC register while handling
1299 * them. We ack the APIC in the end-IRQ handler, not
1300 * in the start-IRQ-handler. Protection against reentrance
1301 * from the same interrupt is still provided, both by the
1302 * generic IRQ layer and by the fact that an unacked local
1303 * APIC does not accept IRQs.
1305 static unsigned int startup_level_ioapic_irq (unsigned int irq)
1307 unmask_IO_APIC_irq(irq);
1309 return 0; /* don't check for pending */
1312 static void end_level_ioapic_irq (unsigned int irq)
1317 static void set_ioapic_affinity_irq(unsigned int irq, cpumask_t mask)
1319 unsigned long flags;
1322 dest = cpu_mask_to_apicid(mask);
1325 * Only the high 8 bits are valid.
1327 dest = SET_APIC_LOGICAL_ID(dest);
1329 spin_lock_irqsave(&ioapic_lock, flags);
1330 __DO_ACTION(1, = dest, )
1331 spin_unlock_irqrestore(&ioapic_lock, flags);
1334 #ifdef CONFIG_PCI_MSI
1335 static unsigned int startup_edge_ioapic_vector(unsigned int vector)
1337 int irq = vector_to_irq(vector);
1339 return startup_edge_ioapic_irq(irq);
1342 static void ack_edge_ioapic_vector(unsigned int vector)
1344 int irq = vector_to_irq(vector);
1346 ack_edge_ioapic_irq(irq);
1349 static unsigned int startup_level_ioapic_vector (unsigned int vector)
1351 int irq = vector_to_irq(vector);
1353 return startup_level_ioapic_irq (irq);
1356 static void end_level_ioapic_vector (unsigned int vector)
1358 int irq = vector_to_irq(vector);
1360 end_level_ioapic_irq(irq);
1363 static void mask_IO_APIC_vector (unsigned int vector)
1365 int irq = vector_to_irq(vector);
1367 mask_IO_APIC_irq(irq);
1370 static void unmask_IO_APIC_vector (unsigned int vector)
1372 int irq = vector_to_irq(vector);
1374 unmask_IO_APIC_irq(irq);
1377 static void set_ioapic_affinity_vector (unsigned int vector,
1380 int irq = vector_to_irq(vector);
1382 set_ioapic_affinity_irq(irq, cpu_mask);
1387 * Level and edge triggered IO-APIC interrupts need different handling,
1388 * so we use two separate IRQ descriptors. Edge triggered IRQs can be
1389 * handled with the level-triggered descriptor, but that one has slightly
1390 * more overhead. Level-triggered interrupts cannot be handled with the
1391 * edge-triggered handler, without risking IRQ storms and other ugly
1395 static struct hw_interrupt_type ioapic_edge_type = {
1396 .typename = "IO-APIC-edge",
1397 .startup = startup_edge_ioapic,
1398 .shutdown = shutdown_edge_ioapic,
1399 .enable = enable_edge_ioapic,
1400 .disable = disable_edge_ioapic,
1401 .ack = ack_edge_ioapic,
1402 .end = end_edge_ioapic,
1403 .set_affinity = set_ioapic_affinity,
1406 static struct hw_interrupt_type ioapic_level_type = {
1407 .typename = "IO-APIC-level",
1408 .startup = startup_level_ioapic,
1409 .shutdown = shutdown_level_ioapic,
1410 .enable = enable_level_ioapic,
1411 .disable = disable_level_ioapic,
1412 .ack = mask_and_ack_level_ioapic,
1413 .end = end_level_ioapic,
1414 .set_affinity = set_ioapic_affinity,
1417 static inline void init_IO_APIC_traps(void)
1422 * NOTE! The local APIC isn't very good at handling
1423 * multiple interrupts at the same interrupt level.
1424 * As the interrupt level is determined by taking the
1425 * vector number and shifting that right by 4, we
1426 * want to spread these out a bit so that they don't
1427 * all fall in the same interrupt level.
1429 * Also, we've got to be careful not to trash gate
1430 * 0x80, because int 0x80 is hm, kind of importantish. ;)
1432 for (irq = 0; irq < NR_IRQS ; irq++) {
1434 if (use_pci_vector()) {
1435 if (!platform_legacy_irq(tmp))
1436 if ((tmp = vector_to_irq(tmp)) == -1)
1439 if (IO_APIC_IRQ(tmp) && !IO_APIC_VECTOR(tmp)) {
1441 * Hmm.. We don't have an entry for this,
1442 * so default to an old-fashioned 8259
1443 * interrupt if we can..
1446 make_8259A_irq(irq);
1448 /* Strange. Oh, well.. */
1449 irq_desc[irq].handler = &no_irq_type;
1454 static void enable_lapic_irq (unsigned int irq)
1458 v = apic_read(APIC_LVT0);
1459 apic_write_around(APIC_LVT0, v & ~APIC_LVT_MASKED);
1462 static void disable_lapic_irq (unsigned int irq)
1466 v = apic_read(APIC_LVT0);
1467 apic_write_around(APIC_LVT0, v | APIC_LVT_MASKED);
1470 static void ack_lapic_irq (unsigned int irq)
1475 static void end_lapic_irq (unsigned int i) { /* nothing */ }
1477 static struct hw_interrupt_type lapic_irq_type = {
1478 .typename = "local-APIC-edge",
1479 .startup = NULL, /* startup_irq() not used for IRQ0 */
1480 .shutdown = NULL, /* shutdown_irq() not used for IRQ0 */
1481 .enable = enable_lapic_irq,
1482 .disable = disable_lapic_irq,
1483 .ack = ack_lapic_irq,
1484 .end = end_lapic_irq,
1487 static void setup_nmi (void)
1490 * Dirty trick to enable the NMI watchdog ...
1491 * We put the 8259A master into AEOI mode and
1492 * unmask on all local APICs LVT0 as NMI.
1494 * The idea to use the 8259A in AEOI mode ('8259A Virtual Wire')
1495 * is from Maciej W. Rozycki - so we do not have to EOI from
1496 * the NMI handler or the timer interrupt.
1498 printk(KERN_INFO "activating NMI Watchdog ...");
1500 enable_NMI_through_LVT0(NULL);
1506 * This looks a bit hackish but it's about the only one way of sending
1507 * a few INTA cycles to 8259As and any associated glue logic. ICR does
1508 * not support the ExtINT mode, unfortunately. We need to send these
1509 * cycles as some i82489DX-based boards have glue logic that keeps the
1510 * 8259A interrupt line asserted until INTA. --macro
1512 static inline void unlock_ExtINT_logic(void)
1515 struct IO_APIC_route_entry entry0, entry1;
1516 unsigned char save_control, save_freq_select;
1517 unsigned long flags;
1519 pin = find_isa_irq_pin(8, mp_INT);
1523 spin_lock_irqsave(&ioapic_lock, flags);
1524 *(((int *)&entry0) + 1) = io_apic_read(0, 0x11 + 2 * pin);
1525 *(((int *)&entry0) + 0) = io_apic_read(0, 0x10 + 2 * pin);
1526 spin_unlock_irqrestore(&ioapic_lock, flags);
1527 clear_IO_APIC_pin(0, pin);
1529 memset(&entry1, 0, sizeof(entry1));
1531 entry1.dest_mode = 0; /* physical delivery */
1532 entry1.mask = 0; /* unmask IRQ now */
1533 entry1.dest.physical.physical_dest = hard_smp_processor_id();
1534 entry1.delivery_mode = dest_ExtINT;
1535 entry1.polarity = entry0.polarity;
1539 spin_lock_irqsave(&ioapic_lock, flags);
1540 io_apic_write(0, 0x11 + 2 * pin, *(((int *)&entry1) + 1));
1541 io_apic_write(0, 0x10 + 2 * pin, *(((int *)&entry1) + 0));
1542 spin_unlock_irqrestore(&ioapic_lock, flags);
1544 save_control = CMOS_READ(RTC_CONTROL);
1545 save_freq_select = CMOS_READ(RTC_FREQ_SELECT);
1546 CMOS_WRITE((save_freq_select & ~RTC_RATE_SELECT) | 0x6,
1548 CMOS_WRITE(save_control | RTC_PIE, RTC_CONTROL);
1553 if ((CMOS_READ(RTC_INTR_FLAGS) & RTC_PF) == RTC_PF)
1557 CMOS_WRITE(save_control, RTC_CONTROL);
1558 CMOS_WRITE(save_freq_select, RTC_FREQ_SELECT);
1559 clear_IO_APIC_pin(0, pin);
1561 spin_lock_irqsave(&ioapic_lock, flags);
1562 io_apic_write(0, 0x11 + 2 * pin, *(((int *)&entry0) + 1));
1563 io_apic_write(0, 0x10 + 2 * pin, *(((int *)&entry0) + 0));
1564 spin_unlock_irqrestore(&ioapic_lock, flags);
1568 * This code may look a bit paranoid, but it's supposed to cooperate with
1569 * a wide range of boards and BIOS bugs. Fortunately only the timer IRQ
1570 * is so screwy. Thanks to Brian Perkins for testing/hacking this beast
1571 * fanatically on his truly buggy board.
1573 static inline void check_timer(void)
1579 * get/set the timer IRQ vector:
1581 disable_8259A_irq(0);
1582 vector = assign_irq_vector(0);
1583 set_intr_gate(vector, interrupt[0]);
1586 * Subtle, code in do_timer_interrupt() expects an AEOI
1587 * mode for the 8259A whenever interrupts are routed
1588 * through I/O APICs. Also IRQ0 has to be enabled in
1589 * the 8259A which implies the virtual wire has to be
1590 * disabled in the local APIC.
1592 apic_write_around(APIC_LVT0, APIC_LVT_MASKED | APIC_DM_EXTINT);
1594 enable_8259A_irq(0);
1596 pin1 = find_isa_irq_pin(0, mp_INT);
1597 pin2 = find_isa_irq_pin(0, mp_ExtINT);
1599 apic_printk(APIC_VERBOSE,KERN_INFO "..TIMER: vector=0x%02X pin1=%d pin2=%d\n", vector, pin1, pin2);
1603 * Ok, does IRQ0 through the IOAPIC work?
1605 unmask_IO_APIC_irq(0);
1606 if (!no_timer_check && timer_irq_works()) {
1607 nmi_watchdog_default();
1608 if (nmi_watchdog == NMI_IO_APIC) {
1609 disable_8259A_irq(0);
1611 enable_8259A_irq(0);
1615 clear_IO_APIC_pin(0, pin1);
1616 apic_printk(APIC_QUIET,KERN_ERR "..MP-BIOS bug: 8254 timer not connected to IO-APIC\n");
1619 apic_printk(APIC_VERBOSE,KERN_INFO "...trying to set up timer (IRQ0) through the 8259A ... ");
1621 apic_printk(APIC_VERBOSE,"\n..... (found pin %d) ...", pin2);
1623 * legacy devices should be connected to IO APIC #0
1625 setup_ExtINT_IRQ0_pin(pin2, vector);
1626 if (timer_irq_works()) {
1628 nmi_watchdog_default();
1629 if (nmi_watchdog == NMI_IO_APIC) {
1635 * Cleanup, just in case ...
1637 clear_IO_APIC_pin(0, pin2);
1639 printk(" failed.\n");
1642 printk(KERN_WARNING "timer doesn't work through the IO-APIC - disabling NMI Watchdog!\n");
1646 apic_printk(APIC_VERBOSE, KERN_INFO "...trying to set up timer as Virtual Wire IRQ...");
1648 disable_8259A_irq(0);
1649 irq_desc[0].handler = &lapic_irq_type;
1650 apic_write_around(APIC_LVT0, APIC_DM_FIXED | vector); /* Fixed mode */
1651 enable_8259A_irq(0);
1653 if (timer_irq_works()) {
1654 apic_printk(APIC_QUIET, " works.\n");
1657 apic_write_around(APIC_LVT0, APIC_LVT_MASKED | APIC_DM_FIXED | vector);
1658 apic_printk(APIC_VERBOSE," failed.\n");
1660 apic_printk(APIC_VERBOSE, KERN_INFO "...trying to set up timer as ExtINT IRQ...");
1664 apic_write_around(APIC_LVT0, APIC_DM_EXTINT);
1666 unlock_ExtINT_logic();
1668 if (timer_irq_works()) {
1669 apic_printk(APIC_VERBOSE," works.\n");
1672 apic_printk(APIC_VERBOSE," failed :(.\n");
1673 panic("IO-APIC + timer doesn't work! Try using the 'noapic' kernel parameter\n");
1676 static int __init notimercheck(char *s)
1681 __setup("no_timer_check", notimercheck);
1685 * IRQ's that are handled by the PIC in the MPS IOAPIC case.
1686 * - IRQ2 is the cascade IRQ, and cannot be a io-apic IRQ.
1687 * Linux doesn't really care, as it's not actually used
1688 * for any interrupt handling anyway.
1690 #define PIC_IRQS (1<<2)
1692 void __init setup_IO_APIC(void)
1697 io_apic_irqs = ~0; /* all IRQs go through IOAPIC */
1699 io_apic_irqs = ~PIC_IRQS;
1701 apic_printk(APIC_VERBOSE, "ENABLING IO-APIC IRQs\n");
1704 * Set up the IO-APIC IRQ routing table.
1707 setup_ioapic_ids_from_mpc();
1709 setup_IO_APIC_irqs();
1710 init_IO_APIC_traps();
1716 struct sysfs_ioapic_data {
1717 struct sys_device dev;
1718 struct IO_APIC_route_entry entry[0];
1720 static struct sysfs_ioapic_data * mp_ioapic_data[MAX_IO_APICS];
1722 static int ioapic_suspend(struct sys_device *dev, pm_message_t state)
1724 struct IO_APIC_route_entry *entry;
1725 struct sysfs_ioapic_data *data;
1726 unsigned long flags;
1729 data = container_of(dev, struct sysfs_ioapic_data, dev);
1730 entry = data->entry;
1731 spin_lock_irqsave(&ioapic_lock, flags);
1732 for (i = 0; i < nr_ioapic_registers[dev->id]; i ++, entry ++ ) {
1733 *(((int *)entry) + 1) = io_apic_read(dev->id, 0x11 + 2 * i);
1734 *(((int *)entry) + 0) = io_apic_read(dev->id, 0x10 + 2 * i);
1736 spin_unlock_irqrestore(&ioapic_lock, flags);
1741 static int ioapic_resume(struct sys_device *dev)
1743 struct IO_APIC_route_entry *entry;
1744 struct sysfs_ioapic_data *data;
1745 unsigned long flags;
1746 union IO_APIC_reg_00 reg_00;
1749 data = container_of(dev, struct sysfs_ioapic_data, dev);
1750 entry = data->entry;
1752 spin_lock_irqsave(&ioapic_lock, flags);
1753 reg_00.raw = io_apic_read(dev->id, 0);
1754 if (reg_00.bits.ID != mp_ioapics[dev->id].mpc_apicid) {
1755 reg_00.bits.ID = mp_ioapics[dev->id].mpc_apicid;
1756 io_apic_write(dev->id, 0, reg_00.raw);
1758 for (i = 0; i < nr_ioapic_registers[dev->id]; i ++, entry ++ ) {
1759 io_apic_write(dev->id, 0x11+2*i, *(((int *)entry)+1));
1760 io_apic_write(dev->id, 0x10+2*i, *(((int *)entry)+0));
1762 spin_unlock_irqrestore(&ioapic_lock, flags);
1767 static struct sysdev_class ioapic_sysdev_class = {
1768 set_kset_name("ioapic"),
1769 .suspend = ioapic_suspend,
1770 .resume = ioapic_resume,
1773 static int __init ioapic_init_sysfs(void)
1775 struct sys_device * dev;
1776 int i, size, error = 0;
1778 error = sysdev_class_register(&ioapic_sysdev_class);
1782 for (i = 0; i < nr_ioapics; i++ ) {
1783 size = sizeof(struct sys_device) + nr_ioapic_registers[i]
1784 * sizeof(struct IO_APIC_route_entry);
1785 mp_ioapic_data[i] = kmalloc(size, GFP_KERNEL);
1786 if (!mp_ioapic_data[i]) {
1787 printk(KERN_ERR "Can't suspend/resume IOAPIC %d\n", i);
1790 memset(mp_ioapic_data[i], 0, size);
1791 dev = &mp_ioapic_data[i]->dev;
1793 dev->cls = &ioapic_sysdev_class;
1794 error = sysdev_register(dev);
1796 kfree(mp_ioapic_data[i]);
1797 mp_ioapic_data[i] = NULL;
1798 printk(KERN_ERR "Can't suspend/resume IOAPIC %d\n", i);
1806 device_initcall(ioapic_init_sysfs);
1808 /* --------------------------------------------------------------------------
1809 ACPI-based IOAPIC Configuration
1810 -------------------------------------------------------------------------- */
1812 #ifdef CONFIG_ACPI_BOOT
1814 #define IO_APIC_MAX_ID 0xFE
1816 int __init io_apic_get_version (int ioapic)
1818 union IO_APIC_reg_01 reg_01;
1819 unsigned long flags;
1821 spin_lock_irqsave(&ioapic_lock, flags);
1822 reg_01.raw = io_apic_read(ioapic, 1);
1823 spin_unlock_irqrestore(&ioapic_lock, flags);
1825 return reg_01.bits.version;
1829 int __init io_apic_get_redir_entries (int ioapic)
1831 union IO_APIC_reg_01 reg_01;
1832 unsigned long flags;
1834 spin_lock_irqsave(&ioapic_lock, flags);
1835 reg_01.raw = io_apic_read(ioapic, 1);
1836 spin_unlock_irqrestore(&ioapic_lock, flags);
1838 return reg_01.bits.entries;
1842 int io_apic_set_pci_routing (int ioapic, int pin, int irq, int edge_level, int active_high_low)
1844 struct IO_APIC_route_entry entry;
1845 unsigned long flags;
1847 if (!IO_APIC_IRQ(irq)) {
1848 apic_printk(APIC_QUIET,KERN_ERR "IOAPIC[%d]: Invalid reference to IRQ 0\n",
1854 * Generate a PCI IRQ routing entry and program the IOAPIC accordingly.
1855 * Note that we mask (disable) IRQs now -- these get enabled when the
1856 * corresponding device driver registers for this IRQ.
1859 memset(&entry,0,sizeof(entry));
1861 entry.delivery_mode = INT_DELIVERY_MODE;
1862 entry.dest_mode = INT_DEST_MODE;
1863 entry.dest.logical.logical_dest = cpu_mask_to_apicid(TARGET_CPUS);
1864 entry.trigger = edge_level;
1865 entry.polarity = active_high_low;
1866 entry.mask = 1; /* Disabled (masked) */
1869 * IRQs < 16 are already in the irq_2_pin[] map
1872 add_pin_to_irq(irq, ioapic, pin);
1874 entry.vector = assign_irq_vector(irq);
1876 apic_printk(APIC_VERBOSE,KERN_DEBUG "IOAPIC[%d]: Set PCI routing entry (%d-%d -> 0x%x -> "
1877 "IRQ %d Mode:%i Active:%i)\n", ioapic,
1878 mp_ioapics[ioapic].mpc_apicid, pin, entry.vector, irq,
1879 edge_level, active_high_low);
1881 ioapic_register_intr(irq, entry.vector, edge_level);
1883 if (!ioapic && (irq < 16))
1884 disable_8259A_irq(irq);
1886 spin_lock_irqsave(&ioapic_lock, flags);
1887 io_apic_write(ioapic, 0x11+2*pin, *(((int *)&entry)+1));
1888 io_apic_write(ioapic, 0x10+2*pin, *(((int *)&entry)+0));
1889 spin_unlock_irqrestore(&ioapic_lock, flags);
1894 #endif /*CONFIG_ACPI_BOOT*/
1898 * This function currently is only a helper for the i386 smp boot process where
1899 * we need to reprogram the ioredtbls to cater for the cpus which have come online
1900 * so mask in all cases should simply be TARGET_CPUS
1902 void __init setup_ioapic_dest(void)
1904 int pin, ioapic, irq, irq_entry;
1906 if (skip_ioapic_setup == 1)
1909 for (ioapic = 0; ioapic < nr_ioapics; ioapic++) {
1910 for (pin = 0; pin < nr_ioapic_registers[ioapic]; pin++) {
1911 irq_entry = find_irq_entry(ioapic, pin, mp_INT);
1912 if (irq_entry == -1)
1914 irq = pin_2_irq(irq_entry, ioapic, pin);
1915 set_ioapic_affinity_irq(irq, TARGET_CPUS);