err.no Git - linux-2.6/blob - arch/x86_64/kernel/io_apic.c

   1 /*
   2  *      Intel IO-APIC support for multi-Pentium hosts.
   3  *
   4  *      Copyright (C) 1997, 1998, 1999, 2000 Ingo Molnar, Hajnalka Szabo
   5  *
   6  *      Many thanks to Stig Venaas for trying out countless experimental
   7  *      patches and reporting/debugging problems patiently!
   8  *
   9  *      (c) 1999, Multiple IO-APIC support, developed by
  10  *      Ken-ichi Yaku <yaku@css1.kbnes.nec.co.jp> and
  11  *      Hidemi Kishimoto <kisimoto@css1.kbnes.nec.co.jp>,
  12  *      further tested and cleaned up by Zach Brown <zab@redhat.com>
  13  *      and Ingo Molnar <mingo@redhat.com>
  14  *
  15  *      Fixes
  16  *      Maciej W. Rozycki       :       Bits for genuine 82489DX APICs;
  17  *                                      thanks to Eric Gilmore
  18  *                                      and Rolf G. Tews
  19  *                                      for testing these extensively
  20  *      Paul Diefenbaugh        :       Added full ACPI support
  21  */
  22
  23 #include <linux/mm.h>
  24 #include <linux/interrupt.h>
  25 #include <linux/init.h>
  26 #include <linux/delay.h>
  27 #include <linux/sched.h>
  28 #include <linux/smp_lock.h>
  29 #include <linux/mc146818rtc.h>
  30 #include <linux/acpi.h>
  31 #include <linux/sysdev.h>
  32 #ifdef CONFIG_ACPI
  33 #include <acpi/acpi_bus.h>
  34 #endif
  35
  36 #include <asm/io.h>
  37 #include <asm/smp.h>
  38 #include <asm/desc.h>
  39 #include <asm/proto.h>
  40 #include <asm/mach_apic.h>
  41 #include <asm/acpi.h>
  42 #include <asm/dma.h>
  43 #include <asm/nmi.h>
  44
  45 #define __apicdebuginit  __init
  46
  47 int sis_apic_bug; /* not actually supported, dummy for compile */
  48
  49 static int no_timer_check;
  50
  51 int disable_timer_pin_1 __initdata;
  52
  53 int timer_over_8254 __initdata = 0;
  54
  55 /* Where if anywhere is the i8259 connect in external int mode */
  56 static struct { int pin, apic; } ioapic_i8259 = { -1, -1 };
  57
  58 static DEFINE_SPINLOCK(ioapic_lock);
  59 static DEFINE_SPINLOCK(vector_lock);
  60
  61 /*
  62  * # of IRQ routing registers
  63  */
  64 int nr_ioapic_registers[MAX_IO_APICS];
  65
  66 /*
  67  * Rough estimation of how many shared IRQs there are, can
  68  * be changed anytime.
  69  */
  70 #define MAX_PLUS_SHARED_IRQS NR_IRQ_VECTORS
  71 #define PIN_MAP_SIZE (MAX_PLUS_SHARED_IRQS + NR_IRQS)
  72
  73 /*
  74  * This is performance-critical, we want to do it O(1)
  75  *
  76  * the indexing order of this array favors 1:1 mappings
  77  * between pins and IRQs.
  78  */
  79
  80 static struct irq_pin_list {
  81         short apic, pin, next;
  82 } irq_2_pin[PIN_MAP_SIZE];
  83
  84 int vector_irq[NR_VECTORS] __read_mostly = { [0 ... NR_VECTORS - 1] = -1};
  85 #ifdef CONFIG_PCI_MSI
  86 #define vector_to_irq(vector)   \
  87         (platform_legacy_irq(vector) ? vector : vector_irq[vector])
  88 #else
  89 #define vector_to_irq(vector)   (vector)
  90 #endif
  91
  92 #define __DO_ACTION(R, ACTION, FINAL)                                   \
  93                                                                         \
  94 {                                                                       \
  95         int pin;                                                        \
  96         struct irq_pin_list *entry = irq_2_pin + irq;                   \
  97                                                                         \
  98         BUG_ON(irq >= NR_IRQS);                                         \
  99         for (;;) {                                                      \
 100                 unsigned int reg;                                       \
 101                 pin = entry->pin;                                       \
 102                 if (pin == -1)                                          \
 103                         break;                                          \
 104                 reg = io_apic_read(entry->apic, 0x10 + R + pin*2);      \
 105                 reg ACTION;                                             \
 106                 io_apic_modify(entry->apic, reg);                       \
 107                 if (!entry->next)                                       \
 108                         break;                                          \
 109                 entry = irq_2_pin + entry->next;                        \
 110         }                                                               \
 111         FINAL;                                                          \
 112 }
 113
 114 union entry_union {
 115         struct { u32 w1, w2; };
 116         struct IO_APIC_route_entry entry;
 117 };
 118
 119 static struct IO_APIC_route_entry ioapic_read_entry(int apic, int pin)
 120 {
 121         union entry_union eu;
 122         unsigned long flags;
 123         spin_lock_irqsave(&ioapic_lock, flags);
 124         eu.w1 = io_apic_read(apic, 0x10 + 2 * pin);
 125         eu.w2 = io_apic_read(apic, 0x11 + 2 * pin);
 126         spin_unlock_irqrestore(&ioapic_lock, flags);
 127         return eu.entry;
 128 }
 129
 130 static void ioapic_write_entry(int apic, int pin, struct IO_APIC_route_entry e)
 131 {
 132         unsigned long flags;
 133         union entry_union eu;
 134         eu.entry = e;
 135         spin_lock_irqsave(&ioapic_lock, flags);
 136         io_apic_write(apic, 0x10 + 2*pin, eu.w1);
 137         io_apic_write(apic, 0x11 + 2*pin, eu.w2);
 138         spin_unlock_irqrestore(&ioapic_lock, flags);
 139 }
 140
 141 #ifdef CONFIG_SMP
 142 static void set_ioapic_affinity_irq(unsigned int irq, cpumask_t mask)
 143 {
 144         unsigned long flags;
 145         unsigned int dest;
 146         cpumask_t tmp;
 147
 148         cpus_and(tmp, mask, cpu_online_map);
 149         if (cpus_empty(tmp))
 150                 tmp = TARGET_CPUS;
 151
 152         cpus_and(mask, tmp, CPU_MASK_ALL);
 153
 154         dest = cpu_mask_to_apicid(mask);
 155
 156         /*
 157          * Only the high 8 bits are valid.
 158          */
 159         dest = SET_APIC_LOGICAL_ID(dest);
 160
 161         spin_lock_irqsave(&ioapic_lock, flags);
 162         __DO_ACTION(1, = dest, )
 163         set_irq_info(irq, mask);
 164         spin_unlock_irqrestore(&ioapic_lock, flags);
 165 }
 166 #endif
 167
 168 static u8 gsi_2_irq[NR_IRQ_VECTORS] = { [0 ... NR_IRQ_VECTORS-1] = 0xFF };
 169
 170 /*
 171  * The common case is 1:1 IRQ<->pin mappings. Sometimes there are
 172  * shared ISA-space IRQs, so we have to support them. We are super
 173  * fast in the common case, and fast for shared ISA-space IRQs.
 174  */
 175 static void add_pin_to_irq(unsigned int irq, int apic, int pin)
 176 {
 177         static int first_free_entry = NR_IRQS;
 178         struct irq_pin_list *entry = irq_2_pin + irq;
 179
 180         BUG_ON(irq >= NR_IRQS);
 181         while (entry->next)
 182                 entry = irq_2_pin + entry->next;
 183
 184         if (entry->pin != -1) {
 185                 entry->next = first_free_entry;
 186                 entry = irq_2_pin + entry->next;
 187                 if (++first_free_entry >= PIN_MAP_SIZE)
 188                         panic("io_apic.c: ran out of irq_2_pin entries!");
 189         }
 190         entry->apic = apic;
 191         entry->pin = pin;
 192 }
 193
 194
 195 #define DO_ACTION(name,R,ACTION, FINAL)                                 \
 196                                                                         \
 197         static void name##_IO_APIC_irq (unsigned int irq)               \
 198         __DO_ACTION(R, ACTION, FINAL)
 199
 200 DO_ACTION( __mask,             0, |= 0x00010000, io_apic_sync(entry->apic) )
 201                                                 /* mask = 1 */
 202 DO_ACTION( __unmask,           0, &= 0xfffeffff, )
 203                                                 /* mask = 0 */
 204
 205 static void mask_IO_APIC_irq (unsigned int irq)
 206 {
 207         unsigned long flags;
 208
 209         spin_lock_irqsave(&ioapic_lock, flags);
 210         __mask_IO_APIC_irq(irq);
 211         spin_unlock_irqrestore(&ioapic_lock, flags);
 212 }
 213
 214 static void unmask_IO_APIC_irq (unsigned int irq)
 215 {
 216         unsigned long flags;
 217
 218         spin_lock_irqsave(&ioapic_lock, flags);
 219         __unmask_IO_APIC_irq(irq);
 220         spin_unlock_irqrestore(&ioapic_lock, flags);
 221 }
 222
 223 static void clear_IO_APIC_pin(unsigned int apic, unsigned int pin)
 224 {
 225         struct IO_APIC_route_entry entry;
 226
 227         /* Check delivery_mode to be sure we're not clearing an SMI pin */
 228         entry = ioapic_read_entry(apic, pin);
 229         if (entry.delivery_mode == dest_SMI)
 230                 return;
 231         /*
 232          * Disable it in the IO-APIC irq-routing table:
 233          */
 234         memset(&entry, 0, sizeof(entry));
 235         entry.mask = 1;
 236         ioapic_write_entry(apic, pin, entry);
 237 }
 238
 239 static void clear_IO_APIC (void)
 240 {
 241         int apic, pin;
 242
 243         for (apic = 0; apic < nr_ioapics; apic++)
 244                 for (pin = 0; pin < nr_ioapic_registers[apic]; pin++)
 245                         clear_IO_APIC_pin(apic, pin);
 246 }
 247
 248 int skip_ioapic_setup;
 249 int ioapic_force;
 250
 251 /* dummy parsing: see setup.c */
 252
 253 static int __init disable_ioapic_setup(char *str)
 254 {
 255         skip_ioapic_setup = 1;
 256         return 1;
 257 }
 258
 259 static int __init enable_ioapic_setup(char *str)
 260 {
 261         ioapic_force = 1;
 262         skip_ioapic_setup = 0;
 263         return 1;
 264 }
 265
 266 __setup("noapic", disable_ioapic_setup);
 267 __setup("apic", enable_ioapic_setup);
 268
 269 static int __init setup_disable_8254_timer(char *s)
 270 {
 271         timer_over_8254 = -1;
 272         return 1;
 273 }
 274 static int __init setup_enable_8254_timer(char *s)
 275 {
 276         timer_over_8254 = 2;
 277         return 1;
 278 }
 279
 280 __setup("disable_8254_timer", setup_disable_8254_timer);
 281 __setup("enable_8254_timer", setup_enable_8254_timer);
 282
 283 #include <asm/pci-direct.h>
 284 #include <linux/pci_ids.h>
 285 #include <linux/pci.h>
 286
 287
 288 #ifdef CONFIG_ACPI
 289
 290 static int nvidia_hpet_detected __initdata;
 291
 292 static int __init nvidia_hpet_check(unsigned long phys, unsigned long size)
 293 {
 294         nvidia_hpet_detected = 1;
 295         return 0;
 296 }
 297 #endif
 298
 299 /* Temporary Hack. Nvidia and VIA boards currently only work with IO-APIC
 300    off. Check for an Nvidia or VIA PCI bridge and turn it off.
 301    Use pci direct infrastructure because this runs before the PCI subsystem.
 302
 303    Can be overwritten with "apic"
 304
 305    And another hack to disable the IOMMU on VIA chipsets.
 306
 307    ... and others. Really should move this somewhere else.
 308
 309    Kludge-O-Rama. */
 310 void __init check_ioapic(void)
 311 {
 312         int num,slot,func;
 313         /* Poor man's PCI discovery */
 314         for (num = 0; num < 32; num++) {
 315                 for (slot = 0; slot < 32; slot++) {
 316                         for (func = 0; func < 8; func++) {
 317                                 u32 class;
 318                                 u32 vendor;
 319                                 u8 type;
 320                                 class = read_pci_config(num,slot,func,
 321                                                         PCI_CLASS_REVISION);
 322                                 if (class == 0xffffffff)
 323                                         break;
 324
 325                                 if ((class >> 16) != PCI_CLASS_BRIDGE_PCI)
 326                                         continue;
 327
 328                                 vendor = read_pci_config(num, slot, func,
 329                                                          PCI_VENDOR_ID);
 330                                 vendor &= 0xffff;
 331                                 switch (vendor) {
 332                                 case PCI_VENDOR_ID_VIA:
 333 #ifdef CONFIG_IOMMU
 334                                         if ((end_pfn > MAX_DMA32_PFN ||
 335                                              force_iommu) &&
 336                                             !iommu_aperture_allowed) {
 337                                                 printk(KERN_INFO
 338     "Looks like a VIA chipset. Disabling IOMMU. Override with \"iommu=allowed\"\n");
 339                                                 iommu_aperture_disabled = 1;
 340                                         }
 341 #endif
 342                                         return;
 343                                 case PCI_VENDOR_ID_NVIDIA:
 344 #ifdef CONFIG_ACPI
 345                                         /*
 346                                          * All timer overrides on Nvidia are
 347                                          * wrong unless HPET is enabled.
 348                                          */
 349                                         nvidia_hpet_detected = 0;
 350                                         acpi_table_parse(ACPI_HPET,
 351                                                         nvidia_hpet_check);
 352                                         if (nvidia_hpet_detected == 0) {
 353                                                 acpi_skip_timer_override = 1;
 354                                                 printk(KERN_INFO "Nvidia board "
 355                                                     "detected. Ignoring ACPI "
 356                                                     "timer override.\n");
 357                                         }
 358 #endif
 359                                         /* RED-PEN skip them on mptables too? */
 360                                         return;
 361
 362                                 /* This should be actually default, but
 363                                    for 2.6.16 let's do it for ATI only where
 364                                    it's really needed. */
 365                                 case PCI_VENDOR_ID_ATI:
 366                                         if (timer_over_8254 == 1) {
 367                                                 timer_over_8254 = 0;
 368                                         printk(KERN_INFO
 369                 "ATI board detected. Disabling timer routing over 8254.\n");
 370                                         }
 371                                         return;
 372                                 }
 373
 374
 375                                 /* No multi-function device? */
 376                                 type = read_pci_config_byte(num,slot,func,
 377                                                             PCI_HEADER_TYPE);
 378                                 if (!(type & 0x80))
 379                                         break;
 380                         }
 381                 }
 382         }
 383 }
 384
 385 /*
 386  * Find the IRQ entry number of a certain pin.
 387  */
 388 static int find_irq_entry(int apic, int pin, int type)
 389 {
 390         int i;
 391
 392         for (i = 0; i < mp_irq_entries; i++)
 393                 if (mp_irqs[i].mpc_irqtype == type &&
 394                     (mp_irqs[i].mpc_dstapic == mp_ioapics[apic].mpc_apicid ||
 395                      mp_irqs[i].mpc_dstapic == MP_APIC_ALL) &&
 396                     mp_irqs[i].mpc_dstirq == pin)
 397                         return i;
 398
 399         return -1;
 400 }
 401
 402 /*
 403  * Find the pin to which IRQ[irq] (ISA) is connected
 404  */
 405 static int __init find_isa_irq_pin(int irq, int type)
 406 {
 407         int i;
 408
 409         for (i = 0; i < mp_irq_entries; i++) {
 410                 int lbus = mp_irqs[i].mpc_srcbus;
 411
 412                 if (mp_bus_id_to_type[lbus] == MP_BUS_ISA &&
 413                     (mp_irqs[i].mpc_irqtype == type) &&
 414                     (mp_irqs[i].mpc_srcbusirq == irq))
 415
 416                         return mp_irqs[i].mpc_dstirq;
 417         }
 418         return -1;
 419 }
 420
 421 static int __init find_isa_irq_apic(int irq, int type)
 422 {
 423         int i;
 424
 425         for (i = 0; i < mp_irq_entries; i++) {
 426                 int lbus = mp_irqs[i].mpc_srcbus;
 427
 428                 if ((mp_bus_id_to_type[lbus] == MP_BUS_ISA) &&
 429                     (mp_irqs[i].mpc_irqtype == type) &&
 430                     (mp_irqs[i].mpc_srcbusirq == irq))
 431                         break;
 432         }
 433         if (i < mp_irq_entries) {
 434                 int apic;
 435                 for(apic = 0; apic < nr_ioapics; apic++) {
 436                         if (mp_ioapics[apic].mpc_apicid == mp_irqs[i].mpc_dstapic)
 437                                 return apic;
 438                 }
 439         }
 440
 441         return -1;
 442 }
 443
 444 /*
 445  * Find a specific PCI IRQ entry.
 446  * Not an __init, possibly needed by modules
 447  */
 448 static int pin_2_irq(int idx, int apic, int pin);
 449
 450 int IO_APIC_get_PCI_irq_vector(int bus, int slot, int pin)
 451 {
 452         int apic, i, best_guess = -1;
 453
 454         apic_printk(APIC_DEBUG, "querying PCI -> IRQ mapping bus:%d, slot:%d, pin:%d.\n",
 455                 bus, slot, pin);
 456         if (mp_bus_id_to_pci_bus[bus] == -1) {
 457                 apic_printk(APIC_VERBOSE, "PCI BIOS passed nonexistent PCI bus %d!\n", bus);
 458                 return -1;
 459         }
 460         for (i = 0; i < mp_irq_entries; i++) {
 461                 int lbus = mp_irqs[i].mpc_srcbus;
 462
 463                 for (apic = 0; apic < nr_ioapics; apic++)
 464                         if (mp_ioapics[apic].mpc_apicid == mp_irqs[i].mpc_dstapic ||
 465                             mp_irqs[i].mpc_dstapic == MP_APIC_ALL)
 466                                 break;
 467
 468                 if ((mp_bus_id_to_type[lbus] == MP_BUS_PCI) &&
 469                     !mp_irqs[i].mpc_irqtype &&
 470                     (bus == lbus) &&
 471                     (slot == ((mp_irqs[i].mpc_srcbusirq >> 2) & 0x1f))) {
 472                         int irq = pin_2_irq(i,apic,mp_irqs[i].mpc_dstirq);
 473
 474                         if (!(apic || IO_APIC_IRQ(irq)))
 475                                 continue;
 476
 477                         if (pin == (mp_irqs[i].mpc_srcbusirq & 3))
 478                                 return irq;
 479                         /*
 480                          * Use the first all-but-pin matching entry as a
 481                          * best-guess fuzzy result for broken mptables.
 482                          */
 483                         if (best_guess < 0)
 484                                 best_guess = irq;
 485                 }
 486         }
 487         BUG_ON(best_guess >= NR_IRQS);
 488         return best_guess;
 489 }
 490
 491 /* ISA interrupts are always polarity zero edge triggered,
 492  * when listed as conforming in the MP table. */
 493
 494 #define default_ISA_trigger(idx)        (0)
 495 #define default_ISA_polarity(idx)       (0)
 496
 497 /* PCI interrupts are always polarity one level triggered,
 498  * when listed as conforming in the MP table. */
 499
 500 #define default_PCI_trigger(idx)        (1)
 501 #define default_PCI_polarity(idx)       (1)
 502
 503 static int __init MPBIOS_polarity(int idx)
 504 {
 505         int bus = mp_irqs[idx].mpc_srcbus;
 506         int polarity;
 507
 508         /*
 509          * Determine IRQ line polarity (high active or low active):
 510          */
 511         switch (mp_irqs[idx].mpc_irqflag & 3)
 512         {
 513                 case 0: /* conforms, ie. bus-type dependent polarity */
 514                 {
 515                         switch (mp_bus_id_to_type[bus])
 516                         {
 517                                 case MP_BUS_ISA: /* ISA pin */
 518                                 {
 519                                         polarity = default_ISA_polarity(idx);
 520                                         break;
 521                                 }
 522                                 case MP_BUS_PCI: /* PCI pin */
 523                                 {
 524                                         polarity = default_PCI_polarity(idx);
 525                                         break;
 526                                 }
 527                                 default:
 528                                 {
 529                                         printk(KERN_WARNING "broken BIOS!!\n");
 530                                         polarity = 1;
 531                                         break;
 532                                 }
 533                         }
 534                         break;
 535                 }
 536                 case 1: /* high active */
 537                 {
 538                         polarity = 0;
 539                         break;
 540                 }
 541                 case 2: /* reserved */
 542                 {
 543                         printk(KERN_WARNING "broken BIOS!!\n");
 544                         polarity = 1;
 545                         break;
 546                 }
 547                 case 3: /* low active */
 548                 {
 549                         polarity = 1;
 550                         break;
 551                 }
 552                 default: /* invalid */
 553                 {
 554                         printk(KERN_WARNING "broken BIOS!!\n");
 555                         polarity = 1;
 556                         break;
 557                 }
 558         }
 559         return polarity;
 560 }
 561
 562 static int MPBIOS_trigger(int idx)
 563 {
 564         int bus = mp_irqs[idx].mpc_srcbus;
 565         int trigger;
 566
 567         /*
 568          * Determine IRQ trigger mode (edge or level sensitive):
 569          */
 570         switch ((mp_irqs[idx].mpc_irqflag>>2) & 3)
 571         {
 572                 case 0: /* conforms, ie. bus-type dependent */
 573                 {
 574                         switch (mp_bus_id_to_type[bus])
 575                         {
 576                                 case MP_BUS_ISA: /* ISA pin */
 577                                 {
 578                                         trigger = default_ISA_trigger(idx);
 579                                         break;
 580                                 }
 581                                 case MP_BUS_PCI: /* PCI pin */
 582                                 {
 583                                         trigger = default_PCI_trigger(idx);
 584                                         break;
 585                                 }
 586                                 default:
 587                                 {
 588                                         printk(KERN_WARNING "broken BIOS!!\n");
 589                                         trigger = 1;
 590                                         break;
 591                                 }
 592                         }
 593                         break;
 594                 }
 595                 case 1: /* edge */
 596                 {
 597                         trigger = 0;
 598                         break;
 599                 }
 600                 case 2: /* reserved */
 601                 {
 602                         printk(KERN_WARNING "broken BIOS!!\n");
 603                         trigger = 1;
 604                         break;
 605                 }
 606                 case 3: /* level */
 607                 {
 608                         trigger = 1;
 609                         break;
 610                 }
 611                 default: /* invalid */
 612                 {
 613                         printk(KERN_WARNING "broken BIOS!!\n");
 614                         trigger = 0;
 615                         break;
 616                 }
 617         }
 618         return trigger;
 619 }
 620
 621 static inline int irq_polarity(int idx)
 622 {
 623         return MPBIOS_polarity(idx);
 624 }
 625
 626 static inline int irq_trigger(int idx)
 627 {
 628         return MPBIOS_trigger(idx);
 629 }
 630
 631 static int next_irq = 16;
 632
 633 /*
 634  * gsi_irq_sharing -- Name overload!  "irq" can be either a legacy IRQ
 635  * in the range 0-15, a linux IRQ in the range 0-223, or a GSI number
 636  * from ACPI, which can reach 800 in large boxen.
 637  *
 638  * Compact the sparse GSI space into a sequential IRQ series and reuse
 639  * vectors if possible.
 640  */
 641 int gsi_irq_sharing(int gsi)
 642 {
 643         int i, tries, vector;
 644
 645         BUG_ON(gsi >= NR_IRQ_VECTORS);
 646
 647         if (platform_legacy_irq(gsi))
 648                 return gsi;
 649
 650         if (gsi_2_irq[gsi] != 0xFF)
 651                 return (int)gsi_2_irq[gsi];
 652
 653         tries = NR_IRQS;
 654   try_again:
 655         vector = assign_irq_vector(gsi);
 656
 657         /*
 658          * Sharing vectors means sharing IRQs, so scan irq_vectors for previous
 659          * use of vector and if found, return that IRQ.  However, we never want
 660          * to share legacy IRQs, which usually have a different trigger mode
 661          * than PCI.
 662          */
 663         for (i = 0; i < NR_IRQS; i++)
 664                 if (IO_APIC_VECTOR(i) == vector)
 665                         break;
 666         if (platform_legacy_irq(i)) {
 667                 if (--tries >= 0) {
 668                         IO_APIC_VECTOR(i) = 0;
 669                         goto try_again;
 670                 }
 671                 panic("gsi_irq_sharing: didn't find an IRQ using vector 0x%02X for GSI %d", vector, gsi);
 672         }
 673         if (i < NR_IRQS) {
 674                 gsi_2_irq[gsi] = i;
 675                 printk(KERN_INFO "GSI %d sharing vector 0x%02X and IRQ %d\n",
 676                                 gsi, vector, i);
 677                 return i;
 678         }
 679
 680         i = next_irq++;
 681         BUG_ON(i >= NR_IRQS);
 682         gsi_2_irq[gsi] = i;
 683         IO_APIC_VECTOR(i) = vector;
 684         printk(KERN_INFO "GSI %d assigned vector 0x%02X and IRQ %d\n",
 685                         gsi, vector, i);
 686         return i;
 687 }
 688
 689 static int pin_2_irq(int idx, int apic, int pin)
 690 {
 691         int irq, i;
 692         int bus = mp_irqs[idx].mpc_srcbus;
 693
 694         /*
 695          * Debugging check, we are in big trouble if this message pops up!
 696          */
 697         if (mp_irqs[idx].mpc_dstirq != pin)
 698                 printk(KERN_ERR "broken BIOS or MPTABLE parser, ayiee!!\n");
 699
 700         switch (mp_bus_id_to_type[bus])
 701         {
 702                 case MP_BUS_ISA: /* ISA pin */
 703                 {
 704                         irq = mp_irqs[idx].mpc_srcbusirq;
 705                         break;
 706                 }
 707                 case MP_BUS_PCI: /* PCI pin */
 708                 {
 709                         /*
 710                          * PCI IRQs are mapped in order
 711                          */
 712                         i = irq = 0;
 713                         while (i < apic)
 714                                 irq += nr_ioapic_registers[i++];
 715                         irq += pin;
 716                         irq = gsi_irq_sharing(irq);
 717                         break;
 718                 }
 719                 default:
 720                 {
 721                         printk(KERN_ERR "unknown bus type %d.\n",bus);
 722                         irq = 0;
 723                         break;
 724                 }
 725         }
 726         BUG_ON(irq >= NR_IRQS);
 727         return irq;
 728 }
 729
 730 static inline int IO_APIC_irq_trigger(int irq)
 731 {
 732         int apic, idx, pin;
 733
 734         for (apic = 0; apic < nr_ioapics; apic++) {
 735                 for (pin = 0; pin < nr_ioapic_registers[apic]; pin++) {
 736                         idx = find_irq_entry(apic,pin,mp_INT);
 737                         if ((idx != -1) && (irq == pin_2_irq(idx,apic,pin)))
 738                                 return irq_trigger(idx);
 739                 }
 740         }
 741         /*
 742          * nonexistent IRQs are edge default
 743          */
 744         return 0;
 745 }
 746
 747 /* irq_vectors is indexed by the sum of all RTEs in all I/O APICs. */
 748 u8 irq_vector[NR_IRQ_VECTORS] __read_mostly = { FIRST_DEVICE_VECTOR , 0 };
 749
 750 int assign_irq_vector(int irq)
 751 {
 752         static int current_vector = FIRST_DEVICE_VECTOR, offset = 0;
 753         unsigned long flags;
 754         int vector;
 755
 756         BUG_ON(irq != AUTO_ASSIGN && (unsigned)irq >= NR_IRQ_VECTORS);
 757
 758         spin_lock_irqsave(&vector_lock, flags);
 759
 760         if (irq != AUTO_ASSIGN && IO_APIC_VECTOR(irq) > 0) {
 761                 spin_unlock_irqrestore(&vector_lock, flags);
 762                 return IO_APIC_VECTOR(irq);
 763         }
 764 next:
 765         current_vector += 8;
 766         if (current_vector == IA32_SYSCALL_VECTOR)
 767                 goto next;
 768
 769         if (current_vector >= FIRST_SYSTEM_VECTOR) {
 770                 /* If we run out of vectors on large boxen, must share them. */
 771                 offset = (offset + 1) % 8;
 772                 current_vector = FIRST_DEVICE_VECTOR + offset;
 773         }
 774
 775         vector = current_vector;
 776         vector_irq[vector] = irq;
 777         if (irq != AUTO_ASSIGN)
 778                 IO_APIC_VECTOR(irq) = vector;
 779
 780         spin_unlock_irqrestore(&vector_lock, flags);
 781
 782         return vector;
 783 }
 784
 785 extern void (*interrupt[NR_IRQS])(void);
 786 static struct hw_interrupt_type ioapic_level_type;
 787 static struct hw_interrupt_type ioapic_edge_type;
 788
 789 #define IOAPIC_AUTO     -1
 790 #define IOAPIC_EDGE     0
 791 #define IOAPIC_LEVEL    1
 792
 793 static void ioapic_register_intr(int irq, int vector, unsigned long trigger)
 794 {
 795         unsigned idx;
 796
 797         idx = use_pci_vector() && !platform_legacy_irq(irq) ? vector : irq;
 798
 799         if ((trigger == IOAPIC_AUTO && IO_APIC_irq_trigger(irq)) ||
 800                         trigger == IOAPIC_LEVEL)
 801                 irq_desc[idx].chip = &ioapic_level_type;
 802         else
 803                 irq_desc[idx].chip = &ioapic_edge_type;
 804         set_intr_gate(vector, interrupt[idx]);
 805 }
 806
 807 static void __init setup_IO_APIC_irqs(void)
 808 {
 809         struct IO_APIC_route_entry entry;
 810         int apic, pin, idx, irq, first_notcon = 1, vector;
 811         unsigned long flags;
 812
 813         apic_printk(APIC_VERBOSE, KERN_DEBUG "init IO_APIC IRQs\n");
 814
 815         for (apic = 0; apic < nr_ioapics; apic++) {
 816         for (pin = 0; pin < nr_ioapic_registers[apic]; pin++) {
 817
 818                 /*
 819                  * add it to the IO-APIC irq-routing table:
 820                  */
 821                 memset(&entry,0,sizeof(entry));
 822
 823                 entry.delivery_mode = INT_DELIVERY_MODE;
 824                 entry.dest_mode = INT_DEST_MODE;
 825                 entry.mask = 0;                         /* enable IRQ */
 826                 entry.dest.logical.logical_dest = cpu_mask_to_apicid(TARGET_CPUS);
 827
 828                 idx = find_irq_entry(apic,pin,mp_INT);
 829                 if (idx == -1) {
 830                         if (first_notcon) {
 831                                 apic_printk(APIC_VERBOSE, KERN_DEBUG " IO-APIC (apicid-pin) %d-%d", mp_ioapics[apic].mpc_apicid, pin);
 832                                 first_notcon = 0;
 833                         } else
 834                                 apic_printk(APIC_VERBOSE, ", %d-%d", mp_ioapics[apic].mpc_apicid, pin);
 835                         continue;
 836                 }
 837
 838                 entry.trigger = irq_trigger(idx);
 839                 entry.polarity = irq_polarity(idx);
 840
 841                 if (irq_trigger(idx)) {
 842                         entry.trigger = 1;
 843                         entry.mask = 1;
 844                         entry.dest.logical.logical_dest = cpu_mask_to_apicid(TARGET_CPUS);
 845                 }
 846
 847                 irq = pin_2_irq(idx, apic, pin);
 848                 add_pin_to_irq(irq, apic, pin);
 849
 850                 if (!apic && !IO_APIC_IRQ(irq))
 851                         continue;
 852
 853                 if (IO_APIC_IRQ(irq)) {
 854                         vector = assign_irq_vector(irq);
 855                         entry.vector = vector;
 856
 857                         ioapic_register_intr(irq, vector, IOAPIC_AUTO);
 858                         if (!apic && (irq < 16))
 859                                 disable_8259A_irq(irq);
 860                 }
 861                 ioapic_write_entry(apic, pin, entry);
 862
 863                 spin_lock_irqsave(&ioapic_lock, flags);
 864                 set_native_irq_info(irq, TARGET_CPUS);
 865                 spin_unlock_irqrestore(&ioapic_lock, flags);
 866         }
 867         }
 868
 869         if (!first_notcon)
 870                 apic_printk(APIC_VERBOSE," not connected.\n");
 871 }
 872
 873 /*
 874  * Set up the 8259A-master output pin as broadcast to all
 875  * CPUs.
 876  */
 877 static void __init setup_ExtINT_IRQ0_pin(unsigned int apic, unsigned int pin, int vector)
 878 {
 879         struct IO_APIC_route_entry entry;
 880         unsigned long flags;
 881
 882         memset(&entry,0,sizeof(entry));
 883
 884         disable_8259A_irq(0);
 885
 886         /* mask LVT0 */
 887         apic_write(APIC_LVT0, APIC_LVT_MASKED | APIC_DM_EXTINT);
 888
 889         /*
 890          * We use logical delivery to get the timer IRQ
 891          * to the first CPU.
 892          */
 893         entry.dest_mode = INT_DEST_MODE;
 894         entry.mask = 0;                                 /* unmask IRQ now */
 895         entry.dest.logical.logical_dest = cpu_mask_to_apicid(TARGET_CPUS);
 896         entry.delivery_mode = INT_DELIVERY_MODE;
 897         entry.polarity = 0;
 898         entry.trigger = 0;
 899         entry.vector = vector;
 900
 901         /*
 902          * The timer IRQ doesn't have to know that behind the
 903          * scene we have a 8259A-master in AEOI mode ...
 904          */
 905         irq_desc[0].chip = &ioapic_edge_type;
 906
 907         /*
 908          * Add it to the IO-APIC irq-routing table:
 909          */
 910         spin_lock_irqsave(&ioapic_lock, flags);
 911         io_apic_write(apic, 0x11+2*pin, *(((int *)&entry)+1));
 912         io_apic_write(apic, 0x10+2*pin, *(((int *)&entry)+0));
 913         spin_unlock_irqrestore(&ioapic_lock, flags);
 914
 915         enable_8259A_irq(0);
 916 }
 917
 918 void __init UNEXPECTED_IO_APIC(void)
 919 {
 920 }
 921
 922 void __apicdebuginit print_IO_APIC(void)
 923 {
 924         int apic, i;
 925         union IO_APIC_reg_00 reg_00;
 926         union IO_APIC_reg_01 reg_01;
 927         union IO_APIC_reg_02 reg_02;
 928         unsigned long flags;
 929
 930         if (apic_verbosity == APIC_QUIET)
 931                 return;
 932
 933         printk(KERN_DEBUG "number of MP IRQ sources: %d.\n", mp_irq_entries);
 934         for (i = 0; i < nr_ioapics; i++)
 935                 printk(KERN_DEBUG "number of IO-APIC #%d registers: %d.\n",
 936                        mp_ioapics[i].mpc_apicid, nr_ioapic_registers[i]);
 937
 938         /*
 939          * We are a bit conservative about what we expect.  We have to
 940          * know about every hardware change ASAP.
 941          */
 942         printk(KERN_INFO "testing the IO APIC.......................\n");
 943
 944         for (apic = 0; apic < nr_ioapics; apic++) {
 945
 946         spin_lock_irqsave(&ioapic_lock, flags);
 947         reg_00.raw = io_apic_read(apic, 0);
 948         reg_01.raw = io_apic_read(apic, 1);
 949         if (reg_01.bits.version >= 0x10)
 950                 reg_02.raw = io_apic_read(apic, 2);
 951         spin_unlock_irqrestore(&ioapic_lock, flags);
 952
 953         printk("\n");
 954         printk(KERN_DEBUG "IO APIC #%d......\n", mp_ioapics[apic].mpc_apicid);
 955         printk(KERN_DEBUG ".... register #00: %08X\n", reg_00.raw);
 956         printk(KERN_DEBUG ".......    : physical APIC id: %02X\n", reg_00.bits.ID);
 957         if (reg_00.bits.__reserved_1 || reg_00.bits.__reserved_2)
 958                 UNEXPECTED_IO_APIC();
 959
 960         printk(KERN_DEBUG ".... register #01: %08X\n", *(int *)&reg_01);
 961         printk(KERN_DEBUG ".......     : max redirection entries: %04X\n", reg_01.bits.entries);
 962         if (    (reg_01.bits.entries != 0x0f) && /* older (Neptune) boards */
 963                 (reg_01.bits.entries != 0x17) && /* typical ISA+PCI boards */
 964                 (reg_01.bits.entries != 0x1b) && /* Compaq Proliant boards */
 965                 (reg_01.bits.entries != 0x1f) && /* dual Xeon boards */
 966                 (reg_01.bits.entries != 0x22) && /* bigger Xeon boards */
 967                 (reg_01.bits.entries != 0x2E) &&
 968                 (reg_01.bits.entries != 0x3F) &&
 969                 (reg_01.bits.entries != 0x03)
 970         )
 971                 UNEXPECTED_IO_APIC();
 972
 973         printk(KERN_DEBUG ".......     : PRQ implemented: %X\n", reg_01.bits.PRQ);
 974         printk(KERN_DEBUG ".......     : IO APIC version: %04X\n", reg_01.bits.version);
 975         if (    (reg_01.bits.version != 0x01) && /* 82489DX IO-APICs */
 976                 (reg_01.bits.version != 0x02) && /* 82801BA IO-APICs (ICH2) */
 977                 (reg_01.bits.version != 0x10) && /* oldest IO-APICs */
 978                 (reg_01.bits.version != 0x11) && /* Pentium/Pro IO-APICs */
 979                 (reg_01.bits.version != 0x13) && /* Xeon IO-APICs */
 980                 (reg_01.bits.version != 0x20)    /* Intel P64H (82806 AA) */
 981         )
 982                 UNEXPECTED_IO_APIC();
 983         if (reg_01.bits.__reserved_1 || reg_01.bits.__reserved_2)
 984                 UNEXPECTED_IO_APIC();
 985
 986         if (reg_01.bits.version >= 0x10) {
 987                 printk(KERN_DEBUG ".... register #02: %08X\n", reg_02.raw);
 988                 printk(KERN_DEBUG ".......     : arbitration: %02X\n", reg_02.bits.arbitration);
 989                 if (reg_02.bits.__reserved_1 || reg_02.bits.__reserved_2)
 990                         UNEXPECTED_IO_APIC();
 991         }
 992
 993         printk(KERN_DEBUG ".... IRQ redirection table:\n");
 994
 995         printk(KERN_DEBUG " NR Log Phy Mask Trig IRR Pol"
 996                           " Stat Dest Deli Vect:   \n");
 997
 998         for (i = 0; i <= reg_01.bits.entries; i++) {
 999                 struct IO_APIC_route_entry entry;
1000
1001                 entry = ioapic_read_entry(apic, i);
1002
1003                 printk(KERN_DEBUG " %02x %03X %02X  ",
1004                         i,
1005                         entry.dest.logical.logical_dest,
1006                         entry.dest.physical.physical_dest
1007                 );
1008
1009                 printk("%1d    %1d    %1d   %1d   %1d    %1d    %1d    %02X\n",
1010                         entry.mask,
1011                         entry.trigger,
1012                         entry.irr,
1013                         entry.polarity,
1014                         entry.delivery_status,
1015                         entry.dest_mode,
1016                         entry.delivery_mode,
1017                         entry.vector
1018                 );
1019         }
1020         }
1021         if (use_pci_vector())
1022                 printk(KERN_INFO "Using vector-based indexing\n");
1023         printk(KERN_DEBUG "IRQ to pin mappings:\n");
1024         for (i = 0; i < NR_IRQS; i++) {
1025                 struct irq_pin_list *entry = irq_2_pin + i;
1026                 if (entry->pin < 0)
1027                         continue;
1028                 if (use_pci_vector() && !platform_legacy_irq(i))
1029                         printk(KERN_DEBUG "IRQ%d ", IO_APIC_VECTOR(i));
1030                 else
1031                         printk(KERN_DEBUG "IRQ%d ", i);
1032                 for (;;) {
1033                         printk("-> %d:%d", entry->apic, entry->pin);
1034                         if (!entry->next)
1035                                 break;
1036                         entry = irq_2_pin + entry->next;
1037                 }
1038                 printk("\n");
1039         }
1040
1041         printk(KERN_INFO ".................................... done.\n");
1042
1043         return;
1044 }
1045
1046 #if 0
1047
1048 static __apicdebuginit void print_APIC_bitfield (int base)
1049 {
1050         unsigned int v;
1051         int i, j;
1052
1053         if (apic_verbosity == APIC_QUIET)
1054                 return;
1055
1056         printk(KERN_DEBUG "0123456789abcdef0123456789abcdef\n" KERN_DEBUG);
1057         for (i = 0; i < 8; i++) {
1058                 v = apic_read(base + i*0x10);
1059                 for (j = 0; j < 32; j++) {
1060                         if (v & (1<<j))
1061                                 printk("1");
1062                         else
1063                                 printk("0");
1064                 }
1065                 printk("\n");
1066         }
1067 }
1068
1069 void __apicdebuginit print_local_APIC(void * dummy)
1070 {
1071         unsigned int v, ver, maxlvt;
1072
1073         if (apic_verbosity == APIC_QUIET)
1074                 return;
1075
1076         printk("\n" KERN_DEBUG "printing local APIC contents on CPU#%d/%d:\n",
1077                 smp_processor_id(), hard_smp_processor_id());
1078         v = apic_read(APIC_ID);
1079         printk(KERN_INFO "... APIC ID:      %08x (%01x)\n", v, GET_APIC_ID(v));
1080         v = apic_read(APIC_LVR);
1081         printk(KERN_INFO "... APIC VERSION: %08x\n", v);
1082         ver = GET_APIC_VERSION(v);
1083         maxlvt = get_maxlvt();
1084
1085         v = apic_read(APIC_TASKPRI);
1086         printk(KERN_DEBUG "... APIC TASKPRI: %08x (%02x)\n", v, v & APIC_TPRI_MASK);
1087
1088         v = apic_read(APIC_ARBPRI);
1089         printk(KERN_DEBUG "... APIC ARBPRI: %08x (%02x)\n", v,
1090                 v & APIC_ARBPRI_MASK);
1091         v = apic_read(APIC_PROCPRI);
1092         printk(KERN_DEBUG "... APIC PROCPRI: %08x\n", v);
1093
1094         v = apic_read(APIC_EOI);
1095         printk(KERN_DEBUG "... APIC EOI: %08x\n", v);
1096         v = apic_read(APIC_RRR);
1097         printk(KERN_DEBUG "... APIC RRR: %08x\n", v);
1098         v = apic_read(APIC_LDR);
1099         printk(KERN_DEBUG "... APIC LDR: %08x\n", v);
1100         v = apic_read(APIC_DFR);
1101         printk(KERN_DEBUG "... APIC DFR: %08x\n", v);
1102         v = apic_read(APIC_SPIV);
1103         printk(KERN_DEBUG "... APIC SPIV: %08x\n", v);
1104
1105         printk(KERN_DEBUG "... APIC ISR field:\n");
1106         print_APIC_bitfield(APIC_ISR);
1107         printk(KERN_DEBUG "... APIC TMR field:\n");
1108         print_APIC_bitfield(APIC_TMR);
1109         printk(KERN_DEBUG "... APIC IRR field:\n");
1110         print_APIC_bitfield(APIC_IRR);
1111
1112         v = apic_read(APIC_ESR);
1113         printk(KERN_DEBUG "... APIC ESR: %08x\n", v);
1114
1115         v = apic_read(APIC_ICR);
1116         printk(KERN_DEBUG "... APIC ICR: %08x\n", v);
1117         v = apic_read(APIC_ICR2);
1118         printk(KERN_DEBUG "... APIC ICR2: %08x\n", v);
1119
1120         v = apic_read(APIC_LVTT);
1121         printk(KERN_DEBUG "... APIC LVTT: %08x\n", v);
1122
1123         if (maxlvt > 3) {                       /* PC is LVT#4. */
1124                 v = apic_read(APIC_LVTPC);
1125                 printk(KERN_DEBUG "... APIC LVTPC: %08x\n", v);
1126         }
1127         v = apic_read(APIC_LVT0);
1128         printk(KERN_DEBUG "... APIC LVT0: %08x\n", v);
1129         v = apic_read(APIC_LVT1);
1130         printk(KERN_DEBUG "... APIC LVT1: %08x\n", v);
1131
1132         if (maxlvt > 2) {                       /* ERR is LVT#3. */
1133                 v = apic_read(APIC_LVTERR);
1134                 printk(KERN_DEBUG "... APIC LVTERR: %08x\n", v);
1135         }
1136
1137         v = apic_read(APIC_TMICT);
1138         printk(KERN_DEBUG "... APIC TMICT: %08x\n", v);
1139         v = apic_read(APIC_TMCCT);
1140         printk(KERN_DEBUG "... APIC TMCCT: %08x\n", v);
1141         v = apic_read(APIC_TDCR);
1142         printk(KERN_DEBUG "... APIC TDCR: %08x\n", v);
1143         printk("\n");
1144 }
1145
1146 void print_all_local_APICs (void)
1147 {
1148         on_each_cpu(print_local_APIC, NULL, 1, 1);
1149 }
1150
1151 void __apicdebuginit print_PIC(void)
1152 {
1153         unsigned int v;
1154         unsigned long flags;
1155
1156         if (apic_verbosity == APIC_QUIET)
1157                 return;
1158
1159         printk(KERN_DEBUG "\nprinting PIC contents\n");
1160
1161         spin_lock_irqsave(&i8259A_lock, flags);
1162
1163         v = inb(0xa1) << 8 | inb(0x21);
1164         printk(KERN_DEBUG "... PIC  IMR: %04x\n", v);
1165
1166         v = inb(0xa0) << 8 | inb(0x20);
1167         printk(KERN_DEBUG "... PIC  IRR: %04x\n", v);
1168
1169         outb(0x0b,0xa0);
1170         outb(0x0b,0x20);
1171         v = inb(0xa0) << 8 | inb(0x20);
1172         outb(0x0a,0xa0);
1173         outb(0x0a,0x20);
1174
1175         spin_unlock_irqrestore(&i8259A_lock, flags);
1176
1177         printk(KERN_DEBUG "... PIC  ISR: %04x\n", v);
1178
1179         v = inb(0x4d1) << 8 | inb(0x4d0);
1180         printk(KERN_DEBUG "... PIC ELCR: %04x\n", v);
1181 }
1182
1183 #endif  /*  0  */
1184
1185 static void __init enable_IO_APIC(void)
1186 {
1187         union IO_APIC_reg_01 reg_01;
1188         int i8259_apic, i8259_pin;
1189         int i, apic;
1190         unsigned long flags;
1191
1192         for (i = 0; i < PIN_MAP_SIZE; i++) {
1193                 irq_2_pin[i].pin = -1;
1194                 irq_2_pin[i].next = 0;
1195         }
1196
1197         /*
1198          * The number of IO-APIC IRQ registers (== #pins):
1199          */
1200         for (apic = 0; apic < nr_ioapics; apic++) {
1201                 spin_lock_irqsave(&ioapic_lock, flags);
1202                 reg_01.raw = io_apic_read(apic, 1);
1203                 spin_unlock_irqrestore(&ioapic_lock, flags);
1204                 nr_ioapic_registers[apic] = reg_01.bits.entries+1;
1205         }
1206         for(apic = 0; apic < nr_ioapics; apic++) {
1207                 int pin;
1208                 /* See if any of the pins is in ExtINT mode */
1209                 for (pin = 0; pin < nr_ioapic_registers[apic]; pin++) {
1210                         struct IO_APIC_route_entry entry;
1211                         entry = ioapic_read_entry(apic, pin);
1212
1213                         /* If the interrupt line is enabled and in ExtInt mode
1214                          * I have found the pin where the i8259 is connected.
1215                          */
1216                         if ((entry.mask == 0) && (entry.delivery_mode == dest_ExtINT)) {
1217                                 ioapic_i8259.apic = apic;
1218                                 ioapic_i8259.pin  = pin;
1219                                 goto found_i8259;
1220                         }
1221                 }
1222         }
1223  found_i8259:
1224         /* Look to see what if the MP table has reported the ExtINT */
1225         i8259_pin  = find_isa_irq_pin(0, mp_ExtINT);
1226         i8259_apic = find_isa_irq_apic(0, mp_ExtINT);
1227         /* Trust the MP table if nothing is setup in the hardware */
1228         if ((ioapic_i8259.pin == -1) && (i8259_pin >= 0)) {
1229                 printk(KERN_WARNING "ExtINT not setup in hardware but reported by MP table\n");
1230                 ioapic_i8259.pin  = i8259_pin;
1231                 ioapic_i8259.apic = i8259_apic;
1232         }
1233         /* Complain if the MP table and the hardware disagree */
1234         if (((ioapic_i8259.apic != i8259_apic) || (ioapic_i8259.pin != i8259_pin)) &&
1235                 (i8259_pin >= 0) && (ioapic_i8259.pin >= 0))
1236         {
1237                 printk(KERN_WARNING "ExtINT in hardware and MP table differ\n");
1238         }
1239
1240         /*
1241          * Do not trust the IO-APIC being empty at bootup
1242          */
1243         clear_IO_APIC();
1244 }
1245
1246 /*
1247  * Not an __init, needed by the reboot code
1248  */
1249 void disable_IO_APIC(void)
1250 {
1251         /*
1252          * Clear the IO-APIC before rebooting:
1253          */
1254         clear_IO_APIC();
1255
1256         /*
1257          * If the i8259 is routed through an IOAPIC
1258          * Put that IOAPIC in virtual wire mode
1259          * so legacy interrupts can be delivered.
1260          */
1261         if (ioapic_i8259.pin != -1) {
1262                 struct IO_APIC_route_entry entry;
1263
1264                 memset(&entry, 0, sizeof(entry));
1265                 entry.mask            = 0; /* Enabled */
1266                 entry.trigger         = 0; /* Edge */
1267                 entry.irr             = 0;
1268                 entry.polarity        = 0; /* High */
1269                 entry.delivery_status = 0;
1270                 entry.dest_mode       = 0; /* Physical */
1271                 entry.delivery_mode   = dest_ExtINT; /* ExtInt */
1272                 entry.vector          = 0;
1273                 entry.dest.physical.physical_dest =
1274                                         GET_APIC_ID(apic_read(APIC_ID));
1275
1276                 /*
1277                  * Add it to the IO-APIC irq-routing table:
1278                  */
1279                 ioapic_write_entry(ioapic_i8259.apic, ioapic_i8259.pin, entry);
1280         }
1281
1282         disconnect_bsp_APIC(ioapic_i8259.pin != -1);
1283 }
1284
1285 /*
1286  * There is a nasty bug in some older SMP boards, their mptable lies
1287  * about the timer IRQ. We do the following to work around the situation:
1288  *
1289  *      - timer IRQ defaults to IO-APIC IRQ
1290  *      - if this function detects that timer IRQs are defunct, then we fall
1291  *        back to ISA timer IRQs
1292  */
1293 static int __init timer_irq_works(void)
1294 {
1295         unsigned long t1 = jiffies;
1296
1297         local_irq_enable();
1298         /* Let ten ticks pass... */
1299         mdelay((10 * 1000) / HZ);
1300
1301         /*
1302          * Expect a few ticks at least, to be sure some possible
1303          * glue logic does not lock up after one or two first
1304          * ticks in a non-ExtINT mode.  Also the local APIC
1305          * might have cached one ExtINT interrupt.  Finally, at
1306          * least one tick may be lost due to delays.
1307          */
1308
1309         /* jiffies wrap? */
1310         if (jiffies - t1 > 4)
1311                 return 1;
1312         return 0;
1313 }
1314
1315 /*
1316  * In the SMP+IOAPIC case it might happen that there are an unspecified
1317  * number of pending IRQ events unhandled. These cases are very rare,
1318  * so we 'resend' these IRQs via IPIs, to the same CPU. It's much
1319  * better to do it this way as thus we do not have to be aware of
1320  * 'pending' interrupts in the IRQ path, except at this point.
1321  */
1322 /*
1323  * Edge triggered needs to resend any interrupt
1324  * that was delayed but this is now handled in the device
1325  * independent code.
1326  */
1327
1328 /*
1329  * Starting up a edge-triggered IO-APIC interrupt is
1330  * nasty - we need to make sure that we get the edge.
1331  * If it is already asserted for some reason, we need
1332  * return 1 to indicate that is was pending.
1333  *
1334  * This is not complete - we should be able to fake
1335  * an edge even if it isn't on the 8259A...
1336  */
1337
1338 static unsigned int startup_edge_ioapic_irq(unsigned int irq)
1339 {
1340         int was_pending = 0;
1341         unsigned long flags;
1342
1343         spin_lock_irqsave(&ioapic_lock, flags);
1344         if (irq < 16) {
1345                 disable_8259A_irq(irq);
1346                 if (i8259A_irq_pending(irq))
1347                         was_pending = 1;
1348         }
1349         __unmask_IO_APIC_irq(irq);
1350         spin_unlock_irqrestore(&ioapic_lock, flags);
1351
1352         return was_pending;
1353 }
1354
1355 /*
1356  * Once we have recorded IRQ_PENDING already, we can mask the
1357  * interrupt for real. This prevents IRQ storms from unhandled
1358  * devices.
1359  */
1360 static void ack_edge_ioapic_irq(unsigned int irq)
1361 {
1362         move_irq(irq);
1363         if ((irq_desc[irq].status & (IRQ_PENDING | IRQ_DISABLED))
1364                                         == (IRQ_PENDING | IRQ_DISABLED))
1365                 mask_IO_APIC_irq(irq);
1366         ack_APIC_irq();
1367 }
1368
1369 /*
1370  * Level triggered interrupts can just be masked,
1371  * and shutting down and starting up the interrupt
1372  * is the same as enabling and disabling them -- except
1373  * with a startup need to return a "was pending" value.
1374  *
1375  * Level triggered interrupts are special because we
1376  * do not touch any IO-APIC register while handling
1377  * them. We ack the APIC in the end-IRQ handler, not
1378  * in the start-IRQ-handler. Protection against reentrance
1379  * from the same interrupt is still provided, both by the
1380  * generic IRQ layer and by the fact that an unacked local
1381  * APIC does not accept IRQs.
1382  */
1383 static unsigned int startup_level_ioapic_irq (unsigned int irq)
1384 {
1385         unmask_IO_APIC_irq(irq);
1386
1387         return 0; /* don't check for pending */
1388 }
1389
1390 static void end_level_ioapic_irq (unsigned int irq)
1391 {
1392         move_irq(irq);
1393         ack_APIC_irq();
1394 }
1395
1396 #ifdef CONFIG_PCI_MSI
1397 static unsigned int startup_edge_ioapic_vector(unsigned int vector)
1398 {
1399         int irq = vector_to_irq(vector);
1400
1401         return startup_edge_ioapic_irq(irq);
1402 }
1403
1404 static void ack_edge_ioapic_vector(unsigned int vector)
1405 {
1406         int irq = vector_to_irq(vector);
1407
1408         move_native_irq(vector);
1409         ack_edge_ioapic_irq(irq);
1410 }
1411
1412 static unsigned int startup_level_ioapic_vector (unsigned int vector)
1413 {
1414         int irq = vector_to_irq(vector);
1415
1416         return startup_level_ioapic_irq (irq);
1417 }
1418
1419 static void end_level_ioapic_vector (unsigned int vector)
1420 {
1421         int irq = vector_to_irq(vector);
1422
1423         move_native_irq(vector);
1424         end_level_ioapic_irq(irq);
1425 }
1426
1427 static void mask_IO_APIC_vector (unsigned int vector)
1428 {
1429         int irq = vector_to_irq(vector);
1430
1431         mask_IO_APIC_irq(irq);
1432 }
1433
1434 static void unmask_IO_APIC_vector (unsigned int vector)
1435 {
1436         int irq = vector_to_irq(vector);
1437
1438         unmask_IO_APIC_irq(irq);
1439 }
1440
1441 #ifdef CONFIG_SMP
1442 static void set_ioapic_affinity_vector (unsigned int vector,
1443                                         cpumask_t cpu_mask)
1444 {
1445         int irq = vector_to_irq(vector);
1446
1447         set_native_irq_info(vector, cpu_mask);
1448         set_ioapic_affinity_irq(irq, cpu_mask);
1449 }
1450 #endif // CONFIG_SMP
1451 #endif // CONFIG_PCI_MSI
1452
1453 static int ioapic_retrigger(unsigned int irq)
1454 {
1455         send_IPI_self(IO_APIC_VECTOR(irq));
1456
1457         return 1;
1458 }
1459
1460 /*
1461  * Level and edge triggered IO-APIC interrupts need different handling,
1462  * so we use two separate IRQ descriptors. Edge triggered IRQs can be
1463  * handled with the level-triggered descriptor, but that one has slightly
1464  * more overhead. Level-triggered interrupts cannot be handled with the
1465  * edge-triggered handler, without risking IRQ storms and other ugly
1466  * races.
1467  */
1468
1469 static struct hw_interrupt_type ioapic_edge_type __read_mostly = {
1470         .typename = "IO-APIC-edge",
1471         .startup        = startup_edge_ioapic,
1472         .shutdown       = shutdown_edge_ioapic,
1473         .enable         = enable_edge_ioapic,
1474         .disable        = disable_edge_ioapic,
1475         .ack            = ack_edge_ioapic,
1476         .end            = end_edge_ioapic,
1477 #ifdef CONFIG_SMP
1478         .set_affinity = set_ioapic_affinity,
1479 #endif
1480         .retrigger      = ioapic_retrigger,
1481 };
1482
1483 static struct hw_interrupt_type ioapic_level_type __read_mostly = {
1484         .typename = "IO-APIC-level",
1485         .startup        = startup_level_ioapic,
1486         .shutdown       = shutdown_level_ioapic,
1487         .enable         = enable_level_ioapic,
1488         .disable        = disable_level_ioapic,
1489         .ack            = mask_and_ack_level_ioapic,
1490         .end            = end_level_ioapic,
1491 #ifdef CONFIG_SMP
1492         .set_affinity = set_ioapic_affinity,
1493 #endif
1494         .retrigger      = ioapic_retrigger,
1495 };
1496
1497 static inline void init_IO_APIC_traps(void)
1498 {
1499         int irq;
1500
1501         /*
1502          * NOTE! The local APIC isn't very good at handling
1503          * multiple interrupts at the same interrupt level.
1504          * As the interrupt level is determined by taking the
1505          * vector number and shifting that right by 4, we
1506          * want to spread these out a bit so that they don't
1507          * all fall in the same interrupt level.
1508          *
1509          * Also, we've got to be careful not to trash gate
1510          * 0x80, because int 0x80 is hm, kind of importantish. ;)
1511          */
1512         for (irq = 0; irq < NR_IRQS ; irq++) {
1513                 int tmp = irq;
1514                 if (use_pci_vector()) {
1515                         if (!platform_legacy_irq(tmp))
1516                                 if ((tmp = vector_to_irq(tmp)) == -1)
1517                                         continue;
1518                 }
1519                 if (IO_APIC_IRQ(tmp) && !IO_APIC_VECTOR(tmp)) {
1520                         /*
1521                          * Hmm.. We don't have an entry for this,
1522                          * so default to an old-fashioned 8259
1523                          * interrupt if we can..
1524                          */
1525                         if (irq < 16)
1526                                 make_8259A_irq(irq);
1527                         else
1528                                 /* Strange. Oh, well.. */
1529                                 irq_desc[irq].chip = &no_irq_type;
1530                 }
1531         }
1532 }
1533
1534 static void enable_lapic_irq (unsigned int irq)
1535 {
1536         unsigned long v;
1537
1538         v = apic_read(APIC_LVT0);
1539         apic_write(APIC_LVT0, v & ~APIC_LVT_MASKED);
1540 }
1541
1542 static void disable_lapic_irq (unsigned int irq)
1543 {
1544         unsigned long v;
1545
1546         v = apic_read(APIC_LVT0);
1547         apic_write(APIC_LVT0, v | APIC_LVT_MASKED);
1548 }
1549
1550 static void ack_lapic_irq (unsigned int irq)
1551 {
1552         ack_APIC_irq();
1553 }
1554
1555 static void end_lapic_irq (unsigned int i) { /* nothing */ }
1556
1557 static struct hw_interrupt_type lapic_irq_type __read_mostly = {
1558         .typename = "local-APIC-edge",
1559         .startup = NULL, /* startup_irq() not used for IRQ0 */
1560         .shutdown = NULL, /* shutdown_irq() not used for IRQ0 */
1561         .enable = enable_lapic_irq,
1562         .disable = disable_lapic_irq,
1563         .ack = ack_lapic_irq,
1564         .end = end_lapic_irq,
1565 };
1566
1567 static void setup_nmi (void)
1568 {
1569         /*
1570          * Dirty trick to enable the NMI watchdog ...
1571          * We put the 8259A master into AEOI mode and
1572          * unmask on all local APICs LVT0 as NMI.
1573          *
1574          * The idea to use the 8259A in AEOI mode ('8259A Virtual Wire')
1575          * is from Maciej W. Rozycki - so we do not have to EOI from
1576          * the NMI handler or the timer interrupt.
1577          */
1578         printk(KERN_INFO "activating NMI Watchdog ...");
1579
1580         enable_NMI_through_LVT0(NULL);
1581
1582         printk(" done.\n");
1583 }
1584
1585 /*
1586  * This looks a bit hackish but it's about the only one way of sending
1587  * a few INTA cycles to 8259As and any associated glue logic.  ICR does
1588  * not support the ExtINT mode, unfortunately.  We need to send these
1589  * cycles as some i82489DX-based boards have glue logic that keeps the
1590  * 8259A interrupt line asserted until INTA.  --macro
1591  */
1592 static inline void unlock_ExtINT_logic(void)
1593 {
1594         int apic, pin, i;
1595         struct IO_APIC_route_entry entry0, entry1;
1596         unsigned char save_control, save_freq_select;
1597         unsigned long flags;
1598
1599         pin  = find_isa_irq_pin(8, mp_INT);
1600         apic = find_isa_irq_apic(8, mp_INT);
1601         if (pin == -1)
1602                 return;
1603
1604         spin_lock_irqsave(&ioapic_lock, flags);
1605         *(((int *)&entry0) + 1) = io_apic_read(apic, 0x11 + 2 * pin);
1606         *(((int *)&entry0) + 0) = io_apic_read(apic, 0x10 + 2 * pin);
1607         spin_unlock_irqrestore(&ioapic_lock, flags);
1608         clear_IO_APIC_pin(apic, pin);
1609
1610         memset(&entry1, 0, sizeof(entry1));
1611
1612         entry1.dest_mode = 0;                   /* physical delivery */
1613         entry1.mask = 0;                        /* unmask IRQ now */
1614         entry1.dest.physical.physical_dest = hard_smp_processor_id();
1615         entry1.delivery_mode = dest_ExtINT;
1616         entry1.polarity = entry0.polarity;
1617         entry1.trigger = 0;
1618         entry1.vector = 0;
1619
1620         spin_lock_irqsave(&ioapic_lock, flags);
1621         io_apic_write(apic, 0x11 + 2 * pin, *(((int *)&entry1) + 1));
1622         io_apic_write(apic, 0x10 + 2 * pin, *(((int *)&entry1) + 0));
1623         spin_unlock_irqrestore(&ioapic_lock, flags);
1624
1625         save_control = CMOS_READ(RTC_CONTROL);
1626         save_freq_select = CMOS_READ(RTC_FREQ_SELECT);
1627         CMOS_WRITE((save_freq_select & ~RTC_RATE_SELECT) | 0x6,
1628                    RTC_FREQ_SELECT);
1629         CMOS_WRITE(save_control | RTC_PIE, RTC_CONTROL);
1630
1631         i = 100;
1632         while (i-- > 0) {
1633                 mdelay(10);
1634                 if ((CMOS_READ(RTC_INTR_FLAGS) & RTC_PF) == RTC_PF)
1635                         i -= 10;
1636         }
1637
1638         CMOS_WRITE(save_control, RTC_CONTROL);
1639         CMOS_WRITE(save_freq_select, RTC_FREQ_SELECT);
1640         clear_IO_APIC_pin(apic, pin);
1641
1642         spin_lock_irqsave(&ioapic_lock, flags);
1643         io_apic_write(apic, 0x11 + 2 * pin, *(((int *)&entry0) + 1));
1644         io_apic_write(apic, 0x10 + 2 * pin, *(((int *)&entry0) + 0));
1645         spin_unlock_irqrestore(&ioapic_lock, flags);
1646 }
1647
1648 int timer_uses_ioapic_pin_0;
1649
1650 /*
1651  * This code may look a bit paranoid, but it's supposed to cooperate with
1652  * a wide range of boards and BIOS bugs.  Fortunately only the timer IRQ
1653  * is so screwy.  Thanks to Brian Perkins for testing/hacking this beast
1654  * fanatically on his truly buggy board.
1655  *
1656  * FIXME: really need to revamp this for modern platforms only.
1657  */
1658 static inline void check_timer(void)
1659 {
1660         int apic1, pin1, apic2, pin2;
1661         int vector;
1662
1663         /*
1664          * get/set the timer IRQ vector:
1665          */
1666         disable_8259A_irq(0);
1667         vector = assign_irq_vector(0);
1668         set_intr_gate(vector, interrupt[0]);
1669
1670         /*
1671          * Subtle, code in do_timer_interrupt() expects an AEOI
1672          * mode for the 8259A whenever interrupts are routed
1673          * through I/O APICs.  Also IRQ0 has to be enabled in
1674          * the 8259A which implies the virtual wire has to be
1675          * disabled in the local APIC.
1676          */
1677         apic_write(APIC_LVT0, APIC_LVT_MASKED | APIC_DM_EXTINT);
1678         init_8259A(1);
1679         if (timer_over_8254 > 0)
1680                 enable_8259A_irq(0);
1681
1682         pin1  = find_isa_irq_pin(0, mp_INT);
1683         apic1 = find_isa_irq_apic(0, mp_INT);
1684         pin2  = ioapic_i8259.pin;
1685         apic2 = ioapic_i8259.apic;
1686
1687         if (pin1 == 0)
1688                 timer_uses_ioapic_pin_0 = 1;
1689
1690         apic_printk(APIC_VERBOSE,KERN_INFO "..TIMER: vector=0x%02X apic1=%d pin1=%d apic2=%d pin2=%d\n",
1691                 vector, apic1, pin1, apic2, pin2);
1692
1693         if (pin1 != -1) {
1694                 /*
1695                  * Ok, does IRQ0 through the IOAPIC work?
1696                  */
1697                 unmask_IO_APIC_irq(0);
1698                 if (!no_timer_check && timer_irq_works()) {
1699                         nmi_watchdog_default();
1700                         if (nmi_watchdog == NMI_IO_APIC) {
1701                                 disable_8259A_irq(0);
1702                                 setup_nmi();
1703                                 enable_8259A_irq(0);
1704                         }
1705                         if (disable_timer_pin_1 > 0)
1706                                 clear_IO_APIC_pin(0, pin1);
1707                         return;
1708                 }
1709                 clear_IO_APIC_pin(apic1, pin1);
1710                 apic_printk(APIC_QUIET,KERN_ERR "..MP-BIOS bug: 8254 timer not "
1711                                 "connected to IO-APIC\n");
1712         }
1713
1714         apic_printk(APIC_VERBOSE,KERN_INFO "...trying to set up timer (IRQ0) "
1715                                 "through the 8259A ... ");
1716         if (pin2 != -1) {
1717                 apic_printk(APIC_VERBOSE,"\n..... (found apic %d pin %d) ...",
1718                         apic2, pin2);
1719                 /*
1720                  * legacy devices should be connected to IO APIC #0
1721                  */
1722                 setup_ExtINT_IRQ0_pin(apic2, pin2, vector);
1723                 if (timer_irq_works()) {
1724                         apic_printk(APIC_VERBOSE," works.\n");
1725                         nmi_watchdog_default();
1726                         if (nmi_watchdog == NMI_IO_APIC) {
1727                                 setup_nmi();
1728                         }
1729                         return;
1730                 }
1731                 /*
1732                  * Cleanup, just in case ...
1733                  */
1734                 clear_IO_APIC_pin(apic2, pin2);
1735         }
1736         apic_printk(APIC_VERBOSE," failed.\n");
1737
1738         if (nmi_watchdog == NMI_IO_APIC) {
1739                 printk(KERN_WARNING "timer doesn't work through the IO-APIC - disabling NMI Watchdog!\n");
1740                 nmi_watchdog = 0;
1741         }
1742
1743         apic_printk(APIC_VERBOSE, KERN_INFO "...trying to set up timer as Virtual Wire IRQ...");
1744
1745         disable_8259A_irq(0);
1746         irq_desc[0].chip = &lapic_irq_type;
1747         apic_write(APIC_LVT0, APIC_DM_FIXED | vector);  /* Fixed mode */
1748         enable_8259A_irq(0);
1749
1750         if (timer_irq_works()) {
1751                 apic_printk(APIC_VERBOSE," works.\n");
1752                 return;
1753         }
1754         apic_write(APIC_LVT0, APIC_LVT_MASKED | APIC_DM_FIXED | vector);
1755         apic_printk(APIC_VERBOSE," failed.\n");
1756
1757         apic_printk(APIC_VERBOSE, KERN_INFO "...trying to set up timer as ExtINT IRQ...");
1758
1759         init_8259A(0);
1760         make_8259A_irq(0);
1761         apic_write(APIC_LVT0, APIC_DM_EXTINT);
1762
1763         unlock_ExtINT_logic();
1764
1765         if (timer_irq_works()) {
1766                 apic_printk(APIC_VERBOSE," works.\n");
1767                 return;
1768         }
1769         apic_printk(APIC_VERBOSE," failed :(.\n");
1770         panic("IO-APIC + timer doesn't work! Try using the 'noapic' kernel parameter\n");
1771 }
1772
1773 static int __init notimercheck(char *s)
1774 {
1775         no_timer_check = 1;
1776         return 1;
1777 }
1778 __setup("no_timer_check", notimercheck);
1779
1780 /*
1781  *
1782  * IRQ's that are handled by the PIC in the MPS IOAPIC case.
1783  * - IRQ2 is the cascade IRQ, and cannot be a io-apic IRQ.
1784  *   Linux doesn't really care, as it's not actually used
1785  *   for any interrupt handling anyway.
1786  */
1787 #define PIC_IRQS        (1<<2)
1788
1789 void __init setup_IO_APIC(void)
1790 {
1791         enable_IO_APIC();
1792
1793         if (acpi_ioapic)
1794                 io_apic_irqs = ~0;      /* all IRQs go through IOAPIC */
1795         else
1796                 io_apic_irqs = ~PIC_IRQS;
1797
1798         apic_printk(APIC_VERBOSE, "ENABLING IO-APIC IRQs\n");
1799
1800         sync_Arb_IDs();
1801         setup_IO_APIC_irqs();
1802         init_IO_APIC_traps();
1803         check_timer();
1804         if (!acpi_ioapic)
1805                 print_IO_APIC();
1806 }
1807
1808 struct sysfs_ioapic_data {
1809         struct sys_device dev;
1810         struct IO_APIC_route_entry entry[0];
1811 };
1812 static struct sysfs_ioapic_data * mp_ioapic_data[MAX_IO_APICS];
1813
1814 static int ioapic_suspend(struct sys_device *dev, pm_message_t state)
1815 {
1816         struct IO_APIC_route_entry *entry;
1817         struct sysfs_ioapic_data *data;
1818         int i;
1819
1820         data = container_of(dev, struct sysfs_ioapic_data, dev);
1821         entry = data->entry;
1822         for (i = 0; i < nr_ioapic_registers[dev->id]; i ++, entry ++ )
1823                 *entry = ioapic_read_entry(dev->id, i);
1824
1825         return 0;
1826 }
1827
1828 static int ioapic_resume(struct sys_device *dev)
1829 {
1830         struct IO_APIC_route_entry *entry;
1831         struct sysfs_ioapic_data *data;
1832         unsigned long flags;
1833         union IO_APIC_reg_00 reg_00;
1834         int i;
1835
1836         data = container_of(dev, struct sysfs_ioapic_data, dev);
1837         entry = data->entry;
1838
1839         spin_lock_irqsave(&ioapic_lock, flags);
1840         reg_00.raw = io_apic_read(dev->id, 0);
1841         if (reg_00.bits.ID != mp_ioapics[dev->id].mpc_apicid) {
1842                 reg_00.bits.ID = mp_ioapics[dev->id].mpc_apicid;
1843                 io_apic_write(dev->id, 0, reg_00.raw);
1844         }
1845         spin_unlock_irqrestore(&ioapic_lock, flags);
1846         for (i = 0; i < nr_ioapic_registers[dev->id]; i++)
1847                 ioapic_write_entry(dev->id, i, entry[i]);
1848
1849         return 0;
1850 }
1851
1852 static struct sysdev_class ioapic_sysdev_class = {
1853         set_kset_name("ioapic"),
1854         .suspend = ioapic_suspend,
1855         .resume = ioapic_resume,
1856 };
1857
1858 static int __init ioapic_init_sysfs(void)
1859 {
1860         struct sys_device * dev;
1861         int i, size, error = 0;
1862
1863         error = sysdev_class_register(&ioapic_sysdev_class);
1864         if (error)
1865                 return error;
1866
1867         for (i = 0; i < nr_ioapics; i++ ) {
1868                 size = sizeof(struct sys_device) + nr_ioapic_registers[i]
1869                         * sizeof(struct IO_APIC_route_entry);
1870                 mp_ioapic_data[i] = kmalloc(size, GFP_KERNEL);
1871                 if (!mp_ioapic_data[i]) {
1872                         printk(KERN_ERR "Can't suspend/resume IOAPIC %d\n", i);
1873                         continue;
1874                 }
1875                 memset(mp_ioapic_data[i], 0, size);
1876                 dev = &mp_ioapic_data[i]->dev;
1877                 dev->id = i;
1878                 dev->cls = &ioapic_sysdev_class;
1879                 error = sysdev_register(dev);
1880                 if (error) {
1881                         kfree(mp_ioapic_data[i]);
1882                         mp_ioapic_data[i] = NULL;
1883                         printk(KERN_ERR "Can't suspend/resume IOAPIC %d\n", i);
1884                         continue;
1885                 }
1886         }
1887
1888         return 0;
1889 }
1890
1891 device_initcall(ioapic_init_sysfs);
1892
1893 /* --------------------------------------------------------------------------
1894                           ACPI-based IOAPIC Configuration
1895    -------------------------------------------------------------------------- */
1896
1897 #ifdef CONFIG_ACPI
1898
1899 #define IO_APIC_MAX_ID          0xFE
1900
1901 int __init io_apic_get_version (int ioapic)
1902 {
1903         union IO_APIC_reg_01    reg_01;
1904         unsigned long flags;
1905
1906         spin_lock_irqsave(&ioapic_lock, flags);
1907         reg_01.raw = io_apic_read(ioapic, 1);
1908         spin_unlock_irqrestore(&ioapic_lock, flags);
1909
1910         return reg_01.bits.version;
1911 }
1912
1913
1914 int __init io_apic_get_redir_entries (int ioapic)
1915 {
1916         union IO_APIC_reg_01    reg_01;
1917         unsigned long flags;
1918
1919         spin_lock_irqsave(&ioapic_lock, flags);
1920         reg_01.raw = io_apic_read(ioapic, 1);
1921         spin_unlock_irqrestore(&ioapic_lock, flags);
1922
1923         return reg_01.bits.entries;
1924 }
1925
1926
1927 int io_apic_set_pci_routing (int ioapic, int pin, int irq, int triggering, int polarity)
1928 {
1929         struct IO_APIC_route_entry entry;
1930         unsigned long flags;
1931
1932         if (!IO_APIC_IRQ(irq)) {
1933                 apic_printk(APIC_QUIET,KERN_ERR "IOAPIC[%d]: Invalid reference to IRQ 0\n",
1934                         ioapic);
1935                 return -EINVAL;
1936         }
1937
1938         /*
1939          * Generate a PCI IRQ routing entry and program the IOAPIC accordingly.
1940          * Note that we mask (disable) IRQs now -- these get enabled when the
1941          * corresponding device driver registers for this IRQ.
1942          */
1943
1944         memset(&entry,0,sizeof(entry));
1945
1946         entry.delivery_mode = INT_DELIVERY_MODE;
1947         entry.dest_mode = INT_DEST_MODE;
1948         entry.dest.logical.logical_dest = cpu_mask_to_apicid(TARGET_CPUS);
1949         entry.trigger = triggering;
1950         entry.polarity = polarity;
1951         entry.mask = 1;                                  /* Disabled (masked) */
1952
1953         irq = gsi_irq_sharing(irq);
1954         /*
1955          * IRQs < 16 are already in the irq_2_pin[] map
1956          */
1957         if (irq >= 16)
1958                 add_pin_to_irq(irq, ioapic, pin);
1959
1960         entry.vector = assign_irq_vector(irq);
1961
1962         apic_printk(APIC_VERBOSE,KERN_DEBUG "IOAPIC[%d]: Set PCI routing entry (%d-%d -> 0x%x -> "
1963                 "IRQ %d Mode:%i Active:%i)\n", ioapic,
1964                mp_ioapics[ioapic].mpc_apicid, pin, entry.vector, irq,
1965                triggering, polarity);
1966
1967         ioapic_register_intr(irq, entry.vector, triggering);
1968
1969         if (!ioapic && (irq < 16))
1970                 disable_8259A_irq(irq);
1971
1972         ioapic_write_entry(ioapic, pin, entry);
1973
1974         spin_lock_irqsave(&ioapic_lock, flags);
1975         set_native_irq_info(use_pci_vector() ? entry.vector : irq, TARGET_CPUS);
1976         spin_unlock_irqrestore(&ioapic_lock, flags);
1977
1978         return 0;
1979 }
1980
1981 #endif /* CONFIG_ACPI */
1982
1983
1984 /*
1985  * This function currently is only a helper for the i386 smp boot process where
1986  * we need to reprogram the ioredtbls to cater for the cpus which have come online
1987  * so mask in all cases should simply be TARGET_CPUS
1988  */
1989 #ifdef CONFIG_SMP
1990 void __init setup_ioapic_dest(void)
1991 {
1992         int pin, ioapic, irq, irq_entry;
1993
1994         if (skip_ioapic_setup == 1)
1995                 return;
1996
1997         for (ioapic = 0; ioapic < nr_ioapics; ioapic++) {
1998                 for (pin = 0; pin < nr_ioapic_registers[ioapic]; pin++) {
1999                         irq_entry = find_irq_entry(ioapic, pin, mp_INT);
2000                         if (irq_entry == -1)
2001                                 continue;
2002                         irq = pin_2_irq(irq_entry, ioapic, pin);
2003                         set_ioapic_affinity_irq(irq, TARGET_CPUS);
2004                 }
2005
2006         }
2007 }
2008 #endif