err.no Git - linux-2.6/blob - arch/x86_64/kernel/io_apic.c

   1 /*
   2  *      Intel IO-APIC support for multi-Pentium hosts.
   3  *
   4  *      Copyright (C) 1997, 1998, 1999, 2000 Ingo Molnar, Hajnalka Szabo
   5  *
   6  *      Many thanks to Stig Venaas for trying out countless experimental
   7  *      patches and reporting/debugging problems patiently!
   8  *
   9  *      (c) 1999, Multiple IO-APIC support, developed by
  10  *      Ken-ichi Yaku <yaku@css1.kbnes.nec.co.jp> and
  11  *      Hidemi Kishimoto <kisimoto@css1.kbnes.nec.co.jp>,
  12  *      further tested and cleaned up by Zach Brown <zab@redhat.com>
  13  *      and Ingo Molnar <mingo@redhat.com>
  14  *
  15  *      Fixes
  16  *      Maciej W. Rozycki       :       Bits for genuine 82489DX APICs;
  17  *                                      thanks to Eric Gilmore
  18  *                                      and Rolf G. Tews
  19  *                                      for testing these extensively
  20  *      Paul Diefenbaugh        :       Added full ACPI support
  21  */
  22
  23 #include <linux/mm.h>
  24 #include <linux/interrupt.h>
  25 #include <linux/init.h>
  26 #include <linux/delay.h>
  27 #include <linux/sched.h>
  28 #include <linux/smp_lock.h>
  29 #include <linux/mc146818rtc.h>
  30 #include <linux/acpi.h>
  31 #include <linux/sysdev.h>
  32 #ifdef CONFIG_ACPI
  33 #include <acpi/acpi_bus.h>
  34 #endif
  35
  36 #include <asm/io.h>
  37 #include <asm/smp.h>
  38 #include <asm/desc.h>
  39 #include <asm/proto.h>
  40 #include <asm/mach_apic.h>
  41 #include <asm/acpi.h>
  42 #include <asm/dma.h>
  43 #include <asm/nmi.h>
  44
  45 #define __apicdebuginit  __init
  46
  47 int sis_apic_bug; /* not actually supported, dummy for compile */
  48
  49 static int no_timer_check;
  50
  51 int disable_timer_pin_1 __initdata;
  52
  53 int timer_over_8254 __initdata = 0;
  54
  55 /* Where if anywhere is the i8259 connect in external int mode */
  56 static struct { int pin, apic; } ioapic_i8259 = { -1, -1 };
  57
  58 static DEFINE_SPINLOCK(ioapic_lock);
  59 static DEFINE_SPINLOCK(vector_lock);
  60
  61 /*
  62  * # of IRQ routing registers
  63  */
  64 int nr_ioapic_registers[MAX_IO_APICS];
  65
  66 /*
  67  * Rough estimation of how many shared IRQs there are, can
  68  * be changed anytime.
  69  */
  70 #define MAX_PLUS_SHARED_IRQS NR_IRQ_VECTORS
  71 #define PIN_MAP_SIZE (MAX_PLUS_SHARED_IRQS + NR_IRQS)
  72
  73 /*
  74  * This is performance-critical, we want to do it O(1)
  75  *
  76  * the indexing order of this array favors 1:1 mappings
  77  * between pins and IRQs.
  78  */
  79
  80 static struct irq_pin_list {
  81         short apic, pin, next;
  82 } irq_2_pin[PIN_MAP_SIZE];
  83
  84 int vector_irq[NR_VECTORS] __read_mostly = { [0 ... NR_VECTORS - 1] = -1};
  85 #ifdef CONFIG_PCI_MSI
  86 #define vector_to_irq(vector)   \
  87         (platform_legacy_irq(vector) ? vector : vector_irq[vector])
  88 #else
  89 #define vector_to_irq(vector)   (vector)
  90 #endif
  91
  92 #define __DO_ACTION(R, ACTION, FINAL)                                   \
  93                                                                         \
  94 {                                                                       \
  95         int pin;                                                        \
  96         struct irq_pin_list *entry = irq_2_pin + irq;                   \
  97                                                                         \
  98         BUG_ON(irq >= NR_IRQS);                                         \
  99         for (;;) {                                                      \
 100                 unsigned int reg;                                       \
 101                 pin = entry->pin;                                       \
 102                 if (pin == -1)                                          \
 103                         break;                                          \
 104                 reg = io_apic_read(entry->apic, 0x10 + R + pin*2);      \
 105                 reg ACTION;                                             \
 106                 io_apic_modify(entry->apic, reg);                       \
 107                 if (!entry->next)                                       \
 108                         break;                                          \
 109                 entry = irq_2_pin + entry->next;                        \
 110         }                                                               \
 111         FINAL;                                                          \
 112 }
 113
 114 union entry_union {
 115         struct { u32 w1, w2; };
 116         struct IO_APIC_route_entry entry;
 117 };
 118
 119 static struct IO_APIC_route_entry ioapic_read_entry(int apic, int pin)
 120 {
 121         union entry_union eu;
 122         unsigned long flags;
 123         spin_lock_irqsave(&ioapic_lock, flags);
 124         eu.w1 = io_apic_read(apic, 0x10 + 2 * pin);
 125         eu.w2 = io_apic_read(apic, 0x11 + 2 * pin);
 126         spin_unlock_irqrestore(&ioapic_lock, flags);
 127         return eu.entry;
 128 }
 129
 130 static void ioapic_write_entry(int apic, int pin, struct IO_APIC_route_entry e)
 131 {
 132         unsigned long flags;
 133         union entry_union eu;
 134         eu.entry = e;
 135         spin_lock_irqsave(&ioapic_lock, flags);
 136         io_apic_write(apic, 0x10 + 2*pin, eu.w1);
 137         io_apic_write(apic, 0x11 + 2*pin, eu.w2);
 138         spin_unlock_irqrestore(&ioapic_lock, flags);
 139 }
 140
 141 #ifdef CONFIG_SMP
 142 static void set_ioapic_affinity_irq(unsigned int irq, cpumask_t mask)
 143 {
 144         unsigned long flags;
 145         unsigned int dest;
 146         cpumask_t tmp;
 147
 148         cpus_and(tmp, mask, cpu_online_map);
 149         if (cpus_empty(tmp))
 150                 tmp = TARGET_CPUS;
 151
 152         cpus_and(mask, tmp, CPU_MASK_ALL);
 153
 154         dest = cpu_mask_to_apicid(mask);
 155
 156         /*
 157          * Only the high 8 bits are valid.
 158          */
 159         dest = SET_APIC_LOGICAL_ID(dest);
 160
 161         spin_lock_irqsave(&ioapic_lock, flags);
 162         __DO_ACTION(1, = dest, )
 163         set_irq_info(irq, mask);
 164         spin_unlock_irqrestore(&ioapic_lock, flags);
 165 }
 166 #endif
 167
 168 static u8 gsi_2_irq[NR_IRQ_VECTORS] = { [0 ... NR_IRQ_VECTORS-1] = 0xFF };
 169
 170 /*
 171  * The common case is 1:1 IRQ<->pin mappings. Sometimes there are
 172  * shared ISA-space IRQs, so we have to support them. We are super
 173  * fast in the common case, and fast for shared ISA-space IRQs.
 174  */
 175 static void add_pin_to_irq(unsigned int irq, int apic, int pin)
 176 {
 177         static int first_free_entry = NR_IRQS;
 178         struct irq_pin_list *entry = irq_2_pin + irq;
 179
 180         BUG_ON(irq >= NR_IRQS);
 181         while (entry->next)
 182                 entry = irq_2_pin + entry->next;
 183
 184         if (entry->pin != -1) {
 185                 entry->next = first_free_entry;
 186                 entry = irq_2_pin + entry->next;
 187                 if (++first_free_entry >= PIN_MAP_SIZE)
 188                         panic("io_apic.c: ran out of irq_2_pin entries!");
 189         }
 190         entry->apic = apic;
 191         entry->pin = pin;
 192 }
 193
 194
 195 #define DO_ACTION(name,R,ACTION, FINAL)                                 \
 196                                                                         \
 197         static void name##_IO_APIC_irq (unsigned int irq)               \
 198         __DO_ACTION(R, ACTION, FINAL)
 199
 200 DO_ACTION( __mask,             0, |= 0x00010000, io_apic_sync(entry->apic) )
 201                                                 /* mask = 1 */
 202 DO_ACTION( __unmask,           0, &= 0xfffeffff, )
 203                                                 /* mask = 0 */
 204
 205 static void mask_IO_APIC_irq (unsigned int irq)
 206 {
 207         unsigned long flags;
 208
 209         spin_lock_irqsave(&ioapic_lock, flags);
 210         __mask_IO_APIC_irq(irq);
 211         spin_unlock_irqrestore(&ioapic_lock, flags);
 212 }
 213
 214 static void unmask_IO_APIC_irq (unsigned int irq)
 215 {
 216         unsigned long flags;
 217
 218         spin_lock_irqsave(&ioapic_lock, flags);
 219         __unmask_IO_APIC_irq(irq);
 220         spin_unlock_irqrestore(&ioapic_lock, flags);
 221 }
 222
 223 static void clear_IO_APIC_pin(unsigned int apic, unsigned int pin)
 224 {
 225         struct IO_APIC_route_entry entry;
 226
 227         /* Check delivery_mode to be sure we're not clearing an SMI pin */
 228         entry = ioapic_read_entry(apic, pin);
 229         if (entry.delivery_mode == dest_SMI)
 230                 return;
 231         /*
 232          * Disable it in the IO-APIC irq-routing table:
 233          */
 234         memset(&entry, 0, sizeof(entry));
 235         entry.mask = 1;
 236         ioapic_write_entry(apic, pin, entry);
 237 }
 238
 239 static void clear_IO_APIC (void)
 240 {
 241         int apic, pin;
 242
 243         for (apic = 0; apic < nr_ioapics; apic++)
 244                 for (pin = 0; pin < nr_ioapic_registers[apic]; pin++)
 245                         clear_IO_APIC_pin(apic, pin);
 246 }
 247
 248 int skip_ioapic_setup;
 249 int ioapic_force;
 250
 251 /* dummy parsing: see setup.c */
 252
 253 static int __init disable_ioapic_setup(char *str)
 254 {
 255         skip_ioapic_setup = 1;
 256         return 1;
 257 }
 258
 259 static int __init enable_ioapic_setup(char *str)
 260 {
 261         ioapic_force = 1;
 262         skip_ioapic_setup = 0;
 263         return 1;
 264 }
 265
 266 __setup("noapic", disable_ioapic_setup);
 267 __setup("apic", enable_ioapic_setup);
 268
 269 static int __init setup_disable_8254_timer(char *s)
 270 {
 271         timer_over_8254 = -1;
 272         return 1;
 273 }
 274 static int __init setup_enable_8254_timer(char *s)
 275 {
 276         timer_over_8254 = 2;
 277         return 1;
 278 }
 279
 280 __setup("disable_8254_timer", setup_disable_8254_timer);
 281 __setup("enable_8254_timer", setup_enable_8254_timer);
 282
 283
 284 /*
 285  * Find the IRQ entry number of a certain pin.
 286  */
 287 static int find_irq_entry(int apic, int pin, int type)
 288 {
 289         int i;
 290
 291         for (i = 0; i < mp_irq_entries; i++)
 292                 if (mp_irqs[i].mpc_irqtype == type &&
 293                     (mp_irqs[i].mpc_dstapic == mp_ioapics[apic].mpc_apicid ||
 294                      mp_irqs[i].mpc_dstapic == MP_APIC_ALL) &&
 295                     mp_irqs[i].mpc_dstirq == pin)
 296                         return i;
 297
 298         return -1;
 299 }
 300
 301 /*
 302  * Find the pin to which IRQ[irq] (ISA) is connected
 303  */
 304 static int __init find_isa_irq_pin(int irq, int type)
 305 {
 306         int i;
 307
 308         for (i = 0; i < mp_irq_entries; i++) {
 309                 int lbus = mp_irqs[i].mpc_srcbus;
 310
 311                 if (mp_bus_id_to_type[lbus] == MP_BUS_ISA &&
 312                     (mp_irqs[i].mpc_irqtype == type) &&
 313                     (mp_irqs[i].mpc_srcbusirq == irq))
 314
 315                         return mp_irqs[i].mpc_dstirq;
 316         }
 317         return -1;
 318 }
 319
 320 static int __init find_isa_irq_apic(int irq, int type)
 321 {
 322         int i;
 323
 324         for (i = 0; i < mp_irq_entries; i++) {
 325                 int lbus = mp_irqs[i].mpc_srcbus;
 326
 327                 if ((mp_bus_id_to_type[lbus] == MP_BUS_ISA) &&
 328                     (mp_irqs[i].mpc_irqtype == type) &&
 329                     (mp_irqs[i].mpc_srcbusirq == irq))
 330                         break;
 331         }
 332         if (i < mp_irq_entries) {
 333                 int apic;
 334                 for(apic = 0; apic < nr_ioapics; apic++) {
 335                         if (mp_ioapics[apic].mpc_apicid == mp_irqs[i].mpc_dstapic)
 336                                 return apic;
 337                 }
 338         }
 339
 340         return -1;
 341 }
 342
 343 /*
 344  * Find a specific PCI IRQ entry.
 345  * Not an __init, possibly needed by modules
 346  */
 347 static int pin_2_irq(int idx, int apic, int pin);
 348
 349 int IO_APIC_get_PCI_irq_vector(int bus, int slot, int pin)
 350 {
 351         int apic, i, best_guess = -1;
 352
 353         apic_printk(APIC_DEBUG, "querying PCI -> IRQ mapping bus:%d, slot:%d, pin:%d.\n",
 354                 bus, slot, pin);
 355         if (mp_bus_id_to_pci_bus[bus] == -1) {
 356                 apic_printk(APIC_VERBOSE, "PCI BIOS passed nonexistent PCI bus %d!\n", bus);
 357                 return -1;
 358         }
 359         for (i = 0; i < mp_irq_entries; i++) {
 360                 int lbus = mp_irqs[i].mpc_srcbus;
 361
 362                 for (apic = 0; apic < nr_ioapics; apic++)
 363                         if (mp_ioapics[apic].mpc_apicid == mp_irqs[i].mpc_dstapic ||
 364                             mp_irqs[i].mpc_dstapic == MP_APIC_ALL)
 365                                 break;
 366
 367                 if ((mp_bus_id_to_type[lbus] == MP_BUS_PCI) &&
 368                     !mp_irqs[i].mpc_irqtype &&
 369                     (bus == lbus) &&
 370                     (slot == ((mp_irqs[i].mpc_srcbusirq >> 2) & 0x1f))) {
 371                         int irq = pin_2_irq(i,apic,mp_irqs[i].mpc_dstirq);
 372
 373                         if (!(apic || IO_APIC_IRQ(irq)))
 374                                 continue;
 375
 376                         if (pin == (mp_irqs[i].mpc_srcbusirq & 3))
 377                                 return irq;
 378                         /*
 379                          * Use the first all-but-pin matching entry as a
 380                          * best-guess fuzzy result for broken mptables.
 381                          */
 382                         if (best_guess < 0)
 383                                 best_guess = irq;
 384                 }
 385         }
 386         BUG_ON(best_guess >= NR_IRQS);
 387         return best_guess;
 388 }
 389
 390 /* ISA interrupts are always polarity zero edge triggered,
 391  * when listed as conforming in the MP table. */
 392
 393 #define default_ISA_trigger(idx)        (0)
 394 #define default_ISA_polarity(idx)       (0)
 395
 396 /* PCI interrupts are always polarity one level triggered,
 397  * when listed as conforming in the MP table. */
 398
 399 #define default_PCI_trigger(idx)        (1)
 400 #define default_PCI_polarity(idx)       (1)
 401
 402 static int __init MPBIOS_polarity(int idx)
 403 {
 404         int bus = mp_irqs[idx].mpc_srcbus;
 405         int polarity;
 406
 407         /*
 408          * Determine IRQ line polarity (high active or low active):
 409          */
 410         switch (mp_irqs[idx].mpc_irqflag & 3)
 411         {
 412                 case 0: /* conforms, ie. bus-type dependent polarity */
 413                 {
 414                         switch (mp_bus_id_to_type[bus])
 415                         {
 416                                 case MP_BUS_ISA: /* ISA pin */
 417                                 {
 418                                         polarity = default_ISA_polarity(idx);
 419                                         break;
 420                                 }
 421                                 case MP_BUS_PCI: /* PCI pin */
 422                                 {
 423                                         polarity = default_PCI_polarity(idx);
 424                                         break;
 425                                 }
 426                                 default:
 427                                 {
 428                                         printk(KERN_WARNING "broken BIOS!!\n");
 429                                         polarity = 1;
 430                                         break;
 431                                 }
 432                         }
 433                         break;
 434                 }
 435                 case 1: /* high active */
 436                 {
 437                         polarity = 0;
 438                         break;
 439                 }
 440                 case 2: /* reserved */
 441                 {
 442                         printk(KERN_WARNING "broken BIOS!!\n");
 443                         polarity = 1;
 444                         break;
 445                 }
 446                 case 3: /* low active */
 447                 {
 448                         polarity = 1;
 449                         break;
 450                 }
 451                 default: /* invalid */
 452                 {
 453                         printk(KERN_WARNING "broken BIOS!!\n");
 454                         polarity = 1;
 455                         break;
 456                 }
 457         }
 458         return polarity;
 459 }
 460
 461 static int MPBIOS_trigger(int idx)
 462 {
 463         int bus = mp_irqs[idx].mpc_srcbus;
 464         int trigger;
 465
 466         /*
 467          * Determine IRQ trigger mode (edge or level sensitive):
 468          */
 469         switch ((mp_irqs[idx].mpc_irqflag>>2) & 3)
 470         {
 471                 case 0: /* conforms, ie. bus-type dependent */
 472                 {
 473                         switch (mp_bus_id_to_type[bus])
 474                         {
 475                                 case MP_BUS_ISA: /* ISA pin */
 476                                 {
 477                                         trigger = default_ISA_trigger(idx);
 478                                         break;
 479                                 }
 480                                 case MP_BUS_PCI: /* PCI pin */
 481                                 {
 482                                         trigger = default_PCI_trigger(idx);
 483                                         break;
 484                                 }
 485                                 default:
 486                                 {
 487                                         printk(KERN_WARNING "broken BIOS!!\n");
 488                                         trigger = 1;
 489                                         break;
 490                                 }
 491                         }
 492                         break;
 493                 }
 494                 case 1: /* edge */
 495                 {
 496                         trigger = 0;
 497                         break;
 498                 }
 499                 case 2: /* reserved */
 500                 {
 501                         printk(KERN_WARNING "broken BIOS!!\n");
 502                         trigger = 1;
 503                         break;
 504                 }
 505                 case 3: /* level */
 506                 {
 507                         trigger = 1;
 508                         break;
 509                 }
 510                 default: /* invalid */
 511                 {
 512                         printk(KERN_WARNING "broken BIOS!!\n");
 513                         trigger = 0;
 514                         break;
 515                 }
 516         }
 517         return trigger;
 518 }
 519
 520 static inline int irq_polarity(int idx)
 521 {
 522         return MPBIOS_polarity(idx);
 523 }
 524
 525 static inline int irq_trigger(int idx)
 526 {
 527         return MPBIOS_trigger(idx);
 528 }
 529
 530 static int next_irq = 16;
 531
 532 /*
 533  * gsi_irq_sharing -- Name overload!  "irq" can be either a legacy IRQ
 534  * in the range 0-15, a linux IRQ in the range 0-223, or a GSI number
 535  * from ACPI, which can reach 800 in large boxen.
 536  *
 537  * Compact the sparse GSI space into a sequential IRQ series and reuse
 538  * vectors if possible.
 539  */
 540 int gsi_irq_sharing(int gsi)
 541 {
 542         int i, tries, vector;
 543
 544         BUG_ON(gsi >= NR_IRQ_VECTORS);
 545
 546         if (platform_legacy_irq(gsi))
 547                 return gsi;
 548
 549         if (gsi_2_irq[gsi] != 0xFF)
 550                 return (int)gsi_2_irq[gsi];
 551
 552         tries = NR_IRQS;
 553   try_again:
 554         vector = assign_irq_vector(gsi);
 555
 556         /*
 557          * Sharing vectors means sharing IRQs, so scan irq_vectors for previous
 558          * use of vector and if found, return that IRQ.  However, we never want
 559          * to share legacy IRQs, which usually have a different trigger mode
 560          * than PCI.
 561          */
 562         for (i = 0; i < NR_IRQS; i++)
 563                 if (IO_APIC_VECTOR(i) == vector)
 564                         break;
 565         if (platform_legacy_irq(i)) {
 566                 if (--tries >= 0) {
 567                         IO_APIC_VECTOR(i) = 0;
 568                         goto try_again;
 569                 }
 570                 panic("gsi_irq_sharing: didn't find an IRQ using vector 0x%02X for GSI %d", vector, gsi);
 571         }
 572         if (i < NR_IRQS) {
 573                 gsi_2_irq[gsi] = i;
 574                 printk(KERN_INFO "GSI %d sharing vector 0x%02X and IRQ %d\n",
 575                                 gsi, vector, i);
 576                 return i;
 577         }
 578
 579         i = next_irq++;
 580         BUG_ON(i >= NR_IRQS);
 581         gsi_2_irq[gsi] = i;
 582         IO_APIC_VECTOR(i) = vector;
 583         printk(KERN_INFO "GSI %d assigned vector 0x%02X and IRQ %d\n",
 584                         gsi, vector, i);
 585         return i;
 586 }
 587
 588 static int pin_2_irq(int idx, int apic, int pin)
 589 {
 590         int irq, i;
 591         int bus = mp_irqs[idx].mpc_srcbus;
 592
 593         /*
 594          * Debugging check, we are in big trouble if this message pops up!
 595          */
 596         if (mp_irqs[idx].mpc_dstirq != pin)
 597                 printk(KERN_ERR "broken BIOS or MPTABLE parser, ayiee!!\n");
 598
 599         switch (mp_bus_id_to_type[bus])
 600         {
 601                 case MP_BUS_ISA: /* ISA pin */
 602                 {
 603                         irq = mp_irqs[idx].mpc_srcbusirq;
 604                         break;
 605                 }
 606                 case MP_BUS_PCI: /* PCI pin */
 607                 {
 608                         /*
 609                          * PCI IRQs are mapped in order
 610                          */
 611                         i = irq = 0;
 612                         while (i < apic)
 613                                 irq += nr_ioapic_registers[i++];
 614                         irq += pin;
 615                         irq = gsi_irq_sharing(irq);
 616                         break;
 617                 }
 618                 default:
 619                 {
 620                         printk(KERN_ERR "unknown bus type %d.\n",bus);
 621                         irq = 0;
 622                         break;
 623                 }
 624         }
 625         BUG_ON(irq >= NR_IRQS);
 626         return irq;
 627 }
 628
 629 static inline int IO_APIC_irq_trigger(int irq)
 630 {
 631         int apic, idx, pin;
 632
 633         for (apic = 0; apic < nr_ioapics; apic++) {
 634                 for (pin = 0; pin < nr_ioapic_registers[apic]; pin++) {
 635                         idx = find_irq_entry(apic,pin,mp_INT);
 636                         if ((idx != -1) && (irq == pin_2_irq(idx,apic,pin)))
 637                                 return irq_trigger(idx);
 638                 }
 639         }
 640         /*
 641          * nonexistent IRQs are edge default
 642          */
 643         return 0;
 644 }
 645
 646 /* irq_vectors is indexed by the sum of all RTEs in all I/O APICs. */
 647 u8 irq_vector[NR_IRQ_VECTORS] __read_mostly = { FIRST_DEVICE_VECTOR , 0 };
 648
 649 int assign_irq_vector(int irq)
 650 {
 651         static int current_vector = FIRST_DEVICE_VECTOR, offset = 0;
 652         unsigned long flags;
 653         int vector;
 654
 655         BUG_ON(irq != AUTO_ASSIGN && (unsigned)irq >= NR_IRQ_VECTORS);
 656
 657         spin_lock_irqsave(&vector_lock, flags);
 658
 659         if (irq != AUTO_ASSIGN && IO_APIC_VECTOR(irq) > 0) {
 660                 spin_unlock_irqrestore(&vector_lock, flags);
 661                 return IO_APIC_VECTOR(irq);
 662         }
 663 next:
 664         current_vector += 8;
 665         if (current_vector == IA32_SYSCALL_VECTOR)
 666                 goto next;
 667
 668         if (current_vector >= FIRST_SYSTEM_VECTOR) {
 669                 /* If we run out of vectors on large boxen, must share them. */
 670                 offset = (offset + 1) % 8;
 671                 current_vector = FIRST_DEVICE_VECTOR + offset;
 672         }
 673
 674         vector = current_vector;
 675         vector_irq[vector] = irq;
 676         if (irq != AUTO_ASSIGN)
 677                 IO_APIC_VECTOR(irq) = vector;
 678
 679         spin_unlock_irqrestore(&vector_lock, flags);
 680
 681         return vector;
 682 }
 683
 684 extern void (*interrupt[NR_IRQS])(void);
 685 static struct hw_interrupt_type ioapic_level_type;
 686 static struct hw_interrupt_type ioapic_edge_type;
 687
 688 #define IOAPIC_AUTO     -1
 689 #define IOAPIC_EDGE     0
 690 #define IOAPIC_LEVEL    1
 691
 692 static void ioapic_register_intr(int irq, int vector, unsigned long trigger)
 693 {
 694         unsigned idx;
 695
 696         idx = use_pci_vector() && !platform_legacy_irq(irq) ? vector : irq;
 697
 698         if ((trigger == IOAPIC_AUTO && IO_APIC_irq_trigger(irq)) ||
 699                         trigger == IOAPIC_LEVEL)
 700                 irq_desc[idx].chip = &ioapic_level_type;
 701         else
 702                 irq_desc[idx].chip = &ioapic_edge_type;
 703         set_intr_gate(vector, interrupt[idx]);
 704 }
 705
 706 static void __init setup_IO_APIC_irqs(void)
 707 {
 708         struct IO_APIC_route_entry entry;
 709         int apic, pin, idx, irq, first_notcon = 1, vector;
 710         unsigned long flags;
 711
 712         apic_printk(APIC_VERBOSE, KERN_DEBUG "init IO_APIC IRQs\n");
 713
 714         for (apic = 0; apic < nr_ioapics; apic++) {
 715         for (pin = 0; pin < nr_ioapic_registers[apic]; pin++) {
 716
 717                 /*
 718                  * add it to the IO-APIC irq-routing table:
 719                  */
 720                 memset(&entry,0,sizeof(entry));
 721
 722                 entry.delivery_mode = INT_DELIVERY_MODE;
 723                 entry.dest_mode = INT_DEST_MODE;
 724                 entry.mask = 0;                         /* enable IRQ */
 725                 entry.dest.logical.logical_dest = cpu_mask_to_apicid(TARGET_CPUS);
 726
 727                 idx = find_irq_entry(apic,pin,mp_INT);
 728                 if (idx == -1) {
 729                         if (first_notcon) {
 730                                 apic_printk(APIC_VERBOSE, KERN_DEBUG " IO-APIC (apicid-pin) %d-%d", mp_ioapics[apic].mpc_apicid, pin);
 731                                 first_notcon = 0;
 732                         } else
 733                                 apic_printk(APIC_VERBOSE, ", %d-%d", mp_ioapics[apic].mpc_apicid, pin);
 734                         continue;
 735                 }
 736
 737                 entry.trigger = irq_trigger(idx);
 738                 entry.polarity = irq_polarity(idx);
 739
 740                 if (irq_trigger(idx)) {
 741                         entry.trigger = 1;
 742                         entry.mask = 1;
 743                         entry.dest.logical.logical_dest = cpu_mask_to_apicid(TARGET_CPUS);
 744                 }
 745
 746                 irq = pin_2_irq(idx, apic, pin);
 747                 add_pin_to_irq(irq, apic, pin);
 748
 749                 if (!apic && !IO_APIC_IRQ(irq))
 750                         continue;
 751
 752                 if (IO_APIC_IRQ(irq)) {
 753                         vector = assign_irq_vector(irq);
 754                         entry.vector = vector;
 755
 756                         ioapic_register_intr(irq, vector, IOAPIC_AUTO);
 757                         if (!apic && (irq < 16))
 758                                 disable_8259A_irq(irq);
 759                 }
 760                 ioapic_write_entry(apic, pin, entry);
 761
 762                 spin_lock_irqsave(&ioapic_lock, flags);
 763                 set_native_irq_info(irq, TARGET_CPUS);
 764                 spin_unlock_irqrestore(&ioapic_lock, flags);
 765         }
 766         }
 767
 768         if (!first_notcon)
 769                 apic_printk(APIC_VERBOSE," not connected.\n");
 770 }
 771
 772 /*
 773  * Set up the 8259A-master output pin as broadcast to all
 774  * CPUs.
 775  */
 776 static void __init setup_ExtINT_IRQ0_pin(unsigned int apic, unsigned int pin, int vector)
 777 {
 778         struct IO_APIC_route_entry entry;
 779         unsigned long flags;
 780
 781         memset(&entry,0,sizeof(entry));
 782
 783         disable_8259A_irq(0);
 784
 785         /* mask LVT0 */
 786         apic_write(APIC_LVT0, APIC_LVT_MASKED | APIC_DM_EXTINT);
 787
 788         /*
 789          * We use logical delivery to get the timer IRQ
 790          * to the first CPU.
 791          */
 792         entry.dest_mode = INT_DEST_MODE;
 793         entry.mask = 0;                                 /* unmask IRQ now */
 794         entry.dest.logical.logical_dest = cpu_mask_to_apicid(TARGET_CPUS);
 795         entry.delivery_mode = INT_DELIVERY_MODE;
 796         entry.polarity = 0;
 797         entry.trigger = 0;
 798         entry.vector = vector;
 799
 800         /*
 801          * The timer IRQ doesn't have to know that behind the
 802          * scene we have a 8259A-master in AEOI mode ...
 803          */
 804         irq_desc[0].chip = &ioapic_edge_type;
 805
 806         /*
 807          * Add it to the IO-APIC irq-routing table:
 808          */
 809         spin_lock_irqsave(&ioapic_lock, flags);
 810         io_apic_write(apic, 0x11+2*pin, *(((int *)&entry)+1));
 811         io_apic_write(apic, 0x10+2*pin, *(((int *)&entry)+0));
 812         spin_unlock_irqrestore(&ioapic_lock, flags);
 813
 814         enable_8259A_irq(0);
 815 }
 816
 817 void __init UNEXPECTED_IO_APIC(void)
 818 {
 819 }
 820
 821 void __apicdebuginit print_IO_APIC(void)
 822 {
 823         int apic, i;
 824         union IO_APIC_reg_00 reg_00;
 825         union IO_APIC_reg_01 reg_01;
 826         union IO_APIC_reg_02 reg_02;
 827         unsigned long flags;
 828
 829         if (apic_verbosity == APIC_QUIET)
 830                 return;
 831
 832         printk(KERN_DEBUG "number of MP IRQ sources: %d.\n", mp_irq_entries);
 833         for (i = 0; i < nr_ioapics; i++)
 834                 printk(KERN_DEBUG "number of IO-APIC #%d registers: %d.\n",
 835                        mp_ioapics[i].mpc_apicid, nr_ioapic_registers[i]);
 836
 837         /*
 838          * We are a bit conservative about what we expect.  We have to
 839          * know about every hardware change ASAP.
 840          */
 841         printk(KERN_INFO "testing the IO APIC.......................\n");
 842
 843         for (apic = 0; apic < nr_ioapics; apic++) {
 844
 845         spin_lock_irqsave(&ioapic_lock, flags);
 846         reg_00.raw = io_apic_read(apic, 0);
 847         reg_01.raw = io_apic_read(apic, 1);
 848         if (reg_01.bits.version >= 0x10)
 849                 reg_02.raw = io_apic_read(apic, 2);
 850         spin_unlock_irqrestore(&ioapic_lock, flags);
 851
 852         printk("\n");
 853         printk(KERN_DEBUG "IO APIC #%d......\n", mp_ioapics[apic].mpc_apicid);
 854         printk(KERN_DEBUG ".... register #00: %08X\n", reg_00.raw);
 855         printk(KERN_DEBUG ".......    : physical APIC id: %02X\n", reg_00.bits.ID);
 856         if (reg_00.bits.__reserved_1 || reg_00.bits.__reserved_2)
 857                 UNEXPECTED_IO_APIC();
 858
 859         printk(KERN_DEBUG ".... register #01: %08X\n", *(int *)&reg_01);
 860         printk(KERN_DEBUG ".......     : max redirection entries: %04X\n", reg_01.bits.entries);
 861         if (    (reg_01.bits.entries != 0x0f) && /* older (Neptune) boards */
 862                 (reg_01.bits.entries != 0x17) && /* typical ISA+PCI boards */
 863                 (reg_01.bits.entries != 0x1b) && /* Compaq Proliant boards */
 864                 (reg_01.bits.entries != 0x1f) && /* dual Xeon boards */
 865                 (reg_01.bits.entries != 0x22) && /* bigger Xeon boards */
 866                 (reg_01.bits.entries != 0x2E) &&
 867                 (reg_01.bits.entries != 0x3F) &&
 868                 (reg_01.bits.entries != 0x03)
 869         )
 870                 UNEXPECTED_IO_APIC();
 871
 872         printk(KERN_DEBUG ".......     : PRQ implemented: %X\n", reg_01.bits.PRQ);
 873         printk(KERN_DEBUG ".......     : IO APIC version: %04X\n", reg_01.bits.version);
 874         if (    (reg_01.bits.version != 0x01) && /* 82489DX IO-APICs */
 875                 (reg_01.bits.version != 0x02) && /* 82801BA IO-APICs (ICH2) */
 876                 (reg_01.bits.version != 0x10) && /* oldest IO-APICs */
 877                 (reg_01.bits.version != 0x11) && /* Pentium/Pro IO-APICs */
 878                 (reg_01.bits.version != 0x13) && /* Xeon IO-APICs */
 879                 (reg_01.bits.version != 0x20)    /* Intel P64H (82806 AA) */
 880         )
 881                 UNEXPECTED_IO_APIC();
 882         if (reg_01.bits.__reserved_1 || reg_01.bits.__reserved_2)
 883                 UNEXPECTED_IO_APIC();
 884
 885         if (reg_01.bits.version >= 0x10) {
 886                 printk(KERN_DEBUG ".... register #02: %08X\n", reg_02.raw);
 887                 printk(KERN_DEBUG ".......     : arbitration: %02X\n", reg_02.bits.arbitration);
 888                 if (reg_02.bits.__reserved_1 || reg_02.bits.__reserved_2)
 889                         UNEXPECTED_IO_APIC();
 890         }
 891
 892         printk(KERN_DEBUG ".... IRQ redirection table:\n");
 893
 894         printk(KERN_DEBUG " NR Log Phy Mask Trig IRR Pol"
 895                           " Stat Dest Deli Vect:   \n");
 896
 897         for (i = 0; i <= reg_01.bits.entries; i++) {
 898                 struct IO_APIC_route_entry entry;
 899
 900                 entry = ioapic_read_entry(apic, i);
 901
 902                 printk(KERN_DEBUG " %02x %03X %02X  ",
 903                         i,
 904                         entry.dest.logical.logical_dest,
 905                         entry.dest.physical.physical_dest
 906                 );
 907
 908                 printk("%1d    %1d    %1d   %1d   %1d    %1d    %1d    %02X\n",
 909                         entry.mask,
 910                         entry.trigger,
 911                         entry.irr,
 912                         entry.polarity,
 913                         entry.delivery_status,
 914                         entry.dest_mode,
 915                         entry.delivery_mode,
 916                         entry.vector
 917                 );
 918         }
 919         }
 920         if (use_pci_vector())
 921                 printk(KERN_INFO "Using vector-based indexing\n");
 922         printk(KERN_DEBUG "IRQ to pin mappings:\n");
 923         for (i = 0; i < NR_IRQS; i++) {
 924                 struct irq_pin_list *entry = irq_2_pin + i;
 925                 if (entry->pin < 0)
 926                         continue;
 927                 if (use_pci_vector() && !platform_legacy_irq(i))
 928                         printk(KERN_DEBUG "IRQ%d ", IO_APIC_VECTOR(i));
 929                 else
 930                         printk(KERN_DEBUG "IRQ%d ", i);
 931                 for (;;) {
 932                         printk("-> %d:%d", entry->apic, entry->pin);
 933                         if (!entry->next)
 934                                 break;
 935                         entry = irq_2_pin + entry->next;
 936                 }
 937                 printk("\n");
 938         }
 939
 940         printk(KERN_INFO ".................................... done.\n");
 941
 942         return;
 943 }
 944
 945 #if 0
 946
 947 static __apicdebuginit void print_APIC_bitfield (int base)
 948 {
 949         unsigned int v;
 950         int i, j;
 951
 952         if (apic_verbosity == APIC_QUIET)
 953                 return;
 954
 955         printk(KERN_DEBUG "0123456789abcdef0123456789abcdef\n" KERN_DEBUG);
 956         for (i = 0; i < 8; i++) {
 957                 v = apic_read(base + i*0x10);
 958                 for (j = 0; j < 32; j++) {
 959                         if (v & (1<<j))
 960                                 printk("1");
 961                         else
 962                                 printk("0");
 963                 }
 964                 printk("\n");
 965         }
 966 }
 967
 968 void __apicdebuginit print_local_APIC(void * dummy)
 969 {
 970         unsigned int v, ver, maxlvt;
 971
 972         if (apic_verbosity == APIC_QUIET)
 973                 return;
 974
 975         printk("\n" KERN_DEBUG "printing local APIC contents on CPU#%d/%d:\n",
 976                 smp_processor_id(), hard_smp_processor_id());
 977         v = apic_read(APIC_ID);
 978         printk(KERN_INFO "... APIC ID:      %08x (%01x)\n", v, GET_APIC_ID(v));
 979         v = apic_read(APIC_LVR);
 980         printk(KERN_INFO "... APIC VERSION: %08x\n", v);
 981         ver = GET_APIC_VERSION(v);
 982         maxlvt = get_maxlvt();
 983
 984         v = apic_read(APIC_TASKPRI);
 985         printk(KERN_DEBUG "... APIC TASKPRI: %08x (%02x)\n", v, v & APIC_TPRI_MASK);
 986
 987         v = apic_read(APIC_ARBPRI);
 988         printk(KERN_DEBUG "... APIC ARBPRI: %08x (%02x)\n", v,
 989                 v & APIC_ARBPRI_MASK);
 990         v = apic_read(APIC_PROCPRI);
 991         printk(KERN_DEBUG "... APIC PROCPRI: %08x\n", v);
 992
 993         v = apic_read(APIC_EOI);
 994         printk(KERN_DEBUG "... APIC EOI: %08x\n", v);
 995         v = apic_read(APIC_RRR);
 996         printk(KERN_DEBUG "... APIC RRR: %08x\n", v);
 997         v = apic_read(APIC_LDR);
 998         printk(KERN_DEBUG "... APIC LDR: %08x\n", v);
 999         v = apic_read(APIC_DFR);
1000         printk(KERN_DEBUG "... APIC DFR: %08x\n", v);
1001         v = apic_read(APIC_SPIV);
1002         printk(KERN_DEBUG "... APIC SPIV: %08x\n", v);
1003
1004         printk(KERN_DEBUG "... APIC ISR field:\n");
1005         print_APIC_bitfield(APIC_ISR);
1006         printk(KERN_DEBUG "... APIC TMR field:\n");
1007         print_APIC_bitfield(APIC_TMR);
1008         printk(KERN_DEBUG "... APIC IRR field:\n");
1009         print_APIC_bitfield(APIC_IRR);
1010
1011         v = apic_read(APIC_ESR);
1012         printk(KERN_DEBUG "... APIC ESR: %08x\n", v);
1013
1014         v = apic_read(APIC_ICR);
1015         printk(KERN_DEBUG "... APIC ICR: %08x\n", v);
1016         v = apic_read(APIC_ICR2);
1017         printk(KERN_DEBUG "... APIC ICR2: %08x\n", v);
1018
1019         v = apic_read(APIC_LVTT);
1020         printk(KERN_DEBUG "... APIC LVTT: %08x\n", v);
1021
1022         if (maxlvt > 3) {                       /* PC is LVT#4. */
1023                 v = apic_read(APIC_LVTPC);
1024                 printk(KERN_DEBUG "... APIC LVTPC: %08x\n", v);
1025         }
1026         v = apic_read(APIC_LVT0);
1027         printk(KERN_DEBUG "... APIC LVT0: %08x\n", v);
1028         v = apic_read(APIC_LVT1);
1029         printk(KERN_DEBUG "... APIC LVT1: %08x\n", v);
1030
1031         if (maxlvt > 2) {                       /* ERR is LVT#3. */
1032                 v = apic_read(APIC_LVTERR);
1033                 printk(KERN_DEBUG "... APIC LVTERR: %08x\n", v);
1034         }
1035
1036         v = apic_read(APIC_TMICT);
1037         printk(KERN_DEBUG "... APIC TMICT: %08x\n", v);
1038         v = apic_read(APIC_TMCCT);
1039         printk(KERN_DEBUG "... APIC TMCCT: %08x\n", v);
1040         v = apic_read(APIC_TDCR);
1041         printk(KERN_DEBUG "... APIC TDCR: %08x\n", v);
1042         printk("\n");
1043 }
1044
1045 void print_all_local_APICs (void)
1046 {
1047         on_each_cpu(print_local_APIC, NULL, 1, 1);
1048 }
1049
1050 void __apicdebuginit print_PIC(void)
1051 {
1052         unsigned int v;
1053         unsigned long flags;
1054
1055         if (apic_verbosity == APIC_QUIET)
1056                 return;
1057
1058         printk(KERN_DEBUG "\nprinting PIC contents\n");
1059
1060         spin_lock_irqsave(&i8259A_lock, flags);
1061
1062         v = inb(0xa1) << 8 | inb(0x21);
1063         printk(KERN_DEBUG "... PIC  IMR: %04x\n", v);
1064
1065         v = inb(0xa0) << 8 | inb(0x20);
1066         printk(KERN_DEBUG "... PIC  IRR: %04x\n", v);
1067
1068         outb(0x0b,0xa0);
1069         outb(0x0b,0x20);
1070         v = inb(0xa0) << 8 | inb(0x20);
1071         outb(0x0a,0xa0);
1072         outb(0x0a,0x20);
1073
1074         spin_unlock_irqrestore(&i8259A_lock, flags);
1075
1076         printk(KERN_DEBUG "... PIC  ISR: %04x\n", v);
1077
1078         v = inb(0x4d1) << 8 | inb(0x4d0);
1079         printk(KERN_DEBUG "... PIC ELCR: %04x\n", v);
1080 }
1081
1082 #endif  /*  0  */
1083
1084 static void __init enable_IO_APIC(void)
1085 {
1086         union IO_APIC_reg_01 reg_01;
1087         int i8259_apic, i8259_pin;
1088         int i, apic;
1089         unsigned long flags;
1090
1091         for (i = 0; i < PIN_MAP_SIZE; i++) {
1092                 irq_2_pin[i].pin = -1;
1093                 irq_2_pin[i].next = 0;
1094         }
1095
1096         /*
1097          * The number of IO-APIC IRQ registers (== #pins):
1098          */
1099         for (apic = 0; apic < nr_ioapics; apic++) {
1100                 spin_lock_irqsave(&ioapic_lock, flags);
1101                 reg_01.raw = io_apic_read(apic, 1);
1102                 spin_unlock_irqrestore(&ioapic_lock, flags);
1103                 nr_ioapic_registers[apic] = reg_01.bits.entries+1;
1104         }
1105         for(apic = 0; apic < nr_ioapics; apic++) {
1106                 int pin;
1107                 /* See if any of the pins is in ExtINT mode */
1108                 for (pin = 0; pin < nr_ioapic_registers[apic]; pin++) {
1109                         struct IO_APIC_route_entry entry;
1110                         entry = ioapic_read_entry(apic, pin);
1111
1112                         /* If the interrupt line is enabled and in ExtInt mode
1113                          * I have found the pin where the i8259 is connected.
1114                          */
1115                         if ((entry.mask == 0) && (entry.delivery_mode == dest_ExtINT)) {
1116                                 ioapic_i8259.apic = apic;
1117                                 ioapic_i8259.pin  = pin;
1118                                 goto found_i8259;
1119                         }
1120                 }
1121         }
1122  found_i8259:
1123         /* Look to see what if the MP table has reported the ExtINT */
1124         i8259_pin  = find_isa_irq_pin(0, mp_ExtINT);
1125         i8259_apic = find_isa_irq_apic(0, mp_ExtINT);
1126         /* Trust the MP table if nothing is setup in the hardware */
1127         if ((ioapic_i8259.pin == -1) && (i8259_pin >= 0)) {
1128                 printk(KERN_WARNING "ExtINT not setup in hardware but reported by MP table\n");
1129                 ioapic_i8259.pin  = i8259_pin;
1130                 ioapic_i8259.apic = i8259_apic;
1131         }
1132         /* Complain if the MP table and the hardware disagree */
1133         if (((ioapic_i8259.apic != i8259_apic) || (ioapic_i8259.pin != i8259_pin)) &&
1134                 (i8259_pin >= 0) && (ioapic_i8259.pin >= 0))
1135         {
1136                 printk(KERN_WARNING "ExtINT in hardware and MP table differ\n");
1137         }
1138
1139         /*
1140          * Do not trust the IO-APIC being empty at bootup
1141          */
1142         clear_IO_APIC();
1143 }
1144
1145 /*
1146  * Not an __init, needed by the reboot code
1147  */
1148 void disable_IO_APIC(void)
1149 {
1150         /*
1151          * Clear the IO-APIC before rebooting:
1152          */
1153         clear_IO_APIC();
1154
1155         /*
1156          * If the i8259 is routed through an IOAPIC
1157          * Put that IOAPIC in virtual wire mode
1158          * so legacy interrupts can be delivered.
1159          */
1160         if (ioapic_i8259.pin != -1) {
1161                 struct IO_APIC_route_entry entry;
1162
1163                 memset(&entry, 0, sizeof(entry));
1164                 entry.mask            = 0; /* Enabled */
1165                 entry.trigger         = 0; /* Edge */
1166                 entry.irr             = 0;
1167                 entry.polarity        = 0; /* High */
1168                 entry.delivery_status = 0;
1169                 entry.dest_mode       = 0; /* Physical */
1170                 entry.delivery_mode   = dest_ExtINT; /* ExtInt */
1171                 entry.vector          = 0;
1172                 entry.dest.physical.physical_dest =
1173                                         GET_APIC_ID(apic_read(APIC_ID));
1174
1175                 /*
1176                  * Add it to the IO-APIC irq-routing table:
1177                  */
1178                 ioapic_write_entry(ioapic_i8259.apic, ioapic_i8259.pin, entry);
1179         }
1180
1181         disconnect_bsp_APIC(ioapic_i8259.pin != -1);
1182 }
1183
1184 /*
1185  * There is a nasty bug in some older SMP boards, their mptable lies
1186  * about the timer IRQ. We do the following to work around the situation:
1187  *
1188  *      - timer IRQ defaults to IO-APIC IRQ
1189  *      - if this function detects that timer IRQs are defunct, then we fall
1190  *        back to ISA timer IRQs
1191  */
1192 static int __init timer_irq_works(void)
1193 {
1194         unsigned long t1 = jiffies;
1195
1196         local_irq_enable();
1197         /* Let ten ticks pass... */
1198         mdelay((10 * 1000) / HZ);
1199
1200         /*
1201          * Expect a few ticks at least, to be sure some possible
1202          * glue logic does not lock up after one or two first
1203          * ticks in a non-ExtINT mode.  Also the local APIC
1204          * might have cached one ExtINT interrupt.  Finally, at
1205          * least one tick may be lost due to delays.
1206          */
1207
1208         /* jiffies wrap? */
1209         if (jiffies - t1 > 4)
1210                 return 1;
1211         return 0;
1212 }
1213
1214 /*
1215  * In the SMP+IOAPIC case it might happen that there are an unspecified
1216  * number of pending IRQ events unhandled. These cases are very rare,
1217  * so we 'resend' these IRQs via IPIs, to the same CPU. It's much
1218  * better to do it this way as thus we do not have to be aware of
1219  * 'pending' interrupts in the IRQ path, except at this point.
1220  */
1221 /*
1222  * Edge triggered needs to resend any interrupt
1223  * that was delayed but this is now handled in the device
1224  * independent code.
1225  */
1226
1227 /*
1228  * Starting up a edge-triggered IO-APIC interrupt is
1229  * nasty - we need to make sure that we get the edge.
1230  * If it is already asserted for some reason, we need
1231  * return 1 to indicate that is was pending.
1232  *
1233  * This is not complete - we should be able to fake
1234  * an edge even if it isn't on the 8259A...
1235  */
1236
1237 static unsigned int startup_edge_ioapic_irq(unsigned int irq)
1238 {
1239         int was_pending = 0;
1240         unsigned long flags;
1241
1242         spin_lock_irqsave(&ioapic_lock, flags);
1243         if (irq < 16) {
1244                 disable_8259A_irq(irq);
1245                 if (i8259A_irq_pending(irq))
1246                         was_pending = 1;
1247         }
1248         __unmask_IO_APIC_irq(irq);
1249         spin_unlock_irqrestore(&ioapic_lock, flags);
1250
1251         return was_pending;
1252 }
1253
1254 /*
1255  * Once we have recorded IRQ_PENDING already, we can mask the
1256  * interrupt for real. This prevents IRQ storms from unhandled
1257  * devices.
1258  */
1259 static void ack_edge_ioapic_irq(unsigned int irq)
1260 {
1261         move_irq(irq);
1262         if ((irq_desc[irq].status & (IRQ_PENDING | IRQ_DISABLED))
1263                                         == (IRQ_PENDING | IRQ_DISABLED))
1264                 mask_IO_APIC_irq(irq);
1265         ack_APIC_irq();
1266 }
1267
1268 /*
1269  * Level triggered interrupts can just be masked,
1270  * and shutting down and starting up the interrupt
1271  * is the same as enabling and disabling them -- except
1272  * with a startup need to return a "was pending" value.
1273  *
1274  * Level triggered interrupts are special because we
1275  * do not touch any IO-APIC register while handling
1276  * them. We ack the APIC in the end-IRQ handler, not
1277  * in the start-IRQ-handler. Protection against reentrance
1278  * from the same interrupt is still provided, both by the
1279  * generic IRQ layer and by the fact that an unacked local
1280  * APIC does not accept IRQs.
1281  */
1282 static unsigned int startup_level_ioapic_irq (unsigned int irq)
1283 {
1284         unmask_IO_APIC_irq(irq);
1285
1286         return 0; /* don't check for pending */
1287 }
1288
1289 static void end_level_ioapic_irq (unsigned int irq)
1290 {
1291         move_irq(irq);
1292         ack_APIC_irq();
1293 }
1294
1295 #ifdef CONFIG_PCI_MSI
1296 static unsigned int startup_edge_ioapic_vector(unsigned int vector)
1297 {
1298         int irq = vector_to_irq(vector);
1299
1300         return startup_edge_ioapic_irq(irq);
1301 }
1302
1303 static void ack_edge_ioapic_vector(unsigned int vector)
1304 {
1305         int irq = vector_to_irq(vector);
1306
1307         move_native_irq(vector);
1308         ack_edge_ioapic_irq(irq);
1309 }
1310
1311 static unsigned int startup_level_ioapic_vector (unsigned int vector)
1312 {
1313         int irq = vector_to_irq(vector);
1314
1315         return startup_level_ioapic_irq (irq);
1316 }
1317
1318 static void end_level_ioapic_vector (unsigned int vector)
1319 {
1320         int irq = vector_to_irq(vector);
1321
1322         move_native_irq(vector);
1323         end_level_ioapic_irq(irq);
1324 }
1325
1326 static void mask_IO_APIC_vector (unsigned int vector)
1327 {
1328         int irq = vector_to_irq(vector);
1329
1330         mask_IO_APIC_irq(irq);
1331 }
1332
1333 static void unmask_IO_APIC_vector (unsigned int vector)
1334 {
1335         int irq = vector_to_irq(vector);
1336
1337         unmask_IO_APIC_irq(irq);
1338 }
1339
1340 #ifdef CONFIG_SMP
1341 static void set_ioapic_affinity_vector (unsigned int vector,
1342                                         cpumask_t cpu_mask)
1343 {
1344         int irq = vector_to_irq(vector);
1345
1346         set_native_irq_info(vector, cpu_mask);
1347         set_ioapic_affinity_irq(irq, cpu_mask);
1348 }
1349 #endif // CONFIG_SMP
1350 #endif // CONFIG_PCI_MSI
1351
1352 static int ioapic_retrigger(unsigned int irq)
1353 {
1354         send_IPI_self(IO_APIC_VECTOR(irq));
1355
1356         return 1;
1357 }
1358
1359 /*
1360  * Level and edge triggered IO-APIC interrupts need different handling,
1361  * so we use two separate IRQ descriptors. Edge triggered IRQs can be
1362  * handled with the level-triggered descriptor, but that one has slightly
1363  * more overhead. Level-triggered interrupts cannot be handled with the
1364  * edge-triggered handler, without risking IRQ storms and other ugly
1365  * races.
1366  */
1367
1368 static struct hw_interrupt_type ioapic_edge_type __read_mostly = {
1369         .typename = "IO-APIC-edge",
1370         .startup        = startup_edge_ioapic,
1371         .shutdown       = shutdown_edge_ioapic,
1372         .enable         = enable_edge_ioapic,
1373         .disable        = disable_edge_ioapic,
1374         .ack            = ack_edge_ioapic,
1375         .end            = end_edge_ioapic,
1376 #ifdef CONFIG_SMP
1377         .set_affinity = set_ioapic_affinity,
1378 #endif
1379         .retrigger      = ioapic_retrigger,
1380 };
1381
1382 static struct hw_interrupt_type ioapic_level_type __read_mostly = {
1383         .typename = "IO-APIC-level",
1384         .startup        = startup_level_ioapic,
1385         .shutdown       = shutdown_level_ioapic,
1386         .enable         = enable_level_ioapic,
1387         .disable        = disable_level_ioapic,
1388         .ack            = mask_and_ack_level_ioapic,
1389         .end            = end_level_ioapic,
1390 #ifdef CONFIG_SMP
1391         .set_affinity = set_ioapic_affinity,
1392 #endif
1393         .retrigger      = ioapic_retrigger,
1394 };
1395
1396 static inline void init_IO_APIC_traps(void)
1397 {
1398         int irq;
1399
1400         /*
1401          * NOTE! The local APIC isn't very good at handling
1402          * multiple interrupts at the same interrupt level.
1403          * As the interrupt level is determined by taking the
1404          * vector number and shifting that right by 4, we
1405          * want to spread these out a bit so that they don't
1406          * all fall in the same interrupt level.
1407          *
1408          * Also, we've got to be careful not to trash gate
1409          * 0x80, because int 0x80 is hm, kind of importantish. ;)
1410          */
1411         for (irq = 0; irq < NR_IRQS ; irq++) {
1412                 int tmp = irq;
1413                 if (use_pci_vector()) {
1414                         if (!platform_legacy_irq(tmp))
1415                                 if ((tmp = vector_to_irq(tmp)) == -1)
1416                                         continue;
1417                 }
1418                 if (IO_APIC_IRQ(tmp) && !IO_APIC_VECTOR(tmp)) {
1419                         /*
1420                          * Hmm.. We don't have an entry for this,
1421                          * so default to an old-fashioned 8259
1422                          * interrupt if we can..
1423                          */
1424                         if (irq < 16)
1425                                 make_8259A_irq(irq);
1426                         else
1427                                 /* Strange. Oh, well.. */
1428                                 irq_desc[irq].chip = &no_irq_type;
1429                 }
1430         }
1431 }
1432
1433 static void enable_lapic_irq (unsigned int irq)
1434 {
1435         unsigned long v;
1436
1437         v = apic_read(APIC_LVT0);
1438         apic_write(APIC_LVT0, v & ~APIC_LVT_MASKED);
1439 }
1440
1441 static void disable_lapic_irq (unsigned int irq)
1442 {
1443         unsigned long v;
1444
1445         v = apic_read(APIC_LVT0);
1446         apic_write(APIC_LVT0, v | APIC_LVT_MASKED);
1447 }
1448
1449 static void ack_lapic_irq (unsigned int irq)
1450 {
1451         ack_APIC_irq();
1452 }
1453
1454 static void end_lapic_irq (unsigned int i) { /* nothing */ }
1455
1456 static struct hw_interrupt_type lapic_irq_type __read_mostly = {
1457         .typename = "local-APIC-edge",
1458         .startup = NULL, /* startup_irq() not used for IRQ0 */
1459         .shutdown = NULL, /* shutdown_irq() not used for IRQ0 */
1460         .enable = enable_lapic_irq,
1461         .disable = disable_lapic_irq,
1462         .ack = ack_lapic_irq,
1463         .end = end_lapic_irq,
1464 };
1465
1466 static void setup_nmi (void)
1467 {
1468         /*
1469          * Dirty trick to enable the NMI watchdog ...
1470          * We put the 8259A master into AEOI mode and
1471          * unmask on all local APICs LVT0 as NMI.
1472          *
1473          * The idea to use the 8259A in AEOI mode ('8259A Virtual Wire')
1474          * is from Maciej W. Rozycki - so we do not have to EOI from
1475          * the NMI handler or the timer interrupt.
1476          */
1477         printk(KERN_INFO "activating NMI Watchdog ...");
1478
1479         enable_NMI_through_LVT0(NULL);
1480
1481         printk(" done.\n");
1482 }
1483
1484 /*
1485  * This looks a bit hackish but it's about the only one way of sending
1486  * a few INTA cycles to 8259As and any associated glue logic.  ICR does
1487  * not support the ExtINT mode, unfortunately.  We need to send these
1488  * cycles as some i82489DX-based boards have glue logic that keeps the
1489  * 8259A interrupt line asserted until INTA.  --macro
1490  */
1491 static inline void unlock_ExtINT_logic(void)
1492 {
1493         int apic, pin, i;
1494         struct IO_APIC_route_entry entry0, entry1;
1495         unsigned char save_control, save_freq_select;
1496         unsigned long flags;
1497
1498         pin  = find_isa_irq_pin(8, mp_INT);
1499         apic = find_isa_irq_apic(8, mp_INT);
1500         if (pin == -1)
1501                 return;
1502
1503         spin_lock_irqsave(&ioapic_lock, flags);
1504         *(((int *)&entry0) + 1) = io_apic_read(apic, 0x11 + 2 * pin);
1505         *(((int *)&entry0) + 0) = io_apic_read(apic, 0x10 + 2 * pin);
1506         spin_unlock_irqrestore(&ioapic_lock, flags);
1507         clear_IO_APIC_pin(apic, pin);
1508
1509         memset(&entry1, 0, sizeof(entry1));
1510
1511         entry1.dest_mode = 0;                   /* physical delivery */
1512         entry1.mask = 0;                        /* unmask IRQ now */
1513         entry1.dest.physical.physical_dest = hard_smp_processor_id();
1514         entry1.delivery_mode = dest_ExtINT;
1515         entry1.polarity = entry0.polarity;
1516         entry1.trigger = 0;
1517         entry1.vector = 0;
1518
1519         spin_lock_irqsave(&ioapic_lock, flags);
1520         io_apic_write(apic, 0x11 + 2 * pin, *(((int *)&entry1) + 1));
1521         io_apic_write(apic, 0x10 + 2 * pin, *(((int *)&entry1) + 0));
1522         spin_unlock_irqrestore(&ioapic_lock, flags);
1523
1524         save_control = CMOS_READ(RTC_CONTROL);
1525         save_freq_select = CMOS_READ(RTC_FREQ_SELECT);
1526         CMOS_WRITE((save_freq_select & ~RTC_RATE_SELECT) | 0x6,
1527                    RTC_FREQ_SELECT);
1528         CMOS_WRITE(save_control | RTC_PIE, RTC_CONTROL);
1529
1530         i = 100;
1531         while (i-- > 0) {
1532                 mdelay(10);
1533                 if ((CMOS_READ(RTC_INTR_FLAGS) & RTC_PF) == RTC_PF)
1534                         i -= 10;
1535         }
1536
1537         CMOS_WRITE(save_control, RTC_CONTROL);
1538         CMOS_WRITE(save_freq_select, RTC_FREQ_SELECT);
1539         clear_IO_APIC_pin(apic, pin);
1540
1541         spin_lock_irqsave(&ioapic_lock, flags);
1542         io_apic_write(apic, 0x11 + 2 * pin, *(((int *)&entry0) + 1));
1543         io_apic_write(apic, 0x10 + 2 * pin, *(((int *)&entry0) + 0));
1544         spin_unlock_irqrestore(&ioapic_lock, flags);
1545 }
1546
1547 int timer_uses_ioapic_pin_0;
1548
1549 /*
1550  * This code may look a bit paranoid, but it's supposed to cooperate with
1551  * a wide range of boards and BIOS bugs.  Fortunately only the timer IRQ
1552  * is so screwy.  Thanks to Brian Perkins for testing/hacking this beast
1553  * fanatically on his truly buggy board.
1554  *
1555  * FIXME: really need to revamp this for modern platforms only.
1556  */
1557 static inline void check_timer(void)
1558 {
1559         int apic1, pin1, apic2, pin2;
1560         int vector;
1561
1562         /*
1563          * get/set the timer IRQ vector:
1564          */
1565         disable_8259A_irq(0);
1566         vector = assign_irq_vector(0);
1567         set_intr_gate(vector, interrupt[0]);
1568
1569         /*
1570          * Subtle, code in do_timer_interrupt() expects an AEOI
1571          * mode for the 8259A whenever interrupts are routed
1572          * through I/O APICs.  Also IRQ0 has to be enabled in
1573          * the 8259A which implies the virtual wire has to be
1574          * disabled in the local APIC.
1575          */
1576         apic_write(APIC_LVT0, APIC_LVT_MASKED | APIC_DM_EXTINT);
1577         init_8259A(1);
1578         if (timer_over_8254 > 0)
1579                 enable_8259A_irq(0);
1580
1581         pin1  = find_isa_irq_pin(0, mp_INT);
1582         apic1 = find_isa_irq_apic(0, mp_INT);
1583         pin2  = ioapic_i8259.pin;
1584         apic2 = ioapic_i8259.apic;
1585
1586         if (pin1 == 0)
1587                 timer_uses_ioapic_pin_0 = 1;
1588
1589         apic_printk(APIC_VERBOSE,KERN_INFO "..TIMER: vector=0x%02X apic1=%d pin1=%d apic2=%d pin2=%d\n",
1590                 vector, apic1, pin1, apic2, pin2);
1591
1592         if (pin1 != -1) {
1593                 /*
1594                  * Ok, does IRQ0 through the IOAPIC work?
1595                  */
1596                 unmask_IO_APIC_irq(0);
1597                 if (!no_timer_check && timer_irq_works()) {
1598                         nmi_watchdog_default();
1599                         if (nmi_watchdog == NMI_IO_APIC) {
1600                                 disable_8259A_irq(0);
1601                                 setup_nmi();
1602                                 enable_8259A_irq(0);
1603                         }
1604                         if (disable_timer_pin_1 > 0)
1605                                 clear_IO_APIC_pin(0, pin1);
1606                         return;
1607                 }
1608                 clear_IO_APIC_pin(apic1, pin1);
1609                 apic_printk(APIC_QUIET,KERN_ERR "..MP-BIOS bug: 8254 timer not "
1610                                 "connected to IO-APIC\n");
1611         }
1612
1613         apic_printk(APIC_VERBOSE,KERN_INFO "...trying to set up timer (IRQ0) "
1614                                 "through the 8259A ... ");
1615         if (pin2 != -1) {
1616                 apic_printk(APIC_VERBOSE,"\n..... (found apic %d pin %d) ...",
1617                         apic2, pin2);
1618                 /*
1619                  * legacy devices should be connected to IO APIC #0
1620                  */
1621                 setup_ExtINT_IRQ0_pin(apic2, pin2, vector);
1622                 if (timer_irq_works()) {
1623                         apic_printk(APIC_VERBOSE," works.\n");
1624                         nmi_watchdog_default();
1625                         if (nmi_watchdog == NMI_IO_APIC) {
1626                                 setup_nmi();
1627                         }
1628                         return;
1629                 }
1630                 /*
1631                  * Cleanup, just in case ...
1632                  */
1633                 clear_IO_APIC_pin(apic2, pin2);
1634         }
1635         apic_printk(APIC_VERBOSE," failed.\n");
1636
1637         if (nmi_watchdog == NMI_IO_APIC) {
1638                 printk(KERN_WARNING "timer doesn't work through the IO-APIC - disabling NMI Watchdog!\n");
1639                 nmi_watchdog = 0;
1640         }
1641
1642         apic_printk(APIC_VERBOSE, KERN_INFO "...trying to set up timer as Virtual Wire IRQ...");
1643
1644         disable_8259A_irq(0);
1645         irq_desc[0].chip = &lapic_irq_type;
1646         apic_write(APIC_LVT0, APIC_DM_FIXED | vector);  /* Fixed mode */
1647         enable_8259A_irq(0);
1648
1649         if (timer_irq_works()) {
1650                 apic_printk(APIC_VERBOSE," works.\n");
1651                 return;
1652         }
1653         apic_write(APIC_LVT0, APIC_LVT_MASKED | APIC_DM_FIXED | vector);
1654         apic_printk(APIC_VERBOSE," failed.\n");
1655
1656         apic_printk(APIC_VERBOSE, KERN_INFO "...trying to set up timer as ExtINT IRQ...");
1657
1658         init_8259A(0);
1659         make_8259A_irq(0);
1660         apic_write(APIC_LVT0, APIC_DM_EXTINT);
1661
1662         unlock_ExtINT_logic();
1663
1664         if (timer_irq_works()) {
1665                 apic_printk(APIC_VERBOSE," works.\n");
1666                 return;
1667         }
1668         apic_printk(APIC_VERBOSE," failed :(.\n");
1669         panic("IO-APIC + timer doesn't work! Try using the 'noapic' kernel parameter\n");
1670 }
1671
1672 static int __init notimercheck(char *s)
1673 {
1674         no_timer_check = 1;
1675         return 1;
1676 }
1677 __setup("no_timer_check", notimercheck);
1678
1679 /*
1680  *
1681  * IRQ's that are handled by the PIC in the MPS IOAPIC case.
1682  * - IRQ2 is the cascade IRQ, and cannot be a io-apic IRQ.
1683  *   Linux doesn't really care, as it's not actually used
1684  *   for any interrupt handling anyway.
1685  */
1686 #define PIC_IRQS        (1<<2)
1687
1688 void __init setup_IO_APIC(void)
1689 {
1690         enable_IO_APIC();
1691
1692         if (acpi_ioapic)
1693                 io_apic_irqs = ~0;      /* all IRQs go through IOAPIC */
1694         else
1695                 io_apic_irqs = ~PIC_IRQS;
1696
1697         apic_printk(APIC_VERBOSE, "ENABLING IO-APIC IRQs\n");
1698
1699         sync_Arb_IDs();
1700         setup_IO_APIC_irqs();
1701         init_IO_APIC_traps();
1702         check_timer();
1703         if (!acpi_ioapic)
1704                 print_IO_APIC();
1705 }
1706
1707 struct sysfs_ioapic_data {
1708         struct sys_device dev;
1709         struct IO_APIC_route_entry entry[0];
1710 };
1711 static struct sysfs_ioapic_data * mp_ioapic_data[MAX_IO_APICS];
1712
1713 static int ioapic_suspend(struct sys_device *dev, pm_message_t state)
1714 {
1715         struct IO_APIC_route_entry *entry;
1716         struct sysfs_ioapic_data *data;
1717         int i;
1718
1719         data = container_of(dev, struct sysfs_ioapic_data, dev);
1720         entry = data->entry;
1721         for (i = 0; i < nr_ioapic_registers[dev->id]; i ++, entry ++ )
1722                 *entry = ioapic_read_entry(dev->id, i);
1723
1724         return 0;
1725 }
1726
1727 static int ioapic_resume(struct sys_device *dev)
1728 {
1729         struct IO_APIC_route_entry *entry;
1730         struct sysfs_ioapic_data *data;
1731         unsigned long flags;
1732         union IO_APIC_reg_00 reg_00;
1733         int i;
1734
1735         data = container_of(dev, struct sysfs_ioapic_data, dev);
1736         entry = data->entry;
1737
1738         spin_lock_irqsave(&ioapic_lock, flags);
1739         reg_00.raw = io_apic_read(dev->id, 0);
1740         if (reg_00.bits.ID != mp_ioapics[dev->id].mpc_apicid) {
1741                 reg_00.bits.ID = mp_ioapics[dev->id].mpc_apicid;
1742                 io_apic_write(dev->id, 0, reg_00.raw);
1743         }
1744         spin_unlock_irqrestore(&ioapic_lock, flags);
1745         for (i = 0; i < nr_ioapic_registers[dev->id]; i++)
1746                 ioapic_write_entry(dev->id, i, entry[i]);
1747
1748         return 0;
1749 }
1750
1751 static struct sysdev_class ioapic_sysdev_class = {
1752         set_kset_name("ioapic"),
1753         .suspend = ioapic_suspend,
1754         .resume = ioapic_resume,
1755 };
1756
1757 static int __init ioapic_init_sysfs(void)
1758 {
1759         struct sys_device * dev;
1760         int i, size, error = 0;
1761
1762         error = sysdev_class_register(&ioapic_sysdev_class);
1763         if (error)
1764                 return error;
1765
1766         for (i = 0; i < nr_ioapics; i++ ) {
1767                 size = sizeof(struct sys_device) + nr_ioapic_registers[i]
1768                         * sizeof(struct IO_APIC_route_entry);
1769                 mp_ioapic_data[i] = kmalloc(size, GFP_KERNEL);
1770                 if (!mp_ioapic_data[i]) {
1771                         printk(KERN_ERR "Can't suspend/resume IOAPIC %d\n", i);
1772                         continue;
1773                 }
1774                 memset(mp_ioapic_data[i], 0, size);
1775                 dev = &mp_ioapic_data[i]->dev;
1776                 dev->id = i;
1777                 dev->cls = &ioapic_sysdev_class;
1778                 error = sysdev_register(dev);
1779                 if (error) {
1780                         kfree(mp_ioapic_data[i]);
1781                         mp_ioapic_data[i] = NULL;
1782                         printk(KERN_ERR "Can't suspend/resume IOAPIC %d\n", i);
1783                         continue;
1784                 }
1785         }
1786
1787         return 0;
1788 }
1789
1790 device_initcall(ioapic_init_sysfs);
1791
1792 /* --------------------------------------------------------------------------
1793                           ACPI-based IOAPIC Configuration
1794    -------------------------------------------------------------------------- */
1795
1796 #ifdef CONFIG_ACPI
1797
1798 #define IO_APIC_MAX_ID          0xFE
1799
1800 int __init io_apic_get_version (int ioapic)
1801 {
1802         union IO_APIC_reg_01    reg_01;
1803         unsigned long flags;
1804
1805         spin_lock_irqsave(&ioapic_lock, flags);
1806         reg_01.raw = io_apic_read(ioapic, 1);
1807         spin_unlock_irqrestore(&ioapic_lock, flags);
1808
1809         return reg_01.bits.version;
1810 }
1811
1812
1813 int __init io_apic_get_redir_entries (int ioapic)
1814 {
1815         union IO_APIC_reg_01    reg_01;
1816         unsigned long flags;
1817
1818         spin_lock_irqsave(&ioapic_lock, flags);
1819         reg_01.raw = io_apic_read(ioapic, 1);
1820         spin_unlock_irqrestore(&ioapic_lock, flags);
1821
1822         return reg_01.bits.entries;
1823 }
1824
1825
1826 int io_apic_set_pci_routing (int ioapic, int pin, int irq, int triggering, int polarity)
1827 {
1828         struct IO_APIC_route_entry entry;
1829         unsigned long flags;
1830
1831         if (!IO_APIC_IRQ(irq)) {
1832                 apic_printk(APIC_QUIET,KERN_ERR "IOAPIC[%d]: Invalid reference to IRQ 0\n",
1833                         ioapic);
1834                 return -EINVAL;
1835         }
1836
1837         /*
1838          * Generate a PCI IRQ routing entry and program the IOAPIC accordingly.
1839          * Note that we mask (disable) IRQs now -- these get enabled when the
1840          * corresponding device driver registers for this IRQ.
1841          */
1842
1843         memset(&entry,0,sizeof(entry));
1844
1845         entry.delivery_mode = INT_DELIVERY_MODE;
1846         entry.dest_mode = INT_DEST_MODE;
1847         entry.dest.logical.logical_dest = cpu_mask_to_apicid(TARGET_CPUS);
1848         entry.trigger = triggering;
1849         entry.polarity = polarity;
1850         entry.mask = 1;                                  /* Disabled (masked) */
1851
1852         irq = gsi_irq_sharing(irq);
1853         /*
1854          * IRQs < 16 are already in the irq_2_pin[] map
1855          */
1856         if (irq >= 16)
1857                 add_pin_to_irq(irq, ioapic, pin);
1858
1859         entry.vector = assign_irq_vector(irq);
1860
1861         apic_printk(APIC_VERBOSE,KERN_DEBUG "IOAPIC[%d]: Set PCI routing entry (%d-%d -> 0x%x -> "
1862                 "IRQ %d Mode:%i Active:%i)\n", ioapic,
1863                mp_ioapics[ioapic].mpc_apicid, pin, entry.vector, irq,
1864                triggering, polarity);
1865
1866         ioapic_register_intr(irq, entry.vector, triggering);
1867
1868         if (!ioapic && (irq < 16))
1869                 disable_8259A_irq(irq);
1870
1871         ioapic_write_entry(ioapic, pin, entry);
1872
1873         spin_lock_irqsave(&ioapic_lock, flags);
1874         set_native_irq_info(use_pci_vector() ? entry.vector : irq, TARGET_CPUS);
1875         spin_unlock_irqrestore(&ioapic_lock, flags);
1876
1877         return 0;
1878 }
1879
1880 #endif /* CONFIG_ACPI */
1881
1882
1883 /*
1884  * This function currently is only a helper for the i386 smp boot process where
1885  * we need to reprogram the ioredtbls to cater for the cpus which have come online
1886  * so mask in all cases should simply be TARGET_CPUS
1887  */
1888 #ifdef CONFIG_SMP
1889 void __init setup_ioapic_dest(void)
1890 {
1891         int pin, ioapic, irq, irq_entry;
1892
1893         if (skip_ioapic_setup == 1)
1894                 return;
1895
1896         for (ioapic = 0; ioapic < nr_ioapics; ioapic++) {
1897                 for (pin = 0; pin < nr_ioapic_registers[ioapic]; pin++) {
1898                         irq_entry = find_irq_entry(ioapic, pin, mp_INT);
1899                         if (irq_entry == -1)
1900                                 continue;
1901                         irq = pin_2_irq(irq_entry, ioapic, pin);
1902                         set_ioapic_affinity_irq(irq, TARGET_CPUS);
1903                 }
1904
1905         }
1906 }
1907 #endif