2 * Intel IO-APIC support for multi-Pentium hosts.
4 * Copyright (C) 1997, 1998, 1999, 2000 Ingo Molnar, Hajnalka Szabo
6 * Many thanks to Stig Venaas for trying out countless experimental
7 * patches and reporting/debugging problems patiently!
9 * (c) 1999, Multiple IO-APIC support, developed by
10 * Ken-ichi Yaku <yaku@css1.kbnes.nec.co.jp> and
11 * Hidemi Kishimoto <kisimoto@css1.kbnes.nec.co.jp>,
12 * further tested and cleaned up by Zach Brown <zab@redhat.com>
13 * and Ingo Molnar <mingo@redhat.com>
16 * Maciej W. Rozycki : Bits for genuine 82489DX APICs;
17 * thanks to Eric Gilmore
19 * for testing these extensively
20 * Paul Diefenbaugh : Added full ACPI support
24 #include <linux/irq.h>
25 #include <linux/interrupt.h>
26 #include <linux/init.h>
27 #include <linux/delay.h>
28 #include <linux/sched.h>
29 #include <linux/config.h>
30 #include <linux/smp_lock.h>
31 #include <linux/mc146818rtc.h>
32 #include <linux/acpi.h>
33 #include <linux/sysdev.h>
38 #include <asm/proto.h>
39 #include <asm/mach_apic.h>
42 #define __apicdebuginit __init
44 int sis_apic_bug; /* not actually supported, dummy for compile */
46 static int no_timer_check;
48 static DEFINE_SPINLOCK(ioapic_lock);
51 * # of IRQ routing registers
53 int nr_ioapic_registers[MAX_IO_APICS];
56 * Rough estimation of how many shared IRQs there are, can
59 #define MAX_PLUS_SHARED_IRQS NR_IRQS
60 #define PIN_MAP_SIZE (MAX_PLUS_SHARED_IRQS + NR_IRQS)
63 * This is performance-critical, we want to do it O(1)
65 * the indexing order of this array favors 1:1 mappings
66 * between pins and IRQs.
69 static struct irq_pin_list {
70 short apic, pin, next;
71 } irq_2_pin[PIN_MAP_SIZE];
73 int vector_irq[NR_VECTORS] = { [0 ... NR_VECTORS - 1] = -1};
75 #define vector_to_irq(vector) \
76 (platform_legacy_irq(vector) ? vector : vector_irq[vector])
78 #define vector_to_irq(vector) (vector)
82 * The common case is 1:1 IRQ<->pin mappings. Sometimes there are
83 * shared ISA-space IRQs, so we have to support them. We are super
84 * fast in the common case, and fast for shared ISA-space IRQs.
86 static void add_pin_to_irq(unsigned int irq, int apic, int pin)
88 static int first_free_entry = NR_IRQS;
89 struct irq_pin_list *entry = irq_2_pin + irq;
92 entry = irq_2_pin + entry->next;
94 if (entry->pin != -1) {
95 entry->next = first_free_entry;
96 entry = irq_2_pin + entry->next;
97 if (++first_free_entry >= PIN_MAP_SIZE)
98 panic("io_apic.c: whoops");
104 #define __DO_ACTION(R, ACTION, FINAL) \
108 struct irq_pin_list *entry = irq_2_pin + irq; \
115 reg = io_apic_read(entry->apic, 0x10 + R + pin*2); \
117 io_apic_modify(entry->apic, reg); \
120 entry = irq_2_pin + entry->next; \
125 #define DO_ACTION(name,R,ACTION, FINAL) \
127 static void name##_IO_APIC_irq (unsigned int irq) \
128 __DO_ACTION(R, ACTION, FINAL)
130 DO_ACTION( __mask, 0, |= 0x00010000, io_apic_sync(entry->apic) )
132 DO_ACTION( __unmask, 0, &= 0xfffeffff, )
135 static void mask_IO_APIC_irq (unsigned int irq)
139 spin_lock_irqsave(&ioapic_lock, flags);
140 __mask_IO_APIC_irq(irq);
141 spin_unlock_irqrestore(&ioapic_lock, flags);
144 static void unmask_IO_APIC_irq (unsigned int irq)
148 spin_lock_irqsave(&ioapic_lock, flags);
149 __unmask_IO_APIC_irq(irq);
150 spin_unlock_irqrestore(&ioapic_lock, flags);
153 static void clear_IO_APIC_pin(unsigned int apic, unsigned int pin)
155 struct IO_APIC_route_entry entry;
158 /* Check delivery_mode to be sure we're not clearing an SMI pin */
159 spin_lock_irqsave(&ioapic_lock, flags);
160 *(((int*)&entry) + 0) = io_apic_read(apic, 0x10 + 2 * pin);
161 *(((int*)&entry) + 1) = io_apic_read(apic, 0x11 + 2 * pin);
162 spin_unlock_irqrestore(&ioapic_lock, flags);
163 if (entry.delivery_mode == dest_SMI)
166 * Disable it in the IO-APIC irq-routing table:
168 memset(&entry, 0, sizeof(entry));
170 spin_lock_irqsave(&ioapic_lock, flags);
171 io_apic_write(apic, 0x10 + 2 * pin, *(((int *)&entry) + 0));
172 io_apic_write(apic, 0x11 + 2 * pin, *(((int *)&entry) + 1));
173 spin_unlock_irqrestore(&ioapic_lock, flags);
176 static void clear_IO_APIC (void)
180 for (apic = 0; apic < nr_ioapics; apic++)
181 for (pin = 0; pin < nr_ioapic_registers[apic]; pin++)
182 clear_IO_APIC_pin(apic, pin);
186 * support for broken MP BIOSs, enables hand-redirection of PIRQ0-7 to
187 * specific CPU-side IRQs.
191 static int pirq_entries [MAX_PIRQS];
192 static int pirqs_enabled;
193 int skip_ioapic_setup;
196 /* dummy parsing: see setup.c */
198 static int __init disable_ioapic_setup(char *str)
200 skip_ioapic_setup = 1;
204 static int __init enable_ioapic_setup(char *str)
207 skip_ioapic_setup = 0;
211 __setup("noapic", disable_ioapic_setup);
212 __setup("apic", enable_ioapic_setup);
214 #include <asm/pci-direct.h>
215 #include <linux/pci_ids.h>
216 #include <linux/pci.h>
218 /* Temporary Hack. Nvidia and VIA boards currently only work with IO-APIC
219 off. Check for an Nvidia or VIA PCI bridge and turn it off.
220 Use pci direct infrastructure because this runs before the PCI subsystem.
222 Can be overwritten with "apic"
224 And another hack to disable the IOMMU on VIA chipsets.
227 void __init check_ioapic(void)
233 /* Poor man's PCI discovery */
234 for (num = 0; num < 32; num++) {
235 for (slot = 0; slot < 32; slot++) {
236 for (func = 0; func < 8; func++) {
240 class = read_pci_config(num,slot,func,
242 if (class == 0xffffffff)
245 if ((class >> 16) != PCI_CLASS_BRIDGE_PCI)
248 vendor = read_pci_config(num, slot, func,
252 case PCI_VENDOR_ID_VIA:
253 #ifdef CONFIG_GART_IOMMU
254 if ((end_pfn >= (0xffffffff>>PAGE_SHIFT) ||
256 !iommu_aperture_allowed) {
258 "Looks like a VIA chipset. Disabling IOMMU. Overwrite with \"iommu=allowed\"\n");
259 iommu_aperture_disabled = 1;
263 case PCI_VENDOR_ID_NVIDIA:
265 /* All timer overrides on Nvidia
266 seem to be wrong. Skip them. */
267 acpi_skip_timer_override = 1;
269 "Nvidia board detected. Ignoring ACPI timer override.\n");
271 /* RED-PEN skip them on mptables too? */
275 /* No multi-function device? */
276 type = read_pci_config_byte(num,slot,func,
285 static int __init ioapic_pirq_setup(char *str)
288 int ints[MAX_PIRQS+1];
290 get_options(str, ARRAY_SIZE(ints), ints);
292 for (i = 0; i < MAX_PIRQS; i++)
293 pirq_entries[i] = -1;
296 apic_printk(APIC_VERBOSE, "PIRQ redirection, working around broken MP-BIOS.\n");
298 if (ints[0] < MAX_PIRQS)
301 for (i = 0; i < max; i++) {
302 apic_printk(APIC_VERBOSE, "... PIRQ%d -> IRQ %d\n", i, ints[i+1]);
304 * PIRQs are mapped upside down, usually.
306 pirq_entries[MAX_PIRQS-i-1] = ints[i+1];
311 __setup("pirq=", ioapic_pirq_setup);
314 * Find the IRQ entry number of a certain pin.
316 static int find_irq_entry(int apic, int pin, int type)
320 for (i = 0; i < mp_irq_entries; i++)
321 if (mp_irqs[i].mpc_irqtype == type &&
322 (mp_irqs[i].mpc_dstapic == mp_ioapics[apic].mpc_apicid ||
323 mp_irqs[i].mpc_dstapic == MP_APIC_ALL) &&
324 mp_irqs[i].mpc_dstirq == pin)
331 * Find the pin to which IRQ[irq] (ISA) is connected
333 static int find_isa_irq_pin(int irq, int type)
337 for (i = 0; i < mp_irq_entries; i++) {
338 int lbus = mp_irqs[i].mpc_srcbus;
340 if ((mp_bus_id_to_type[lbus] == MP_BUS_ISA ||
341 mp_bus_id_to_type[lbus] == MP_BUS_EISA ||
342 mp_bus_id_to_type[lbus] == MP_BUS_MCA) &&
343 (mp_irqs[i].mpc_irqtype == type) &&
344 (mp_irqs[i].mpc_srcbusirq == irq))
346 return mp_irqs[i].mpc_dstirq;
352 * Find a specific PCI IRQ entry.
353 * Not an __init, possibly needed by modules
355 static int pin_2_irq(int idx, int apic, int pin);
357 int IO_APIC_get_PCI_irq_vector(int bus, int slot, int pin)
359 int apic, i, best_guess = -1;
361 apic_printk(APIC_DEBUG, "querying PCI -> IRQ mapping bus:%d, slot:%d, pin:%d.\n",
363 if (mp_bus_id_to_pci_bus[bus] == -1) {
364 apic_printk(APIC_VERBOSE, "PCI BIOS passed nonexistent PCI bus %d!\n", bus);
367 for (i = 0; i < mp_irq_entries; i++) {
368 int lbus = mp_irqs[i].mpc_srcbus;
370 for (apic = 0; apic < nr_ioapics; apic++)
371 if (mp_ioapics[apic].mpc_apicid == mp_irqs[i].mpc_dstapic ||
372 mp_irqs[i].mpc_dstapic == MP_APIC_ALL)
375 if ((mp_bus_id_to_type[lbus] == MP_BUS_PCI) &&
376 !mp_irqs[i].mpc_irqtype &&
378 (slot == ((mp_irqs[i].mpc_srcbusirq >> 2) & 0x1f))) {
379 int irq = pin_2_irq(i,apic,mp_irqs[i].mpc_dstirq);
381 if (!(apic || IO_APIC_IRQ(irq)))
384 if (pin == (mp_irqs[i].mpc_srcbusirq & 3))
387 * Use the first all-but-pin matching entry as a
388 * best-guess fuzzy result for broken mptables.
398 * EISA Edge/Level control register, ELCR
400 static int EISA_ELCR(unsigned int irq)
403 unsigned int port = 0x4d0 + (irq >> 3);
404 return (inb(port) >> (irq & 7)) & 1;
406 apic_printk(APIC_VERBOSE, "Broken MPtable reports ISA irq %d\n", irq);
410 /* EISA interrupts are always polarity zero and can be edge or level
411 * trigger depending on the ELCR value. If an interrupt is listed as
412 * EISA conforming in the MP table, that means its trigger type must
413 * be read in from the ELCR */
415 #define default_EISA_trigger(idx) (EISA_ELCR(mp_irqs[idx].mpc_srcbusirq))
416 #define default_EISA_polarity(idx) (0)
418 /* ISA interrupts are always polarity zero edge triggered,
419 * when listed as conforming in the MP table. */
421 #define default_ISA_trigger(idx) (0)
422 #define default_ISA_polarity(idx) (0)
424 /* PCI interrupts are always polarity one level triggered,
425 * when listed as conforming in the MP table. */
427 #define default_PCI_trigger(idx) (1)
428 #define default_PCI_polarity(idx) (1)
430 /* MCA interrupts are always polarity zero level triggered,
431 * when listed as conforming in the MP table. */
433 #define default_MCA_trigger(idx) (1)
434 #define default_MCA_polarity(idx) (0)
436 static int __init MPBIOS_polarity(int idx)
438 int bus = mp_irqs[idx].mpc_srcbus;
442 * Determine IRQ line polarity (high active or low active):
444 switch (mp_irqs[idx].mpc_irqflag & 3)
446 case 0: /* conforms, ie. bus-type dependent polarity */
448 switch (mp_bus_id_to_type[bus])
450 case MP_BUS_ISA: /* ISA pin */
452 polarity = default_ISA_polarity(idx);
455 case MP_BUS_EISA: /* EISA pin */
457 polarity = default_EISA_polarity(idx);
460 case MP_BUS_PCI: /* PCI pin */
462 polarity = default_PCI_polarity(idx);
465 case MP_BUS_MCA: /* MCA pin */
467 polarity = default_MCA_polarity(idx);
472 printk(KERN_WARNING "broken BIOS!!\n");
479 case 1: /* high active */
484 case 2: /* reserved */
486 printk(KERN_WARNING "broken BIOS!!\n");
490 case 3: /* low active */
495 default: /* invalid */
497 printk(KERN_WARNING "broken BIOS!!\n");
505 static int MPBIOS_trigger(int idx)
507 int bus = mp_irqs[idx].mpc_srcbus;
511 * Determine IRQ trigger mode (edge or level sensitive):
513 switch ((mp_irqs[idx].mpc_irqflag>>2) & 3)
515 case 0: /* conforms, ie. bus-type dependent */
517 switch (mp_bus_id_to_type[bus])
519 case MP_BUS_ISA: /* ISA pin */
521 trigger = default_ISA_trigger(idx);
524 case MP_BUS_EISA: /* EISA pin */
526 trigger = default_EISA_trigger(idx);
529 case MP_BUS_PCI: /* PCI pin */
531 trigger = default_PCI_trigger(idx);
534 case MP_BUS_MCA: /* MCA pin */
536 trigger = default_MCA_trigger(idx);
541 printk(KERN_WARNING "broken BIOS!!\n");
553 case 2: /* reserved */
555 printk(KERN_WARNING "broken BIOS!!\n");
564 default: /* invalid */
566 printk(KERN_WARNING "broken BIOS!!\n");
574 static inline int irq_polarity(int idx)
576 return MPBIOS_polarity(idx);
579 static inline int irq_trigger(int idx)
581 return MPBIOS_trigger(idx);
584 static int pin_2_irq(int idx, int apic, int pin)
587 int bus = mp_irqs[idx].mpc_srcbus;
590 * Debugging check, we are in big trouble if this message pops up!
592 if (mp_irqs[idx].mpc_dstirq != pin)
593 printk(KERN_ERR "broken BIOS or MPTABLE parser, ayiee!!\n");
595 switch (mp_bus_id_to_type[bus])
597 case MP_BUS_ISA: /* ISA pin */
601 irq = mp_irqs[idx].mpc_srcbusirq;
604 case MP_BUS_PCI: /* PCI pin */
607 * PCI IRQs are mapped in order
611 irq += nr_ioapic_registers[i++];
617 printk(KERN_ERR "unknown bus type %d.\n",bus);
624 * PCI IRQ command line redirection. Yes, limits are hardcoded.
626 if ((pin >= 16) && (pin <= 23)) {
627 if (pirq_entries[pin-16] != -1) {
628 if (!pirq_entries[pin-16]) {
629 apic_printk(APIC_VERBOSE, "disabling PIRQ%d\n", pin-16);
631 irq = pirq_entries[pin-16];
632 apic_printk(APIC_VERBOSE, "using PIRQ%d -> IRQ %d\n",
640 static inline int IO_APIC_irq_trigger(int irq)
644 for (apic = 0; apic < nr_ioapics; apic++) {
645 for (pin = 0; pin < nr_ioapic_registers[apic]; pin++) {
646 idx = find_irq_entry(apic,pin,mp_INT);
647 if ((idx != -1) && (irq == pin_2_irq(idx,apic,pin)))
648 return irq_trigger(idx);
652 * nonexistent IRQs are edge default
657 /* irq_vectors is indexed by the sum of all RTEs in all I/O APICs. */
658 u8 irq_vector[NR_IRQ_VECTORS] = { FIRST_DEVICE_VECTOR , 0 };
660 int assign_irq_vector(int irq)
662 static int current_vector = FIRST_DEVICE_VECTOR, offset = 0;
664 BUG_ON(irq >= NR_IRQ_VECTORS);
665 if (IO_APIC_VECTOR(irq) > 0)
666 return IO_APIC_VECTOR(irq);
669 if (current_vector == IA32_SYSCALL_VECTOR)
672 if (current_vector >= FIRST_SYSTEM_VECTOR) {
676 current_vector = FIRST_DEVICE_VECTOR + offset;
679 vector_irq[current_vector] = irq;
680 if (irq != AUTO_ASSIGN)
681 IO_APIC_VECTOR(irq) = current_vector;
683 return current_vector;
686 extern void (*interrupt[NR_IRQS])(void);
687 static struct hw_interrupt_type ioapic_level_type;
688 static struct hw_interrupt_type ioapic_edge_type;
690 #define IOAPIC_AUTO -1
691 #define IOAPIC_EDGE 0
692 #define IOAPIC_LEVEL 1
694 static inline void ioapic_register_intr(int irq, int vector, unsigned long trigger)
696 if (use_pci_vector() && !platform_legacy_irq(irq)) {
697 if ((trigger == IOAPIC_AUTO && IO_APIC_irq_trigger(irq)) ||
698 trigger == IOAPIC_LEVEL)
699 irq_desc[vector].handler = &ioapic_level_type;
701 irq_desc[vector].handler = &ioapic_edge_type;
702 set_intr_gate(vector, interrupt[vector]);
704 if ((trigger == IOAPIC_AUTO && IO_APIC_irq_trigger(irq)) ||
705 trigger == IOAPIC_LEVEL)
706 irq_desc[irq].handler = &ioapic_level_type;
708 irq_desc[irq].handler = &ioapic_edge_type;
709 set_intr_gate(vector, interrupt[irq]);
713 static void __init setup_IO_APIC_irqs(void)
715 struct IO_APIC_route_entry entry;
716 int apic, pin, idx, irq, first_notcon = 1, vector;
719 apic_printk(APIC_VERBOSE, KERN_DEBUG "init IO_APIC IRQs\n");
721 for (apic = 0; apic < nr_ioapics; apic++) {
722 for (pin = 0; pin < nr_ioapic_registers[apic]; pin++) {
725 * add it to the IO-APIC irq-routing table:
727 memset(&entry,0,sizeof(entry));
729 entry.delivery_mode = INT_DELIVERY_MODE;
730 entry.dest_mode = INT_DEST_MODE;
731 entry.mask = 0; /* enable IRQ */
732 entry.dest.logical.logical_dest = cpu_mask_to_apicid(TARGET_CPUS);
734 idx = find_irq_entry(apic,pin,mp_INT);
737 apic_printk(APIC_VERBOSE, KERN_DEBUG " IO-APIC (apicid-pin) %d-%d", mp_ioapics[apic].mpc_apicid, pin);
740 apic_printk(APIC_VERBOSE, ", %d-%d", mp_ioapics[apic].mpc_apicid, pin);
744 entry.trigger = irq_trigger(idx);
745 entry.polarity = irq_polarity(idx);
747 if (irq_trigger(idx)) {
750 entry.dest.logical.logical_dest = cpu_mask_to_apicid(TARGET_CPUS);
753 irq = pin_2_irq(idx, apic, pin);
754 add_pin_to_irq(irq, apic, pin);
756 if (!apic && !IO_APIC_IRQ(irq))
759 if (IO_APIC_IRQ(irq)) {
760 vector = assign_irq_vector(irq);
761 entry.vector = vector;
763 ioapic_register_intr(irq, vector, IOAPIC_AUTO);
764 if (!apic && (irq < 16))
765 disable_8259A_irq(irq);
767 spin_lock_irqsave(&ioapic_lock, flags);
768 io_apic_write(apic, 0x11+2*pin, *(((int *)&entry)+1));
769 io_apic_write(apic, 0x10+2*pin, *(((int *)&entry)+0));
770 spin_unlock_irqrestore(&ioapic_lock, flags);
775 apic_printk(APIC_VERBOSE," not connected.\n");
779 * Set up the 8259A-master output pin as broadcast to all
782 static void __init setup_ExtINT_IRQ0_pin(unsigned int pin, int vector)
784 struct IO_APIC_route_entry entry;
787 memset(&entry,0,sizeof(entry));
789 disable_8259A_irq(0);
792 apic_write_around(APIC_LVT0, APIC_LVT_MASKED | APIC_DM_EXTINT);
795 * We use logical delivery to get the timer IRQ
798 entry.dest_mode = INT_DEST_MODE;
799 entry.mask = 0; /* unmask IRQ now */
800 entry.dest.logical.logical_dest = cpu_mask_to_apicid(TARGET_CPUS);
801 entry.delivery_mode = INT_DELIVERY_MODE;
804 entry.vector = vector;
807 * The timer IRQ doesn't have to know that behind the
808 * scene we have a 8259A-master in AEOI mode ...
810 irq_desc[0].handler = &ioapic_edge_type;
813 * Add it to the IO-APIC irq-routing table:
815 spin_lock_irqsave(&ioapic_lock, flags);
816 io_apic_write(0, 0x11+2*pin, *(((int *)&entry)+1));
817 io_apic_write(0, 0x10+2*pin, *(((int *)&entry)+0));
818 spin_unlock_irqrestore(&ioapic_lock, flags);
823 void __init UNEXPECTED_IO_APIC(void)
827 void __apicdebuginit print_IO_APIC(void)
830 union IO_APIC_reg_00 reg_00;
831 union IO_APIC_reg_01 reg_01;
832 union IO_APIC_reg_02 reg_02;
835 if (apic_verbosity == APIC_QUIET)
838 printk(KERN_DEBUG "number of MP IRQ sources: %d.\n", mp_irq_entries);
839 for (i = 0; i < nr_ioapics; i++)
840 printk(KERN_DEBUG "number of IO-APIC #%d registers: %d.\n",
841 mp_ioapics[i].mpc_apicid, nr_ioapic_registers[i]);
844 * We are a bit conservative about what we expect. We have to
845 * know about every hardware change ASAP.
847 printk(KERN_INFO "testing the IO APIC.......................\n");
849 for (apic = 0; apic < nr_ioapics; apic++) {
851 spin_lock_irqsave(&ioapic_lock, flags);
852 reg_00.raw = io_apic_read(apic, 0);
853 reg_01.raw = io_apic_read(apic, 1);
854 if (reg_01.bits.version >= 0x10)
855 reg_02.raw = io_apic_read(apic, 2);
856 spin_unlock_irqrestore(&ioapic_lock, flags);
859 printk(KERN_DEBUG "IO APIC #%d......\n", mp_ioapics[apic].mpc_apicid);
860 printk(KERN_DEBUG ".... register #00: %08X\n", reg_00.raw);
861 printk(KERN_DEBUG "....... : physical APIC id: %02X\n", reg_00.bits.ID);
862 if (reg_00.bits.__reserved_1 || reg_00.bits.__reserved_2)
863 UNEXPECTED_IO_APIC();
865 printk(KERN_DEBUG ".... register #01: %08X\n", *(int *)®_01);
866 printk(KERN_DEBUG "....... : max redirection entries: %04X\n", reg_01.bits.entries);
867 if ( (reg_01.bits.entries != 0x0f) && /* older (Neptune) boards */
868 (reg_01.bits.entries != 0x17) && /* typical ISA+PCI boards */
869 (reg_01.bits.entries != 0x1b) && /* Compaq Proliant boards */
870 (reg_01.bits.entries != 0x1f) && /* dual Xeon boards */
871 (reg_01.bits.entries != 0x22) && /* bigger Xeon boards */
872 (reg_01.bits.entries != 0x2E) &&
873 (reg_01.bits.entries != 0x3F) &&
874 (reg_01.bits.entries != 0x03)
876 UNEXPECTED_IO_APIC();
878 printk(KERN_DEBUG "....... : PRQ implemented: %X\n", reg_01.bits.PRQ);
879 printk(KERN_DEBUG "....... : IO APIC version: %04X\n", reg_01.bits.version);
880 if ( (reg_01.bits.version != 0x01) && /* 82489DX IO-APICs */
881 (reg_01.bits.version != 0x02) && /* 82801BA IO-APICs (ICH2) */
882 (reg_01.bits.version != 0x10) && /* oldest IO-APICs */
883 (reg_01.bits.version != 0x11) && /* Pentium/Pro IO-APICs */
884 (reg_01.bits.version != 0x13) && /* Xeon IO-APICs */
885 (reg_01.bits.version != 0x20) /* Intel P64H (82806 AA) */
887 UNEXPECTED_IO_APIC();
888 if (reg_01.bits.__reserved_1 || reg_01.bits.__reserved_2)
889 UNEXPECTED_IO_APIC();
891 if (reg_01.bits.version >= 0x10) {
892 printk(KERN_DEBUG ".... register #02: %08X\n", reg_02.raw);
893 printk(KERN_DEBUG "....... : arbitration: %02X\n", reg_02.bits.arbitration);
894 if (reg_02.bits.__reserved_1 || reg_02.bits.__reserved_2)
895 UNEXPECTED_IO_APIC();
898 printk(KERN_DEBUG ".... IRQ redirection table:\n");
900 printk(KERN_DEBUG " NR Log Phy Mask Trig IRR Pol"
901 " Stat Dest Deli Vect: \n");
903 for (i = 0; i <= reg_01.bits.entries; i++) {
904 struct IO_APIC_route_entry entry;
906 spin_lock_irqsave(&ioapic_lock, flags);
907 *(((int *)&entry)+0) = io_apic_read(apic, 0x10+i*2);
908 *(((int *)&entry)+1) = io_apic_read(apic, 0x11+i*2);
909 spin_unlock_irqrestore(&ioapic_lock, flags);
911 printk(KERN_DEBUG " %02x %03X %02X ",
913 entry.dest.logical.logical_dest,
914 entry.dest.physical.physical_dest
917 printk("%1d %1d %1d %1d %1d %1d %1d %02X\n",
922 entry.delivery_status,
929 if (use_pci_vector())
930 printk(KERN_INFO "Using vector-based indexing\n");
931 printk(KERN_DEBUG "IRQ to pin mappings:\n");
932 for (i = 0; i < NR_IRQS; i++) {
933 struct irq_pin_list *entry = irq_2_pin + i;
936 if (use_pci_vector() && !platform_legacy_irq(i))
937 printk(KERN_DEBUG "IRQ%d ", IO_APIC_VECTOR(i));
939 printk(KERN_DEBUG "IRQ%d ", i);
941 printk("-> %d:%d", entry->apic, entry->pin);
944 entry = irq_2_pin + entry->next;
949 printk(KERN_INFO ".................................... done.\n");
956 static __apicdebuginit void print_APIC_bitfield (int base)
961 if (apic_verbosity == APIC_QUIET)
964 printk(KERN_DEBUG "0123456789abcdef0123456789abcdef\n" KERN_DEBUG);
965 for (i = 0; i < 8; i++) {
966 v = apic_read(base + i*0x10);
967 for (j = 0; j < 32; j++) {
977 void __apicdebuginit print_local_APIC(void * dummy)
979 unsigned int v, ver, maxlvt;
981 if (apic_verbosity == APIC_QUIET)
984 printk("\n" KERN_DEBUG "printing local APIC contents on CPU#%d/%d:\n",
985 smp_processor_id(), hard_smp_processor_id());
986 v = apic_read(APIC_ID);
987 printk(KERN_INFO "... APIC ID: %08x (%01x)\n", v, GET_APIC_ID(v));
988 v = apic_read(APIC_LVR);
989 printk(KERN_INFO "... APIC VERSION: %08x\n", v);
990 ver = GET_APIC_VERSION(v);
991 maxlvt = get_maxlvt();
993 v = apic_read(APIC_TASKPRI);
994 printk(KERN_DEBUG "... APIC TASKPRI: %08x (%02x)\n", v, v & APIC_TPRI_MASK);
996 if (APIC_INTEGRATED(ver)) { /* !82489DX */
997 v = apic_read(APIC_ARBPRI);
998 printk(KERN_DEBUG "... APIC ARBPRI: %08x (%02x)\n", v,
999 v & APIC_ARBPRI_MASK);
1000 v = apic_read(APIC_PROCPRI);
1001 printk(KERN_DEBUG "... APIC PROCPRI: %08x\n", v);
1004 v = apic_read(APIC_EOI);
1005 printk(KERN_DEBUG "... APIC EOI: %08x\n", v);
1006 v = apic_read(APIC_RRR);
1007 printk(KERN_DEBUG "... APIC RRR: %08x\n", v);
1008 v = apic_read(APIC_LDR);
1009 printk(KERN_DEBUG "... APIC LDR: %08x\n", v);
1010 v = apic_read(APIC_DFR);
1011 printk(KERN_DEBUG "... APIC DFR: %08x\n", v);
1012 v = apic_read(APIC_SPIV);
1013 printk(KERN_DEBUG "... APIC SPIV: %08x\n", v);
1015 printk(KERN_DEBUG "... APIC ISR field:\n");
1016 print_APIC_bitfield(APIC_ISR);
1017 printk(KERN_DEBUG "... APIC TMR field:\n");
1018 print_APIC_bitfield(APIC_TMR);
1019 printk(KERN_DEBUG "... APIC IRR field:\n");
1020 print_APIC_bitfield(APIC_IRR);
1022 if (APIC_INTEGRATED(ver)) { /* !82489DX */
1023 if (maxlvt > 3) /* Due to the Pentium erratum 3AP. */
1024 apic_write(APIC_ESR, 0);
1025 v = apic_read(APIC_ESR);
1026 printk(KERN_DEBUG "... APIC ESR: %08x\n", v);
1029 v = apic_read(APIC_ICR);
1030 printk(KERN_DEBUG "... APIC ICR: %08x\n", v);
1031 v = apic_read(APIC_ICR2);
1032 printk(KERN_DEBUG "... APIC ICR2: %08x\n", v);
1034 v = apic_read(APIC_LVTT);
1035 printk(KERN_DEBUG "... APIC LVTT: %08x\n", v);
1037 if (maxlvt > 3) { /* PC is LVT#4. */
1038 v = apic_read(APIC_LVTPC);
1039 printk(KERN_DEBUG "... APIC LVTPC: %08x\n", v);
1041 v = apic_read(APIC_LVT0);
1042 printk(KERN_DEBUG "... APIC LVT0: %08x\n", v);
1043 v = apic_read(APIC_LVT1);
1044 printk(KERN_DEBUG "... APIC LVT1: %08x\n", v);
1046 if (maxlvt > 2) { /* ERR is LVT#3. */
1047 v = apic_read(APIC_LVTERR);
1048 printk(KERN_DEBUG "... APIC LVTERR: %08x\n", v);
1051 v = apic_read(APIC_TMICT);
1052 printk(KERN_DEBUG "... APIC TMICT: %08x\n", v);
1053 v = apic_read(APIC_TMCCT);
1054 printk(KERN_DEBUG "... APIC TMCCT: %08x\n", v);
1055 v = apic_read(APIC_TDCR);
1056 printk(KERN_DEBUG "... APIC TDCR: %08x\n", v);
1060 void print_all_local_APICs (void)
1062 on_each_cpu(print_local_APIC, NULL, 1, 1);
1065 void __apicdebuginit print_PIC(void)
1067 extern spinlock_t i8259A_lock;
1069 unsigned long flags;
1071 if (apic_verbosity == APIC_QUIET)
1074 printk(KERN_DEBUG "\nprinting PIC contents\n");
1076 spin_lock_irqsave(&i8259A_lock, flags);
1078 v = inb(0xa1) << 8 | inb(0x21);
1079 printk(KERN_DEBUG "... PIC IMR: %04x\n", v);
1081 v = inb(0xa0) << 8 | inb(0x20);
1082 printk(KERN_DEBUG "... PIC IRR: %04x\n", v);
1086 v = inb(0xa0) << 8 | inb(0x20);
1090 spin_unlock_irqrestore(&i8259A_lock, flags);
1092 printk(KERN_DEBUG "... PIC ISR: %04x\n", v);
1094 v = inb(0x4d1) << 8 | inb(0x4d0);
1095 printk(KERN_DEBUG "... PIC ELCR: %04x\n", v);
1100 static void __init enable_IO_APIC(void)
1102 union IO_APIC_reg_01 reg_01;
1104 unsigned long flags;
1106 for (i = 0; i < PIN_MAP_SIZE; i++) {
1107 irq_2_pin[i].pin = -1;
1108 irq_2_pin[i].next = 0;
1111 for (i = 0; i < MAX_PIRQS; i++)
1112 pirq_entries[i] = -1;
1115 * The number of IO-APIC IRQ registers (== #pins):
1117 for (i = 0; i < nr_ioapics; i++) {
1118 spin_lock_irqsave(&ioapic_lock, flags);
1119 reg_01.raw = io_apic_read(i, 1);
1120 spin_unlock_irqrestore(&ioapic_lock, flags);
1121 nr_ioapic_registers[i] = reg_01.bits.entries+1;
1125 * Do not trust the IO-APIC being empty at bootup
1131 * Not an __init, needed by the reboot code
1133 void disable_IO_APIC(void)
1137 * Clear the IO-APIC before rebooting:
1142 * If the i82559 is routed through an IOAPIC
1143 * Put that IOAPIC in virtual wire mode
1144 * so legacy interrups can be delivered.
1146 pin = find_isa_irq_pin(0, mp_ExtINT);
1148 struct IO_APIC_route_entry entry;
1149 unsigned long flags;
1151 memset(&entry, 0, sizeof(entry));
1152 entry.mask = 0; /* Enabled */
1153 entry.trigger = 0; /* Edge */
1155 entry.polarity = 0; /* High */
1156 entry.delivery_status = 0;
1157 entry.dest_mode = 0; /* Physical */
1158 entry.delivery_mode = 7; /* ExtInt */
1160 entry.dest.physical.physical_dest = 0;
1164 * Add it to the IO-APIC irq-routing table:
1166 spin_lock_irqsave(&ioapic_lock, flags);
1167 io_apic_write(0, 0x11+2*pin, *(((int *)&entry)+1));
1168 io_apic_write(0, 0x10+2*pin, *(((int *)&entry)+0));
1169 spin_unlock_irqrestore(&ioapic_lock, flags);
1172 disconnect_bsp_APIC(pin != -1);
1176 * function to set the IO-APIC physical IDs based on the
1177 * values stored in the MPC table.
1179 * by Matt Domsch <Matt_Domsch@dell.com> Tue Dec 21 12:25:05 CST 1999
1182 static void __init setup_ioapic_ids_from_mpc (void)
1184 union IO_APIC_reg_00 reg_00;
1187 unsigned char old_id;
1188 unsigned long flags;
1191 * Set the IOAPIC ID to the value stored in the MPC table.
1193 for (apic = 0; apic < nr_ioapics; apic++) {
1195 /* Read the register 0 value */
1196 spin_lock_irqsave(&ioapic_lock, flags);
1197 reg_00.raw = io_apic_read(apic, 0);
1198 spin_unlock_irqrestore(&ioapic_lock, flags);
1200 old_id = mp_ioapics[apic].mpc_apicid;
1203 printk(KERN_INFO "Using IO-APIC %d\n", mp_ioapics[apic].mpc_apicid);
1207 * We need to adjust the IRQ routing table
1208 * if the ID changed.
1210 if (old_id != mp_ioapics[apic].mpc_apicid)
1211 for (i = 0; i < mp_irq_entries; i++)
1212 if (mp_irqs[i].mpc_dstapic == old_id)
1213 mp_irqs[i].mpc_dstapic
1214 = mp_ioapics[apic].mpc_apicid;
1217 * Read the right value from the MPC table and
1218 * write it into the ID register.
1220 apic_printk(APIC_VERBOSE,KERN_INFO "...changing IO-APIC physical APIC ID to %d ...",
1221 mp_ioapics[apic].mpc_apicid);
1223 reg_00.bits.ID = mp_ioapics[apic].mpc_apicid;
1224 spin_lock_irqsave(&ioapic_lock, flags);
1225 io_apic_write(apic, 0, reg_00.raw);
1226 spin_unlock_irqrestore(&ioapic_lock, flags);
1231 spin_lock_irqsave(&ioapic_lock, flags);
1232 reg_00.raw = io_apic_read(apic, 0);
1233 spin_unlock_irqrestore(&ioapic_lock, flags);
1234 if (reg_00.bits.ID != mp_ioapics[apic].mpc_apicid)
1235 printk("could not set ID!\n");
1237 apic_printk(APIC_VERBOSE," ok.\n");
1242 * There is a nasty bug in some older SMP boards, their mptable lies
1243 * about the timer IRQ. We do the following to work around the situation:
1245 * - timer IRQ defaults to IO-APIC IRQ
1246 * - if this function detects that timer IRQs are defunct, then we fall
1247 * back to ISA timer IRQs
1249 static int __init timer_irq_works(void)
1251 unsigned long t1 = jiffies;
1254 /* Let ten ticks pass... */
1255 mdelay((10 * 1000) / HZ);
1258 * Expect a few ticks at least, to be sure some possible
1259 * glue logic does not lock up after one or two first
1260 * ticks in a non-ExtINT mode. Also the local APIC
1261 * might have cached one ExtINT interrupt. Finally, at
1262 * least one tick may be lost due to delays.
1266 if (jiffies - t1 > 4)
1272 * In the SMP+IOAPIC case it might happen that there are an unspecified
1273 * number of pending IRQ events unhandled. These cases are very rare,
1274 * so we 'resend' these IRQs via IPIs, to the same CPU. It's much
1275 * better to do it this way as thus we do not have to be aware of
1276 * 'pending' interrupts in the IRQ path, except at this point.
1279 * Edge triggered needs to resend any interrupt
1280 * that was delayed but this is now handled in the device
1285 * Starting up a edge-triggered IO-APIC interrupt is
1286 * nasty - we need to make sure that we get the edge.
1287 * If it is already asserted for some reason, we need
1288 * return 1 to indicate that is was pending.
1290 * This is not complete - we should be able to fake
1291 * an edge even if it isn't on the 8259A...
1294 static unsigned int startup_edge_ioapic_irq(unsigned int irq)
1296 int was_pending = 0;
1297 unsigned long flags;
1299 spin_lock_irqsave(&ioapic_lock, flags);
1301 disable_8259A_irq(irq);
1302 if (i8259A_irq_pending(irq))
1305 __unmask_IO_APIC_irq(irq);
1306 spin_unlock_irqrestore(&ioapic_lock, flags);
1312 * Once we have recorded IRQ_PENDING already, we can mask the
1313 * interrupt for real. This prevents IRQ storms from unhandled
1316 static void ack_edge_ioapic_irq(unsigned int irq)
1318 if ((irq_desc[irq].status & (IRQ_PENDING | IRQ_DISABLED))
1319 == (IRQ_PENDING | IRQ_DISABLED))
1320 mask_IO_APIC_irq(irq);
1325 * Level triggered interrupts can just be masked,
1326 * and shutting down and starting up the interrupt
1327 * is the same as enabling and disabling them -- except
1328 * with a startup need to return a "was pending" value.
1330 * Level triggered interrupts are special because we
1331 * do not touch any IO-APIC register while handling
1332 * them. We ack the APIC in the end-IRQ handler, not
1333 * in the start-IRQ-handler. Protection against reentrance
1334 * from the same interrupt is still provided, both by the
1335 * generic IRQ layer and by the fact that an unacked local
1336 * APIC does not accept IRQs.
1338 static unsigned int startup_level_ioapic_irq (unsigned int irq)
1340 unmask_IO_APIC_irq(irq);
1342 return 0; /* don't check for pending */
1345 static void end_level_ioapic_irq (unsigned int irq)
1350 static void set_ioapic_affinity_irq(unsigned int irq, cpumask_t mask)
1352 unsigned long flags;
1355 dest = cpu_mask_to_apicid(mask);
1358 * Only the high 8 bits are valid.
1360 dest = SET_APIC_LOGICAL_ID(dest);
1362 spin_lock_irqsave(&ioapic_lock, flags);
1363 __DO_ACTION(1, = dest, )
1364 spin_unlock_irqrestore(&ioapic_lock, flags);
1367 #ifdef CONFIG_PCI_MSI
1368 static unsigned int startup_edge_ioapic_vector(unsigned int vector)
1370 int irq = vector_to_irq(vector);
1372 return startup_edge_ioapic_irq(irq);
1375 static void ack_edge_ioapic_vector(unsigned int vector)
1377 int irq = vector_to_irq(vector);
1379 ack_edge_ioapic_irq(irq);
1382 static unsigned int startup_level_ioapic_vector (unsigned int vector)
1384 int irq = vector_to_irq(vector);
1386 return startup_level_ioapic_irq (irq);
1389 static void end_level_ioapic_vector (unsigned int vector)
1391 int irq = vector_to_irq(vector);
1393 end_level_ioapic_irq(irq);
1396 static void mask_IO_APIC_vector (unsigned int vector)
1398 int irq = vector_to_irq(vector);
1400 mask_IO_APIC_irq(irq);
1403 static void unmask_IO_APIC_vector (unsigned int vector)
1405 int irq = vector_to_irq(vector);
1407 unmask_IO_APIC_irq(irq);
1410 static void set_ioapic_affinity_vector (unsigned int vector,
1413 int irq = vector_to_irq(vector);
1415 set_ioapic_affinity_irq(irq, cpu_mask);
1420 * Level and edge triggered IO-APIC interrupts need different handling,
1421 * so we use two separate IRQ descriptors. Edge triggered IRQs can be
1422 * handled with the level-triggered descriptor, but that one has slightly
1423 * more overhead. Level-triggered interrupts cannot be handled with the
1424 * edge-triggered handler, without risking IRQ storms and other ugly
1428 static struct hw_interrupt_type ioapic_edge_type = {
1429 .typename = "IO-APIC-edge",
1430 .startup = startup_edge_ioapic,
1431 .shutdown = shutdown_edge_ioapic,
1432 .enable = enable_edge_ioapic,
1433 .disable = disable_edge_ioapic,
1434 .ack = ack_edge_ioapic,
1435 .end = end_edge_ioapic,
1436 .set_affinity = set_ioapic_affinity,
1439 static struct hw_interrupt_type ioapic_level_type = {
1440 .typename = "IO-APIC-level",
1441 .startup = startup_level_ioapic,
1442 .shutdown = shutdown_level_ioapic,
1443 .enable = enable_level_ioapic,
1444 .disable = disable_level_ioapic,
1445 .ack = mask_and_ack_level_ioapic,
1446 .end = end_level_ioapic,
1447 .set_affinity = set_ioapic_affinity,
1450 static inline void init_IO_APIC_traps(void)
1455 * NOTE! The local APIC isn't very good at handling
1456 * multiple interrupts at the same interrupt level.
1457 * As the interrupt level is determined by taking the
1458 * vector number and shifting that right by 4, we
1459 * want to spread these out a bit so that they don't
1460 * all fall in the same interrupt level.
1462 * Also, we've got to be careful not to trash gate
1463 * 0x80, because int 0x80 is hm, kind of importantish. ;)
1465 for (irq = 0; irq < NR_IRQS ; irq++) {
1467 if (use_pci_vector()) {
1468 if (!platform_legacy_irq(tmp))
1469 if ((tmp = vector_to_irq(tmp)) == -1)
1472 if (IO_APIC_IRQ(tmp) && !IO_APIC_VECTOR(tmp)) {
1474 * Hmm.. We don't have an entry for this,
1475 * so default to an old-fashioned 8259
1476 * interrupt if we can..
1479 make_8259A_irq(irq);
1481 /* Strange. Oh, well.. */
1482 irq_desc[irq].handler = &no_irq_type;
1487 static void enable_lapic_irq (unsigned int irq)
1491 v = apic_read(APIC_LVT0);
1492 apic_write_around(APIC_LVT0, v & ~APIC_LVT_MASKED);
1495 static void disable_lapic_irq (unsigned int irq)
1499 v = apic_read(APIC_LVT0);
1500 apic_write_around(APIC_LVT0, v | APIC_LVT_MASKED);
1503 static void ack_lapic_irq (unsigned int irq)
1508 static void end_lapic_irq (unsigned int i) { /* nothing */ }
1510 static struct hw_interrupt_type lapic_irq_type = {
1511 .typename = "local-APIC-edge",
1512 .startup = NULL, /* startup_irq() not used for IRQ0 */
1513 .shutdown = NULL, /* shutdown_irq() not used for IRQ0 */
1514 .enable = enable_lapic_irq,
1515 .disable = disable_lapic_irq,
1516 .ack = ack_lapic_irq,
1517 .end = end_lapic_irq,
1520 static void setup_nmi (void)
1523 * Dirty trick to enable the NMI watchdog ...
1524 * We put the 8259A master into AEOI mode and
1525 * unmask on all local APICs LVT0 as NMI.
1527 * The idea to use the 8259A in AEOI mode ('8259A Virtual Wire')
1528 * is from Maciej W. Rozycki - so we do not have to EOI from
1529 * the NMI handler or the timer interrupt.
1531 printk(KERN_INFO "activating NMI Watchdog ...");
1533 enable_NMI_through_LVT0(NULL);
1539 * This looks a bit hackish but it's about the only one way of sending
1540 * a few INTA cycles to 8259As and any associated glue logic. ICR does
1541 * not support the ExtINT mode, unfortunately. We need to send these
1542 * cycles as some i82489DX-based boards have glue logic that keeps the
1543 * 8259A interrupt line asserted until INTA. --macro
1545 static inline void unlock_ExtINT_logic(void)
1548 struct IO_APIC_route_entry entry0, entry1;
1549 unsigned char save_control, save_freq_select;
1550 unsigned long flags;
1552 pin = find_isa_irq_pin(8, mp_INT);
1556 spin_lock_irqsave(&ioapic_lock, flags);
1557 *(((int *)&entry0) + 1) = io_apic_read(0, 0x11 + 2 * pin);
1558 *(((int *)&entry0) + 0) = io_apic_read(0, 0x10 + 2 * pin);
1559 spin_unlock_irqrestore(&ioapic_lock, flags);
1560 clear_IO_APIC_pin(0, pin);
1562 memset(&entry1, 0, sizeof(entry1));
1564 entry1.dest_mode = 0; /* physical delivery */
1565 entry1.mask = 0; /* unmask IRQ now */
1566 entry1.dest.physical.physical_dest = hard_smp_processor_id();
1567 entry1.delivery_mode = dest_ExtINT;
1568 entry1.polarity = entry0.polarity;
1572 spin_lock_irqsave(&ioapic_lock, flags);
1573 io_apic_write(0, 0x11 + 2 * pin, *(((int *)&entry1) + 1));
1574 io_apic_write(0, 0x10 + 2 * pin, *(((int *)&entry1) + 0));
1575 spin_unlock_irqrestore(&ioapic_lock, flags);
1577 save_control = CMOS_READ(RTC_CONTROL);
1578 save_freq_select = CMOS_READ(RTC_FREQ_SELECT);
1579 CMOS_WRITE((save_freq_select & ~RTC_RATE_SELECT) | 0x6,
1581 CMOS_WRITE(save_control | RTC_PIE, RTC_CONTROL);
1586 if ((CMOS_READ(RTC_INTR_FLAGS) & RTC_PF) == RTC_PF)
1590 CMOS_WRITE(save_control, RTC_CONTROL);
1591 CMOS_WRITE(save_freq_select, RTC_FREQ_SELECT);
1592 clear_IO_APIC_pin(0, pin);
1594 spin_lock_irqsave(&ioapic_lock, flags);
1595 io_apic_write(0, 0x11 + 2 * pin, *(((int *)&entry0) + 1));
1596 io_apic_write(0, 0x10 + 2 * pin, *(((int *)&entry0) + 0));
1597 spin_unlock_irqrestore(&ioapic_lock, flags);
1601 * This code may look a bit paranoid, but it's supposed to cooperate with
1602 * a wide range of boards and BIOS bugs. Fortunately only the timer IRQ
1603 * is so screwy. Thanks to Brian Perkins for testing/hacking this beast
1604 * fanatically on his truly buggy board.
1606 static inline void check_timer(void)
1612 * get/set the timer IRQ vector:
1614 disable_8259A_irq(0);
1615 vector = assign_irq_vector(0);
1616 set_intr_gate(vector, interrupt[0]);
1619 * Subtle, code in do_timer_interrupt() expects an AEOI
1620 * mode for the 8259A whenever interrupts are routed
1621 * through I/O APICs. Also IRQ0 has to be enabled in
1622 * the 8259A which implies the virtual wire has to be
1623 * disabled in the local APIC.
1625 apic_write_around(APIC_LVT0, APIC_LVT_MASKED | APIC_DM_EXTINT);
1627 enable_8259A_irq(0);
1629 pin1 = find_isa_irq_pin(0, mp_INT);
1630 pin2 = find_isa_irq_pin(0, mp_ExtINT);
1632 apic_printk(APIC_VERBOSE,KERN_INFO "..TIMER: vector=0x%02X pin1=%d pin2=%d\n", vector, pin1, pin2);
1636 * Ok, does IRQ0 through the IOAPIC work?
1638 unmask_IO_APIC_irq(0);
1639 if (!no_timer_check && timer_irq_works()) {
1640 nmi_watchdog_default();
1641 if (nmi_watchdog == NMI_IO_APIC) {
1642 disable_8259A_irq(0);
1644 enable_8259A_irq(0);
1648 clear_IO_APIC_pin(0, pin1);
1649 apic_printk(APIC_QUIET,KERN_ERR "..MP-BIOS bug: 8254 timer not connected to IO-APIC\n");
1652 apic_printk(APIC_VERBOSE,KERN_INFO "...trying to set up timer (IRQ0) through the 8259A ... ");
1654 apic_printk(APIC_VERBOSE,"\n..... (found pin %d) ...", pin2);
1656 * legacy devices should be connected to IO APIC #0
1658 setup_ExtINT_IRQ0_pin(pin2, vector);
1659 if (timer_irq_works()) {
1661 nmi_watchdog_default();
1662 if (nmi_watchdog == NMI_IO_APIC) {
1668 * Cleanup, just in case ...
1670 clear_IO_APIC_pin(0, pin2);
1672 printk(" failed.\n");
1675 printk(KERN_WARNING "timer doesn't work through the IO-APIC - disabling NMI Watchdog!\n");
1679 apic_printk(APIC_VERBOSE, KERN_INFO "...trying to set up timer as Virtual Wire IRQ...");
1681 disable_8259A_irq(0);
1682 irq_desc[0].handler = &lapic_irq_type;
1683 apic_write_around(APIC_LVT0, APIC_DM_FIXED | vector); /* Fixed mode */
1684 enable_8259A_irq(0);
1686 if (timer_irq_works()) {
1687 apic_printk(APIC_QUIET, " works.\n");
1690 apic_write_around(APIC_LVT0, APIC_LVT_MASKED | APIC_DM_FIXED | vector);
1691 apic_printk(APIC_VERBOSE," failed.\n");
1693 apic_printk(APIC_VERBOSE, KERN_INFO "...trying to set up timer as ExtINT IRQ...");
1697 apic_write_around(APIC_LVT0, APIC_DM_EXTINT);
1699 unlock_ExtINT_logic();
1701 if (timer_irq_works()) {
1702 apic_printk(APIC_VERBOSE," works.\n");
1705 apic_printk(APIC_VERBOSE," failed :(.\n");
1706 panic("IO-APIC + timer doesn't work! Try using the 'noapic' kernel parameter\n");
1709 static int __init notimercheck(char *s)
1714 __setup("no_timer_check", notimercheck);
1718 * IRQ's that are handled by the PIC in the MPS IOAPIC case.
1719 * - IRQ2 is the cascade IRQ, and cannot be a io-apic IRQ.
1720 * Linux doesn't really care, as it's not actually used
1721 * for any interrupt handling anyway.
1723 #define PIC_IRQS (1<<2)
1725 void __init setup_IO_APIC(void)
1730 io_apic_irqs = ~0; /* all IRQs go through IOAPIC */
1732 io_apic_irqs = ~PIC_IRQS;
1734 apic_printk(APIC_VERBOSE, "ENABLING IO-APIC IRQs\n");
1737 * Set up the IO-APIC IRQ routing table.
1740 setup_ioapic_ids_from_mpc();
1742 setup_IO_APIC_irqs();
1743 init_IO_APIC_traps();
1749 struct sysfs_ioapic_data {
1750 struct sys_device dev;
1751 struct IO_APIC_route_entry entry[0];
1753 static struct sysfs_ioapic_data * mp_ioapic_data[MAX_IO_APICS];
1755 static int ioapic_suspend(struct sys_device *dev, pm_message_t state)
1757 struct IO_APIC_route_entry *entry;
1758 struct sysfs_ioapic_data *data;
1759 unsigned long flags;
1762 data = container_of(dev, struct sysfs_ioapic_data, dev);
1763 entry = data->entry;
1764 spin_lock_irqsave(&ioapic_lock, flags);
1765 for (i = 0; i < nr_ioapic_registers[dev->id]; i ++, entry ++ ) {
1766 *(((int *)entry) + 1) = io_apic_read(dev->id, 0x11 + 2 * i);
1767 *(((int *)entry) + 0) = io_apic_read(dev->id, 0x10 + 2 * i);
1769 spin_unlock_irqrestore(&ioapic_lock, flags);
1774 static int ioapic_resume(struct sys_device *dev)
1776 struct IO_APIC_route_entry *entry;
1777 struct sysfs_ioapic_data *data;
1778 unsigned long flags;
1779 union IO_APIC_reg_00 reg_00;
1782 data = container_of(dev, struct sysfs_ioapic_data, dev);
1783 entry = data->entry;
1785 spin_lock_irqsave(&ioapic_lock, flags);
1786 reg_00.raw = io_apic_read(dev->id, 0);
1787 if (reg_00.bits.ID != mp_ioapics[dev->id].mpc_apicid) {
1788 reg_00.bits.ID = mp_ioapics[dev->id].mpc_apicid;
1789 io_apic_write(dev->id, 0, reg_00.raw);
1791 for (i = 0; i < nr_ioapic_registers[dev->id]; i ++, entry ++ ) {
1792 io_apic_write(dev->id, 0x11+2*i, *(((int *)entry)+1));
1793 io_apic_write(dev->id, 0x10+2*i, *(((int *)entry)+0));
1795 spin_unlock_irqrestore(&ioapic_lock, flags);
1800 static struct sysdev_class ioapic_sysdev_class = {
1801 set_kset_name("ioapic"),
1802 .suspend = ioapic_suspend,
1803 .resume = ioapic_resume,
1806 static int __init ioapic_init_sysfs(void)
1808 struct sys_device * dev;
1809 int i, size, error = 0;
1811 error = sysdev_class_register(&ioapic_sysdev_class);
1815 for (i = 0; i < nr_ioapics; i++ ) {
1816 size = sizeof(struct sys_device) + nr_ioapic_registers[i]
1817 * sizeof(struct IO_APIC_route_entry);
1818 mp_ioapic_data[i] = kmalloc(size, GFP_KERNEL);
1819 if (!mp_ioapic_data[i]) {
1820 printk(KERN_ERR "Can't suspend/resume IOAPIC %d\n", i);
1823 memset(mp_ioapic_data[i], 0, size);
1824 dev = &mp_ioapic_data[i]->dev;
1826 dev->cls = &ioapic_sysdev_class;
1827 error = sysdev_register(dev);
1829 kfree(mp_ioapic_data[i]);
1830 mp_ioapic_data[i] = NULL;
1831 printk(KERN_ERR "Can't suspend/resume IOAPIC %d\n", i);
1839 device_initcall(ioapic_init_sysfs);
1841 /* --------------------------------------------------------------------------
1842 ACPI-based IOAPIC Configuration
1843 -------------------------------------------------------------------------- */
1845 #ifdef CONFIG_ACPI_BOOT
1847 #define IO_APIC_MAX_ID 0xFE
1849 int __init io_apic_get_version (int ioapic)
1851 union IO_APIC_reg_01 reg_01;
1852 unsigned long flags;
1854 spin_lock_irqsave(&ioapic_lock, flags);
1855 reg_01.raw = io_apic_read(ioapic, 1);
1856 spin_unlock_irqrestore(&ioapic_lock, flags);
1858 return reg_01.bits.version;
1862 int __init io_apic_get_redir_entries (int ioapic)
1864 union IO_APIC_reg_01 reg_01;
1865 unsigned long flags;
1867 spin_lock_irqsave(&ioapic_lock, flags);
1868 reg_01.raw = io_apic_read(ioapic, 1);
1869 spin_unlock_irqrestore(&ioapic_lock, flags);
1871 return reg_01.bits.entries;
1875 int io_apic_set_pci_routing (int ioapic, int pin, int irq, int edge_level, int active_high_low)
1877 struct IO_APIC_route_entry entry;
1878 unsigned long flags;
1880 if (!IO_APIC_IRQ(irq)) {
1881 apic_printk(APIC_QUIET,KERN_ERR "IOAPIC[%d]: Invalid reference to IRQ 0\n",
1887 * Generate a PCI IRQ routing entry and program the IOAPIC accordingly.
1888 * Note that we mask (disable) IRQs now -- these get enabled when the
1889 * corresponding device driver registers for this IRQ.
1892 memset(&entry,0,sizeof(entry));
1894 entry.delivery_mode = INT_DELIVERY_MODE;
1895 entry.dest_mode = INT_DEST_MODE;
1896 entry.dest.logical.logical_dest = cpu_mask_to_apicid(TARGET_CPUS);
1897 entry.trigger = edge_level;
1898 entry.polarity = active_high_low;
1899 entry.mask = 1; /* Disabled (masked) */
1902 * IRQs < 16 are already in the irq_2_pin[] map
1905 add_pin_to_irq(irq, ioapic, pin);
1907 entry.vector = assign_irq_vector(irq);
1909 apic_printk(APIC_VERBOSE,KERN_DEBUG "IOAPIC[%d]: Set PCI routing entry (%d-%d -> 0x%x -> "
1910 "IRQ %d Mode:%i Active:%i)\n", ioapic,
1911 mp_ioapics[ioapic].mpc_apicid, pin, entry.vector, irq,
1912 edge_level, active_high_low);
1914 ioapic_register_intr(irq, entry.vector, edge_level);
1916 if (!ioapic && (irq < 16))
1917 disable_8259A_irq(irq);
1919 spin_lock_irqsave(&ioapic_lock, flags);
1920 io_apic_write(ioapic, 0x11+2*pin, *(((int *)&entry)+1));
1921 io_apic_write(ioapic, 0x10+2*pin, *(((int *)&entry)+0));
1922 spin_unlock_irqrestore(&ioapic_lock, flags);
1927 #endif /*CONFIG_ACPI_BOOT*/
1931 * This function currently is only a helper for the i386 smp boot process where
1932 * we need to reprogram the ioredtbls to cater for the cpus which have come online
1933 * so mask in all cases should simply be TARGET_CPUS
1935 void __init setup_ioapic_dest(void)
1937 int pin, ioapic, irq, irq_entry;
1939 if (skip_ioapic_setup == 1)
1942 for (ioapic = 0; ioapic < nr_ioapics; ioapic++) {
1943 for (pin = 0; pin < nr_ioapic_registers[ioapic]; pin++) {
1944 irq_entry = find_irq_entry(ioapic, pin, mp_INT);
1945 if (irq_entry == -1)
1947 irq = pin_2_irq(irq_entry, ioapic, pin);
1948 set_ioapic_affinity_irq(irq, TARGET_CPUS);