2 * Intel IO-APIC support for multi-Pentium hosts.
4 * Copyright (C) 1997, 1998, 1999, 2000 Ingo Molnar, Hajnalka Szabo
6 * Many thanks to Stig Venaas for trying out countless experimental
7 * patches and reporting/debugging problems patiently!
9 * (c) 1999, Multiple IO-APIC support, developed by
10 * Ken-ichi Yaku <yaku@css1.kbnes.nec.co.jp> and
11 * Hidemi Kishimoto <kisimoto@css1.kbnes.nec.co.jp>,
12 * further tested and cleaned up by Zach Brown <zab@redhat.com>
13 * and Ingo Molnar <mingo@redhat.com>
16 * Maciej W. Rozycki : Bits for genuine 82489DX APICs;
17 * thanks to Eric Gilmore
19 * for testing these extensively
20 * Paul Diefenbaugh : Added full ACPI support
24 #include <linux/interrupt.h>
25 #include <linux/init.h>
26 #include <linux/delay.h>
27 #include <linux/sched.h>
28 #include <linux/smp_lock.h>
29 #include <linux/mc146818rtc.h>
30 #include <linux/acpi.h>
31 #include <linux/sysdev.h>
33 #include <acpi/acpi_bus.h>
39 #include <asm/proto.h>
40 #include <asm/mach_apic.h>
45 #define __apicdebuginit __init
47 int sis_apic_bug; /* not actually supported, dummy for compile */
49 static int no_timer_check;
51 static int disable_timer_pin_1 __initdata;
53 int timer_over_8254 __initdata = 0;
55 /* Where if anywhere is the i8259 connect in external int mode */
56 static struct { int pin, apic; } ioapic_i8259 = { -1, -1 };
58 static DEFINE_SPINLOCK(ioapic_lock);
59 static DEFINE_SPINLOCK(vector_lock);
62 * # of IRQ routing registers
64 int nr_ioapic_registers[MAX_IO_APICS];
67 * Rough estimation of how many shared IRQs there are, can
70 #define MAX_PLUS_SHARED_IRQS NR_IRQ_VECTORS
71 #define PIN_MAP_SIZE (MAX_PLUS_SHARED_IRQS + NR_IRQS)
74 * This is performance-critical, we want to do it O(1)
76 * the indexing order of this array favors 1:1 mappings
77 * between pins and IRQs.
80 static struct irq_pin_list {
81 short apic, pin, next;
82 } irq_2_pin[PIN_MAP_SIZE];
84 int vector_irq[NR_VECTORS] __read_mostly = { [0 ... NR_VECTORS - 1] = -1};
86 #define vector_to_irq(vector) \
87 (platform_legacy_irq(vector) ? vector : vector_irq[vector])
89 #define vector_to_irq(vector) (vector)
92 #define __DO_ACTION(R, ACTION, FINAL) \
96 struct irq_pin_list *entry = irq_2_pin + irq; \
98 BUG_ON(irq >= NR_IRQS); \
104 reg = io_apic_read(entry->apic, 0x10 + R + pin*2); \
106 io_apic_modify(entry->apic, reg); \
109 entry = irq_2_pin + entry->next; \
115 struct { u32 w1, w2; };
116 struct IO_APIC_route_entry entry;
119 static struct IO_APIC_route_entry ioapic_read_entry(int apic, int pin)
121 union entry_union eu;
123 spin_lock_irqsave(&ioapic_lock, flags);
124 eu.w1 = io_apic_read(apic, 0x10 + 2 * pin);
125 eu.w2 = io_apic_read(apic, 0x11 + 2 * pin);
126 spin_unlock_irqrestore(&ioapic_lock, flags);
130 static void ioapic_write_entry(int apic, int pin, struct IO_APIC_route_entry e)
133 union entry_union eu;
135 spin_lock_irqsave(&ioapic_lock, flags);
136 io_apic_write(apic, 0x10 + 2*pin, eu.w1);
137 io_apic_write(apic, 0x11 + 2*pin, eu.w2);
138 spin_unlock_irqrestore(&ioapic_lock, flags);
142 static void set_ioapic_affinity_irq(unsigned int irq, cpumask_t mask)
148 cpus_and(tmp, mask, cpu_online_map);
152 cpus_and(mask, tmp, CPU_MASK_ALL);
154 dest = cpu_mask_to_apicid(mask);
157 * Only the high 8 bits are valid.
159 dest = SET_APIC_LOGICAL_ID(dest);
161 spin_lock_irqsave(&ioapic_lock, flags);
162 __DO_ACTION(1, = dest, )
163 set_irq_info(irq, mask);
164 spin_unlock_irqrestore(&ioapic_lock, flags);
168 static u8 gsi_2_irq[NR_IRQ_VECTORS] = { [0 ... NR_IRQ_VECTORS-1] = 0xFF };
171 * The common case is 1:1 IRQ<->pin mappings. Sometimes there are
172 * shared ISA-space IRQs, so we have to support them. We are super
173 * fast in the common case, and fast for shared ISA-space IRQs.
175 static void add_pin_to_irq(unsigned int irq, int apic, int pin)
177 static int first_free_entry = NR_IRQS;
178 struct irq_pin_list *entry = irq_2_pin + irq;
180 BUG_ON(irq >= NR_IRQS);
182 entry = irq_2_pin + entry->next;
184 if (entry->pin != -1) {
185 entry->next = first_free_entry;
186 entry = irq_2_pin + entry->next;
187 if (++first_free_entry >= PIN_MAP_SIZE)
188 panic("io_apic.c: ran out of irq_2_pin entries!");
195 #define DO_ACTION(name,R,ACTION, FINAL) \
197 static void name##_IO_APIC_irq (unsigned int irq) \
198 __DO_ACTION(R, ACTION, FINAL)
200 DO_ACTION( __mask, 0, |= 0x00010000, io_apic_sync(entry->apic) )
202 DO_ACTION( __unmask, 0, &= 0xfffeffff, )
205 static void mask_IO_APIC_irq (unsigned int irq)
209 spin_lock_irqsave(&ioapic_lock, flags);
210 __mask_IO_APIC_irq(irq);
211 spin_unlock_irqrestore(&ioapic_lock, flags);
214 static void unmask_IO_APIC_irq (unsigned int irq)
218 spin_lock_irqsave(&ioapic_lock, flags);
219 __unmask_IO_APIC_irq(irq);
220 spin_unlock_irqrestore(&ioapic_lock, flags);
223 static void clear_IO_APIC_pin(unsigned int apic, unsigned int pin)
225 struct IO_APIC_route_entry entry;
227 /* Check delivery_mode to be sure we're not clearing an SMI pin */
228 entry = ioapic_read_entry(apic, pin);
229 if (entry.delivery_mode == dest_SMI)
232 * Disable it in the IO-APIC irq-routing table:
234 memset(&entry, 0, sizeof(entry));
236 ioapic_write_entry(apic, pin, entry);
239 static void clear_IO_APIC (void)
243 for (apic = 0; apic < nr_ioapics; apic++)
244 for (pin = 0; pin < nr_ioapic_registers[apic]; pin++)
245 clear_IO_APIC_pin(apic, pin);
248 int skip_ioapic_setup;
251 /* dummy parsing: see setup.c */
253 static int __init disable_ioapic_setup(char *str)
255 skip_ioapic_setup = 1;
258 early_param("noapic", disable_ioapic_setup);
260 /* Actually the next is obsolete, but keep it for paranoid reasons -AK */
261 static int __init disable_timer_pin_setup(char *arg)
263 disable_timer_pin_1 = 1;
266 __setup("disable_timer_pin_1", disable_timer_pin_setup);
268 static int __init setup_disable_8254_timer(char *s)
270 timer_over_8254 = -1;
273 static int __init setup_enable_8254_timer(char *s)
279 __setup("disable_8254_timer", setup_disable_8254_timer);
280 __setup("enable_8254_timer", setup_enable_8254_timer);
284 * Find the IRQ entry number of a certain pin.
286 static int find_irq_entry(int apic, int pin, int type)
290 for (i = 0; i < mp_irq_entries; i++)
291 if (mp_irqs[i].mpc_irqtype == type &&
292 (mp_irqs[i].mpc_dstapic == mp_ioapics[apic].mpc_apicid ||
293 mp_irqs[i].mpc_dstapic == MP_APIC_ALL) &&
294 mp_irqs[i].mpc_dstirq == pin)
301 * Find the pin to which IRQ[irq] (ISA) is connected
303 static int __init find_isa_irq_pin(int irq, int type)
307 for (i = 0; i < mp_irq_entries; i++) {
308 int lbus = mp_irqs[i].mpc_srcbus;
310 if (test_bit(lbus, mp_bus_not_pci) &&
311 (mp_irqs[i].mpc_irqtype == type) &&
312 (mp_irqs[i].mpc_srcbusirq == irq))
314 return mp_irqs[i].mpc_dstirq;
319 static int __init find_isa_irq_apic(int irq, int type)
323 for (i = 0; i < mp_irq_entries; i++) {
324 int lbus = mp_irqs[i].mpc_srcbus;
326 if (test_bit(lbus, mp_bus_not_pci) &&
327 (mp_irqs[i].mpc_irqtype == type) &&
328 (mp_irqs[i].mpc_srcbusirq == irq))
331 if (i < mp_irq_entries) {
333 for(apic = 0; apic < nr_ioapics; apic++) {
334 if (mp_ioapics[apic].mpc_apicid == mp_irqs[i].mpc_dstapic)
343 * Find a specific PCI IRQ entry.
344 * Not an __init, possibly needed by modules
346 static int pin_2_irq(int idx, int apic, int pin);
348 int IO_APIC_get_PCI_irq_vector(int bus, int slot, int pin)
350 int apic, i, best_guess = -1;
352 apic_printk(APIC_DEBUG, "querying PCI -> IRQ mapping bus:%d, slot:%d, pin:%d.\n",
354 if (mp_bus_id_to_pci_bus[bus] == -1) {
355 apic_printk(APIC_VERBOSE, "PCI BIOS passed nonexistent PCI bus %d!\n", bus);
358 for (i = 0; i < mp_irq_entries; i++) {
359 int lbus = mp_irqs[i].mpc_srcbus;
361 for (apic = 0; apic < nr_ioapics; apic++)
362 if (mp_ioapics[apic].mpc_apicid == mp_irqs[i].mpc_dstapic ||
363 mp_irqs[i].mpc_dstapic == MP_APIC_ALL)
366 if (!test_bit(lbus, mp_bus_not_pci) &&
367 !mp_irqs[i].mpc_irqtype &&
369 (slot == ((mp_irqs[i].mpc_srcbusirq >> 2) & 0x1f))) {
370 int irq = pin_2_irq(i,apic,mp_irqs[i].mpc_dstirq);
372 if (!(apic || IO_APIC_IRQ(irq)))
375 if (pin == (mp_irqs[i].mpc_srcbusirq & 3))
378 * Use the first all-but-pin matching entry as a
379 * best-guess fuzzy result for broken mptables.
385 BUG_ON(best_guess >= NR_IRQS);
389 /* ISA interrupts are always polarity zero edge triggered,
390 * when listed as conforming in the MP table. */
392 #define default_ISA_trigger(idx) (0)
393 #define default_ISA_polarity(idx) (0)
395 /* PCI interrupts are always polarity one level triggered,
396 * when listed as conforming in the MP table. */
398 #define default_PCI_trigger(idx) (1)
399 #define default_PCI_polarity(idx) (1)
401 static int __init MPBIOS_polarity(int idx)
403 int bus = mp_irqs[idx].mpc_srcbus;
407 * Determine IRQ line polarity (high active or low active):
409 switch (mp_irqs[idx].mpc_irqflag & 3)
411 case 0: /* conforms, ie. bus-type dependent polarity */
412 if (test_bit(bus, mp_bus_not_pci))
413 polarity = default_ISA_polarity(idx);
415 polarity = default_PCI_polarity(idx);
417 case 1: /* high active */
422 case 2: /* reserved */
424 printk(KERN_WARNING "broken BIOS!!\n");
428 case 3: /* low active */
433 default: /* invalid */
435 printk(KERN_WARNING "broken BIOS!!\n");
443 static int MPBIOS_trigger(int idx)
445 int bus = mp_irqs[idx].mpc_srcbus;
449 * Determine IRQ trigger mode (edge or level sensitive):
451 switch ((mp_irqs[idx].mpc_irqflag>>2) & 3)
453 case 0: /* conforms, ie. bus-type dependent */
454 if (test_bit(bus, mp_bus_not_pci))
455 trigger = default_ISA_trigger(idx);
457 trigger = default_PCI_trigger(idx);
464 case 2: /* reserved */
466 printk(KERN_WARNING "broken BIOS!!\n");
475 default: /* invalid */
477 printk(KERN_WARNING "broken BIOS!!\n");
485 static inline int irq_polarity(int idx)
487 return MPBIOS_polarity(idx);
490 static inline int irq_trigger(int idx)
492 return MPBIOS_trigger(idx);
495 static int next_irq = 16;
498 * gsi_irq_sharing -- Name overload! "irq" can be either a legacy IRQ
499 * in the range 0-15, a linux IRQ in the range 0-223, or a GSI number
500 * from ACPI, which can reach 800 in large boxen.
502 * Compact the sparse GSI space into a sequential IRQ series and reuse
503 * vectors if possible.
505 int gsi_irq_sharing(int gsi)
507 int i, tries, vector;
509 BUG_ON(gsi >= NR_IRQ_VECTORS);
511 if (platform_legacy_irq(gsi))
514 if (gsi_2_irq[gsi] != 0xFF)
515 return (int)gsi_2_irq[gsi];
519 vector = assign_irq_vector(gsi);
522 * Sharing vectors means sharing IRQs, so scan irq_vectors for previous
523 * use of vector and if found, return that IRQ. However, we never want
524 * to share legacy IRQs, which usually have a different trigger mode
527 for (i = 0; i < NR_IRQS; i++)
528 if (IO_APIC_VECTOR(i) == vector)
530 if (platform_legacy_irq(i)) {
532 IO_APIC_VECTOR(i) = 0;
535 panic("gsi_irq_sharing: didn't find an IRQ using vector 0x%02X for GSI %d", vector, gsi);
539 printk(KERN_INFO "GSI %d sharing vector 0x%02X and IRQ %d\n",
545 BUG_ON(i >= NR_IRQS);
547 IO_APIC_VECTOR(i) = vector;
548 printk(KERN_INFO "GSI %d assigned vector 0x%02X and IRQ %d\n",
553 static int pin_2_irq(int idx, int apic, int pin)
556 int bus = mp_irqs[idx].mpc_srcbus;
559 * Debugging check, we are in big trouble if this message pops up!
561 if (mp_irqs[idx].mpc_dstirq != pin)
562 printk(KERN_ERR "broken BIOS or MPTABLE parser, ayiee!!\n");
564 if (test_bit(bus, mp_bus_not_pci)) {
565 irq = mp_irqs[idx].mpc_srcbusirq;
568 * PCI IRQs are mapped in order
572 irq += nr_ioapic_registers[i++];
574 irq = gsi_irq_sharing(irq);
576 BUG_ON(irq >= NR_IRQS);
580 static inline int IO_APIC_irq_trigger(int irq)
584 for (apic = 0; apic < nr_ioapics; apic++) {
585 for (pin = 0; pin < nr_ioapic_registers[apic]; pin++) {
586 idx = find_irq_entry(apic,pin,mp_INT);
587 if ((idx != -1) && (irq == pin_2_irq(idx,apic,pin)))
588 return irq_trigger(idx);
592 * nonexistent IRQs are edge default
597 /* irq_vectors is indexed by the sum of all RTEs in all I/O APICs. */
598 u8 irq_vector[NR_IRQ_VECTORS] __read_mostly = { FIRST_DEVICE_VECTOR , 0 };
600 int assign_irq_vector(int irq)
602 static int current_vector = FIRST_DEVICE_VECTOR, offset = 0;
606 BUG_ON(irq != AUTO_ASSIGN && (unsigned)irq >= NR_IRQ_VECTORS);
608 spin_lock_irqsave(&vector_lock, flags);
610 if (irq != AUTO_ASSIGN && IO_APIC_VECTOR(irq) > 0) {
611 spin_unlock_irqrestore(&vector_lock, flags);
612 return IO_APIC_VECTOR(irq);
616 if (current_vector == IA32_SYSCALL_VECTOR)
619 if (current_vector >= FIRST_SYSTEM_VECTOR) {
620 /* If we run out of vectors on large boxen, must share them. */
621 offset = (offset + 1) % 8;
622 current_vector = FIRST_DEVICE_VECTOR + offset;
625 vector = current_vector;
626 vector_irq[vector] = irq;
627 if (irq != AUTO_ASSIGN)
628 IO_APIC_VECTOR(irq) = vector;
630 spin_unlock_irqrestore(&vector_lock, flags);
635 extern void (*interrupt[NR_IRQS])(void);
637 static struct irq_chip ioapic_chip;
639 #define IOAPIC_AUTO -1
640 #define IOAPIC_EDGE 0
641 #define IOAPIC_LEVEL 1
643 static void ioapic_register_intr(int irq, int vector, unsigned long trigger)
647 idx = use_pci_vector() && !platform_legacy_irq(irq) ? vector : irq;
649 if ((trigger == IOAPIC_AUTO && IO_APIC_irq_trigger(irq)) ||
650 trigger == IOAPIC_LEVEL)
651 set_irq_chip_and_handler(idx, &ioapic_chip,
654 set_irq_chip_and_handler(idx, &ioapic_chip,
656 set_intr_gate(vector, interrupt[idx]);
659 static void __init setup_IO_APIC_irqs(void)
661 struct IO_APIC_route_entry entry;
662 int apic, pin, idx, irq, first_notcon = 1, vector;
665 apic_printk(APIC_VERBOSE, KERN_DEBUG "init IO_APIC IRQs\n");
667 for (apic = 0; apic < nr_ioapics; apic++) {
668 for (pin = 0; pin < nr_ioapic_registers[apic]; pin++) {
671 * add it to the IO-APIC irq-routing table:
673 memset(&entry,0,sizeof(entry));
675 entry.delivery_mode = INT_DELIVERY_MODE;
676 entry.dest_mode = INT_DEST_MODE;
677 entry.mask = 0; /* enable IRQ */
678 entry.dest.logical.logical_dest = cpu_mask_to_apicid(TARGET_CPUS);
680 idx = find_irq_entry(apic,pin,mp_INT);
683 apic_printk(APIC_VERBOSE, KERN_DEBUG " IO-APIC (apicid-pin) %d-%d", mp_ioapics[apic].mpc_apicid, pin);
686 apic_printk(APIC_VERBOSE, ", %d-%d", mp_ioapics[apic].mpc_apicid, pin);
690 entry.trigger = irq_trigger(idx);
691 entry.polarity = irq_polarity(idx);
693 if (irq_trigger(idx)) {
696 entry.dest.logical.logical_dest = cpu_mask_to_apicid(TARGET_CPUS);
699 irq = pin_2_irq(idx, apic, pin);
700 add_pin_to_irq(irq, apic, pin);
702 if (!apic && !IO_APIC_IRQ(irq))
705 if (IO_APIC_IRQ(irq)) {
706 vector = assign_irq_vector(irq);
707 entry.vector = vector;
709 ioapic_register_intr(irq, vector, IOAPIC_AUTO);
710 if (!apic && (irq < 16))
711 disable_8259A_irq(irq);
713 ioapic_write_entry(apic, pin, entry);
715 spin_lock_irqsave(&ioapic_lock, flags);
716 set_native_irq_info(irq, TARGET_CPUS);
717 spin_unlock_irqrestore(&ioapic_lock, flags);
722 apic_printk(APIC_VERBOSE," not connected.\n");
726 * Set up the 8259A-master output pin as broadcast to all
729 static void __init setup_ExtINT_IRQ0_pin(unsigned int apic, unsigned int pin, int vector)
731 struct IO_APIC_route_entry entry;
734 memset(&entry,0,sizeof(entry));
736 disable_8259A_irq(0);
739 apic_write(APIC_LVT0, APIC_LVT_MASKED | APIC_DM_EXTINT);
742 * We use logical delivery to get the timer IRQ
745 entry.dest_mode = INT_DEST_MODE;
746 entry.mask = 0; /* unmask IRQ now */
747 entry.dest.logical.logical_dest = cpu_mask_to_apicid(TARGET_CPUS);
748 entry.delivery_mode = INT_DELIVERY_MODE;
751 entry.vector = vector;
754 * The timer IRQ doesn't have to know that behind the
755 * scene we have a 8259A-master in AEOI mode ...
757 set_irq_chip_and_handler(0, &ioapic_chip, handle_edge_irq);
760 * Add it to the IO-APIC irq-routing table:
762 spin_lock_irqsave(&ioapic_lock, flags);
763 io_apic_write(apic, 0x11+2*pin, *(((int *)&entry)+1));
764 io_apic_write(apic, 0x10+2*pin, *(((int *)&entry)+0));
765 spin_unlock_irqrestore(&ioapic_lock, flags);
770 void __init UNEXPECTED_IO_APIC(void)
774 void __apicdebuginit print_IO_APIC(void)
777 union IO_APIC_reg_00 reg_00;
778 union IO_APIC_reg_01 reg_01;
779 union IO_APIC_reg_02 reg_02;
782 if (apic_verbosity == APIC_QUIET)
785 printk(KERN_DEBUG "number of MP IRQ sources: %d.\n", mp_irq_entries);
786 for (i = 0; i < nr_ioapics; i++)
787 printk(KERN_DEBUG "number of IO-APIC #%d registers: %d.\n",
788 mp_ioapics[i].mpc_apicid, nr_ioapic_registers[i]);
791 * We are a bit conservative about what we expect. We have to
792 * know about every hardware change ASAP.
794 printk(KERN_INFO "testing the IO APIC.......................\n");
796 for (apic = 0; apic < nr_ioapics; apic++) {
798 spin_lock_irqsave(&ioapic_lock, flags);
799 reg_00.raw = io_apic_read(apic, 0);
800 reg_01.raw = io_apic_read(apic, 1);
801 if (reg_01.bits.version >= 0x10)
802 reg_02.raw = io_apic_read(apic, 2);
803 spin_unlock_irqrestore(&ioapic_lock, flags);
806 printk(KERN_DEBUG "IO APIC #%d......\n", mp_ioapics[apic].mpc_apicid);
807 printk(KERN_DEBUG ".... register #00: %08X\n", reg_00.raw);
808 printk(KERN_DEBUG "....... : physical APIC id: %02X\n", reg_00.bits.ID);
809 if (reg_00.bits.__reserved_1 || reg_00.bits.__reserved_2)
810 UNEXPECTED_IO_APIC();
812 printk(KERN_DEBUG ".... register #01: %08X\n", *(int *)®_01);
813 printk(KERN_DEBUG "....... : max redirection entries: %04X\n", reg_01.bits.entries);
814 if ( (reg_01.bits.entries != 0x0f) && /* older (Neptune) boards */
815 (reg_01.bits.entries != 0x17) && /* typical ISA+PCI boards */
816 (reg_01.bits.entries != 0x1b) && /* Compaq Proliant boards */
817 (reg_01.bits.entries != 0x1f) && /* dual Xeon boards */
818 (reg_01.bits.entries != 0x22) && /* bigger Xeon boards */
819 (reg_01.bits.entries != 0x2E) &&
820 (reg_01.bits.entries != 0x3F) &&
821 (reg_01.bits.entries != 0x03)
823 UNEXPECTED_IO_APIC();
825 printk(KERN_DEBUG "....... : PRQ implemented: %X\n", reg_01.bits.PRQ);
826 printk(KERN_DEBUG "....... : IO APIC version: %04X\n", reg_01.bits.version);
827 if ( (reg_01.bits.version != 0x01) && /* 82489DX IO-APICs */
828 (reg_01.bits.version != 0x02) && /* 82801BA IO-APICs (ICH2) */
829 (reg_01.bits.version != 0x10) && /* oldest IO-APICs */
830 (reg_01.bits.version != 0x11) && /* Pentium/Pro IO-APICs */
831 (reg_01.bits.version != 0x13) && /* Xeon IO-APICs */
832 (reg_01.bits.version != 0x20) /* Intel P64H (82806 AA) */
834 UNEXPECTED_IO_APIC();
835 if (reg_01.bits.__reserved_1 || reg_01.bits.__reserved_2)
836 UNEXPECTED_IO_APIC();
838 if (reg_01.bits.version >= 0x10) {
839 printk(KERN_DEBUG ".... register #02: %08X\n", reg_02.raw);
840 printk(KERN_DEBUG "....... : arbitration: %02X\n", reg_02.bits.arbitration);
841 if (reg_02.bits.__reserved_1 || reg_02.bits.__reserved_2)
842 UNEXPECTED_IO_APIC();
845 printk(KERN_DEBUG ".... IRQ redirection table:\n");
847 printk(KERN_DEBUG " NR Log Phy Mask Trig IRR Pol"
848 " Stat Dest Deli Vect: \n");
850 for (i = 0; i <= reg_01.bits.entries; i++) {
851 struct IO_APIC_route_entry entry;
853 entry = ioapic_read_entry(apic, i);
855 printk(KERN_DEBUG " %02x %03X %02X ",
857 entry.dest.logical.logical_dest,
858 entry.dest.physical.physical_dest
861 printk("%1d %1d %1d %1d %1d %1d %1d %02X\n",
866 entry.delivery_status,
873 if (use_pci_vector())
874 printk(KERN_INFO "Using vector-based indexing\n");
875 printk(KERN_DEBUG "IRQ to pin mappings:\n");
876 for (i = 0; i < NR_IRQS; i++) {
877 struct irq_pin_list *entry = irq_2_pin + i;
880 if (use_pci_vector() && !platform_legacy_irq(i))
881 printk(KERN_DEBUG "IRQ%d ", IO_APIC_VECTOR(i));
883 printk(KERN_DEBUG "IRQ%d ", i);
885 printk("-> %d:%d", entry->apic, entry->pin);
888 entry = irq_2_pin + entry->next;
893 printk(KERN_INFO ".................................... done.\n");
900 static __apicdebuginit void print_APIC_bitfield (int base)
905 if (apic_verbosity == APIC_QUIET)
908 printk(KERN_DEBUG "0123456789abcdef0123456789abcdef\n" KERN_DEBUG);
909 for (i = 0; i < 8; i++) {
910 v = apic_read(base + i*0x10);
911 for (j = 0; j < 32; j++) {
921 void __apicdebuginit print_local_APIC(void * dummy)
923 unsigned int v, ver, maxlvt;
925 if (apic_verbosity == APIC_QUIET)
928 printk("\n" KERN_DEBUG "printing local APIC contents on CPU#%d/%d:\n",
929 smp_processor_id(), hard_smp_processor_id());
930 v = apic_read(APIC_ID);
931 printk(KERN_INFO "... APIC ID: %08x (%01x)\n", v, GET_APIC_ID(v));
932 v = apic_read(APIC_LVR);
933 printk(KERN_INFO "... APIC VERSION: %08x\n", v);
934 ver = GET_APIC_VERSION(v);
935 maxlvt = get_maxlvt();
937 v = apic_read(APIC_TASKPRI);
938 printk(KERN_DEBUG "... APIC TASKPRI: %08x (%02x)\n", v, v & APIC_TPRI_MASK);
940 v = apic_read(APIC_ARBPRI);
941 printk(KERN_DEBUG "... APIC ARBPRI: %08x (%02x)\n", v,
942 v & APIC_ARBPRI_MASK);
943 v = apic_read(APIC_PROCPRI);
944 printk(KERN_DEBUG "... APIC PROCPRI: %08x\n", v);
946 v = apic_read(APIC_EOI);
947 printk(KERN_DEBUG "... APIC EOI: %08x\n", v);
948 v = apic_read(APIC_RRR);
949 printk(KERN_DEBUG "... APIC RRR: %08x\n", v);
950 v = apic_read(APIC_LDR);
951 printk(KERN_DEBUG "... APIC LDR: %08x\n", v);
952 v = apic_read(APIC_DFR);
953 printk(KERN_DEBUG "... APIC DFR: %08x\n", v);
954 v = apic_read(APIC_SPIV);
955 printk(KERN_DEBUG "... APIC SPIV: %08x\n", v);
957 printk(KERN_DEBUG "... APIC ISR field:\n");
958 print_APIC_bitfield(APIC_ISR);
959 printk(KERN_DEBUG "... APIC TMR field:\n");
960 print_APIC_bitfield(APIC_TMR);
961 printk(KERN_DEBUG "... APIC IRR field:\n");
962 print_APIC_bitfield(APIC_IRR);
964 v = apic_read(APIC_ESR);
965 printk(KERN_DEBUG "... APIC ESR: %08x\n", v);
967 v = apic_read(APIC_ICR);
968 printk(KERN_DEBUG "... APIC ICR: %08x\n", v);
969 v = apic_read(APIC_ICR2);
970 printk(KERN_DEBUG "... APIC ICR2: %08x\n", v);
972 v = apic_read(APIC_LVTT);
973 printk(KERN_DEBUG "... APIC LVTT: %08x\n", v);
975 if (maxlvt > 3) { /* PC is LVT#4. */
976 v = apic_read(APIC_LVTPC);
977 printk(KERN_DEBUG "... APIC LVTPC: %08x\n", v);
979 v = apic_read(APIC_LVT0);
980 printk(KERN_DEBUG "... APIC LVT0: %08x\n", v);
981 v = apic_read(APIC_LVT1);
982 printk(KERN_DEBUG "... APIC LVT1: %08x\n", v);
984 if (maxlvt > 2) { /* ERR is LVT#3. */
985 v = apic_read(APIC_LVTERR);
986 printk(KERN_DEBUG "... APIC LVTERR: %08x\n", v);
989 v = apic_read(APIC_TMICT);
990 printk(KERN_DEBUG "... APIC TMICT: %08x\n", v);
991 v = apic_read(APIC_TMCCT);
992 printk(KERN_DEBUG "... APIC TMCCT: %08x\n", v);
993 v = apic_read(APIC_TDCR);
994 printk(KERN_DEBUG "... APIC TDCR: %08x\n", v);
998 void print_all_local_APICs (void)
1000 on_each_cpu(print_local_APIC, NULL, 1, 1);
1003 void __apicdebuginit print_PIC(void)
1006 unsigned long flags;
1008 if (apic_verbosity == APIC_QUIET)
1011 printk(KERN_DEBUG "\nprinting PIC contents\n");
1013 spin_lock_irqsave(&i8259A_lock, flags);
1015 v = inb(0xa1) << 8 | inb(0x21);
1016 printk(KERN_DEBUG "... PIC IMR: %04x\n", v);
1018 v = inb(0xa0) << 8 | inb(0x20);
1019 printk(KERN_DEBUG "... PIC IRR: %04x\n", v);
1023 v = inb(0xa0) << 8 | inb(0x20);
1027 spin_unlock_irqrestore(&i8259A_lock, flags);
1029 printk(KERN_DEBUG "... PIC ISR: %04x\n", v);
1031 v = inb(0x4d1) << 8 | inb(0x4d0);
1032 printk(KERN_DEBUG "... PIC ELCR: %04x\n", v);
1037 static void __init enable_IO_APIC(void)
1039 union IO_APIC_reg_01 reg_01;
1040 int i8259_apic, i8259_pin;
1042 unsigned long flags;
1044 for (i = 0; i < PIN_MAP_SIZE; i++) {
1045 irq_2_pin[i].pin = -1;
1046 irq_2_pin[i].next = 0;
1050 * The number of IO-APIC IRQ registers (== #pins):
1052 for (apic = 0; apic < nr_ioapics; apic++) {
1053 spin_lock_irqsave(&ioapic_lock, flags);
1054 reg_01.raw = io_apic_read(apic, 1);
1055 spin_unlock_irqrestore(&ioapic_lock, flags);
1056 nr_ioapic_registers[apic] = reg_01.bits.entries+1;
1058 for(apic = 0; apic < nr_ioapics; apic++) {
1060 /* See if any of the pins is in ExtINT mode */
1061 for (pin = 0; pin < nr_ioapic_registers[apic]; pin++) {
1062 struct IO_APIC_route_entry entry;
1063 entry = ioapic_read_entry(apic, pin);
1065 /* If the interrupt line is enabled and in ExtInt mode
1066 * I have found the pin where the i8259 is connected.
1068 if ((entry.mask == 0) && (entry.delivery_mode == dest_ExtINT)) {
1069 ioapic_i8259.apic = apic;
1070 ioapic_i8259.pin = pin;
1076 /* Look to see what if the MP table has reported the ExtINT */
1077 i8259_pin = find_isa_irq_pin(0, mp_ExtINT);
1078 i8259_apic = find_isa_irq_apic(0, mp_ExtINT);
1079 /* Trust the MP table if nothing is setup in the hardware */
1080 if ((ioapic_i8259.pin == -1) && (i8259_pin >= 0)) {
1081 printk(KERN_WARNING "ExtINT not setup in hardware but reported by MP table\n");
1082 ioapic_i8259.pin = i8259_pin;
1083 ioapic_i8259.apic = i8259_apic;
1085 /* Complain if the MP table and the hardware disagree */
1086 if (((ioapic_i8259.apic != i8259_apic) || (ioapic_i8259.pin != i8259_pin)) &&
1087 (i8259_pin >= 0) && (ioapic_i8259.pin >= 0))
1089 printk(KERN_WARNING "ExtINT in hardware and MP table differ\n");
1093 * Do not trust the IO-APIC being empty at bootup
1099 * Not an __init, needed by the reboot code
1101 void disable_IO_APIC(void)
1104 * Clear the IO-APIC before rebooting:
1109 * If the i8259 is routed through an IOAPIC
1110 * Put that IOAPIC in virtual wire mode
1111 * so legacy interrupts can be delivered.
1113 if (ioapic_i8259.pin != -1) {
1114 struct IO_APIC_route_entry entry;
1116 memset(&entry, 0, sizeof(entry));
1117 entry.mask = 0; /* Enabled */
1118 entry.trigger = 0; /* Edge */
1120 entry.polarity = 0; /* High */
1121 entry.delivery_status = 0;
1122 entry.dest_mode = 0; /* Physical */
1123 entry.delivery_mode = dest_ExtINT; /* ExtInt */
1125 entry.dest.physical.physical_dest =
1126 GET_APIC_ID(apic_read(APIC_ID));
1129 * Add it to the IO-APIC irq-routing table:
1131 ioapic_write_entry(ioapic_i8259.apic, ioapic_i8259.pin, entry);
1134 disconnect_bsp_APIC(ioapic_i8259.pin != -1);
1138 * There is a nasty bug in some older SMP boards, their mptable lies
1139 * about the timer IRQ. We do the following to work around the situation:
1141 * - timer IRQ defaults to IO-APIC IRQ
1142 * - if this function detects that timer IRQs are defunct, then we fall
1143 * back to ISA timer IRQs
1145 static int __init timer_irq_works(void)
1147 unsigned long t1 = jiffies;
1150 /* Let ten ticks pass... */
1151 mdelay((10 * 1000) / HZ);
1154 * Expect a few ticks at least, to be sure some possible
1155 * glue logic does not lock up after one or two first
1156 * ticks in a non-ExtINT mode. Also the local APIC
1157 * might have cached one ExtINT interrupt. Finally, at
1158 * least one tick may be lost due to delays.
1162 if (jiffies - t1 > 4)
1168 * In the SMP+IOAPIC case it might happen that there are an unspecified
1169 * number of pending IRQ events unhandled. These cases are very rare,
1170 * so we 'resend' these IRQs via IPIs, to the same CPU. It's much
1171 * better to do it this way as thus we do not have to be aware of
1172 * 'pending' interrupts in the IRQ path, except at this point.
1175 * Edge triggered needs to resend any interrupt
1176 * that was delayed but this is now handled in the device
1181 * Starting up a edge-triggered IO-APIC interrupt is
1182 * nasty - we need to make sure that we get the edge.
1183 * If it is already asserted for some reason, we need
1184 * return 1 to indicate that is was pending.
1186 * This is not complete - we should be able to fake
1187 * an edge even if it isn't on the 8259A...
1190 static unsigned int startup_ioapic_irq(unsigned int irq)
1192 int was_pending = 0;
1193 unsigned long flags;
1195 spin_lock_irqsave(&ioapic_lock, flags);
1197 disable_8259A_irq(irq);
1198 if (i8259A_irq_pending(irq))
1201 __unmask_IO_APIC_irq(irq);
1202 spin_unlock_irqrestore(&ioapic_lock, flags);
1207 static unsigned int startup_ioapic_vector(unsigned int vector)
1209 int irq = vector_to_irq(vector);
1211 return startup_ioapic_irq(irq);
1214 static void mask_ioapic_vector (unsigned int vector)
1216 int irq = vector_to_irq(vector);
1218 mask_IO_APIC_irq(irq);
1221 static void unmask_ioapic_vector (unsigned int vector)
1223 int irq = vector_to_irq(vector);
1225 unmask_IO_APIC_irq(irq);
1229 static void set_ioapic_affinity_vector (unsigned int vector,
1232 int irq = vector_to_irq(vector);
1234 set_native_irq_info(vector, cpu_mask);
1235 set_ioapic_affinity_irq(irq, cpu_mask);
1237 #endif // CONFIG_SMP
1239 static int ioapic_retrigger_vector(unsigned int vector)
1241 int irq = vector_to_irq(vector);
1243 send_IPI_self(IO_APIC_VECTOR(irq));
1249 * Level and edge triggered IO-APIC interrupts need different handling,
1250 * so we use two separate IRQ descriptors. Edge triggered IRQs can be
1251 * handled with the level-triggered descriptor, but that one has slightly
1252 * more overhead. Level-triggered interrupts cannot be handled with the
1253 * edge-triggered handler, without risking IRQ storms and other ugly
1257 static void ack_apic(unsigned int irq)
1262 static void ack_apic_edge(unsigned int irq)
1264 move_native_irq(irq);
1268 static void ack_apic_level(unsigned int irq)
1270 int do_unmask_irq = 0;
1272 #if defined(CONFIG_GENERIC_PENDING_IRQ) || defined(CONFIG_IRQBALANCE)
1273 /* If we are moving the irq we need to mask it */
1274 if (unlikely(irq_desc[irq].status & IRQ_MOVE_PENDING)) {
1276 mask_IO_APIC_irq(irq);
1281 * We must acknowledge the irq before we move it or the acknowledge will
1282 * not propogate properly.
1286 /* Now we can move and renable the irq */
1287 move_masked_irq(irq);
1288 if (unlikely(do_unmask_irq))
1289 unmask_IO_APIC_irq(irq);
1292 static struct irq_chip ioapic_chip __read_mostly = {
1294 .startup = startup_ioapic_vector,
1295 .mask = mask_ioapic_vector,
1296 .unmask = unmask_ioapic_vector,
1297 .ack = ack_apic_edge,
1298 .eoi = ack_apic_level,
1300 .set_affinity = set_ioapic_affinity_vector,
1302 .retrigger = ioapic_retrigger_vector,
1305 static inline void init_IO_APIC_traps(void)
1310 * NOTE! The local APIC isn't very good at handling
1311 * multiple interrupts at the same interrupt level.
1312 * As the interrupt level is determined by taking the
1313 * vector number and shifting that right by 4, we
1314 * want to spread these out a bit so that they don't
1315 * all fall in the same interrupt level.
1317 * Also, we've got to be careful not to trash gate
1318 * 0x80, because int 0x80 is hm, kind of importantish. ;)
1320 for (irq = 0; irq < NR_IRQS ; irq++) {
1322 if (use_pci_vector()) {
1323 if (!platform_legacy_irq(tmp))
1324 if ((tmp = vector_to_irq(tmp)) == -1)
1327 if (IO_APIC_IRQ(tmp) && !IO_APIC_VECTOR(tmp)) {
1329 * Hmm.. We don't have an entry for this,
1330 * so default to an old-fashioned 8259
1331 * interrupt if we can..
1334 make_8259A_irq(irq);
1336 /* Strange. Oh, well.. */
1337 irq_desc[irq].chip = &no_irq_chip;
1342 static void enable_lapic_irq (unsigned int irq)
1346 v = apic_read(APIC_LVT0);
1347 apic_write(APIC_LVT0, v & ~APIC_LVT_MASKED);
1350 static void disable_lapic_irq (unsigned int irq)
1354 v = apic_read(APIC_LVT0);
1355 apic_write(APIC_LVT0, v | APIC_LVT_MASKED);
1358 static void ack_lapic_irq (unsigned int irq)
1363 static void end_lapic_irq (unsigned int i) { /* nothing */ }
1365 static struct hw_interrupt_type lapic_irq_type __read_mostly = {
1366 .typename = "local-APIC-edge",
1367 .startup = NULL, /* startup_irq() not used for IRQ0 */
1368 .shutdown = NULL, /* shutdown_irq() not used for IRQ0 */
1369 .enable = enable_lapic_irq,
1370 .disable = disable_lapic_irq,
1371 .ack = ack_lapic_irq,
1372 .end = end_lapic_irq,
1375 static void setup_nmi (void)
1378 * Dirty trick to enable the NMI watchdog ...
1379 * We put the 8259A master into AEOI mode and
1380 * unmask on all local APICs LVT0 as NMI.
1382 * The idea to use the 8259A in AEOI mode ('8259A Virtual Wire')
1383 * is from Maciej W. Rozycki - so we do not have to EOI from
1384 * the NMI handler or the timer interrupt.
1386 printk(KERN_INFO "activating NMI Watchdog ...");
1388 enable_NMI_through_LVT0(NULL);
1394 * This looks a bit hackish but it's about the only one way of sending
1395 * a few INTA cycles to 8259As and any associated glue logic. ICR does
1396 * not support the ExtINT mode, unfortunately. We need to send these
1397 * cycles as some i82489DX-based boards have glue logic that keeps the
1398 * 8259A interrupt line asserted until INTA. --macro
1400 static inline void unlock_ExtINT_logic(void)
1403 struct IO_APIC_route_entry entry0, entry1;
1404 unsigned char save_control, save_freq_select;
1405 unsigned long flags;
1407 pin = find_isa_irq_pin(8, mp_INT);
1408 apic = find_isa_irq_apic(8, mp_INT);
1412 spin_lock_irqsave(&ioapic_lock, flags);
1413 *(((int *)&entry0) + 1) = io_apic_read(apic, 0x11 + 2 * pin);
1414 *(((int *)&entry0) + 0) = io_apic_read(apic, 0x10 + 2 * pin);
1415 spin_unlock_irqrestore(&ioapic_lock, flags);
1416 clear_IO_APIC_pin(apic, pin);
1418 memset(&entry1, 0, sizeof(entry1));
1420 entry1.dest_mode = 0; /* physical delivery */
1421 entry1.mask = 0; /* unmask IRQ now */
1422 entry1.dest.physical.physical_dest = hard_smp_processor_id();
1423 entry1.delivery_mode = dest_ExtINT;
1424 entry1.polarity = entry0.polarity;
1428 spin_lock_irqsave(&ioapic_lock, flags);
1429 io_apic_write(apic, 0x11 + 2 * pin, *(((int *)&entry1) + 1));
1430 io_apic_write(apic, 0x10 + 2 * pin, *(((int *)&entry1) + 0));
1431 spin_unlock_irqrestore(&ioapic_lock, flags);
1433 save_control = CMOS_READ(RTC_CONTROL);
1434 save_freq_select = CMOS_READ(RTC_FREQ_SELECT);
1435 CMOS_WRITE((save_freq_select & ~RTC_RATE_SELECT) | 0x6,
1437 CMOS_WRITE(save_control | RTC_PIE, RTC_CONTROL);
1442 if ((CMOS_READ(RTC_INTR_FLAGS) & RTC_PF) == RTC_PF)
1446 CMOS_WRITE(save_control, RTC_CONTROL);
1447 CMOS_WRITE(save_freq_select, RTC_FREQ_SELECT);
1448 clear_IO_APIC_pin(apic, pin);
1450 spin_lock_irqsave(&ioapic_lock, flags);
1451 io_apic_write(apic, 0x11 + 2 * pin, *(((int *)&entry0) + 1));
1452 io_apic_write(apic, 0x10 + 2 * pin, *(((int *)&entry0) + 0));
1453 spin_unlock_irqrestore(&ioapic_lock, flags);
1456 int timer_uses_ioapic_pin_0;
1459 * This code may look a bit paranoid, but it's supposed to cooperate with
1460 * a wide range of boards and BIOS bugs. Fortunately only the timer IRQ
1461 * is so screwy. Thanks to Brian Perkins for testing/hacking this beast
1462 * fanatically on his truly buggy board.
1464 * FIXME: really need to revamp this for modern platforms only.
1466 static inline void check_timer(void)
1468 int apic1, pin1, apic2, pin2;
1472 * get/set the timer IRQ vector:
1474 disable_8259A_irq(0);
1475 vector = assign_irq_vector(0);
1476 set_intr_gate(vector, interrupt[0]);
1479 * Subtle, code in do_timer_interrupt() expects an AEOI
1480 * mode for the 8259A whenever interrupts are routed
1481 * through I/O APICs. Also IRQ0 has to be enabled in
1482 * the 8259A which implies the virtual wire has to be
1483 * disabled in the local APIC.
1485 apic_write(APIC_LVT0, APIC_LVT_MASKED | APIC_DM_EXTINT);
1487 if (timer_over_8254 > 0)
1488 enable_8259A_irq(0);
1490 pin1 = find_isa_irq_pin(0, mp_INT);
1491 apic1 = find_isa_irq_apic(0, mp_INT);
1492 pin2 = ioapic_i8259.pin;
1493 apic2 = ioapic_i8259.apic;
1496 timer_uses_ioapic_pin_0 = 1;
1498 apic_printk(APIC_VERBOSE,KERN_INFO "..TIMER: vector=0x%02X apic1=%d pin1=%d apic2=%d pin2=%d\n",
1499 vector, apic1, pin1, apic2, pin2);
1503 * Ok, does IRQ0 through the IOAPIC work?
1505 unmask_IO_APIC_irq(0);
1506 if (!no_timer_check && timer_irq_works()) {
1507 nmi_watchdog_default();
1508 if (nmi_watchdog == NMI_IO_APIC) {
1509 disable_8259A_irq(0);
1511 enable_8259A_irq(0);
1513 if (disable_timer_pin_1 > 0)
1514 clear_IO_APIC_pin(0, pin1);
1517 clear_IO_APIC_pin(apic1, pin1);
1518 apic_printk(APIC_QUIET,KERN_ERR "..MP-BIOS bug: 8254 timer not "
1519 "connected to IO-APIC\n");
1522 apic_printk(APIC_VERBOSE,KERN_INFO "...trying to set up timer (IRQ0) "
1523 "through the 8259A ... ");
1525 apic_printk(APIC_VERBOSE,"\n..... (found apic %d pin %d) ...",
1528 * legacy devices should be connected to IO APIC #0
1530 setup_ExtINT_IRQ0_pin(apic2, pin2, vector);
1531 if (timer_irq_works()) {
1532 apic_printk(APIC_VERBOSE," works.\n");
1533 nmi_watchdog_default();
1534 if (nmi_watchdog == NMI_IO_APIC) {
1540 * Cleanup, just in case ...
1542 clear_IO_APIC_pin(apic2, pin2);
1544 apic_printk(APIC_VERBOSE," failed.\n");
1546 if (nmi_watchdog == NMI_IO_APIC) {
1547 printk(KERN_WARNING "timer doesn't work through the IO-APIC - disabling NMI Watchdog!\n");
1551 apic_printk(APIC_VERBOSE, KERN_INFO "...trying to set up timer as Virtual Wire IRQ...");
1553 disable_8259A_irq(0);
1554 irq_desc[0].chip = &lapic_irq_type;
1555 apic_write(APIC_LVT0, APIC_DM_FIXED | vector); /* Fixed mode */
1556 enable_8259A_irq(0);
1558 if (timer_irq_works()) {
1559 apic_printk(APIC_VERBOSE," works.\n");
1562 apic_write(APIC_LVT0, APIC_LVT_MASKED | APIC_DM_FIXED | vector);
1563 apic_printk(APIC_VERBOSE," failed.\n");
1565 apic_printk(APIC_VERBOSE, KERN_INFO "...trying to set up timer as ExtINT IRQ...");
1569 apic_write(APIC_LVT0, APIC_DM_EXTINT);
1571 unlock_ExtINT_logic();
1573 if (timer_irq_works()) {
1574 apic_printk(APIC_VERBOSE," works.\n");
1577 apic_printk(APIC_VERBOSE," failed :(.\n");
1578 panic("IO-APIC + timer doesn't work! Try using the 'noapic' kernel parameter\n");
1581 static int __init notimercheck(char *s)
1586 __setup("no_timer_check", notimercheck);
1590 * IRQ's that are handled by the PIC in the MPS IOAPIC case.
1591 * - IRQ2 is the cascade IRQ, and cannot be a io-apic IRQ.
1592 * Linux doesn't really care, as it's not actually used
1593 * for any interrupt handling anyway.
1595 #define PIC_IRQS (1<<2)
1597 void __init setup_IO_APIC(void)
1602 io_apic_irqs = ~0; /* all IRQs go through IOAPIC */
1604 io_apic_irqs = ~PIC_IRQS;
1606 apic_printk(APIC_VERBOSE, "ENABLING IO-APIC IRQs\n");
1609 setup_IO_APIC_irqs();
1610 init_IO_APIC_traps();
1616 struct sysfs_ioapic_data {
1617 struct sys_device dev;
1618 struct IO_APIC_route_entry entry[0];
1620 static struct sysfs_ioapic_data * mp_ioapic_data[MAX_IO_APICS];
1622 static int ioapic_suspend(struct sys_device *dev, pm_message_t state)
1624 struct IO_APIC_route_entry *entry;
1625 struct sysfs_ioapic_data *data;
1628 data = container_of(dev, struct sysfs_ioapic_data, dev);
1629 entry = data->entry;
1630 for (i = 0; i < nr_ioapic_registers[dev->id]; i ++, entry ++ )
1631 *entry = ioapic_read_entry(dev->id, i);
1636 static int ioapic_resume(struct sys_device *dev)
1638 struct IO_APIC_route_entry *entry;
1639 struct sysfs_ioapic_data *data;
1640 unsigned long flags;
1641 union IO_APIC_reg_00 reg_00;
1644 data = container_of(dev, struct sysfs_ioapic_data, dev);
1645 entry = data->entry;
1647 spin_lock_irqsave(&ioapic_lock, flags);
1648 reg_00.raw = io_apic_read(dev->id, 0);
1649 if (reg_00.bits.ID != mp_ioapics[dev->id].mpc_apicid) {
1650 reg_00.bits.ID = mp_ioapics[dev->id].mpc_apicid;
1651 io_apic_write(dev->id, 0, reg_00.raw);
1653 spin_unlock_irqrestore(&ioapic_lock, flags);
1654 for (i = 0; i < nr_ioapic_registers[dev->id]; i++)
1655 ioapic_write_entry(dev->id, i, entry[i]);
1660 static struct sysdev_class ioapic_sysdev_class = {
1661 set_kset_name("ioapic"),
1662 .suspend = ioapic_suspend,
1663 .resume = ioapic_resume,
1666 static int __init ioapic_init_sysfs(void)
1668 struct sys_device * dev;
1669 int i, size, error = 0;
1671 error = sysdev_class_register(&ioapic_sysdev_class);
1675 for (i = 0; i < nr_ioapics; i++ ) {
1676 size = sizeof(struct sys_device) + nr_ioapic_registers[i]
1677 * sizeof(struct IO_APIC_route_entry);
1678 mp_ioapic_data[i] = kmalloc(size, GFP_KERNEL);
1679 if (!mp_ioapic_data[i]) {
1680 printk(KERN_ERR "Can't suspend/resume IOAPIC %d\n", i);
1683 memset(mp_ioapic_data[i], 0, size);
1684 dev = &mp_ioapic_data[i]->dev;
1686 dev->cls = &ioapic_sysdev_class;
1687 error = sysdev_register(dev);
1689 kfree(mp_ioapic_data[i]);
1690 mp_ioapic_data[i] = NULL;
1691 printk(KERN_ERR "Can't suspend/resume IOAPIC %d\n", i);
1699 device_initcall(ioapic_init_sysfs);
1701 /* --------------------------------------------------------------------------
1702 ACPI-based IOAPIC Configuration
1703 -------------------------------------------------------------------------- */
1707 #define IO_APIC_MAX_ID 0xFE
1709 int __init io_apic_get_redir_entries (int ioapic)
1711 union IO_APIC_reg_01 reg_01;
1712 unsigned long flags;
1714 spin_lock_irqsave(&ioapic_lock, flags);
1715 reg_01.raw = io_apic_read(ioapic, 1);
1716 spin_unlock_irqrestore(&ioapic_lock, flags);
1718 return reg_01.bits.entries;
1722 int io_apic_set_pci_routing (int ioapic, int pin, int irq, int triggering, int polarity)
1724 struct IO_APIC_route_entry entry;
1725 unsigned long flags;
1727 if (!IO_APIC_IRQ(irq)) {
1728 apic_printk(APIC_QUIET,KERN_ERR "IOAPIC[%d]: Invalid reference to IRQ 0\n",
1734 * Generate a PCI IRQ routing entry and program the IOAPIC accordingly.
1735 * Note that we mask (disable) IRQs now -- these get enabled when the
1736 * corresponding device driver registers for this IRQ.
1739 memset(&entry,0,sizeof(entry));
1741 entry.delivery_mode = INT_DELIVERY_MODE;
1742 entry.dest_mode = INT_DEST_MODE;
1743 entry.dest.logical.logical_dest = cpu_mask_to_apicid(TARGET_CPUS);
1744 entry.trigger = triggering;
1745 entry.polarity = polarity;
1746 entry.mask = 1; /* Disabled (masked) */
1748 irq = gsi_irq_sharing(irq);
1750 * IRQs < 16 are already in the irq_2_pin[] map
1753 add_pin_to_irq(irq, ioapic, pin);
1755 entry.vector = assign_irq_vector(irq);
1757 apic_printk(APIC_VERBOSE,KERN_DEBUG "IOAPIC[%d]: Set PCI routing entry (%d-%d -> 0x%x -> "
1758 "IRQ %d Mode:%i Active:%i)\n", ioapic,
1759 mp_ioapics[ioapic].mpc_apicid, pin, entry.vector, irq,
1760 triggering, polarity);
1762 ioapic_register_intr(irq, entry.vector, triggering);
1764 if (!ioapic && (irq < 16))
1765 disable_8259A_irq(irq);
1767 ioapic_write_entry(ioapic, pin, entry);
1769 spin_lock_irqsave(&ioapic_lock, flags);
1770 set_native_irq_info(use_pci_vector() ? entry.vector : irq, TARGET_CPUS);
1771 spin_unlock_irqrestore(&ioapic_lock, flags);
1776 #endif /* CONFIG_ACPI */
1780 * This function currently is only a helper for the i386 smp boot process where
1781 * we need to reprogram the ioredtbls to cater for the cpus which have come online
1782 * so mask in all cases should simply be TARGET_CPUS
1785 void __init setup_ioapic_dest(void)
1787 int pin, ioapic, irq, irq_entry;
1789 if (skip_ioapic_setup == 1)
1792 for (ioapic = 0; ioapic < nr_ioapics; ioapic++) {
1793 for (pin = 0; pin < nr_ioapic_registers[ioapic]; pin++) {
1794 irq_entry = find_irq_entry(ioapic, pin, mp_INT);
1795 if (irq_entry == -1)
1797 irq = pin_2_irq(irq_entry, ioapic, pin);
1798 set_ioapic_affinity_irq(irq, TARGET_CPUS);