2 * numa.c - Low-level PCI access for NUMA-Q machines
6 #include <linux/init.h>
7 #include <linux/nodemask.h>
11 #define XQUAD_PORTIO_BASE 0xfe400000
12 #define XQUAD_PORTIO_QUAD 0x40000 /* 256k per quad. */
14 #define BUS2QUAD(global) (mp_bus_id_to_node[global])
16 int mp_bus_id_to_local[MAX_MP_BUSSES];
17 #define BUS2LOCAL(global) (mp_bus_id_to_local[global])
19 int quad_local_to_mp_bus_id [NR_CPUS/4][4];
20 #define QUADLOCAL2BUS(quad,local) (quad_local_to_mp_bus_id[quad][local])
22 extern void *xquad_portio; /* Where the IO area was mapped */
23 #define XQUAD_PORT_ADDR(port, quad) (xquad_portio + (XQUAD_PORTIO_QUAD*quad) + port)
25 #define PCI_CONF1_MQ_ADDRESS(bus, devfn, reg) \
26 (0x80000000 | (BUS2LOCAL(bus) << 16) | (devfn << 8) | (reg & ~3))
28 static void write_cf8(unsigned bus, unsigned devfn, unsigned reg)
30 unsigned val = PCI_CONF1_MQ_ADDRESS(bus, devfn, reg);
32 writel(val, XQUAD_PORT_ADDR(0xcf8, BUS2QUAD(bus)));
37 static int pci_conf1_mq_read(unsigned int seg, unsigned int bus,
38 unsigned int devfn, int reg, int len, u32 *value)
41 void *adr __iomem = XQUAD_PORT_ADDR(0xcfc, BUS2QUAD(bus));
43 if (!value || (bus >= MAX_MP_BUSSES) || (devfn > 255) || (reg > 255))
46 spin_lock_irqsave(&pci_config_lock, flags);
48 write_cf8(bus, devfn, reg);
53 *value = readb(adr + (reg & 3));
55 *value = inb(0xCFC + (reg & 3));
59 *value = readw(adr + (reg & 2));
61 *value = inw(0xCFC + (reg & 2));
71 spin_unlock_irqrestore(&pci_config_lock, flags);
76 static int pci_conf1_mq_write(unsigned int seg, unsigned int bus,
77 unsigned int devfn, int reg, int len, u32 value)
80 void *adr __iomem = XQUAD_PORT_ADDR(0xcfc, BUS2QUAD(bus));
82 if ((bus >= MAX_MP_BUSSES) || (devfn > 255) || (reg > 255))
85 spin_lock_irqsave(&pci_config_lock, flags);
87 write_cf8(bus, devfn, reg);
92 writeb(value, adr + (reg & 3));
94 outb((u8)value, 0xCFC + (reg & 3));
98 writew(value, adr + (reg & 2));
100 outw((u16)value, 0xCFC + (reg & 2));
104 writel(value, adr + reg);
106 outl((u32)value, 0xCFC);
110 spin_unlock_irqrestore(&pci_config_lock, flags);
115 #undef PCI_CONF1_MQ_ADDRESS
117 static struct pci_raw_ops pci_direct_conf1_mq = {
118 .read = pci_conf1_mq_read,
119 .write = pci_conf1_mq_write
123 static void __devinit pci_fixup_i450nx(struct pci_dev *d)
126 * i450NX -- Find and scan all secondary buses on all PXB's.
129 u8 busno, suba, subb;
130 int quad = BUS2QUAD(d->bus->number);
132 printk("PCI: Searching for i450NX host bridges on %s\n", pci_name(d));
134 for(pxb=0; pxb<2; pxb++) {
135 pci_read_config_byte(d, reg++, &busno);
136 pci_read_config_byte(d, reg++, &suba);
137 pci_read_config_byte(d, reg++, &subb);
138 DBG("i450NX PXB %d: %02x/%02x/%02x\n", pxb, busno, suba, subb);
141 pci_scan_bus_with_sysdata(QUADLOCAL2BUS(quad, busno));
145 pci_scan_bus_with_sysdata(QUADLOCAL2BUS(quad, suba+1));
148 pcibios_last_bus = -1;
150 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82451NX, pci_fixup_i450nx);
152 static int __init pci_numa_init(void)
156 raw_pci_ops = &pci_direct_conf1_mq;
158 if (pcibios_scanned++)
161 pci_root_bus = pcibios_scan_root(0);
163 pci_bus_add_devices(pci_root_bus);
164 if (num_online_nodes() > 1)
165 for_each_online_node(quad) {
168 printk("Scanning PCI bus %d for quad %d\n",
169 QUADLOCAL2BUS(quad,0), quad);
170 pci_scan_bus_with_sysdata(QUADLOCAL2BUS(quad, 0));
175 subsys_initcall(pci_numa_init);