2 * numa.c - Low-level PCI access for NUMA-Q machines
6 #include <linux/init.h>
7 #include <linux/nodemask.h>
11 #define XQUAD_PORTIO_BASE 0xfe400000
12 #define XQUAD_PORTIO_QUAD 0x40000 /* 256k per quad. */
14 int mp_bus_id_to_node[MAX_MP_BUSSES];
15 #define BUS2QUAD(global) (mp_bus_id_to_node[global])
17 int mp_bus_id_to_local[MAX_MP_BUSSES];
18 #define BUS2LOCAL(global) (mp_bus_id_to_local[global])
20 int quad_local_to_mp_bus_id [NR_CPUS/4][4];
21 #define QUADLOCAL2BUS(quad,local) (quad_local_to_mp_bus_id[quad][local])
23 /* Where the IO area was mapped on multiquad, always 0 otherwise */
25 #ifdef CONFIG_X86_NUMAQ
26 EXPORT_SYMBOL(xquad_portio);
29 #define XQUAD_PORT_ADDR(port, quad) (xquad_portio + (XQUAD_PORTIO_QUAD*quad) + port)
31 #define PCI_CONF1_MQ_ADDRESS(bus, devfn, reg) \
32 (0x80000000 | (BUS2LOCAL(bus) << 16) | (devfn << 8) | (reg & ~3))
34 static void write_cf8(unsigned bus, unsigned devfn, unsigned reg)
36 unsigned val = PCI_CONF1_MQ_ADDRESS(bus, devfn, reg);
38 writel(val, XQUAD_PORT_ADDR(0xcf8, BUS2QUAD(bus)));
43 static int pci_conf1_mq_read(unsigned int seg, unsigned int bus,
44 unsigned int devfn, int reg, int len, u32 *value)
47 void *adr __iomem = XQUAD_PORT_ADDR(0xcfc, BUS2QUAD(bus));
49 if (!value || (bus >= MAX_MP_BUSSES) || (devfn > 255) || (reg > 255))
52 spin_lock_irqsave(&pci_config_lock, flags);
54 write_cf8(bus, devfn, reg);
59 *value = readb(adr + (reg & 3));
61 *value = inb(0xCFC + (reg & 3));
65 *value = readw(adr + (reg & 2));
67 *value = inw(0xCFC + (reg & 2));
77 spin_unlock_irqrestore(&pci_config_lock, flags);
82 static int pci_conf1_mq_write(unsigned int seg, unsigned int bus,
83 unsigned int devfn, int reg, int len, u32 value)
86 void *adr __iomem = XQUAD_PORT_ADDR(0xcfc, BUS2QUAD(bus));
88 if ((bus >= MAX_MP_BUSSES) || (devfn > 255) || (reg > 255))
91 spin_lock_irqsave(&pci_config_lock, flags);
93 write_cf8(bus, devfn, reg);
98 writeb(value, adr + (reg & 3));
100 outb((u8)value, 0xCFC + (reg & 3));
104 writew(value, adr + (reg & 2));
106 outw((u16)value, 0xCFC + (reg & 2));
110 writel(value, adr + reg);
112 outl((u32)value, 0xCFC);
116 spin_unlock_irqrestore(&pci_config_lock, flags);
121 #undef PCI_CONF1_MQ_ADDRESS
123 static struct pci_raw_ops pci_direct_conf1_mq = {
124 .read = pci_conf1_mq_read,
125 .write = pci_conf1_mq_write
129 static void __devinit pci_fixup_i450nx(struct pci_dev *d)
132 * i450NX -- Find and scan all secondary buses on all PXB's.
135 u8 busno, suba, subb;
136 int quad = BUS2QUAD(d->bus->number);
138 printk("PCI: Searching for i450NX host bridges on %s\n", pci_name(d));
140 for(pxb=0; pxb<2; pxb++) {
141 pci_read_config_byte(d, reg++, &busno);
142 pci_read_config_byte(d, reg++, &suba);
143 pci_read_config_byte(d, reg++, &subb);
144 DBG("i450NX PXB %d: %02x/%02x/%02x\n", pxb, busno, suba, subb);
147 pci_scan_bus_with_sysdata(QUADLOCAL2BUS(quad, busno));
151 pci_scan_bus_with_sysdata(QUADLOCAL2BUS(quad, suba+1));
154 pcibios_last_bus = -1;
156 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82451NX, pci_fixup_i450nx);
158 static int __init pci_numa_init(void)
162 raw_pci_ops = &pci_direct_conf1_mq;
164 if (pcibios_scanned++)
167 pci_root_bus = pcibios_scan_root(0);
169 pci_bus_add_devices(pci_root_bus);
170 if (num_online_nodes() > 1)
171 for_each_online_node(quad) {
174 printk("Scanning PCI bus %d for quad %d\n",
175 QUADLOCAL2BUS(quad,0), quad);
176 pci_scan_bus_with_sysdata(QUADLOCAL2BUS(quad, 0));
181 subsys_initcall(pci_numa_init);