2 * mmconfig-shared.c - Low-level direct PCI config space access via
3 * MMCONFIG - common code between i386 and x86-64.
6 * - known chipset handling
7 * - ACPI decoding and validation
9 * Per-architecture code takes care of the mappings and accesses
13 #include <linux/pci.h>
14 #include <linux/init.h>
15 #include <linux/acpi.h>
16 #include <linux/bitmap.h>
21 /* aperture is up to 256MB but BIOS may reserve less */
22 #define MMCONFIG_APER_MIN (2 * 1024*1024)
23 #define MMCONFIG_APER_MAX (256 * 1024*1024)
25 /* Indicate if the mmcfg resources have been placed into the resource table. */
26 static int __initdata pci_mmcfg_resources_inserted;
28 static const char __init *pci_mmcfg_e7520(void)
31 pci_direct_conf1.read(0, 0, PCI_DEVFN(0,0), 0xce, 2, &win);
34 if(win == 0x0000 || win == 0xf000)
35 pci_mmcfg_config_num = 0;
37 pci_mmcfg_config_num = 1;
38 pci_mmcfg_config = kzalloc(sizeof(pci_mmcfg_config[0]), GFP_KERNEL);
39 if (!pci_mmcfg_config)
41 pci_mmcfg_config[0].address = win << 16;
42 pci_mmcfg_config[0].pci_segment = 0;
43 pci_mmcfg_config[0].start_bus_number = 0;
44 pci_mmcfg_config[0].end_bus_number = 255;
47 return "Intel Corporation E7520 Memory Controller Hub";
50 static const char __init *pci_mmcfg_intel_945(void)
52 u32 pciexbar, mask = 0, len = 0;
54 pci_mmcfg_config_num = 1;
56 pci_direct_conf1.read(0, 0, PCI_DEVFN(0,0), 0x48, 4, &pciexbar);
60 pci_mmcfg_config_num = 0;
63 switch ((pciexbar >> 1) & 3) {
77 pci_mmcfg_config_num = 0;
80 /* Errata #2, things break when not aligned on a 256Mb boundary */
81 /* Can only happen in 64M/128M mode */
83 if ((pciexbar & mask) & 0x0fffffffU)
84 pci_mmcfg_config_num = 0;
86 /* Don't hit the APIC registers and their friends */
87 if ((pciexbar & mask) >= 0xf0000000U)
88 pci_mmcfg_config_num = 0;
90 if (pci_mmcfg_config_num) {
91 pci_mmcfg_config = kzalloc(sizeof(pci_mmcfg_config[0]), GFP_KERNEL);
92 if (!pci_mmcfg_config)
94 pci_mmcfg_config[0].address = pciexbar & mask;
95 pci_mmcfg_config[0].pci_segment = 0;
96 pci_mmcfg_config[0].start_bus_number = 0;
97 pci_mmcfg_config[0].end_bus_number = (len >> 20) - 1;
100 return "Intel Corporation 945G/GZ/P/PL Express Memory Controller Hub";
103 static const char __init *pci_mmcfg_amd_fam10h(void)
105 u32 low, high, address;
108 unsigned segnbits = 0, busnbits;
110 address = MSR_FAM10H_MMIO_CONF_BASE;
111 if (rdmsr_safe(address, &low, &high))
118 /* mmconfig is not enable */
119 if (!(msr & FAM10H_MMIO_CONF_ENABLE))
122 base = msr & (FAM10H_MMIO_CONF_BASE_MASK<<FAM10H_MMIO_CONF_BASE_SHIFT);
124 busnbits = (msr >> FAM10H_MMIO_CONF_BUSRANGE_SHIFT) &
125 FAM10H_MMIO_CONF_BUSRANGE_MASK;
128 * only handle bus 0 ?
135 segnbits = busnbits - 8;
139 pci_mmcfg_config_num = (1 << segnbits);
140 pci_mmcfg_config = kzalloc(sizeof(pci_mmcfg_config[0]) *
141 pci_mmcfg_config_num, GFP_KERNEL);
142 if (!pci_mmcfg_config)
145 for (i = 0; i < (1 << segnbits); i++) {
146 pci_mmcfg_config[i].address = base + (1<<28) * i;
147 pci_mmcfg_config[i].pci_segment = i;
148 pci_mmcfg_config[i].start_bus_number = 0;
149 pci_mmcfg_config[i].end_bus_number = (1 << busnbits) - 1;
152 return "AMD Family 10h NB";
155 struct pci_mmcfg_hostbridge_probe {
160 const char *(*probe)(void);
163 static struct pci_mmcfg_hostbridge_probe pci_mmcfg_probes[] __initdata = {
164 { 0, PCI_DEVFN(0, 0), PCI_VENDOR_ID_INTEL,
165 PCI_DEVICE_ID_INTEL_E7520_MCH, pci_mmcfg_e7520 },
166 { 0, PCI_DEVFN(0, 0), PCI_VENDOR_ID_INTEL,
167 PCI_DEVICE_ID_INTEL_82945G_HB, pci_mmcfg_intel_945 },
168 { 0, PCI_DEVFN(0x18, 0), PCI_VENDOR_ID_AMD,
169 0x1200, pci_mmcfg_amd_fam10h },
170 { 0xff, PCI_DEVFN(0, 0), PCI_VENDOR_ID_AMD,
171 0x1200, pci_mmcfg_amd_fam10h },
174 static int __init pci_mmcfg_check_hostbridge(void)
182 pci_mmcfg_config_num = 0;
183 pci_mmcfg_config = NULL;
186 for (i = 0; !name && i < ARRAY_SIZE(pci_mmcfg_probes); i++) {
187 bus = pci_mmcfg_probes[i].bus;
188 devfn = pci_mmcfg_probes[i].devfn;
189 pci_direct_conf1.read(0, bus, devfn, 0, 4, &l);
191 device = (l >> 16) & 0xffff;
193 if (pci_mmcfg_probes[i].vendor == vendor &&
194 pci_mmcfg_probes[i].device == device)
195 name = pci_mmcfg_probes[i].probe();
199 printk(KERN_INFO "PCI: Found %s %s MMCONFIG support.\n",
200 name, pci_mmcfg_config_num ? "with" : "without");
206 static void __init pci_mmcfg_insert_resources(unsigned long resource_flags)
208 #define PCI_MMCFG_RESOURCE_NAME_LEN 19
210 struct resource *res;
214 res = kcalloc(PCI_MMCFG_RESOURCE_NAME_LEN + sizeof(*res),
215 pci_mmcfg_config_num, GFP_KERNEL);
217 printk(KERN_ERR "PCI: Unable to allocate MMCONFIG resources\n");
221 names = (void *)&res[pci_mmcfg_config_num];
222 for (i = 0; i < pci_mmcfg_config_num; i++, res++) {
223 struct acpi_mcfg_allocation *cfg = &pci_mmcfg_config[i];
224 num_buses = cfg->end_bus_number - cfg->start_bus_number + 1;
226 snprintf(names, PCI_MMCFG_RESOURCE_NAME_LEN, "PCI MMCONFIG %u",
228 res->start = cfg->address;
229 res->end = res->start + (num_buses << 20) - 1;
230 res->flags = IORESOURCE_MEM | resource_flags;
231 insert_resource(&iomem_resource, res);
232 names += PCI_MMCFG_RESOURCE_NAME_LEN;
235 /* Mark that the resources have been inserted. */
236 pci_mmcfg_resources_inserted = 1;
239 static acpi_status __init check_mcfg_resource(struct acpi_resource *res,
242 struct resource *mcfg_res = data;
243 struct acpi_resource_address64 address;
246 if (res->type == ACPI_RESOURCE_TYPE_FIXED_MEMORY32) {
247 struct acpi_resource_fixed_memory32 *fixmem32 =
248 &res->data.fixed_memory32;
251 if ((mcfg_res->start >= fixmem32->address) &&
252 (mcfg_res->end < (fixmem32->address +
253 fixmem32->address_length))) {
255 return AE_CTRL_TERMINATE;
258 if ((res->type != ACPI_RESOURCE_TYPE_ADDRESS32) &&
259 (res->type != ACPI_RESOURCE_TYPE_ADDRESS64))
262 status = acpi_resource_to_address64(res, &address);
263 if (ACPI_FAILURE(status) ||
264 (address.address_length <= 0) ||
265 (address.resource_type != ACPI_MEMORY_RANGE))
268 if ((mcfg_res->start >= address.minimum) &&
269 (mcfg_res->end < (address.minimum + address.address_length))) {
271 return AE_CTRL_TERMINATE;
276 static acpi_status __init find_mboard_resource(acpi_handle handle, u32 lvl,
277 void *context, void **rv)
279 struct resource *mcfg_res = context;
281 acpi_walk_resources(handle, METHOD_NAME__CRS,
282 check_mcfg_resource, context);
285 return AE_CTRL_TERMINATE;
290 static int __init is_acpi_reserved(unsigned long start, unsigned long end)
292 struct resource mcfg_res;
294 mcfg_res.start = start;
298 acpi_get_devices("PNP0C01", find_mboard_resource, &mcfg_res, NULL);
301 acpi_get_devices("PNP0C02", find_mboard_resource, &mcfg_res,
304 return mcfg_res.flags;
307 static void __init pci_mmcfg_reject_broken(int type, int early)
309 typeof(pci_mmcfg_config[0]) *cfg;
312 if ((pci_mmcfg_config_num == 0) ||
313 (pci_mmcfg_config == NULL) ||
314 (pci_mmcfg_config[0].address == 0))
317 cfg = &pci_mmcfg_config[0];
319 for (i = 0; i < pci_mmcfg_config_num; i++) {
321 u32 size = (cfg->end_bus_number + 1) << 20;
322 cfg = &pci_mmcfg_config[i];
323 printk(KERN_NOTICE "PCI: MCFG configuration %d: base %lx "
324 "segment %hu buses %u - %u\n",
325 i, (unsigned long)cfg->address, cfg->pci_segment,
326 (unsigned int)cfg->start_bus_number,
327 (unsigned int)cfg->end_bus_number);
330 is_acpi_reserved(cfg->address, cfg->address + size - 1)) {
331 printk(KERN_NOTICE "PCI: MCFG area at %Lx reserved "
332 "in ACPI motherboard resources\n",
341 printk(KERN_ERR "PCI: BIOS Bug: MCFG area at %Lx is not"
342 " reserved in ACPI motherboard resources\n",
344 /* Don't try to do this check unless configuration
345 type 1 is available. */
346 if (type == 1 && e820_all_mapped(cfg->address,
347 cfg->address + size - 1,
350 "PCI: MCFG area at %Lx reserved in E820\n",
362 printk(KERN_ERR "PCI: Not using MMCONFIG.\n");
363 pci_mmcfg_arch_free();
364 kfree(pci_mmcfg_config);
365 pci_mmcfg_config = NULL;
366 pci_mmcfg_config_num = 0;
369 static int __initdata known_bridge;
371 void __init __pci_mmcfg_init(int type, int early)
373 /* MMCONFIG disabled */
374 if ((pci_probe & PCI_PROBE_MMCONF) == 0)
377 /* MMCONFIG already enabled */
378 if (!early && !(pci_probe & PCI_PROBE_MASK & ~PCI_PROBE_MMCONF))
381 /* for late to exit */
385 if (early && type == 1) {
386 if (pci_mmcfg_check_hostbridge())
391 acpi_table_parse(ACPI_SIG_MCFG, acpi_parse_mcfg);
392 pci_mmcfg_reject_broken(type, early);
395 if ((pci_mmcfg_config_num == 0) ||
396 (pci_mmcfg_config == NULL) ||
397 (pci_mmcfg_config[0].address == 0))
400 if (pci_mmcfg_arch_init()) {
402 pci_mmcfg_insert_resources(IORESOURCE_BUSY);
403 pci_probe = (pci_probe & ~PCI_PROBE_MASK) | PCI_PROBE_MMCONF;
406 * Signal not to attempt to insert mmcfg resources because
407 * the architecture mmcfg setup could not initialize.
409 pci_mmcfg_resources_inserted = 1;
413 void __init pci_mmcfg_early_init(int type)
415 __pci_mmcfg_init(type, 1);
418 void __init pci_mmcfg_late_init(void)
422 if (pci_probe & PCI_PROBE_CONF1)
425 __pci_mmcfg_init(type, 0);
428 static int __init pci_mmcfg_late_insert_resources(void)
431 * If resources are already inserted or we are not using MMCONFIG,
432 * don't insert the resources.
434 if ((pci_mmcfg_resources_inserted == 1) ||
435 (pci_probe & PCI_PROBE_MMCONF) == 0 ||
436 (pci_mmcfg_config_num == 0) ||
437 (pci_mmcfg_config == NULL) ||
438 (pci_mmcfg_config[0].address == 0))
442 * Attempt to insert the mmcfg resources but not with the busy flag
443 * marked so it won't cause request errors when __request_region is
446 pci_mmcfg_insert_resources(0);
452 * Perform MMCONFIG resource insertion after PCI initialization to allow for
453 * misprogrammed MCFG tables that state larger sizes but actually conflict
454 * with other system resources.
456 late_initcall(pci_mmcfg_late_insert_resources);