1 #include <linux/init.h>
3 #include <asm/pci-direct.h>
4 #include <asm/mpspec.h>
5 #include <linux/cpumask.h>
6 #include <linux/topology.h>
9 * This discovers the pcibus <-> node mapping on AMD K8.
10 * also get peer root bus resource for io,mmio
15 * sub bus (transparent) will use entres from 3 to store extra from root,
16 * so need to make sure have enought slot there, increase PCI_BUS_NUM_RESOURCES?
19 struct pci_root_info {
22 struct resource res[RES_NUM];
29 /* 4 at this time, it may become to 32 */
31 static int pci_root_num;
32 static struct pci_root_info pci_root_info[PCI_ROOT_NR];
38 static int mp_bus_to_node[BUS_NR];
40 void set_mp_bus_to_node(int busnum, int node)
42 if (busnum >= 0 && busnum < BUS_NR)
43 mp_bus_to_node[busnum] = node;
46 int get_mp_bus_to_node(int busnum)
50 if (busnum < 0 || busnum > (BUS_NR - 1))
53 node = mp_bus_to_node[busnum];
56 * let numa_node_id to decide it later in dma_alloc_pages
57 * if there is no ram on that node
59 if (node != -1 && !node_online(node))
66 void set_pci_bus_resources_arch_default(struct pci_bus *b)
70 struct pci_root_info *info;
72 /* if only one root bus, don't need to anything */
76 for (i = 0; i < pci_root_num; i++) {
77 if (pci_root_info[i].bus_min == b->number)
81 if (i == pci_root_num)
84 info = &pci_root_info[i];
85 for (j = 0; j < info->res_num; j++) {
87 struct resource *root;
91 if (res->flags & IORESOURCE_IO)
92 root = &ioport_resource;
94 root = &iomem_resource;
95 insert_resource(root, res);
106 static void __init update_range(struct res_range *range, size_t start,
112 for (j = 0; j < RANGE_NUM; j++) {
115 if (start == range[j].start && end < range[j].end) {
116 range[j].start = end + 1;
118 } else if (start == range[j].start && end == range[j].end) {
122 } else if (start > range[j].start && end == range[j].end) {
123 range[j].end = start - 1;
125 } else if (start > range[j].start && end < range[j].end) {
126 /* find the new spare */
127 for (i = 0; i < RANGE_NUM; i++) {
128 if (range[i].end == 0)
132 range[i].end = range[j].end;
133 range[i].start = end + 1;
135 printk(KERN_ERR "run of slot in ranges\n");
137 range[j].end = start - 1;
143 static void __init update_res(struct pci_root_info *info, size_t start,
144 size_t end, unsigned long flags, int merge)
147 struct resource *res;
152 /* try to merge it with old one */
153 for (i = 0; i < info->res_num; i++) {
155 if (res->flags != flags)
157 if (res->end + 1 == start) {
160 } else if (end + 1 == res->start) {
168 /* need to add that */
169 if (info->res_num >= RES_NUM)
172 res = &info->res[info->res_num];
173 res->name = info->name;
181 struct pci_hostbridge_probe {
188 static struct pci_hostbridge_probe pci_probes[] __initdata = {
189 { 0, 0x18, PCI_VENDOR_ID_AMD, 0x1100 },
190 { 0, 0x18, PCI_VENDOR_ID_AMD, 0x1200 },
191 { 0xff, 0, PCI_VENDOR_ID_AMD, 0x1200 },
192 { 0, 0x18, PCI_VENDOR_ID_AMD, 0x1300 },
195 static u64 __initdata fam10h_mmconf_start;
196 static u64 __initdata fam10h_mmconf_end;
197 static void __init get_pci_mmcfg_amd_fam10h_range(void)
201 unsigned segn_busn_bits;
203 /* assume all cpus from fam10h have mmconf */
204 if (boot_cpu_data.x86 < 0x10)
207 address = MSR_FAM10H_MMIO_CONF_BASE;
208 rdmsrl(address, msr);
210 /* mmconfig is not enable */
211 if (!(msr & FAM10H_MMIO_CONF_ENABLE))
214 base = msr & (FAM10H_MMIO_CONF_BASE_MASK<<FAM10H_MMIO_CONF_BASE_SHIFT);
216 segn_busn_bits = (msr >> FAM10H_MMIO_CONF_BUSRANGE_SHIFT) &
217 FAM10H_MMIO_CONF_BUSRANGE_MASK;
219 fam10h_mmconf_start = base;
220 fam10h_mmconf_end = base + (1ULL<<(segn_busn_bits + 20)) - 1;
224 * early_fill_mp_bus_to_node()
225 * called before pcibios_scan_root and pci_scan_bus
226 * fills the mp_bus_to_cpumask array based according to the LDT Bus Number
227 * Registers found in the K8 northbridge
229 static int __init early_fill_mp_bus_info(void)
240 struct pci_root_info *info;
242 struct resource *res;
245 struct res_range range[RANGE_NUM];
250 for (i = 0; i < BUS_NR; i++)
251 mp_bus_to_node[i] = -1;
254 if (!early_pci_allowed())
258 for (i = 0; i < ARRAY_SIZE(pci_probes); i++) {
263 bus = pci_probes[i].bus;
264 slot = pci_probes[i].slot;
265 id = read_pci_config(bus, slot, 0, PCI_VENDOR_ID);
267 vendor = id & 0xffff;
268 device = (id>>16) & 0xffff;
269 if (pci_probes[i].vendor == vendor &&
270 pci_probes[i].device == device) {
280 for (i = 0; i < 4; i++) {
283 reg = read_pci_config(bus, slot, 1, 0xe0 + (i << 2));
285 /* Check if that register is enabled for bus range */
289 min_bus = (reg >> 16) & 0xff;
290 max_bus = (reg >> 24) & 0xff;
291 node = (reg >> 4) & 0x07;
293 for (j = min_bus; j <= max_bus; j++)
294 mp_bus_to_node[j] = (unsigned char) node;
296 link = (reg >> 8) & 0x03;
298 info = &pci_root_info[pci_root_num];
299 info->bus_min = min_bus;
300 info->bus_max = max_bus;
303 sprintf(info->name, "PCI Bus #%02x", min_bus);
307 /* get the default node and link for left over res */
308 reg = read_pci_config(bus, slot, 0, 0x60);
309 def_node = (reg >> 8) & 0x07;
310 reg = read_pci_config(bus, slot, 0, 0x64);
311 def_link = (reg >> 8) & 0x03;
313 memset(range, 0, sizeof(range));
314 range[0].end = 0xffff;
315 /* io port resource */
316 for (i = 0; i < 4; i++) {
317 reg = read_pci_config(bus, slot, 1, 0xc0 + (i << 3));
321 start = reg & 0xfff000;
322 reg = read_pci_config(bus, slot, 1, 0xc4 + (i << 3));
324 link = (reg >> 4) & 0x03;
325 end = (reg & 0xfff000) | 0xfff;
327 /* find the position */
328 for (j = 0; j < pci_root_num; j++) {
329 info = &pci_root_info[j];
330 if (info->node == node && info->link == link)
333 if (j == pci_root_num)
334 continue; /* not found */
336 info = &pci_root_info[j];
337 printk(KERN_DEBUG "node %d link %d: io port [%llx, %llx]\n",
338 node, link, (u64)start, (u64)end);
339 update_res(info, start, end, IORESOURCE_IO, 0);
340 update_range(range, start, end);
342 /* add left over io port range to def node/link, [0, 0xffff] */
343 /* find the position */
344 for (j = 0; j < pci_root_num; j++) {
345 info = &pci_root_info[j];
346 if (info->node == def_node && info->link == def_link)
349 if (j < pci_root_num) {
350 info = &pci_root_info[j];
351 for (i = 0; i < RANGE_NUM; i++) {
355 update_res(info, range[i].start, range[i].end,
360 memset(range, 0, sizeof(range));
361 /* 0xfd00000000-0xffffffffff for HT */
362 range[0].end = (0xfdULL<<32) - 1;
364 /* need to take out [0, TOM) for RAM*/
365 address = MSR_K8_TOP_MEM1;
366 rdmsrl(address, val);
367 end = (val & 0xffffff8000000ULL);
368 printk(KERN_INFO "TOM: %016lx aka %ldM\n", end, end>>20);
369 if (end < (1ULL<<32))
370 update_range(range, 0, end - 1);
373 get_pci_mmcfg_amd_fam10h_range();
374 /* need to take out mmconf range */
375 if (fam10h_mmconf_end) {
376 printk(KERN_DEBUG "Fam 10h mmconf [%llx, %llx]\n", fam10h_mmconf_start, fam10h_mmconf_end);
377 update_range(range, fam10h_mmconf_start, fam10h_mmconf_end);
381 for (i = 0; i < 8; i++) {
382 reg = read_pci_config(bus, slot, 1, 0x80 + (i << 3));
386 start = reg & 0xffffff00; /* 39:16 on 31:8*/
388 reg = read_pci_config(bus, slot, 1, 0x84 + (i << 3));
390 link = (reg >> 4) & 0x03;
391 end = (reg & 0xffffff00);
395 /* find the position */
396 for (j = 0; j < pci_root_num; j++) {
397 info = &pci_root_info[j];
398 if (info->node == node && info->link == link)
401 if (j == pci_root_num)
402 continue; /* not found */
404 info = &pci_root_info[j];
406 printk(KERN_DEBUG "node %d link %d: mmio [%llx, %llx]",
407 node, link, (u64)start, (u64)end);
409 * some sick allocation would have range overlap with fam10h
410 * mmconf range, so need to update start and end.
412 if (fam10h_mmconf_end) {
415 if (start >= fam10h_mmconf_start &&
416 start <= fam10h_mmconf_end) {
417 start = fam10h_mmconf_end + 1;
421 if (end >= fam10h_mmconf_start &&
422 end <= fam10h_mmconf_end) {
423 end = fam10h_mmconf_start - 1;
427 if (start < fam10h_mmconf_start &&
428 end > fam10h_mmconf_end) {
430 endx = fam10h_mmconf_start - 1;
431 update_res(info, start, endx, IORESOURCE_MEM, 0);
432 update_range(range, start, endx);
433 printk(KERN_CONT " ==> [%llx, %llx]", (u64)start, endx);
434 start = fam10h_mmconf_end + 1;
439 printk(KERN_CONT " %s [%llx, %llx]", endx?"and":"==>", (u64)start, (u64)end);
441 printk(KERN_CONT "%s\n", endx?"":" ==> none");
447 update_res(info, start, end, IORESOURCE_MEM, 0);
448 update_range(range, start, end);
449 printk(KERN_CONT "\n");
452 /* need to take out [4G, TOM2) for RAM*/
454 address = MSR_K8_SYSCFG;
455 rdmsrl(address, val);
456 /* TOP_MEM2 is enabled? */
459 address = MSR_K8_TOP_MEM2;
460 rdmsrl(address, val);
461 end = (val & 0xffffff8000000ULL);
462 printk(KERN_INFO "TOM2: %016lx aka %ldM\n", end, end>>20);
463 update_range(range, 1ULL<<32, end - 1);
467 * add left over mmio range to def node/link ?
468 * that is tricky, just record range in from start_min to 4G
470 for (j = 0; j < pci_root_num; j++) {
471 info = &pci_root_info[j];
472 if (info->node == def_node && info->link == def_link)
475 if (j < pci_root_num) {
476 info = &pci_root_info[j];
478 for (i = 0; i < RANGE_NUM; i++) {
482 update_res(info, range[i].start, range[i].end,
488 for (i = 0; i < BUS_NR; i++) {
489 node = mp_bus_to_node[i];
491 printk(KERN_DEBUG "bus: %02x to node: %02x\n", i, node);
495 for (i = 0; i < pci_root_num; i++) {
499 info = &pci_root_info[i];
500 res_num = info->res_num;
501 busnum = info->bus_min;
502 printk(KERN_DEBUG "bus: [%02x,%02x] on node %x link %x\n",
503 info->bus_min, info->bus_max, info->node, info->link);
504 for (j = 0; j < res_num; j++) {
506 printk(KERN_DEBUG "bus: %02x index %x %s: [%llx, %llx]\n",
508 (res->flags & IORESOURCE_IO)?"io port":"mmio",
509 res->start, res->end);
516 postcore_initcall(early_fill_mp_bus_info);