1 /******************************************************************************
4 * Generic x86 (32-bit and 64-bit) instruction decoder and emulator.
6 * Copyright (c) 2005 Keir Fraser
8 * Linux coding style, mod r/m decoder, segment base fixes, real-mode
9 * privileged instructions:
11 * Copyright (C) 2006 Qumranet
13 * Avi Kivity <avi@qumranet.com>
14 * Yaniv Kamay <yaniv@qumranet.com>
16 * This work is licensed under the terms of the GNU GPL, version 2. See
17 * the COPYING file in the top-level directory.
19 * From: xen-unstable 10676:af9809f51f81a3c43f276f00c81a52ef558afda4
25 #include <public/xen.h>
26 #define DPRINTF(_f, _a ...) printf(_f , ## _a)
28 #include <linux/kvm_host.h>
29 #define DPRINTF(x...) do {} while (0)
31 #include <linux/module.h>
32 #include <asm/kvm_x86_emulate.h>
35 * Opcode effective-address decode tables.
36 * Note that we only emulate instructions that have at least one memory
37 * operand (excluding implicit stack references). We assume that stack
38 * references and instruction fetches will never occur in special memory
39 * areas that require emulation. So, for example, 'mov <imm>,<reg>' need
43 /* Operand sizes: 8-bit operands or specified/overridden size. */
44 #define ByteOp (1<<0) /* 8-bit operands. */
45 /* Destination operand type. */
46 #define ImplicitOps (1<<1) /* Implicit in opcode. No generic decode. */
47 #define DstReg (2<<1) /* Register operand. */
48 #define DstMem (3<<1) /* Memory operand. */
49 #define DstMask (3<<1)
50 /* Source operand type. */
51 #define SrcNone (0<<3) /* No source operand. */
52 #define SrcImplicit (0<<3) /* Source operand is implicit in the opcode. */
53 #define SrcReg (1<<3) /* Register operand. */
54 #define SrcMem (2<<3) /* Memory operand. */
55 #define SrcMem16 (3<<3) /* Memory operand (16-bit). */
56 #define SrcMem32 (4<<3) /* Memory operand (32-bit). */
57 #define SrcImm (5<<3) /* Immediate operand. */
58 #define SrcImmByte (6<<3) /* 8-bit sign-extended immediate operand. */
59 #define SrcMask (7<<3)
60 /* Generic ModRM decode. */
62 /* Destination is only written; never read. */
65 #define MemAbs (1<<9) /* Memory operand is absolute displacement */
66 #define String (1<<10) /* String instruction (rep capable) */
67 #define Stack (1<<11) /* Stack instruction (push/pop) */
68 #define Group (1<<14) /* Bits 3:5 of modrm byte extend opcode */
69 #define GroupDual (1<<15) /* Alternate decoding of mod == 3 */
70 #define GroupMask 0xff /* Group number stored in bits 0:7 */
73 Group1_80, Group1_81, Group1_82, Group1_83,
74 Group1A, Group3_Byte, Group3, Group4, Group5, Group7,
77 static u16 opcode_table[256] = {
79 ByteOp | DstMem | SrcReg | ModRM, DstMem | SrcReg | ModRM,
80 ByteOp | DstReg | SrcMem | ModRM, DstReg | SrcMem | ModRM,
83 ByteOp | DstMem | SrcReg | ModRM, DstMem | SrcReg | ModRM,
84 ByteOp | DstReg | SrcMem | ModRM, DstReg | SrcMem | ModRM,
87 ByteOp | DstMem | SrcReg | ModRM, DstMem | SrcReg | ModRM,
88 ByteOp | DstReg | SrcMem | ModRM, DstReg | SrcMem | ModRM,
91 ByteOp | DstMem | SrcReg | ModRM, DstMem | SrcReg | ModRM,
92 ByteOp | DstReg | SrcMem | ModRM, DstReg | SrcMem | ModRM,
95 ByteOp | DstMem | SrcReg | ModRM, DstMem | SrcReg | ModRM,
96 ByteOp | DstReg | SrcMem | ModRM, DstReg | SrcMem | ModRM,
97 SrcImmByte, SrcImm, 0, 0,
99 ByteOp | DstMem | SrcReg | ModRM, DstMem | SrcReg | ModRM,
100 ByteOp | DstReg | SrcMem | ModRM, DstReg | SrcMem | ModRM,
103 ByteOp | DstMem | SrcReg | ModRM, DstMem | SrcReg | ModRM,
104 ByteOp | DstReg | SrcMem | ModRM, DstReg | SrcMem | ModRM,
107 ByteOp | DstMem | SrcReg | ModRM, DstMem | SrcReg | ModRM,
108 ByteOp | DstReg | SrcMem | ModRM, DstReg | SrcMem | ModRM,
111 DstReg, DstReg, DstReg, DstReg, DstReg, DstReg, DstReg, DstReg,
113 DstReg, DstReg, DstReg, DstReg, DstReg, DstReg, DstReg, DstReg,
115 SrcReg | Stack, SrcReg | Stack, SrcReg | Stack, SrcReg | Stack,
116 SrcReg | Stack, SrcReg | Stack, SrcReg | Stack, SrcReg | Stack,
118 DstReg | Stack, DstReg | Stack, DstReg | Stack, DstReg | Stack,
119 DstReg | Stack, DstReg | Stack, DstReg | Stack, DstReg | Stack,
121 0, 0, 0, DstReg | SrcMem32 | ModRM | Mov /* movsxd (x86/64) */ ,
124 0, 0, ImplicitOps | Mov | Stack, 0,
125 SrcNone | ByteOp | ImplicitOps, SrcNone | ImplicitOps, /* insb, insw/insd */
126 SrcNone | ByteOp | ImplicitOps, SrcNone | ImplicitOps, /* outsb, outsw/outsd */
128 ImplicitOps, ImplicitOps, ImplicitOps, ImplicitOps,
129 ImplicitOps, ImplicitOps, ImplicitOps, ImplicitOps,
131 ImplicitOps, ImplicitOps, ImplicitOps, ImplicitOps,
132 ImplicitOps, ImplicitOps, ImplicitOps, ImplicitOps,
134 Group | Group1_80, Group | Group1_81,
135 Group | Group1_82, Group | Group1_83,
136 ByteOp | DstMem | SrcReg | ModRM, DstMem | SrcReg | ModRM,
137 ByteOp | DstMem | SrcReg | ModRM, DstMem | SrcReg | ModRM,
139 ByteOp | DstMem | SrcReg | ModRM | Mov, DstMem | SrcReg | ModRM | Mov,
140 ByteOp | DstReg | SrcMem | ModRM | Mov, DstReg | SrcMem | ModRM | Mov,
141 0, ModRM | DstReg, 0, Group | Group1A,
143 0, 0, 0, 0, 0, 0, 0, 0,
144 0, 0, 0, 0, ImplicitOps | Stack, ImplicitOps | Stack, 0, 0,
146 ByteOp | DstReg | SrcMem | Mov | MemAbs, DstReg | SrcMem | Mov | MemAbs,
147 ByteOp | DstMem | SrcReg | Mov | MemAbs, DstMem | SrcReg | Mov | MemAbs,
148 ByteOp | ImplicitOps | Mov | String, ImplicitOps | Mov | String,
149 ByteOp | ImplicitOps | String, ImplicitOps | String,
151 0, 0, ByteOp | ImplicitOps | Mov | String, ImplicitOps | Mov | String,
152 ByteOp | ImplicitOps | Mov | String, ImplicitOps | Mov | String,
153 ByteOp | ImplicitOps | String, ImplicitOps | String,
155 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
157 ByteOp | DstMem | SrcImm | ModRM, DstMem | SrcImmByte | ModRM,
158 0, ImplicitOps | Stack, 0, 0,
159 ByteOp | DstMem | SrcImm | ModRM | Mov, DstMem | SrcImm | ModRM | Mov,
161 0, 0, 0, 0, 0, 0, 0, 0,
163 ByteOp | DstMem | SrcImplicit | ModRM, DstMem | SrcImplicit | ModRM,
164 ByteOp | DstMem | SrcImplicit | ModRM, DstMem | SrcImplicit | ModRM,
167 0, 0, 0, 0, 0, 0, 0, 0,
169 0, 0, 0, 0, 0, 0, 0, 0,
171 ImplicitOps | Stack, SrcImm|ImplicitOps, 0, SrcImmByte|ImplicitOps,
175 ImplicitOps, ImplicitOps, Group | Group3_Byte, Group | Group3,
177 ImplicitOps, 0, ImplicitOps, ImplicitOps,
178 0, 0, Group | Group4, Group | Group5,
181 static u16 twobyte_table[256] = {
183 0, Group | GroupDual | Group7, 0, 0, 0, 0, ImplicitOps, 0,
184 ImplicitOps, ImplicitOps, 0, 0, 0, ImplicitOps | ModRM, 0, 0,
186 0, 0, 0, 0, 0, 0, 0, 0, ImplicitOps | ModRM, 0, 0, 0, 0, 0, 0, 0,
188 ModRM | ImplicitOps, ModRM, ModRM | ImplicitOps, ModRM, 0, 0, 0, 0,
189 0, 0, 0, 0, 0, 0, 0, 0,
191 ImplicitOps, 0, ImplicitOps, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
193 DstReg | SrcMem | ModRM | Mov, DstReg | SrcMem | ModRM | Mov,
194 DstReg | SrcMem | ModRM | Mov, DstReg | SrcMem | ModRM | Mov,
195 DstReg | SrcMem | ModRM | Mov, DstReg | SrcMem | ModRM | Mov,
196 DstReg | SrcMem | ModRM | Mov, DstReg | SrcMem | ModRM | Mov,
198 DstReg | SrcMem | ModRM | Mov, DstReg | SrcMem | ModRM | Mov,
199 DstReg | SrcMem | ModRM | Mov, DstReg | SrcMem | ModRM | Mov,
200 DstReg | SrcMem | ModRM | Mov, DstReg | SrcMem | ModRM | Mov,
201 DstReg | SrcMem | ModRM | Mov, DstReg | SrcMem | ModRM | Mov,
203 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
205 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
207 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
209 ImplicitOps, ImplicitOps, ImplicitOps, ImplicitOps,
210 ImplicitOps, ImplicitOps, ImplicitOps, ImplicitOps,
211 ImplicitOps, ImplicitOps, ImplicitOps, ImplicitOps,
212 ImplicitOps, ImplicitOps, ImplicitOps, ImplicitOps,
214 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
216 0, 0, 0, DstMem | SrcReg | ModRM | BitOp, 0, 0, 0, 0,
218 0, 0, 0, DstMem | SrcReg | ModRM | BitOp, 0, 0, 0, 0,
220 ByteOp | DstMem | SrcReg | ModRM, DstMem | SrcReg | ModRM, 0,
221 DstMem | SrcReg | ModRM | BitOp,
222 0, 0, ByteOp | DstReg | SrcMem | ModRM | Mov,
223 DstReg | SrcMem16 | ModRM | Mov,
225 0, 0, DstMem | SrcImmByte | ModRM, DstMem | SrcReg | ModRM | BitOp,
226 0, 0, ByteOp | DstReg | SrcMem | ModRM | Mov,
227 DstReg | SrcMem16 | ModRM | Mov,
229 0, 0, 0, DstMem | SrcReg | ModRM | Mov, 0, 0, 0, ImplicitOps | ModRM,
230 0, 0, 0, 0, 0, 0, 0, 0,
232 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
234 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
236 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0
239 static u16 group_table[] = {
241 ByteOp | DstMem | SrcImm | ModRM, ByteOp | DstMem | SrcImm | ModRM,
242 ByteOp | DstMem | SrcImm | ModRM, ByteOp | DstMem | SrcImm | ModRM,
243 ByteOp | DstMem | SrcImm | ModRM, ByteOp | DstMem | SrcImm | ModRM,
244 ByteOp | DstMem | SrcImm | ModRM, ByteOp | DstMem | SrcImm | ModRM,
246 DstMem | SrcImm | ModRM, DstMem | SrcImm | ModRM,
247 DstMem | SrcImm | ModRM, DstMem | SrcImm | ModRM,
248 DstMem | SrcImm | ModRM, DstMem | SrcImm | ModRM,
249 DstMem | SrcImm | ModRM, DstMem | SrcImm | ModRM,
251 ByteOp | DstMem | SrcImm | ModRM, ByteOp | DstMem | SrcImm | ModRM,
252 ByteOp | DstMem | SrcImm | ModRM, ByteOp | DstMem | SrcImm | ModRM,
253 ByteOp | DstMem | SrcImm | ModRM, ByteOp | DstMem | SrcImm | ModRM,
254 ByteOp | DstMem | SrcImm | ModRM, ByteOp | DstMem | SrcImm | ModRM,
256 DstMem | SrcImmByte | ModRM, DstMem | SrcImmByte | ModRM,
257 DstMem | SrcImmByte | ModRM, DstMem | SrcImmByte | ModRM,
258 DstMem | SrcImmByte | ModRM, DstMem | SrcImmByte | ModRM,
259 DstMem | SrcImmByte | ModRM, DstMem | SrcImmByte | ModRM,
261 DstMem | SrcNone | ModRM | Mov | Stack, 0, 0, 0, 0, 0, 0, 0,
263 ByteOp | SrcImm | DstMem | ModRM, 0,
264 ByteOp | DstMem | SrcNone | ModRM, ByteOp | DstMem | SrcNone | ModRM,
267 DstMem | SrcImm | ModRM | SrcImm, 0,
268 DstMem | SrcNone | ModRM, ByteOp | DstMem | SrcNone | ModRM,
271 ByteOp | DstMem | SrcNone | ModRM, ByteOp | DstMem | SrcNone | ModRM,
274 DstMem | SrcNone | ModRM, DstMem | SrcNone | ModRM, 0, 0,
275 SrcMem | ModRM, 0, SrcMem | ModRM | Stack, 0,
277 0, 0, ModRM | SrcMem, ModRM | SrcMem,
278 SrcNone | ModRM | DstMem, 0, SrcMem | ModRM, SrcMem | ModRM | ByteOp,
281 static u16 group2_table[] = {
283 SrcNone | ModRM, 0, 0, 0, SrcNone | ModRM | DstMem, 0, SrcMem | ModRM, 0,
286 /* EFLAGS bit definitions. */
287 #define EFLG_OF (1<<11)
288 #define EFLG_DF (1<<10)
289 #define EFLG_SF (1<<7)
290 #define EFLG_ZF (1<<6)
291 #define EFLG_AF (1<<4)
292 #define EFLG_PF (1<<2)
293 #define EFLG_CF (1<<0)
296 * Instruction emulation:
297 * Most instructions are emulated directly via a fragment of inline assembly
298 * code. This allows us to save/restore EFLAGS and thus very easily pick up
299 * any modified flags.
302 #if defined(CONFIG_X86_64)
303 #define _LO32 "k" /* force 32-bit operand */
304 #define _STK "%%rsp" /* stack pointer */
305 #elif defined(__i386__)
306 #define _LO32 "" /* force 32-bit operand */
307 #define _STK "%%esp" /* stack pointer */
311 * These EFLAGS bits are restored from saved value during emulation, and
312 * any changes are written back to the saved value after emulation.
314 #define EFLAGS_MASK (EFLG_OF|EFLG_SF|EFLG_ZF|EFLG_AF|EFLG_PF|EFLG_CF)
316 /* Before executing instruction: restore necessary bits in EFLAGS. */
317 #define _PRE_EFLAGS(_sav, _msk, _tmp) \
318 /* EFLAGS = (_sav & _msk) | (EFLAGS & ~_msk); _sav &= ~_msk; */ \
319 "movl %"_sav",%"_LO32 _tmp"; " \
322 "movl %"_msk",%"_LO32 _tmp"; " \
323 "andl %"_LO32 _tmp",("_STK"); " \
325 "notl %"_LO32 _tmp"; " \
326 "andl %"_LO32 _tmp",("_STK"); " \
327 "andl %"_LO32 _tmp","__stringify(BITS_PER_LONG/4)"("_STK"); " \
329 "orl %"_LO32 _tmp",("_STK"); " \
333 /* After executing instruction: write-back necessary bits in EFLAGS. */
334 #define _POST_EFLAGS(_sav, _msk, _tmp) \
335 /* _sav |= EFLAGS & _msk; */ \
338 "andl %"_msk",%"_LO32 _tmp"; " \
339 "orl %"_LO32 _tmp",%"_sav"; "
341 /* Raw emulation: instruction has two explicit operands. */
342 #define __emulate_2op_nobyte(_op,_src,_dst,_eflags,_wx,_wy,_lx,_ly,_qx,_qy) \
344 unsigned long _tmp; \
346 switch ((_dst).bytes) { \
348 __asm__ __volatile__ ( \
349 _PRE_EFLAGS("0", "4", "2") \
350 _op"w %"_wx"3,%1; " \
351 _POST_EFLAGS("0", "4", "2") \
352 : "=m" (_eflags), "=m" ((_dst).val), \
354 : _wy ((_src).val), "i" (EFLAGS_MASK)); \
357 __asm__ __volatile__ ( \
358 _PRE_EFLAGS("0", "4", "2") \
359 _op"l %"_lx"3,%1; " \
360 _POST_EFLAGS("0", "4", "2") \
361 : "=m" (_eflags), "=m" ((_dst).val), \
363 : _ly ((_src).val), "i" (EFLAGS_MASK)); \
366 __emulate_2op_8byte(_op, _src, _dst, \
367 _eflags, _qx, _qy); \
372 #define __emulate_2op(_op,_src,_dst,_eflags,_bx,_by,_wx,_wy,_lx,_ly,_qx,_qy) \
374 unsigned long __tmp; \
375 switch ((_dst).bytes) { \
377 __asm__ __volatile__ ( \
378 _PRE_EFLAGS("0", "4", "2") \
379 _op"b %"_bx"3,%1; " \
380 _POST_EFLAGS("0", "4", "2") \
381 : "=m" (_eflags), "=m" ((_dst).val), \
383 : _by ((_src).val), "i" (EFLAGS_MASK)); \
386 __emulate_2op_nobyte(_op, _src, _dst, _eflags, \
387 _wx, _wy, _lx, _ly, _qx, _qy); \
392 /* Source operand is byte-sized and may be restricted to just %cl. */
393 #define emulate_2op_SrcB(_op, _src, _dst, _eflags) \
394 __emulate_2op(_op, _src, _dst, _eflags, \
395 "b", "c", "b", "c", "b", "c", "b", "c")
397 /* Source operand is byte, word, long or quad sized. */
398 #define emulate_2op_SrcV(_op, _src, _dst, _eflags) \
399 __emulate_2op(_op, _src, _dst, _eflags, \
400 "b", "q", "w", "r", _LO32, "r", "", "r")
402 /* Source operand is word, long or quad sized. */
403 #define emulate_2op_SrcV_nobyte(_op, _src, _dst, _eflags) \
404 __emulate_2op_nobyte(_op, _src, _dst, _eflags, \
405 "w", "r", _LO32, "r", "", "r")
407 /* Instruction has only one explicit operand (no source operand). */
408 #define emulate_1op(_op, _dst, _eflags) \
410 unsigned long _tmp; \
412 switch ((_dst).bytes) { \
414 __asm__ __volatile__ ( \
415 _PRE_EFLAGS("0", "3", "2") \
417 _POST_EFLAGS("0", "3", "2") \
418 : "=m" (_eflags), "=m" ((_dst).val), \
420 : "i" (EFLAGS_MASK)); \
423 __asm__ __volatile__ ( \
424 _PRE_EFLAGS("0", "3", "2") \
426 _POST_EFLAGS("0", "3", "2") \
427 : "=m" (_eflags), "=m" ((_dst).val), \
429 : "i" (EFLAGS_MASK)); \
432 __asm__ __volatile__ ( \
433 _PRE_EFLAGS("0", "3", "2") \
435 _POST_EFLAGS("0", "3", "2") \
436 : "=m" (_eflags), "=m" ((_dst).val), \
438 : "i" (EFLAGS_MASK)); \
441 __emulate_1op_8byte(_op, _dst, _eflags); \
446 /* Emulate an instruction with quadword operands (x86/64 only). */
447 #if defined(CONFIG_X86_64)
448 #define __emulate_2op_8byte(_op, _src, _dst, _eflags, _qx, _qy) \
450 __asm__ __volatile__ ( \
451 _PRE_EFLAGS("0", "4", "2") \
452 _op"q %"_qx"3,%1; " \
453 _POST_EFLAGS("0", "4", "2") \
454 : "=m" (_eflags), "=m" ((_dst).val), "=&r" (_tmp) \
455 : _qy ((_src).val), "i" (EFLAGS_MASK)); \
458 #define __emulate_1op_8byte(_op, _dst, _eflags) \
460 __asm__ __volatile__ ( \
461 _PRE_EFLAGS("0", "3", "2") \
463 _POST_EFLAGS("0", "3", "2") \
464 : "=m" (_eflags), "=m" ((_dst).val), "=&r" (_tmp) \
465 : "i" (EFLAGS_MASK)); \
468 #elif defined(__i386__)
469 #define __emulate_2op_8byte(_op, _src, _dst, _eflags, _qx, _qy)
470 #define __emulate_1op_8byte(_op, _dst, _eflags)
471 #endif /* __i386__ */
473 /* Fetch next part of the instruction being emulated. */
474 #define insn_fetch(_type, _size, _eip) \
475 ({ unsigned long _x; \
476 rc = do_insn_fetch(ctxt, ops, (_eip), &_x, (_size)); \
483 static inline unsigned long ad_mask(struct decode_cache *c)
485 return (1UL << (c->ad_bytes << 3)) - 1;
488 /* Access/update address held in a register, based on addressing mode. */
489 static inline unsigned long
490 address_mask(struct decode_cache *c, unsigned long reg)
492 if (c->ad_bytes == sizeof(unsigned long))
495 return reg & ad_mask(c);
498 static inline unsigned long
499 register_address(struct decode_cache *c, unsigned long base, unsigned long reg)
501 return base + address_mask(c, reg);
505 register_address_increment(struct decode_cache *c, unsigned long *reg, int inc)
507 if (c->ad_bytes == sizeof(unsigned long))
510 *reg = (*reg & ~ad_mask(c)) | ((*reg + inc) & ad_mask(c));
513 static inline void jmp_rel(struct decode_cache *c, int rel)
515 register_address_increment(c, &c->eip, rel);
518 static int do_fetch_insn_byte(struct x86_emulate_ctxt *ctxt,
519 struct x86_emulate_ops *ops,
520 unsigned long linear, u8 *dest)
522 struct fetch_cache *fc = &ctxt->decode.fetch;
526 if (linear < fc->start || linear >= fc->end) {
527 size = min(15UL, PAGE_SIZE - offset_in_page(linear));
528 rc = ops->read_std(linear, fc->data, size, ctxt->vcpu);
532 fc->end = linear + size;
534 *dest = fc->data[linear - fc->start];
538 static int do_insn_fetch(struct x86_emulate_ctxt *ctxt,
539 struct x86_emulate_ops *ops,
540 unsigned long eip, void *dest, unsigned size)
544 eip += ctxt->cs_base;
546 rc = do_fetch_insn_byte(ctxt, ops, eip++, dest++);
554 * Given the 'reg' portion of a ModRM byte, and a register block, return a
555 * pointer into the block that addresses the relevant register.
556 * @highbyte_regs specifies whether to decode AH,CH,DH,BH.
558 static void *decode_register(u8 modrm_reg, unsigned long *regs,
563 p = ®s[modrm_reg];
564 if (highbyte_regs && modrm_reg >= 4 && modrm_reg < 8)
565 p = (unsigned char *)®s[modrm_reg & 3] + 1;
569 static int read_descriptor(struct x86_emulate_ctxt *ctxt,
570 struct x86_emulate_ops *ops,
572 u16 *size, unsigned long *address, int op_bytes)
579 rc = ops->read_std((unsigned long)ptr, (unsigned long *)size, 2,
583 rc = ops->read_std((unsigned long)ptr + 2, address, op_bytes,
588 static int test_cc(unsigned int condition, unsigned int flags)
592 switch ((condition & 15) >> 1) {
594 rc |= (flags & EFLG_OF);
596 case 1: /* b/c/nae */
597 rc |= (flags & EFLG_CF);
600 rc |= (flags & EFLG_ZF);
603 rc |= (flags & (EFLG_CF|EFLG_ZF));
606 rc |= (flags & EFLG_SF);
609 rc |= (flags & EFLG_PF);
612 rc |= (flags & EFLG_ZF);
615 rc |= (!(flags & EFLG_SF) != !(flags & EFLG_OF));
619 /* Odd condition identifiers (lsb == 1) have inverted sense. */
620 return (!!rc ^ (condition & 1));
623 static void decode_register_operand(struct operand *op,
624 struct decode_cache *c,
627 unsigned reg = c->modrm_reg;
628 int highbyte_regs = c->rex_prefix == 0;
631 reg = (c->b & 7) | ((c->rex_prefix & 1) << 3);
633 if ((c->d & ByteOp) && !inhibit_bytereg) {
634 op->ptr = decode_register(reg, c->regs, highbyte_regs);
635 op->val = *(u8 *)op->ptr;
638 op->ptr = decode_register(reg, c->regs, 0);
639 op->bytes = c->op_bytes;
642 op->val = *(u16 *)op->ptr;
645 op->val = *(u32 *)op->ptr;
648 op->val = *(u64 *) op->ptr;
652 op->orig_val = op->val;
655 static int decode_modrm(struct x86_emulate_ctxt *ctxt,
656 struct x86_emulate_ops *ops)
658 struct decode_cache *c = &ctxt->decode;
660 int index_reg = 0, base_reg = 0, scale, rip_relative = 0;
664 c->modrm_reg = (c->rex_prefix & 4) << 1; /* REX.R */
665 index_reg = (c->rex_prefix & 2) << 2; /* REX.X */
666 c->modrm_rm = base_reg = (c->rex_prefix & 1) << 3; /* REG.B */
669 c->modrm = insn_fetch(u8, 1, c->eip);
670 c->modrm_mod |= (c->modrm & 0xc0) >> 6;
671 c->modrm_reg |= (c->modrm & 0x38) >> 3;
672 c->modrm_rm |= (c->modrm & 0x07);
676 if (c->modrm_mod == 3) {
677 c->modrm_val = *(unsigned long *)
678 decode_register(c->modrm_rm, c->regs, c->d & ByteOp);
682 if (c->ad_bytes == 2) {
683 unsigned bx = c->regs[VCPU_REGS_RBX];
684 unsigned bp = c->regs[VCPU_REGS_RBP];
685 unsigned si = c->regs[VCPU_REGS_RSI];
686 unsigned di = c->regs[VCPU_REGS_RDI];
688 /* 16-bit ModR/M decode. */
689 switch (c->modrm_mod) {
691 if (c->modrm_rm == 6)
692 c->modrm_ea += insn_fetch(u16, 2, c->eip);
695 c->modrm_ea += insn_fetch(s8, 1, c->eip);
698 c->modrm_ea += insn_fetch(u16, 2, c->eip);
701 switch (c->modrm_rm) {
703 c->modrm_ea += bx + si;
706 c->modrm_ea += bx + di;
709 c->modrm_ea += bp + si;
712 c->modrm_ea += bp + di;
721 if (c->modrm_mod != 0)
728 if (c->modrm_rm == 2 || c->modrm_rm == 3 ||
729 (c->modrm_rm == 6 && c->modrm_mod != 0))
730 if (!c->override_base)
731 c->override_base = &ctxt->ss_base;
732 c->modrm_ea = (u16)c->modrm_ea;
734 /* 32/64-bit ModR/M decode. */
735 switch (c->modrm_rm) {
738 sib = insn_fetch(u8, 1, c->eip);
739 index_reg |= (sib >> 3) & 7;
745 if (c->modrm_mod != 0)
746 c->modrm_ea += c->regs[base_reg];
749 insn_fetch(s32, 4, c->eip);
752 c->modrm_ea += c->regs[base_reg];
758 c->modrm_ea += c->regs[index_reg] << scale;
762 if (c->modrm_mod != 0)
763 c->modrm_ea += c->regs[c->modrm_rm];
764 else if (ctxt->mode == X86EMUL_MODE_PROT64)
768 c->modrm_ea += c->regs[c->modrm_rm];
771 switch (c->modrm_mod) {
773 if (c->modrm_rm == 5)
774 c->modrm_ea += insn_fetch(s32, 4, c->eip);
777 c->modrm_ea += insn_fetch(s8, 1, c->eip);
780 c->modrm_ea += insn_fetch(s32, 4, c->eip);
785 c->modrm_ea += c->eip;
786 switch (c->d & SrcMask) {
794 if (c->op_bytes == 8)
797 c->modrm_ea += c->op_bytes;
804 static int decode_abs(struct x86_emulate_ctxt *ctxt,
805 struct x86_emulate_ops *ops)
807 struct decode_cache *c = &ctxt->decode;
810 switch (c->ad_bytes) {
812 c->modrm_ea = insn_fetch(u16, 2, c->eip);
815 c->modrm_ea = insn_fetch(u32, 4, c->eip);
818 c->modrm_ea = insn_fetch(u64, 8, c->eip);
826 x86_decode_insn(struct x86_emulate_ctxt *ctxt, struct x86_emulate_ops *ops)
828 struct decode_cache *c = &ctxt->decode;
830 int mode = ctxt->mode;
831 int def_op_bytes, def_ad_bytes, group;
833 /* Shadow copy of register state. Committed on successful emulation. */
835 memset(c, 0, sizeof(struct decode_cache));
836 c->eip = ctxt->vcpu->arch.rip;
837 memcpy(c->regs, ctxt->vcpu->arch.regs, sizeof c->regs);
840 case X86EMUL_MODE_REAL:
841 case X86EMUL_MODE_PROT16:
842 def_op_bytes = def_ad_bytes = 2;
844 case X86EMUL_MODE_PROT32:
845 def_op_bytes = def_ad_bytes = 4;
848 case X86EMUL_MODE_PROT64:
857 c->op_bytes = def_op_bytes;
858 c->ad_bytes = def_ad_bytes;
860 /* Legacy prefixes. */
862 switch (c->b = insn_fetch(u8, 1, c->eip)) {
863 case 0x66: /* operand-size override */
864 /* switch between 2/4 bytes */
865 c->op_bytes = def_op_bytes ^ 6;
867 case 0x67: /* address-size override */
868 if (mode == X86EMUL_MODE_PROT64)
869 /* switch between 4/8 bytes */
870 c->ad_bytes = def_ad_bytes ^ 12;
872 /* switch between 2/4 bytes */
873 c->ad_bytes = def_ad_bytes ^ 6;
875 case 0x2e: /* CS override */
876 c->override_base = &ctxt->cs_base;
878 case 0x3e: /* DS override */
879 c->override_base = &ctxt->ds_base;
881 case 0x26: /* ES override */
882 c->override_base = &ctxt->es_base;
884 case 0x64: /* FS override */
885 c->override_base = &ctxt->fs_base;
887 case 0x65: /* GS override */
888 c->override_base = &ctxt->gs_base;
890 case 0x36: /* SS override */
891 c->override_base = &ctxt->ss_base;
893 case 0x40 ... 0x4f: /* REX */
894 if (mode != X86EMUL_MODE_PROT64)
896 c->rex_prefix = c->b;
898 case 0xf0: /* LOCK */
901 case 0xf2: /* REPNE/REPNZ */
902 c->rep_prefix = REPNE_PREFIX;
904 case 0xf3: /* REP/REPE/REPZ */
905 c->rep_prefix = REPE_PREFIX;
911 /* Any legacy prefix after a REX prefix nullifies its effect. */
920 if (c->rex_prefix & 8)
921 c->op_bytes = 8; /* REX.W */
923 /* Opcode byte(s). */
924 c->d = opcode_table[c->b];
926 /* Two-byte opcode? */
929 c->b = insn_fetch(u8, 1, c->eip);
930 c->d = twobyte_table[c->b];
935 group = c->d & GroupMask;
936 c->modrm = insn_fetch(u8, 1, c->eip);
939 group = (group << 3) + ((c->modrm >> 3) & 7);
940 if ((c->d & GroupDual) && (c->modrm >> 6) == 3)
941 c->d = group2_table[group];
943 c->d = group_table[group];
948 DPRINTF("Cannot emulate %02x\n", c->b);
952 if (mode == X86EMUL_MODE_PROT64 && (c->d & Stack))
955 /* ModRM and SIB bytes. */
957 rc = decode_modrm(ctxt, ops);
958 else if (c->d & MemAbs)
959 rc = decode_abs(ctxt, ops);
963 if (!c->override_base)
964 c->override_base = &ctxt->ds_base;
965 if (mode == X86EMUL_MODE_PROT64 &&
966 c->override_base != &ctxt->fs_base &&
967 c->override_base != &ctxt->gs_base)
968 c->override_base = NULL;
970 if (c->override_base)
971 c->modrm_ea += *c->override_base;
973 if (c->ad_bytes != 8)
974 c->modrm_ea = (u32)c->modrm_ea;
976 * Decode and fetch the source operand: register, memory
979 switch (c->d & SrcMask) {
983 decode_register_operand(&c->src, c, 0);
992 c->src.bytes = (c->d & ByteOp) ? 1 :
994 /* Don't fetch the address for invlpg: it could be unmapped. */
995 if (c->twobyte && c->b == 0x01 && c->modrm_reg == 7)
999 * For instructions with a ModR/M byte, switch to register
1000 * access if Mod = 3.
1002 if ((c->d & ModRM) && c->modrm_mod == 3) {
1003 c->src.type = OP_REG;
1006 c->src.type = OP_MEM;
1009 c->src.type = OP_IMM;
1010 c->src.ptr = (unsigned long *)c->eip;
1011 c->src.bytes = (c->d & ByteOp) ? 1 : c->op_bytes;
1012 if (c->src.bytes == 8)
1014 /* NB. Immediates are sign-extended as necessary. */
1015 switch (c->src.bytes) {
1017 c->src.val = insn_fetch(s8, 1, c->eip);
1020 c->src.val = insn_fetch(s16, 2, c->eip);
1023 c->src.val = insn_fetch(s32, 4, c->eip);
1028 c->src.type = OP_IMM;
1029 c->src.ptr = (unsigned long *)c->eip;
1031 c->src.val = insn_fetch(s8, 1, c->eip);
1035 /* Decode and fetch the destination operand: register or memory. */
1036 switch (c->d & DstMask) {
1038 /* Special instructions do their own operand decoding. */
1041 decode_register_operand(&c->dst, c,
1042 c->twobyte && (c->b == 0xb6 || c->b == 0xb7));
1045 if ((c->d & ModRM) && c->modrm_mod == 3) {
1046 c->dst.type = OP_REG;
1049 c->dst.type = OP_MEM;
1054 return (rc == X86EMUL_UNHANDLEABLE) ? -1 : 0;
1057 static inline void emulate_push(struct x86_emulate_ctxt *ctxt)
1059 struct decode_cache *c = &ctxt->decode;
1061 c->dst.type = OP_MEM;
1062 c->dst.bytes = c->op_bytes;
1063 c->dst.val = c->src.val;
1064 register_address_increment(c, &c->regs[VCPU_REGS_RSP], -c->op_bytes);
1065 c->dst.ptr = (void *) register_address(c, ctxt->ss_base,
1066 c->regs[VCPU_REGS_RSP]);
1069 static inline int emulate_grp1a(struct x86_emulate_ctxt *ctxt,
1070 struct x86_emulate_ops *ops)
1072 struct decode_cache *c = &ctxt->decode;
1075 rc = ops->read_std(register_address(c, ctxt->ss_base,
1076 c->regs[VCPU_REGS_RSP]),
1077 &c->dst.val, c->dst.bytes, ctxt->vcpu);
1081 register_address_increment(c, &c->regs[VCPU_REGS_RSP], c->dst.bytes);
1086 static inline void emulate_grp2(struct x86_emulate_ctxt *ctxt)
1088 struct decode_cache *c = &ctxt->decode;
1089 switch (c->modrm_reg) {
1091 emulate_2op_SrcB("rol", c->src, c->dst, ctxt->eflags);
1094 emulate_2op_SrcB("ror", c->src, c->dst, ctxt->eflags);
1097 emulate_2op_SrcB("rcl", c->src, c->dst, ctxt->eflags);
1100 emulate_2op_SrcB("rcr", c->src, c->dst, ctxt->eflags);
1102 case 4: /* sal/shl */
1103 case 6: /* sal/shl */
1104 emulate_2op_SrcB("sal", c->src, c->dst, ctxt->eflags);
1107 emulate_2op_SrcB("shr", c->src, c->dst, ctxt->eflags);
1110 emulate_2op_SrcB("sar", c->src, c->dst, ctxt->eflags);
1115 static inline int emulate_grp3(struct x86_emulate_ctxt *ctxt,
1116 struct x86_emulate_ops *ops)
1118 struct decode_cache *c = &ctxt->decode;
1121 switch (c->modrm_reg) {
1122 case 0 ... 1: /* test */
1123 emulate_2op_SrcV("test", c->src, c->dst, ctxt->eflags);
1126 c->dst.val = ~c->dst.val;
1129 emulate_1op("neg", c->dst, ctxt->eflags);
1132 DPRINTF("Cannot emulate %02x\n", c->b);
1133 rc = X86EMUL_UNHANDLEABLE;
1139 static inline int emulate_grp45(struct x86_emulate_ctxt *ctxt,
1140 struct x86_emulate_ops *ops)
1142 struct decode_cache *c = &ctxt->decode;
1144 switch (c->modrm_reg) {
1146 emulate_1op("inc", c->dst, ctxt->eflags);
1149 emulate_1op("dec", c->dst, ctxt->eflags);
1151 case 4: /* jmp abs */
1152 c->eip = c->src.val;
1161 static inline int emulate_grp9(struct x86_emulate_ctxt *ctxt,
1162 struct x86_emulate_ops *ops,
1163 unsigned long memop)
1165 struct decode_cache *c = &ctxt->decode;
1169 rc = ops->read_emulated(memop, &old, 8, ctxt->vcpu);
1173 if (((u32) (old >> 0) != (u32) c->regs[VCPU_REGS_RAX]) ||
1174 ((u32) (old >> 32) != (u32) c->regs[VCPU_REGS_RDX])) {
1176 c->regs[VCPU_REGS_RAX] = (u32) (old >> 0);
1177 c->regs[VCPU_REGS_RDX] = (u32) (old >> 32);
1178 ctxt->eflags &= ~EFLG_ZF;
1181 new = ((u64)c->regs[VCPU_REGS_RCX] << 32) |
1182 (u32) c->regs[VCPU_REGS_RBX];
1184 rc = ops->cmpxchg_emulated(memop, &old, &new, 8, ctxt->vcpu);
1187 ctxt->eflags |= EFLG_ZF;
1192 static inline int writeback(struct x86_emulate_ctxt *ctxt,
1193 struct x86_emulate_ops *ops)
1196 struct decode_cache *c = &ctxt->decode;
1198 switch (c->dst.type) {
1200 /* The 4-byte case *is* correct:
1201 * in 64-bit mode we zero-extend.
1203 switch (c->dst.bytes) {
1205 *(u8 *)c->dst.ptr = (u8)c->dst.val;
1208 *(u16 *)c->dst.ptr = (u16)c->dst.val;
1211 *c->dst.ptr = (u32)c->dst.val;
1212 break; /* 64b: zero-ext */
1214 *c->dst.ptr = c->dst.val;
1220 rc = ops->cmpxchg_emulated(
1221 (unsigned long)c->dst.ptr,
1227 rc = ops->write_emulated(
1228 (unsigned long)c->dst.ptr,
1245 x86_emulate_insn(struct x86_emulate_ctxt *ctxt, struct x86_emulate_ops *ops)
1247 unsigned long memop = 0;
1249 unsigned long saved_eip = 0;
1250 struct decode_cache *c = &ctxt->decode;
1253 /* Shadow copy of register state. Committed on successful emulation.
1254 * NOTE: we can copy them from vcpu as x86_decode_insn() doesn't
1258 memcpy(c->regs, ctxt->vcpu->arch.regs, sizeof c->regs);
1261 if (((c->d & ModRM) && (c->modrm_mod != 3)) || (c->d & MemAbs))
1262 memop = c->modrm_ea;
1264 if (c->rep_prefix && (c->d & String)) {
1265 /* All REP prefixes have the same first termination condition */
1266 if (c->regs[VCPU_REGS_RCX] == 0) {
1267 ctxt->vcpu->arch.rip = c->eip;
1270 /* The second termination condition only applies for REPE
1271 * and REPNE. Test if the repeat string operation prefix is
1272 * REPE/REPZ or REPNE/REPNZ and if it's the case it tests the
1273 * corresponding termination condition according to:
1274 * - if REPE/REPZ and ZF = 0 then done
1275 * - if REPNE/REPNZ and ZF = 1 then done
1277 if ((c->b == 0xa6) || (c->b == 0xa7) ||
1278 (c->b == 0xae) || (c->b == 0xaf)) {
1279 if ((c->rep_prefix == REPE_PREFIX) &&
1280 ((ctxt->eflags & EFLG_ZF) == 0)) {
1281 ctxt->vcpu->arch.rip = c->eip;
1284 if ((c->rep_prefix == REPNE_PREFIX) &&
1285 ((ctxt->eflags & EFLG_ZF) == EFLG_ZF)) {
1286 ctxt->vcpu->arch.rip = c->eip;
1290 c->regs[VCPU_REGS_RCX]--;
1291 c->eip = ctxt->vcpu->arch.rip;
1294 if (c->src.type == OP_MEM) {
1295 c->src.ptr = (unsigned long *)memop;
1297 rc = ops->read_emulated((unsigned long)c->src.ptr,
1303 c->src.orig_val = c->src.val;
1306 if ((c->d & DstMask) == ImplicitOps)
1310 if (c->dst.type == OP_MEM) {
1311 c->dst.ptr = (unsigned long *)memop;
1312 c->dst.bytes = (c->d & ByteOp) ? 1 : c->op_bytes;
1315 unsigned long mask = ~(c->dst.bytes * 8 - 1);
1317 c->dst.ptr = (void *)c->dst.ptr +
1318 (c->src.val & mask) / 8;
1320 if (!(c->d & Mov) &&
1321 /* optimisation - avoid slow emulated read */
1322 ((rc = ops->read_emulated((unsigned long)c->dst.ptr,
1324 c->dst.bytes, ctxt->vcpu)) != 0))
1327 c->dst.orig_val = c->dst.val;
1337 emulate_2op_SrcV("add", c->src, c->dst, ctxt->eflags);
1341 emulate_2op_SrcV("or", c->src, c->dst, ctxt->eflags);
1345 emulate_2op_SrcV("adc", c->src, c->dst, ctxt->eflags);
1349 emulate_2op_SrcV("sbb", c->src, c->dst, ctxt->eflags);
1353 emulate_2op_SrcV("and", c->src, c->dst, ctxt->eflags);
1355 case 0x24: /* and al imm8 */
1356 c->dst.type = OP_REG;
1357 c->dst.ptr = &c->regs[VCPU_REGS_RAX];
1358 c->dst.val = *(u8 *)c->dst.ptr;
1360 c->dst.orig_val = c->dst.val;
1362 case 0x25: /* and ax imm16, or eax imm32 */
1363 c->dst.type = OP_REG;
1364 c->dst.bytes = c->op_bytes;
1365 c->dst.ptr = &c->regs[VCPU_REGS_RAX];
1366 if (c->op_bytes == 2)
1367 c->dst.val = *(u16 *)c->dst.ptr;
1369 c->dst.val = *(u32 *)c->dst.ptr;
1370 c->dst.orig_val = c->dst.val;
1374 emulate_2op_SrcV("sub", c->src, c->dst, ctxt->eflags);
1378 emulate_2op_SrcV("xor", c->src, c->dst, ctxt->eflags);
1382 emulate_2op_SrcV("cmp", c->src, c->dst, ctxt->eflags);
1384 case 0x40 ... 0x47: /* inc r16/r32 */
1385 emulate_1op("inc", c->dst, ctxt->eflags);
1387 case 0x48 ... 0x4f: /* dec r16/r32 */
1388 emulate_1op("dec", c->dst, ctxt->eflags);
1390 case 0x50 ... 0x57: /* push reg */
1391 c->dst.type = OP_MEM;
1392 c->dst.bytes = c->op_bytes;
1393 c->dst.val = c->src.val;
1394 register_address_increment(c, &c->regs[VCPU_REGS_RSP],
1396 c->dst.ptr = (void *) register_address(
1397 c, ctxt->ss_base, c->regs[VCPU_REGS_RSP]);
1399 case 0x58 ... 0x5f: /* pop reg */
1401 if ((rc = ops->read_std(register_address(c, ctxt->ss_base,
1402 c->regs[VCPU_REGS_RSP]), c->dst.ptr,
1403 c->op_bytes, ctxt->vcpu)) != 0)
1406 register_address_increment(c, &c->regs[VCPU_REGS_RSP],
1408 c->dst.type = OP_NONE; /* Disable writeback. */
1410 case 0x63: /* movsxd */
1411 if (ctxt->mode != X86EMUL_MODE_PROT64)
1412 goto cannot_emulate;
1413 c->dst.val = (s32) c->src.val;
1415 case 0x6a: /* push imm8 */
1417 c->src.val = insn_fetch(s8, 1, c->eip);
1420 case 0x6c: /* insb */
1421 case 0x6d: /* insw/insd */
1422 if (kvm_emulate_pio_string(ctxt->vcpu, NULL,
1424 (c->d & ByteOp) ? 1 : c->op_bytes,
1426 address_mask(c, c->regs[VCPU_REGS_RCX]) : 1,
1427 (ctxt->eflags & EFLG_DF),
1428 register_address(c, ctxt->es_base,
1429 c->regs[VCPU_REGS_RDI]),
1431 c->regs[VCPU_REGS_RDX]) == 0) {
1436 case 0x6e: /* outsb */
1437 case 0x6f: /* outsw/outsd */
1438 if (kvm_emulate_pio_string(ctxt->vcpu, NULL,
1440 (c->d & ByteOp) ? 1 : c->op_bytes,
1442 address_mask(c, c->regs[VCPU_REGS_RCX]) : 1,
1443 (ctxt->eflags & EFLG_DF),
1444 register_address(c, c->override_base ?
1447 c->regs[VCPU_REGS_RSI]),
1449 c->regs[VCPU_REGS_RDX]) == 0) {
1454 case 0x70 ... 0x7f: /* jcc (short) */ {
1455 int rel = insn_fetch(s8, 1, c->eip);
1457 if (test_cc(c->b, ctxt->eflags))
1461 case 0x80 ... 0x83: /* Grp1 */
1462 switch (c->modrm_reg) {
1482 emulate_2op_SrcV("test", c->src, c->dst, ctxt->eflags);
1484 case 0x86 ... 0x87: /* xchg */
1485 /* Write back the register source. */
1486 switch (c->dst.bytes) {
1488 *(u8 *) c->src.ptr = (u8) c->dst.val;
1491 *(u16 *) c->src.ptr = (u16) c->dst.val;
1494 *c->src.ptr = (u32) c->dst.val;
1495 break; /* 64b reg: zero-extend */
1497 *c->src.ptr = c->dst.val;
1501 * Write back the memory destination with implicit LOCK
1504 c->dst.val = c->src.val;
1507 case 0x88 ... 0x8b: /* mov */
1509 case 0x8d: /* lea r16/r32, m */
1510 c->dst.val = c->modrm_val;
1512 case 0x8f: /* pop (sole member of Grp1a) */
1513 rc = emulate_grp1a(ctxt, ops);
1517 case 0x9c: /* pushf */
1518 c->src.val = (unsigned long) ctxt->eflags;
1521 case 0x9d: /* popf */
1522 c->dst.ptr = (unsigned long *) &ctxt->eflags;
1523 goto pop_instruction;
1524 case 0xa0 ... 0xa1: /* mov */
1525 c->dst.ptr = (unsigned long *)&c->regs[VCPU_REGS_RAX];
1526 c->dst.val = c->src.val;
1528 case 0xa2 ... 0xa3: /* mov */
1529 c->dst.val = (unsigned long)c->regs[VCPU_REGS_RAX];
1531 case 0xa4 ... 0xa5: /* movs */
1532 c->dst.type = OP_MEM;
1533 c->dst.bytes = (c->d & ByteOp) ? 1 : c->op_bytes;
1534 c->dst.ptr = (unsigned long *)register_address(c,
1536 c->regs[VCPU_REGS_RDI]);
1537 if ((rc = ops->read_emulated(register_address(c,
1538 c->override_base ? *c->override_base :
1540 c->regs[VCPU_REGS_RSI]),
1542 c->dst.bytes, ctxt->vcpu)) != 0)
1544 register_address_increment(c, &c->regs[VCPU_REGS_RSI],
1545 (ctxt->eflags & EFLG_DF) ? -c->dst.bytes
1547 register_address_increment(c, &c->regs[VCPU_REGS_RDI],
1548 (ctxt->eflags & EFLG_DF) ? -c->dst.bytes
1551 case 0xa6 ... 0xa7: /* cmps */
1552 c->src.type = OP_NONE; /* Disable writeback. */
1553 c->src.bytes = (c->d & ByteOp) ? 1 : c->op_bytes;
1554 c->src.ptr = (unsigned long *)register_address(c,
1555 c->override_base ? *c->override_base :
1557 c->regs[VCPU_REGS_RSI]);
1558 if ((rc = ops->read_emulated((unsigned long)c->src.ptr,
1564 c->dst.type = OP_NONE; /* Disable writeback. */
1565 c->dst.bytes = (c->d & ByteOp) ? 1 : c->op_bytes;
1566 c->dst.ptr = (unsigned long *)register_address(c,
1568 c->regs[VCPU_REGS_RDI]);
1569 if ((rc = ops->read_emulated((unsigned long)c->dst.ptr,
1575 DPRINTF("cmps: mem1=0x%p mem2=0x%p\n", c->src.ptr, c->dst.ptr);
1577 emulate_2op_SrcV("cmp", c->src, c->dst, ctxt->eflags);
1579 register_address_increment(c, &c->regs[VCPU_REGS_RSI],
1580 (ctxt->eflags & EFLG_DF) ? -c->src.bytes
1582 register_address_increment(c, &c->regs[VCPU_REGS_RDI],
1583 (ctxt->eflags & EFLG_DF) ? -c->dst.bytes
1587 case 0xaa ... 0xab: /* stos */
1588 c->dst.type = OP_MEM;
1589 c->dst.bytes = (c->d & ByteOp) ? 1 : c->op_bytes;
1590 c->dst.ptr = (unsigned long *)register_address(c,
1592 c->regs[VCPU_REGS_RDI]);
1593 c->dst.val = c->regs[VCPU_REGS_RAX];
1594 register_address_increment(c, &c->regs[VCPU_REGS_RDI],
1595 (ctxt->eflags & EFLG_DF) ? -c->dst.bytes
1598 case 0xac ... 0xad: /* lods */
1599 c->dst.type = OP_REG;
1600 c->dst.bytes = (c->d & ByteOp) ? 1 : c->op_bytes;
1601 c->dst.ptr = (unsigned long *)&c->regs[VCPU_REGS_RAX];
1602 if ((rc = ops->read_emulated(register_address(c,
1603 c->override_base ? *c->override_base :
1605 c->regs[VCPU_REGS_RSI]),
1610 register_address_increment(c, &c->regs[VCPU_REGS_RSI],
1611 (ctxt->eflags & EFLG_DF) ? -c->dst.bytes
1614 case 0xae ... 0xaf: /* scas */
1615 DPRINTF("Urk! I don't handle SCAS.\n");
1616 goto cannot_emulate;
1620 case 0xc3: /* ret */
1621 c->dst.ptr = &c->eip;
1622 goto pop_instruction;
1623 case 0xc6 ... 0xc7: /* mov (sole member of Grp11) */
1625 c->dst.val = c->src.val;
1627 case 0xd0 ... 0xd1: /* Grp2 */
1631 case 0xd2 ... 0xd3: /* Grp2 */
1632 c->src.val = c->regs[VCPU_REGS_RCX];
1635 case 0xe8: /* call (near) */ {
1637 switch (c->op_bytes) {
1639 rel = insn_fetch(s16, 2, c->eip);
1642 rel = insn_fetch(s32, 4, c->eip);
1645 DPRINTF("Call: Invalid op_bytes\n");
1646 goto cannot_emulate;
1648 c->src.val = (unsigned long) c->eip;
1650 c->op_bytes = c->ad_bytes;
1654 case 0xe9: /* jmp rel */
1655 case 0xeb: /* jmp rel short */
1656 jmp_rel(c, c->src.val);
1657 c->dst.type = OP_NONE; /* Disable writeback. */
1659 case 0xf4: /* hlt */
1660 ctxt->vcpu->arch.halt_request = 1;
1662 case 0xf5: /* cmc */
1663 /* complement carry flag from eflags reg */
1664 ctxt->eflags ^= EFLG_CF;
1665 c->dst.type = OP_NONE; /* Disable writeback. */
1667 case 0xf6 ... 0xf7: /* Grp3 */
1668 rc = emulate_grp3(ctxt, ops);
1672 case 0xf8: /* clc */
1673 ctxt->eflags &= ~EFLG_CF;
1674 c->dst.type = OP_NONE; /* Disable writeback. */
1676 case 0xfa: /* cli */
1677 ctxt->eflags &= ~X86_EFLAGS_IF;
1678 c->dst.type = OP_NONE; /* Disable writeback. */
1680 case 0xfb: /* sti */
1681 ctxt->eflags |= X86_EFLAGS_IF;
1682 c->dst.type = OP_NONE; /* Disable writeback. */
1684 case 0xfe ... 0xff: /* Grp4/Grp5 */
1685 rc = emulate_grp45(ctxt, ops);
1692 rc = writeback(ctxt, ops);
1696 /* Commit shadow register state. */
1697 memcpy(ctxt->vcpu->arch.regs, c->regs, sizeof c->regs);
1698 ctxt->vcpu->arch.rip = c->eip;
1701 if (rc == X86EMUL_UNHANDLEABLE) {
1709 case 0x01: /* lgdt, lidt, lmsw */
1710 switch (c->modrm_reg) {
1712 unsigned long address;
1714 case 0: /* vmcall */
1715 if (c->modrm_mod != 3 || c->modrm_rm != 1)
1716 goto cannot_emulate;
1718 rc = kvm_fix_hypercall(ctxt->vcpu);
1722 kvm_emulate_hypercall(ctxt->vcpu);
1725 rc = read_descriptor(ctxt, ops, c->src.ptr,
1726 &size, &address, c->op_bytes);
1729 realmode_lgdt(ctxt->vcpu, size, address);
1731 case 3: /* lidt/vmmcall */
1732 if (c->modrm_mod == 3 && c->modrm_rm == 1) {
1733 rc = kvm_fix_hypercall(ctxt->vcpu);
1736 kvm_emulate_hypercall(ctxt->vcpu);
1738 rc = read_descriptor(ctxt, ops, c->src.ptr,
1743 realmode_lidt(ctxt->vcpu, size, address);
1747 if (c->modrm_mod != 3)
1748 goto cannot_emulate;
1749 *(u16 *)&c->regs[c->modrm_rm]
1750 = realmode_get_cr(ctxt->vcpu, 0);
1753 if (c->modrm_mod != 3)
1754 goto cannot_emulate;
1755 realmode_lmsw(ctxt->vcpu, (u16)c->modrm_val,
1759 emulate_invlpg(ctxt->vcpu, memop);
1762 goto cannot_emulate;
1764 /* Disable writeback. */
1765 c->dst.type = OP_NONE;
1768 emulate_clts(ctxt->vcpu);
1769 c->dst.type = OP_NONE;
1771 case 0x08: /* invd */
1772 case 0x09: /* wbinvd */
1773 case 0x0d: /* GrpP (prefetch) */
1774 case 0x18: /* Grp16 (prefetch/nop) */
1775 c->dst.type = OP_NONE;
1777 case 0x20: /* mov cr, reg */
1778 if (c->modrm_mod != 3)
1779 goto cannot_emulate;
1780 c->regs[c->modrm_rm] =
1781 realmode_get_cr(ctxt->vcpu, c->modrm_reg);
1782 c->dst.type = OP_NONE; /* no writeback */
1784 case 0x21: /* mov from dr to reg */
1785 if (c->modrm_mod != 3)
1786 goto cannot_emulate;
1787 rc = emulator_get_dr(ctxt, c->modrm_reg, &c->regs[c->modrm_rm]);
1789 goto cannot_emulate;
1790 c->dst.type = OP_NONE; /* no writeback */
1792 case 0x22: /* mov reg, cr */
1793 if (c->modrm_mod != 3)
1794 goto cannot_emulate;
1795 realmode_set_cr(ctxt->vcpu,
1796 c->modrm_reg, c->modrm_val, &ctxt->eflags);
1797 c->dst.type = OP_NONE;
1799 case 0x23: /* mov from reg to dr */
1800 if (c->modrm_mod != 3)
1801 goto cannot_emulate;
1802 rc = emulator_set_dr(ctxt, c->modrm_reg,
1803 c->regs[c->modrm_rm]);
1805 goto cannot_emulate;
1806 c->dst.type = OP_NONE; /* no writeback */
1810 msr_data = (u32)c->regs[VCPU_REGS_RAX]
1811 | ((u64)c->regs[VCPU_REGS_RDX] << 32);
1812 rc = kvm_set_msr(ctxt->vcpu, c->regs[VCPU_REGS_RCX], msr_data);
1814 kvm_inject_gp(ctxt->vcpu, 0);
1815 c->eip = ctxt->vcpu->arch.rip;
1817 rc = X86EMUL_CONTINUE;
1818 c->dst.type = OP_NONE;
1822 rc = kvm_get_msr(ctxt->vcpu, c->regs[VCPU_REGS_RCX], &msr_data);
1824 kvm_inject_gp(ctxt->vcpu, 0);
1825 c->eip = ctxt->vcpu->arch.rip;
1827 c->regs[VCPU_REGS_RAX] = (u32)msr_data;
1828 c->regs[VCPU_REGS_RDX] = msr_data >> 32;
1830 rc = X86EMUL_CONTINUE;
1831 c->dst.type = OP_NONE;
1833 case 0x40 ... 0x4f: /* cmov */
1834 c->dst.val = c->dst.orig_val = c->src.val;
1835 if (!test_cc(c->b, ctxt->eflags))
1836 c->dst.type = OP_NONE; /* no writeback */
1838 case 0x80 ... 0x8f: /* jnz rel, etc*/ {
1841 switch (c->op_bytes) {
1843 rel = insn_fetch(s16, 2, c->eip);
1846 rel = insn_fetch(s32, 4, c->eip);
1849 rel = insn_fetch(s64, 8, c->eip);
1852 DPRINTF("jnz: Invalid op_bytes\n");
1853 goto cannot_emulate;
1855 if (test_cc(c->b, ctxt->eflags))
1857 c->dst.type = OP_NONE;
1862 c->dst.type = OP_NONE;
1863 /* only subword offset */
1864 c->src.val &= (c->dst.bytes << 3) - 1;
1865 emulate_2op_SrcV_nobyte("bt", c->src, c->dst, ctxt->eflags);
1869 /* only subword offset */
1870 c->src.val &= (c->dst.bytes << 3) - 1;
1871 emulate_2op_SrcV_nobyte("bts", c->src, c->dst, ctxt->eflags);
1873 case 0xb0 ... 0xb1: /* cmpxchg */
1875 * Save real source value, then compare EAX against
1878 c->src.orig_val = c->src.val;
1879 c->src.val = c->regs[VCPU_REGS_RAX];
1880 emulate_2op_SrcV("cmp", c->src, c->dst, ctxt->eflags);
1881 if (ctxt->eflags & EFLG_ZF) {
1882 /* Success: write back to memory. */
1883 c->dst.val = c->src.orig_val;
1885 /* Failure: write the value we saw to EAX. */
1886 c->dst.type = OP_REG;
1887 c->dst.ptr = (unsigned long *)&c->regs[VCPU_REGS_RAX];
1892 /* only subword offset */
1893 c->src.val &= (c->dst.bytes << 3) - 1;
1894 emulate_2op_SrcV_nobyte("btr", c->src, c->dst, ctxt->eflags);
1896 case 0xb6 ... 0xb7: /* movzx */
1897 c->dst.bytes = c->op_bytes;
1898 c->dst.val = (c->d & ByteOp) ? (u8) c->src.val
1901 case 0xba: /* Grp8 */
1902 switch (c->modrm_reg & 3) {
1915 /* only subword offset */
1916 c->src.val &= (c->dst.bytes << 3) - 1;
1917 emulate_2op_SrcV_nobyte("btc", c->src, c->dst, ctxt->eflags);
1919 case 0xbe ... 0xbf: /* movsx */
1920 c->dst.bytes = c->op_bytes;
1921 c->dst.val = (c->d & ByteOp) ? (s8) c->src.val :
1924 case 0xc3: /* movnti */
1925 c->dst.bytes = c->op_bytes;
1926 c->dst.val = (c->op_bytes == 4) ? (u32) c->src.val :
1929 case 0xc7: /* Grp9 (cmpxchg8b) */
1930 rc = emulate_grp9(ctxt, ops, memop);
1933 c->dst.type = OP_NONE;
1939 DPRINTF("Cannot emulate %02x\n", c->b);