err.no Git - linux-2.6/blob - arch/x86/kvm/svm.c

   1 /*
   2  * Kernel-based Virtual Machine driver for Linux
   3  *
   4  * AMD SVM support
   5  *
   6  * Copyright (C) 2006 Qumranet, Inc.
   7  *
   8  * Authors:
   9  *   Yaniv Kamay  <yaniv@qumranet.com>
  10  *   Avi Kivity   <avi@qumranet.com>
  11  *
  12  * This work is licensed under the terms of the GNU GPL, version 2.  See
  13  * the COPYING file in the top-level directory.
  14  *
  15  */
  16 #include <linux/kvm_host.h>
  17
  18 #include "kvm_svm.h"
  19 #include "irq.h"
  20 #include "mmu.h"
  21
  22 #include <linux/module.h>
  23 #include <linux/kernel.h>
  24 #include <linux/vmalloc.h>
  25 #include <linux/highmem.h>
  26 #include <linux/sched.h>
  27
  28 #include <asm/desc.h>
  29
  30 MODULE_AUTHOR("Qumranet");
  31 MODULE_LICENSE("GPL");
  32
  33 #define IOPM_ALLOC_ORDER 2
  34 #define MSRPM_ALLOC_ORDER 1
  35
  36 #define DB_VECTOR 1
  37 #define UD_VECTOR 6
  38 #define GP_VECTOR 13
  39
  40 #define DR7_GD_MASK (1 << 13)
  41 #define DR6_BD_MASK (1 << 13)
  42
  43 #define SEG_TYPE_LDT 2
  44 #define SEG_TYPE_BUSY_TSS16 3
  45
  46 #define SVM_FEATURE_NPT  (1 << 0)
  47 #define SVM_FEATURE_LBRV (1 << 1)
  48 #define SVM_DEATURE_SVML (1 << 2)
  49
  50 static void kvm_reput_irq(struct vcpu_svm *svm);
  51
  52 static inline struct vcpu_svm *to_svm(struct kvm_vcpu *vcpu)
  53 {
  54         return container_of(vcpu, struct vcpu_svm, vcpu);
  55 }
  56
  57 unsigned long iopm_base;
  58 unsigned long msrpm_base;
  59
  60 struct kvm_ldttss_desc {
  61         u16 limit0;
  62         u16 base0;
  63         unsigned base1 : 8, type : 5, dpl : 2, p : 1;
  64         unsigned limit1 : 4, zero0 : 3, g : 1, base2 : 8;
  65         u32 base3;
  66         u32 zero1;
  67 } __attribute__((packed));
  68
  69 struct svm_cpu_data {
  70         int cpu;
  71
  72         u64 asid_generation;
  73         u32 max_asid;
  74         u32 next_asid;
  75         struct kvm_ldttss_desc *tss_desc;
  76
  77         struct page *save_area;
  78 };
  79
  80 static DEFINE_PER_CPU(struct svm_cpu_data *, svm_data);
  81 static uint32_t svm_features;
  82
  83 struct svm_init_data {
  84         int cpu;
  85         int r;
  86 };
  87
  88 static u32 msrpm_ranges[] = {0, 0xc0000000, 0xc0010000};
  89
  90 #define NUM_MSR_MAPS ARRAY_SIZE(msrpm_ranges)
  91 #define MSRS_RANGE_SIZE 2048
  92 #define MSRS_IN_RANGE (MSRS_RANGE_SIZE * 8 / 2)
  93
  94 #define MAX_INST_SIZE 15
  95
  96 static inline u32 svm_has(u32 feat)
  97 {
  98         return svm_features & feat;
  99 }
 100
 101 static inline u8 pop_irq(struct kvm_vcpu *vcpu)
 102 {
 103         int word_index = __ffs(vcpu->arch.irq_summary);
 104         int bit_index = __ffs(vcpu->arch.irq_pending[word_index]);
 105         int irq = word_index * BITS_PER_LONG + bit_index;
 106
 107         clear_bit(bit_index, &vcpu->arch.irq_pending[word_index]);
 108         if (!vcpu->arch.irq_pending[word_index])
 109                 clear_bit(word_index, &vcpu->arch.irq_summary);
 110         return irq;
 111 }
 112
 113 static inline void push_irq(struct kvm_vcpu *vcpu, u8 irq)
 114 {
 115         set_bit(irq, vcpu->arch.irq_pending);
 116         set_bit(irq / BITS_PER_LONG, &vcpu->arch.irq_summary);
 117 }
 118
 119 static inline void clgi(void)
 120 {
 121         asm volatile (SVM_CLGI);
 122 }
 123
 124 static inline void stgi(void)
 125 {
 126         asm volatile (SVM_STGI);
 127 }
 128
 129 static inline void invlpga(unsigned long addr, u32 asid)
 130 {
 131         asm volatile (SVM_INVLPGA :: "a"(addr), "c"(asid));
 132 }
 133
 134 static inline unsigned long kvm_read_cr2(void)
 135 {
 136         unsigned long cr2;
 137
 138         asm volatile ("mov %%cr2, %0" : "=r" (cr2));
 139         return cr2;
 140 }
 141
 142 static inline void kvm_write_cr2(unsigned long val)
 143 {
 144         asm volatile ("mov %0, %%cr2" :: "r" (val));
 145 }
 146
 147 static inline unsigned long read_dr6(void)
 148 {
 149         unsigned long dr6;
 150
 151         asm volatile ("mov %%dr6, %0" : "=r" (dr6));
 152         return dr6;
 153 }
 154
 155 static inline void write_dr6(unsigned long val)
 156 {
 157         asm volatile ("mov %0, %%dr6" :: "r" (val));
 158 }
 159
 160 static inline unsigned long read_dr7(void)
 161 {
 162         unsigned long dr7;
 163
 164         asm volatile ("mov %%dr7, %0" : "=r" (dr7));
 165         return dr7;
 166 }
 167
 168 static inline void write_dr7(unsigned long val)
 169 {
 170         asm volatile ("mov %0, %%dr7" :: "r" (val));
 171 }
 172
 173 static inline void force_new_asid(struct kvm_vcpu *vcpu)
 174 {
 175         to_svm(vcpu)->asid_generation--;
 176 }
 177
 178 static inline void flush_guest_tlb(struct kvm_vcpu *vcpu)
 179 {
 180         force_new_asid(vcpu);
 181 }
 182
 183 static void svm_set_efer(struct kvm_vcpu *vcpu, u64 efer)
 184 {
 185         if (!(efer & EFER_LMA))
 186                 efer &= ~EFER_LME;
 187
 188         to_svm(vcpu)->vmcb->save.efer = efer | MSR_EFER_SVME_MASK;
 189         vcpu->arch.shadow_efer = efer;
 190 }
 191
 192 static void svm_queue_exception(struct kvm_vcpu *vcpu, unsigned nr,
 193                                 bool has_error_code, u32 error_code)
 194 {
 195         struct vcpu_svm *svm = to_svm(vcpu);
 196
 197         svm->vmcb->control.event_inj = nr
 198                 | SVM_EVTINJ_VALID
 199                 | (has_error_code ? SVM_EVTINJ_VALID_ERR : 0)
 200                 | SVM_EVTINJ_TYPE_EXEPT;
 201         svm->vmcb->control.event_inj_err = error_code;
 202 }
 203
 204 static bool svm_exception_injected(struct kvm_vcpu *vcpu)
 205 {
 206         struct vcpu_svm *svm = to_svm(vcpu);
 207
 208         return !(svm->vmcb->control.exit_int_info & SVM_EXITINTINFO_VALID);
 209 }
 210
 211 static int is_external_interrupt(u32 info)
 212 {
 213         info &= SVM_EVTINJ_TYPE_MASK | SVM_EVTINJ_VALID;
 214         return info == (SVM_EVTINJ_VALID | SVM_EVTINJ_TYPE_INTR);
 215 }
 216
 217 static void skip_emulated_instruction(struct kvm_vcpu *vcpu)
 218 {
 219         struct vcpu_svm *svm = to_svm(vcpu);
 220
 221         if (!svm->next_rip) {
 222                 printk(KERN_DEBUG "%s: NOP\n", __FUNCTION__);
 223                 return;
 224         }
 225         if (svm->next_rip - svm->vmcb->save.rip > MAX_INST_SIZE)
 226                 printk(KERN_ERR "%s: ip 0x%llx next 0x%llx\n",
 227                        __FUNCTION__,
 228                        svm->vmcb->save.rip,
 229                        svm->next_rip);
 230
 231         vcpu->arch.rip = svm->vmcb->save.rip = svm->next_rip;
 232         svm->vmcb->control.int_state &= ~SVM_INTERRUPT_SHADOW_MASK;
 233
 234         vcpu->arch.interrupt_window_open = 1;
 235 }
 236
 237 static int has_svm(void)
 238 {
 239         uint32_t eax, ebx, ecx, edx;
 240
 241         if (boot_cpu_data.x86_vendor != X86_VENDOR_AMD) {
 242                 printk(KERN_INFO "has_svm: not amd\n");
 243                 return 0;
 244         }
 245
 246         cpuid(0x80000000, &eax, &ebx, &ecx, &edx);
 247         if (eax < SVM_CPUID_FUNC) {
 248                 printk(KERN_INFO "has_svm: can't execute cpuid_8000000a\n");
 249                 return 0;
 250         }
 251
 252         cpuid(0x80000001, &eax, &ebx, &ecx, &edx);
 253         if (!(ecx & (1 << SVM_CPUID_FEATURE_SHIFT))) {
 254                 printk(KERN_DEBUG "has_svm: svm not available\n");
 255                 return 0;
 256         }
 257         return 1;
 258 }
 259
 260 static void svm_hardware_disable(void *garbage)
 261 {
 262         struct svm_cpu_data *svm_data
 263                 = per_cpu(svm_data, raw_smp_processor_id());
 264
 265         if (svm_data) {
 266                 uint64_t efer;
 267
 268                 wrmsrl(MSR_VM_HSAVE_PA, 0);
 269                 rdmsrl(MSR_EFER, efer);
 270                 wrmsrl(MSR_EFER, efer & ~MSR_EFER_SVME_MASK);
 271                 per_cpu(svm_data, raw_smp_processor_id()) = NULL;
 272                 __free_page(svm_data->save_area);
 273                 kfree(svm_data);
 274         }
 275 }
 276
 277 static void svm_hardware_enable(void *garbage)
 278 {
 279
 280         struct svm_cpu_data *svm_data;
 281         uint64_t efer;
 282 #ifdef CONFIG_X86_64
 283         struct desc_ptr gdt_descr;
 284 #else
 285         struct desc_ptr gdt_descr;
 286 #endif
 287         struct desc_struct *gdt;
 288         int me = raw_smp_processor_id();
 289
 290         if (!has_svm()) {
 291                 printk(KERN_ERR "svm_cpu_init: err EOPNOTSUPP on %d\n", me);
 292                 return;
 293         }
 294         svm_data = per_cpu(svm_data, me);
 295
 296         if (!svm_data) {
 297                 printk(KERN_ERR "svm_cpu_init: svm_data is NULL on %d\n",
 298                        me);
 299                 return;
 300         }
 301
 302         svm_data->asid_generation = 1;
 303         svm_data->max_asid = cpuid_ebx(SVM_CPUID_FUNC) - 1;
 304         svm_data->next_asid = svm_data->max_asid + 1;
 305         svm_features = cpuid_edx(SVM_CPUID_FUNC);
 306
 307         asm volatile ("sgdt %0" : "=m"(gdt_descr));
 308         gdt = (struct desc_struct *)gdt_descr.address;
 309         svm_data->tss_desc = (struct kvm_ldttss_desc *)(gdt + GDT_ENTRY_TSS);
 310
 311         rdmsrl(MSR_EFER, efer);
 312         wrmsrl(MSR_EFER, efer | MSR_EFER_SVME_MASK);
 313
 314         wrmsrl(MSR_VM_HSAVE_PA,
 315                page_to_pfn(svm_data->save_area) << PAGE_SHIFT);
 316 }
 317
 318 static int svm_cpu_init(int cpu)
 319 {
 320         struct svm_cpu_data *svm_data;
 321         int r;
 322
 323         svm_data = kzalloc(sizeof(struct svm_cpu_data), GFP_KERNEL);
 324         if (!svm_data)
 325                 return -ENOMEM;
 326         svm_data->cpu = cpu;
 327         svm_data->save_area = alloc_page(GFP_KERNEL);
 328         r = -ENOMEM;
 329         if (!svm_data->save_area)
 330                 goto err_1;
 331
 332         per_cpu(svm_data, cpu) = svm_data;
 333
 334         return 0;
 335
 336 err_1:
 337         kfree(svm_data);
 338         return r;
 339
 340 }
 341
 342 static void set_msr_interception(u32 *msrpm, unsigned msr,
 343                                  int read, int write)
 344 {
 345         int i;
 346
 347         for (i = 0; i < NUM_MSR_MAPS; i++) {
 348                 if (msr >= msrpm_ranges[i] &&
 349                     msr < msrpm_ranges[i] + MSRS_IN_RANGE) {
 350                         u32 msr_offset = (i * MSRS_IN_RANGE + msr -
 351                                           msrpm_ranges[i]) * 2;
 352
 353                         u32 *base = msrpm + (msr_offset / 32);
 354                         u32 msr_shift = msr_offset % 32;
 355                         u32 mask = ((write) ? 0 : 2) | ((read) ? 0 : 1);
 356                         *base = (*base & ~(0x3 << msr_shift)) |
 357                                 (mask << msr_shift);
 358                         return;
 359                 }
 360         }
 361         BUG();
 362 }
 363
 364 static __init int svm_hardware_setup(void)
 365 {
 366         int cpu;
 367         struct page *iopm_pages;
 368         struct page *msrpm_pages;
 369         void *iopm_va, *msrpm_va;
 370         int r;
 371
 372         iopm_pages = alloc_pages(GFP_KERNEL, IOPM_ALLOC_ORDER);
 373
 374         if (!iopm_pages)
 375                 return -ENOMEM;
 376
 377         iopm_va = page_address(iopm_pages);
 378         memset(iopm_va, 0xff, PAGE_SIZE * (1 << IOPM_ALLOC_ORDER));
 379         clear_bit(0x80, iopm_va); /* allow direct access to PC debug port */
 380         iopm_base = page_to_pfn(iopm_pages) << PAGE_SHIFT;
 381
 382
 383         msrpm_pages = alloc_pages(GFP_KERNEL, MSRPM_ALLOC_ORDER);
 384
 385         r = -ENOMEM;
 386         if (!msrpm_pages)
 387                 goto err_1;
 388
 389         msrpm_va = page_address(msrpm_pages);
 390         memset(msrpm_va, 0xff, PAGE_SIZE * (1 << MSRPM_ALLOC_ORDER));
 391         msrpm_base = page_to_pfn(msrpm_pages) << PAGE_SHIFT;
 392
 393 #ifdef CONFIG_X86_64
 394         set_msr_interception(msrpm_va, MSR_GS_BASE, 1, 1);
 395         set_msr_interception(msrpm_va, MSR_FS_BASE, 1, 1);
 396         set_msr_interception(msrpm_va, MSR_KERNEL_GS_BASE, 1, 1);
 397         set_msr_interception(msrpm_va, MSR_LSTAR, 1, 1);
 398         set_msr_interception(msrpm_va, MSR_CSTAR, 1, 1);
 399         set_msr_interception(msrpm_va, MSR_SYSCALL_MASK, 1, 1);
 400 #endif
 401         set_msr_interception(msrpm_va, MSR_K6_STAR, 1, 1);
 402         set_msr_interception(msrpm_va, MSR_IA32_SYSENTER_CS, 1, 1);
 403         set_msr_interception(msrpm_va, MSR_IA32_SYSENTER_ESP, 1, 1);
 404         set_msr_interception(msrpm_va, MSR_IA32_SYSENTER_EIP, 1, 1);
 405
 406         for_each_online_cpu(cpu) {
 407                 r = svm_cpu_init(cpu);
 408                 if (r)
 409                         goto err_2;
 410         }
 411         return 0;
 412
 413 err_2:
 414         __free_pages(msrpm_pages, MSRPM_ALLOC_ORDER);
 415         msrpm_base = 0;
 416 err_1:
 417         __free_pages(iopm_pages, IOPM_ALLOC_ORDER);
 418         iopm_base = 0;
 419         return r;
 420 }
 421
 422 static __exit void svm_hardware_unsetup(void)
 423 {
 424         __free_pages(pfn_to_page(msrpm_base >> PAGE_SHIFT), MSRPM_ALLOC_ORDER);
 425         __free_pages(pfn_to_page(iopm_base >> PAGE_SHIFT), IOPM_ALLOC_ORDER);
 426         iopm_base = msrpm_base = 0;
 427 }
 428
 429 static void init_seg(struct vmcb_seg *seg)
 430 {
 431         seg->selector = 0;
 432         seg->attrib = SVM_SELECTOR_P_MASK | SVM_SELECTOR_S_MASK |
 433                 SVM_SELECTOR_WRITE_MASK; /* Read/Write Data Segment */
 434         seg->limit = 0xffff;
 435         seg->base = 0;
 436 }
 437
 438 static void init_sys_seg(struct vmcb_seg *seg, uint32_t type)
 439 {
 440         seg->selector = 0;
 441         seg->attrib = SVM_SELECTOR_P_MASK | type;
 442         seg->limit = 0xffff;
 443         seg->base = 0;
 444 }
 445
 446 static void init_vmcb(struct vmcb *vmcb)
 447 {
 448         struct vmcb_control_area *control = &vmcb->control;
 449         struct vmcb_save_area *save = &vmcb->save;
 450
 451         control->intercept_cr_read =    INTERCEPT_CR0_MASK |
 452                                         INTERCEPT_CR3_MASK |
 453                                         INTERCEPT_CR4_MASK |
 454                                         INTERCEPT_CR8_MASK;
 455
 456         control->intercept_cr_write =   INTERCEPT_CR0_MASK |
 457                                         INTERCEPT_CR3_MASK |
 458                                         INTERCEPT_CR4_MASK |
 459                                         INTERCEPT_CR8_MASK;
 460
 461         control->intercept_dr_read =    INTERCEPT_DR0_MASK |
 462                                         INTERCEPT_DR1_MASK |
 463                                         INTERCEPT_DR2_MASK |
 464                                         INTERCEPT_DR3_MASK;
 465
 466         control->intercept_dr_write =   INTERCEPT_DR0_MASK |
 467                                         INTERCEPT_DR1_MASK |
 468                                         INTERCEPT_DR2_MASK |
 469                                         INTERCEPT_DR3_MASK |
 470                                         INTERCEPT_DR5_MASK |
 471                                         INTERCEPT_DR7_MASK;
 472
 473         control->intercept_exceptions = (1 << PF_VECTOR) |
 474                                         (1 << UD_VECTOR);
 475
 476
 477         control->intercept =    (1ULL << INTERCEPT_INTR) |
 478                                 (1ULL << INTERCEPT_NMI) |
 479                                 (1ULL << INTERCEPT_SMI) |
 480                 /*
 481                  * selective cr0 intercept bug?
 482                  *      0:   0f 22 d8                mov    %eax,%cr3
 483                  *      3:   0f 20 c0                mov    %cr0,%eax
 484                  *      6:   0d 00 00 00 80          or     $0x80000000,%eax
 485                  *      b:   0f 22 c0                mov    %eax,%cr0
 486                  * set cr3 ->interception
 487                  * get cr0 ->interception
 488                  * set cr0 -> no interception
 489                  */
 490                 /*              (1ULL << INTERCEPT_SELECTIVE_CR0) | */
 491                                 (1ULL << INTERCEPT_CPUID) |
 492                                 (1ULL << INTERCEPT_INVD) |
 493                                 (1ULL << INTERCEPT_HLT) |
 494                                 (1ULL << INTERCEPT_INVLPGA) |
 495                                 (1ULL << INTERCEPT_IOIO_PROT) |
 496                                 (1ULL << INTERCEPT_MSR_PROT) |
 497                                 (1ULL << INTERCEPT_TASK_SWITCH) |
 498                                 (1ULL << INTERCEPT_SHUTDOWN) |
 499                                 (1ULL << INTERCEPT_VMRUN) |
 500                                 (1ULL << INTERCEPT_VMMCALL) |
 501                                 (1ULL << INTERCEPT_VMLOAD) |
 502                                 (1ULL << INTERCEPT_VMSAVE) |
 503                                 (1ULL << INTERCEPT_STGI) |
 504                                 (1ULL << INTERCEPT_CLGI) |
 505                                 (1ULL << INTERCEPT_SKINIT) |
 506                                 (1ULL << INTERCEPT_WBINVD) |
 507                                 (1ULL << INTERCEPT_MONITOR) |
 508                                 (1ULL << INTERCEPT_MWAIT);
 509
 510         control->iopm_base_pa = iopm_base;
 511         control->msrpm_base_pa = msrpm_base;
 512         control->tsc_offset = 0;
 513         control->int_ctl = V_INTR_MASKING_MASK;
 514
 515         init_seg(&save->es);
 516         init_seg(&save->ss);
 517         init_seg(&save->ds);
 518         init_seg(&save->fs);
 519         init_seg(&save->gs);
 520
 521         save->cs.selector = 0xf000;
 522         /* Executable/Readable Code Segment */
 523         save->cs.attrib = SVM_SELECTOR_READ_MASK | SVM_SELECTOR_P_MASK |
 524                 SVM_SELECTOR_S_MASK | SVM_SELECTOR_CODE_MASK;
 525         save->cs.limit = 0xffff;
 526         /*
 527          * cs.base should really be 0xffff0000, but vmx can't handle that, so
 528          * be consistent with it.
 529          *
 530          * Replace when we have real mode working for vmx.
 531          */
 532         save->cs.base = 0xf0000;
 533
 534         save->gdtr.limit = 0xffff;
 535         save->idtr.limit = 0xffff;
 536
 537         init_sys_seg(&save->ldtr, SEG_TYPE_LDT);
 538         init_sys_seg(&save->tr, SEG_TYPE_BUSY_TSS16);
 539
 540         save->efer = MSR_EFER_SVME_MASK;
 541         save->dr6 = 0xffff0ff0;
 542         save->dr7 = 0x400;
 543         save->rflags = 2;
 544         save->rip = 0x0000fff0;
 545
 546         /*
 547          * cr0 val on cpu init should be 0x60000010, we enable cpu
 548          * cache by default. the orderly way is to enable cache in bios.
 549          */
 550         save->cr0 = 0x00000010 | X86_CR0_PG | X86_CR0_WP;
 551         save->cr4 = X86_CR4_PAE;
 552         /* rdx = ?? */
 553 }
 554
 555 static int svm_vcpu_reset(struct kvm_vcpu *vcpu)
 556 {
 557         struct vcpu_svm *svm = to_svm(vcpu);
 558
 559         init_vmcb(svm->vmcb);
 560
 561         if (vcpu->vcpu_id != 0) {
 562                 svm->vmcb->save.rip = 0;
 563                 svm->vmcb->save.cs.base = svm->vcpu.arch.sipi_vector << 12;
 564                 svm->vmcb->save.cs.selector = svm->vcpu.arch.sipi_vector << 8;
 565         }
 566
 567         return 0;
 568 }
 569
 570 static struct kvm_vcpu *svm_create_vcpu(struct kvm *kvm, unsigned int id)
 571 {
 572         struct vcpu_svm *svm;
 573         struct page *page;
 574         int err;
 575
 576         svm = kmem_cache_zalloc(kvm_vcpu_cache, GFP_KERNEL);
 577         if (!svm) {
 578                 err = -ENOMEM;
 579                 goto out;
 580         }
 581
 582         err = kvm_vcpu_init(&svm->vcpu, kvm, id);
 583         if (err)
 584                 goto free_svm;
 585
 586         page = alloc_page(GFP_KERNEL);
 587         if (!page) {
 588                 err = -ENOMEM;
 589                 goto uninit;
 590         }
 591
 592         svm->vmcb = page_address(page);
 593         clear_page(svm->vmcb);
 594         svm->vmcb_pa = page_to_pfn(page) << PAGE_SHIFT;
 595         svm->asid_generation = 0;
 596         memset(svm->db_regs, 0, sizeof(svm->db_regs));
 597         init_vmcb(svm->vmcb);
 598
 599         fx_init(&svm->vcpu);
 600         svm->vcpu.fpu_active = 1;
 601         svm->vcpu.arch.apic_base = 0xfee00000 | MSR_IA32_APICBASE_ENABLE;
 602         if (svm->vcpu.vcpu_id == 0)
 603                 svm->vcpu.arch.apic_base |= MSR_IA32_APICBASE_BSP;
 604
 605         return &svm->vcpu;
 606
 607 uninit:
 608         kvm_vcpu_uninit(&svm->vcpu);
 609 free_svm:
 610         kmem_cache_free(kvm_vcpu_cache, svm);
 611 out:
 612         return ERR_PTR(err);
 613 }
 614
 615 static void svm_free_vcpu(struct kvm_vcpu *vcpu)
 616 {
 617         struct vcpu_svm *svm = to_svm(vcpu);
 618
 619         __free_page(pfn_to_page(svm->vmcb_pa >> PAGE_SHIFT));
 620         kvm_vcpu_uninit(vcpu);
 621         kmem_cache_free(kvm_vcpu_cache, svm);
 622 }
 623
 624 static void svm_vcpu_load(struct kvm_vcpu *vcpu, int cpu)
 625 {
 626         struct vcpu_svm *svm = to_svm(vcpu);
 627         int i;
 628
 629         if (unlikely(cpu != vcpu->cpu)) {
 630                 u64 tsc_this, delta;
 631
 632                 /*
 633                  * Make sure that the guest sees a monotonically
 634                  * increasing TSC.
 635                  */
 636                 rdtscll(tsc_this);
 637                 delta = vcpu->arch.host_tsc - tsc_this;
 638                 svm->vmcb->control.tsc_offset += delta;
 639                 vcpu->cpu = cpu;
 640                 kvm_migrate_apic_timer(vcpu);
 641         }
 642
 643         for (i = 0; i < NR_HOST_SAVE_USER_MSRS; i++)
 644                 rdmsrl(host_save_user_msrs[i], svm->host_user_msrs[i]);
 645 }
 646
 647 static void svm_vcpu_put(struct kvm_vcpu *vcpu)
 648 {
 649         struct vcpu_svm *svm = to_svm(vcpu);
 650         int i;
 651
 652         ++vcpu->stat.host_state_reload;
 653         for (i = 0; i < NR_HOST_SAVE_USER_MSRS; i++)
 654                 wrmsrl(host_save_user_msrs[i], svm->host_user_msrs[i]);
 655
 656         rdtscll(vcpu->arch.host_tsc);
 657 }
 658
 659 static void svm_vcpu_decache(struct kvm_vcpu *vcpu)
 660 {
 661 }
 662
 663 static void svm_cache_regs(struct kvm_vcpu *vcpu)
 664 {
 665         struct vcpu_svm *svm = to_svm(vcpu);
 666
 667         vcpu->arch.regs[VCPU_REGS_RAX] = svm->vmcb->save.rax;
 668         vcpu->arch.regs[VCPU_REGS_RSP] = svm->vmcb->save.rsp;
 669         vcpu->arch.rip = svm->vmcb->save.rip;
 670 }
 671
 672 static void svm_decache_regs(struct kvm_vcpu *vcpu)
 673 {
 674         struct vcpu_svm *svm = to_svm(vcpu);
 675         svm->vmcb->save.rax = vcpu->arch.regs[VCPU_REGS_RAX];
 676         svm->vmcb->save.rsp = vcpu->arch.regs[VCPU_REGS_RSP];
 677         svm->vmcb->save.rip = vcpu->arch.rip;
 678 }
 679
 680 static unsigned long svm_get_rflags(struct kvm_vcpu *vcpu)
 681 {
 682         return to_svm(vcpu)->vmcb->save.rflags;
 683 }
 684
 685 static void svm_set_rflags(struct kvm_vcpu *vcpu, unsigned long rflags)
 686 {
 687         to_svm(vcpu)->vmcb->save.rflags = rflags;
 688 }
 689
 690 static struct vmcb_seg *svm_seg(struct kvm_vcpu *vcpu, int seg)
 691 {
 692         struct vmcb_save_area *save = &to_svm(vcpu)->vmcb->save;
 693
 694         switch (seg) {
 695         case VCPU_SREG_CS: return &save->cs;
 696         case VCPU_SREG_DS: return &save->ds;
 697         case VCPU_SREG_ES: return &save->es;
 698         case VCPU_SREG_FS: return &save->fs;
 699         case VCPU_SREG_GS: return &save->gs;
 700         case VCPU_SREG_SS: return &save->ss;
 701         case VCPU_SREG_TR: return &save->tr;
 702         case VCPU_SREG_LDTR: return &save->ldtr;
 703         }
 704         BUG();
 705         return NULL;
 706 }
 707
 708 static u64 svm_get_segment_base(struct kvm_vcpu *vcpu, int seg)
 709 {
 710         struct vmcb_seg *s = svm_seg(vcpu, seg);
 711
 712         return s->base;
 713 }
 714
 715 static void svm_get_segment(struct kvm_vcpu *vcpu,
 716                             struct kvm_segment *var, int seg)
 717 {
 718         struct vmcb_seg *s = svm_seg(vcpu, seg);
 719
 720         var->base = s->base;
 721         var->limit = s->limit;
 722         var->selector = s->selector;
 723         var->type = s->attrib & SVM_SELECTOR_TYPE_MASK;
 724         var->s = (s->attrib >> SVM_SELECTOR_S_SHIFT) & 1;
 725         var->dpl = (s->attrib >> SVM_SELECTOR_DPL_SHIFT) & 3;
 726         var->present = (s->attrib >> SVM_SELECTOR_P_SHIFT) & 1;
 727         var->avl = (s->attrib >> SVM_SELECTOR_AVL_SHIFT) & 1;
 728         var->l = (s->attrib >> SVM_SELECTOR_L_SHIFT) & 1;
 729         var->db = (s->attrib >> SVM_SELECTOR_DB_SHIFT) & 1;
 730         var->g = (s->attrib >> SVM_SELECTOR_G_SHIFT) & 1;
 731         var->unusable = !var->present;
 732 }
 733
 734 static void svm_get_idt(struct kvm_vcpu *vcpu, struct descriptor_table *dt)
 735 {
 736         struct vcpu_svm *svm = to_svm(vcpu);
 737
 738         dt->limit = svm->vmcb->save.idtr.limit;
 739         dt->base = svm->vmcb->save.idtr.base;
 740 }
 741
 742 static void svm_set_idt(struct kvm_vcpu *vcpu, struct descriptor_table *dt)
 743 {
 744         struct vcpu_svm *svm = to_svm(vcpu);
 745
 746         svm->vmcb->save.idtr.limit = dt->limit;
 747         svm->vmcb->save.idtr.base = dt->base ;
 748 }
 749
 750 static void svm_get_gdt(struct kvm_vcpu *vcpu, struct descriptor_table *dt)
 751 {
 752         struct vcpu_svm *svm = to_svm(vcpu);
 753
 754         dt->limit = svm->vmcb->save.gdtr.limit;
 755         dt->base = svm->vmcb->save.gdtr.base;
 756 }
 757
 758 static void svm_set_gdt(struct kvm_vcpu *vcpu, struct descriptor_table *dt)
 759 {
 760         struct vcpu_svm *svm = to_svm(vcpu);
 761
 762         svm->vmcb->save.gdtr.limit = dt->limit;
 763         svm->vmcb->save.gdtr.base = dt->base ;
 764 }
 765
 766 static void svm_decache_cr4_guest_bits(struct kvm_vcpu *vcpu)
 767 {
 768 }
 769
 770 static void svm_set_cr0(struct kvm_vcpu *vcpu, unsigned long cr0)
 771 {
 772         struct vcpu_svm *svm = to_svm(vcpu);
 773
 774 #ifdef CONFIG_X86_64
 775         if (vcpu->arch.shadow_efer & EFER_LME) {
 776                 if (!is_paging(vcpu) && (cr0 & X86_CR0_PG)) {
 777                         vcpu->arch.shadow_efer |= EFER_LMA;
 778                         svm->vmcb->save.efer |= EFER_LMA | EFER_LME;
 779                 }
 780
 781                 if (is_paging(vcpu) && !(cr0 & X86_CR0_PG)) {
 782                         vcpu->arch.shadow_efer &= ~EFER_LMA;
 783                         svm->vmcb->save.efer &= ~(EFER_LMA | EFER_LME);
 784                 }
 785         }
 786 #endif
 787         if ((vcpu->arch.cr0 & X86_CR0_TS) && !(cr0 & X86_CR0_TS)) {
 788                 svm->vmcb->control.intercept_exceptions &= ~(1 << NM_VECTOR);
 789                 vcpu->fpu_active = 1;
 790         }
 791
 792         vcpu->arch.cr0 = cr0;
 793         cr0 |= X86_CR0_PG | X86_CR0_WP;
 794         cr0 &= ~(X86_CR0_CD | X86_CR0_NW);
 795         if (!vcpu->fpu_active) {
 796                 svm->vmcb->control.intercept_exceptions |= (1 << NM_VECTOR);
 797                 cr0 |= X86_CR0_TS;
 798         }
 799         svm->vmcb->save.cr0 = cr0;
 800 }
 801
 802 static void svm_set_cr4(struct kvm_vcpu *vcpu, unsigned long cr4)
 803 {
 804        vcpu->arch.cr4 = cr4;
 805        to_svm(vcpu)->vmcb->save.cr4 = cr4 | X86_CR4_PAE;
 806 }
 807
 808 static void svm_set_segment(struct kvm_vcpu *vcpu,
 809                             struct kvm_segment *var, int seg)
 810 {
 811         struct vcpu_svm *svm = to_svm(vcpu);
 812         struct vmcb_seg *s = svm_seg(vcpu, seg);
 813
 814         s->base = var->base;
 815         s->limit = var->limit;
 816         s->selector = var->selector;
 817         if (var->unusable)
 818                 s->attrib = 0;
 819         else {
 820                 s->attrib = (var->type & SVM_SELECTOR_TYPE_MASK);
 821                 s->attrib |= (var->s & 1) << SVM_SELECTOR_S_SHIFT;
 822                 s->attrib |= (var->dpl & 3) << SVM_SELECTOR_DPL_SHIFT;
 823                 s->attrib |= (var->present & 1) << SVM_SELECTOR_P_SHIFT;
 824                 s->attrib |= (var->avl & 1) << SVM_SELECTOR_AVL_SHIFT;
 825                 s->attrib |= (var->l & 1) << SVM_SELECTOR_L_SHIFT;
 826                 s->attrib |= (var->db & 1) << SVM_SELECTOR_DB_SHIFT;
 827                 s->attrib |= (var->g & 1) << SVM_SELECTOR_G_SHIFT;
 828         }
 829         if (seg == VCPU_SREG_CS)
 830                 svm->vmcb->save.cpl
 831                         = (svm->vmcb->save.cs.attrib
 832                            >> SVM_SELECTOR_DPL_SHIFT) & 3;
 833
 834 }
 835
 836 /* FIXME:
 837
 838         svm(vcpu)->vmcb->control.int_ctl &= ~V_TPR_MASK;
 839         svm(vcpu)->vmcb->control.int_ctl |= (sregs->cr8 & V_TPR_MASK);
 840
 841 */
 842
 843 static int svm_guest_debug(struct kvm_vcpu *vcpu, struct kvm_debug_guest *dbg)
 844 {
 845         return -EOPNOTSUPP;
 846 }
 847
 848 static int svm_get_irq(struct kvm_vcpu *vcpu)
 849 {
 850         struct vcpu_svm *svm = to_svm(vcpu);
 851         u32 exit_int_info = svm->vmcb->control.exit_int_info;
 852
 853         if (is_external_interrupt(exit_int_info))
 854                 return exit_int_info & SVM_EVTINJ_VEC_MASK;
 855         return -1;
 856 }
 857
 858 static void load_host_msrs(struct kvm_vcpu *vcpu)
 859 {
 860 #ifdef CONFIG_X86_64
 861         wrmsrl(MSR_GS_BASE, to_svm(vcpu)->host_gs_base);
 862 #endif
 863 }
 864
 865 static void save_host_msrs(struct kvm_vcpu *vcpu)
 866 {
 867 #ifdef CONFIG_X86_64
 868         rdmsrl(MSR_GS_BASE, to_svm(vcpu)->host_gs_base);
 869 #endif
 870 }
 871
 872 static void new_asid(struct vcpu_svm *svm, struct svm_cpu_data *svm_data)
 873 {
 874         if (svm_data->next_asid > svm_data->max_asid) {
 875                 ++svm_data->asid_generation;
 876                 svm_data->next_asid = 1;
 877                 svm->vmcb->control.tlb_ctl = TLB_CONTROL_FLUSH_ALL_ASID;
 878         }
 879
 880         svm->vcpu.cpu = svm_data->cpu;
 881         svm->asid_generation = svm_data->asid_generation;
 882         svm->vmcb->control.asid = svm_data->next_asid++;
 883 }
 884
 885 static unsigned long svm_get_dr(struct kvm_vcpu *vcpu, int dr)
 886 {
 887         return to_svm(vcpu)->db_regs[dr];
 888 }
 889
 890 static void svm_set_dr(struct kvm_vcpu *vcpu, int dr, unsigned long value,
 891                        int *exception)
 892 {
 893         struct vcpu_svm *svm = to_svm(vcpu);
 894
 895         *exception = 0;
 896
 897         if (svm->vmcb->save.dr7 & DR7_GD_MASK) {
 898                 svm->vmcb->save.dr7 &= ~DR7_GD_MASK;
 899                 svm->vmcb->save.dr6 |= DR6_BD_MASK;
 900                 *exception = DB_VECTOR;
 901                 return;
 902         }
 903
 904         switch (dr) {
 905         case 0 ... 3:
 906                 svm->db_regs[dr] = value;
 907                 return;
 908         case 4 ... 5:
 909                 if (vcpu->arch.cr4 & X86_CR4_DE) {
 910                         *exception = UD_VECTOR;
 911                         return;
 912                 }
 913         case 7: {
 914                 if (value & ~((1ULL << 32) - 1)) {
 915                         *exception = GP_VECTOR;
 916                         return;
 917                 }
 918                 svm->vmcb->save.dr7 = value;
 919                 return;
 920         }
 921         default:
 922                 printk(KERN_DEBUG "%s: unexpected dr %u\n",
 923                        __FUNCTION__, dr);
 924                 *exception = UD_VECTOR;
 925                 return;
 926         }
 927 }
 928
 929 static int pf_interception(struct vcpu_svm *svm, struct kvm_run *kvm_run)
 930 {
 931         u32 exit_int_info = svm->vmcb->control.exit_int_info;
 932         struct kvm *kvm = svm->vcpu.kvm;
 933         u64 fault_address;
 934         u32 error_code;
 935
 936         if (!irqchip_in_kernel(kvm) &&
 937                 is_external_interrupt(exit_int_info))
 938                 push_irq(&svm->vcpu, exit_int_info & SVM_EVTINJ_VEC_MASK);
 939
 940         fault_address  = svm->vmcb->control.exit_info_2;
 941         error_code = svm->vmcb->control.exit_info_1;
 942         return kvm_mmu_page_fault(&svm->vcpu, fault_address, error_code);
 943 }
 944
 945 static int ud_interception(struct vcpu_svm *svm, struct kvm_run *kvm_run)
 946 {
 947         int er;
 948
 949         er = emulate_instruction(&svm->vcpu, kvm_run, 0, 0, EMULTYPE_TRAP_UD);
 950         if (er != EMULATE_DONE)
 951                 kvm_queue_exception(&svm->vcpu, UD_VECTOR);
 952         return 1;
 953 }
 954
 955 static int nm_interception(struct vcpu_svm *svm, struct kvm_run *kvm_run)
 956 {
 957         svm->vmcb->control.intercept_exceptions &= ~(1 << NM_VECTOR);
 958         if (!(svm->vcpu.arch.cr0 & X86_CR0_TS))
 959                 svm->vmcb->save.cr0 &= ~X86_CR0_TS;
 960         svm->vcpu.fpu_active = 1;
 961
 962         return 1;
 963 }
 964
 965 static int shutdown_interception(struct vcpu_svm *svm, struct kvm_run *kvm_run)
 966 {
 967         /*
 968          * VMCB is undefined after a SHUTDOWN intercept
 969          * so reinitialize it.
 970          */
 971         clear_page(svm->vmcb);
 972         init_vmcb(svm->vmcb);
 973
 974         kvm_run->exit_reason = KVM_EXIT_SHUTDOWN;
 975         return 0;
 976 }
 977
 978 static int io_interception(struct vcpu_svm *svm, struct kvm_run *kvm_run)
 979 {
 980         u32 io_info = svm->vmcb->control.exit_info_1; /* address size bug? */
 981         int size, down, in, string, rep;
 982         unsigned port;
 983
 984         ++svm->vcpu.stat.io_exits;
 985
 986         svm->next_rip = svm->vmcb->control.exit_info_2;
 987
 988         string = (io_info & SVM_IOIO_STR_MASK) != 0;
 989
 990         if (string) {
 991                 if (emulate_instruction(&svm->vcpu,
 992                                         kvm_run, 0, 0, 0) == EMULATE_DO_MMIO)
 993                         return 0;
 994                 return 1;
 995         }
 996
 997         in = (io_info & SVM_IOIO_TYPE_MASK) != 0;
 998         port = io_info >> 16;
 999         size = (io_info & SVM_IOIO_SIZE_MASK) >> SVM_IOIO_SIZE_SHIFT;
1000         rep = (io_info & SVM_IOIO_REP_MASK) != 0;
1001         down = (svm->vmcb->save.rflags & X86_EFLAGS_DF) != 0;
1002
1003         return kvm_emulate_pio(&svm->vcpu, kvm_run, in, size, port);
1004 }
1005
1006 static int nop_on_interception(struct vcpu_svm *svm, struct kvm_run *kvm_run)
1007 {
1008         return 1;
1009 }
1010
1011 static int halt_interception(struct vcpu_svm *svm, struct kvm_run *kvm_run)
1012 {
1013         svm->next_rip = svm->vmcb->save.rip + 1;
1014         skip_emulated_instruction(&svm->vcpu);
1015         return kvm_emulate_halt(&svm->vcpu);
1016 }
1017
1018 static int vmmcall_interception(struct vcpu_svm *svm, struct kvm_run *kvm_run)
1019 {
1020         svm->next_rip = svm->vmcb->save.rip + 3;
1021         skip_emulated_instruction(&svm->vcpu);
1022         kvm_emulate_hypercall(&svm->vcpu);
1023         return 1;
1024 }
1025
1026 static int invalid_op_interception(struct vcpu_svm *svm,
1027                                    struct kvm_run *kvm_run)
1028 {
1029         kvm_queue_exception(&svm->vcpu, UD_VECTOR);
1030         return 1;
1031 }
1032
1033 static int task_switch_interception(struct vcpu_svm *svm,
1034                                     struct kvm_run *kvm_run)
1035 {
1036         pr_unimpl(&svm->vcpu, "%s: task switch is unsupported\n", __FUNCTION__);
1037         kvm_run->exit_reason = KVM_EXIT_UNKNOWN;
1038         return 0;
1039 }
1040
1041 static int cpuid_interception(struct vcpu_svm *svm, struct kvm_run *kvm_run)
1042 {
1043         svm->next_rip = svm->vmcb->save.rip + 2;
1044         kvm_emulate_cpuid(&svm->vcpu);
1045         return 1;
1046 }
1047
1048 static int emulate_on_interception(struct vcpu_svm *svm,
1049                                    struct kvm_run *kvm_run)
1050 {
1051         if (emulate_instruction(&svm->vcpu, NULL, 0, 0, 0) != EMULATE_DONE)
1052                 pr_unimpl(&svm->vcpu, "%s: failed\n", __FUNCTION__);
1053         return 1;
1054 }
1055
1056 static int cr8_write_interception(struct vcpu_svm *svm, struct kvm_run *kvm_run)
1057 {
1058         emulate_instruction(&svm->vcpu, NULL, 0, 0, 0);
1059         if (irqchip_in_kernel(svm->vcpu.kvm))
1060                 return 1;
1061         kvm_run->exit_reason = KVM_EXIT_SET_TPR;
1062         return 0;
1063 }
1064
1065 static int svm_get_msr(struct kvm_vcpu *vcpu, unsigned ecx, u64 *data)
1066 {
1067         struct vcpu_svm *svm = to_svm(vcpu);
1068
1069         switch (ecx) {
1070         case MSR_IA32_TIME_STAMP_COUNTER: {
1071                 u64 tsc;
1072
1073                 rdtscll(tsc);
1074                 *data = svm->vmcb->control.tsc_offset + tsc;
1075                 break;
1076         }
1077         case MSR_K6_STAR:
1078                 *data = svm->vmcb->save.star;
1079                 break;
1080 #ifdef CONFIG_X86_64
1081         case MSR_LSTAR:
1082                 *data = svm->vmcb->save.lstar;
1083                 break;
1084         case MSR_CSTAR:
1085                 *data = svm->vmcb->save.cstar;
1086                 break;
1087         case MSR_KERNEL_GS_BASE:
1088                 *data = svm->vmcb->save.kernel_gs_base;
1089                 break;
1090         case MSR_SYSCALL_MASK:
1091                 *data = svm->vmcb->save.sfmask;
1092                 break;
1093 #endif
1094         case MSR_IA32_SYSENTER_CS:
1095                 *data = svm->vmcb->save.sysenter_cs;
1096                 break;
1097         case MSR_IA32_SYSENTER_EIP:
1098                 *data = svm->vmcb->save.sysenter_eip;
1099                 break;
1100         case MSR_IA32_SYSENTER_ESP:
1101                 *data = svm->vmcb->save.sysenter_esp;
1102                 break;
1103         /* Nobody will change the following 5 values in the VMCB so
1104            we can safely return them on rdmsr. They will always be 0
1105            until LBRV is implemented. */
1106         case MSR_IA32_DEBUGCTLMSR:
1107                 *data = svm->vmcb->save.dbgctl;
1108                 break;
1109         case MSR_IA32_LASTBRANCHFROMIP:
1110                 *data = svm->vmcb->save.br_from;
1111                 break;
1112         case MSR_IA32_LASTBRANCHTOIP:
1113                 *data = svm->vmcb->save.br_to;
1114                 break;
1115         case MSR_IA32_LASTINTFROMIP:
1116                 *data = svm->vmcb->save.last_excp_from;
1117                 break;
1118         case MSR_IA32_LASTINTTOIP:
1119                 *data = svm->vmcb->save.last_excp_to;
1120                 break;
1121         default:
1122                 return kvm_get_msr_common(vcpu, ecx, data);
1123         }
1124         return 0;
1125 }
1126
1127 static int rdmsr_interception(struct vcpu_svm *svm, struct kvm_run *kvm_run)
1128 {
1129         u32 ecx = svm->vcpu.arch.regs[VCPU_REGS_RCX];
1130         u64 data;
1131
1132         if (svm_get_msr(&svm->vcpu, ecx, &data))
1133                 kvm_inject_gp(&svm->vcpu, 0);
1134         else {
1135                 svm->vmcb->save.rax = data & 0xffffffff;
1136                 svm->vcpu.arch.regs[VCPU_REGS_RDX] = data >> 32;
1137                 svm->next_rip = svm->vmcb->save.rip + 2;
1138                 skip_emulated_instruction(&svm->vcpu);
1139         }
1140         return 1;
1141 }
1142
1143 static int svm_set_msr(struct kvm_vcpu *vcpu, unsigned ecx, u64 data)
1144 {
1145         struct vcpu_svm *svm = to_svm(vcpu);
1146
1147         switch (ecx) {
1148         case MSR_IA32_TIME_STAMP_COUNTER: {
1149                 u64 tsc;
1150
1151                 rdtscll(tsc);
1152                 svm->vmcb->control.tsc_offset = data - tsc;
1153                 break;
1154         }
1155         case MSR_K6_STAR:
1156                 svm->vmcb->save.star = data;
1157                 break;
1158 #ifdef CONFIG_X86_64
1159         case MSR_LSTAR:
1160                 svm->vmcb->save.lstar = data;
1161                 break;
1162         case MSR_CSTAR:
1163                 svm->vmcb->save.cstar = data;
1164                 break;
1165         case MSR_KERNEL_GS_BASE:
1166                 svm->vmcb->save.kernel_gs_base = data;
1167                 break;
1168         case MSR_SYSCALL_MASK:
1169                 svm->vmcb->save.sfmask = data;
1170                 break;
1171 #endif
1172         case MSR_IA32_SYSENTER_CS:
1173                 svm->vmcb->save.sysenter_cs = data;
1174                 break;
1175         case MSR_IA32_SYSENTER_EIP:
1176                 svm->vmcb->save.sysenter_eip = data;
1177                 break;
1178         case MSR_IA32_SYSENTER_ESP:
1179                 svm->vmcb->save.sysenter_esp = data;
1180                 break;
1181         case MSR_IA32_DEBUGCTLMSR:
1182                 pr_unimpl(vcpu, "%s: MSR_IA32_DEBUGCTLMSR 0x%llx, nop\n",
1183                                 __FUNCTION__, data);
1184                 break;
1185         case MSR_K7_EVNTSEL0:
1186         case MSR_K7_EVNTSEL1:
1187         case MSR_K7_EVNTSEL2:
1188         case MSR_K7_EVNTSEL3:
1189                 /*
1190                  * only support writing 0 to the performance counters for now
1191                  * to make Windows happy. Should be replaced by a real
1192                  * performance counter emulation later.
1193                  */
1194                 if (data != 0)
1195                         goto unhandled;
1196                 break;
1197         default:
1198         unhandled:
1199                 return kvm_set_msr_common(vcpu, ecx, data);
1200         }
1201         return 0;
1202 }
1203
1204 static int wrmsr_interception(struct vcpu_svm *svm, struct kvm_run *kvm_run)
1205 {
1206         u32 ecx = svm->vcpu.arch.regs[VCPU_REGS_RCX];
1207         u64 data = (svm->vmcb->save.rax & -1u)
1208                 | ((u64)(svm->vcpu.arch.regs[VCPU_REGS_RDX] & -1u) << 32);
1209         svm->next_rip = svm->vmcb->save.rip + 2;
1210         if (svm_set_msr(&svm->vcpu, ecx, data))
1211                 kvm_inject_gp(&svm->vcpu, 0);
1212         else
1213                 skip_emulated_instruction(&svm->vcpu);
1214         return 1;
1215 }
1216
1217 static int msr_interception(struct vcpu_svm *svm, struct kvm_run *kvm_run)
1218 {
1219         if (svm->vmcb->control.exit_info_1)
1220                 return wrmsr_interception(svm, kvm_run);
1221         else
1222                 return rdmsr_interception(svm, kvm_run);
1223 }
1224
1225 static int interrupt_window_interception(struct vcpu_svm *svm,
1226                                    struct kvm_run *kvm_run)
1227 {
1228         svm->vmcb->control.intercept &= ~(1ULL << INTERCEPT_VINTR);
1229         svm->vmcb->control.int_ctl &= ~V_IRQ_MASK;
1230         /*
1231          * If the user space waits to inject interrupts, exit as soon as
1232          * possible
1233          */
1234         if (kvm_run->request_interrupt_window &&
1235             !svm->vcpu.arch.irq_summary) {
1236                 ++svm->vcpu.stat.irq_window_exits;
1237                 kvm_run->exit_reason = KVM_EXIT_IRQ_WINDOW_OPEN;
1238                 return 0;
1239         }
1240
1241         return 1;
1242 }
1243
1244 static int (*svm_exit_handlers[])(struct vcpu_svm *svm,
1245                                       struct kvm_run *kvm_run) = {
1246         [SVM_EXIT_READ_CR0]                     = emulate_on_interception,
1247         [SVM_EXIT_READ_CR3]                     = emulate_on_interception,
1248         [SVM_EXIT_READ_CR4]                     = emulate_on_interception,
1249         [SVM_EXIT_READ_CR8]                     = emulate_on_interception,
1250         /* for now: */
1251         [SVM_EXIT_WRITE_CR0]                    = emulate_on_interception,
1252         [SVM_EXIT_WRITE_CR3]                    = emulate_on_interception,
1253         [SVM_EXIT_WRITE_CR4]                    = emulate_on_interception,
1254         [SVM_EXIT_WRITE_CR8]                    = cr8_write_interception,
1255         [SVM_EXIT_READ_DR0]                     = emulate_on_interception,
1256         [SVM_EXIT_READ_DR1]                     = emulate_on_interception,
1257         [SVM_EXIT_READ_DR2]                     = emulate_on_interception,
1258         [SVM_EXIT_READ_DR3]                     = emulate_on_interception,
1259         [SVM_EXIT_WRITE_DR0]                    = emulate_on_interception,
1260         [SVM_EXIT_WRITE_DR1]                    = emulate_on_interception,
1261         [SVM_EXIT_WRITE_DR2]                    = emulate_on_interception,
1262         [SVM_EXIT_WRITE_DR3]                    = emulate_on_interception,
1263         [SVM_EXIT_WRITE_DR5]                    = emulate_on_interception,
1264         [SVM_EXIT_WRITE_DR7]                    = emulate_on_interception,
1265         [SVM_EXIT_EXCP_BASE + UD_VECTOR]        = ud_interception,
1266         [SVM_EXIT_EXCP_BASE + PF_VECTOR]        = pf_interception,
1267         [SVM_EXIT_EXCP_BASE + NM_VECTOR]        = nm_interception,
1268         [SVM_EXIT_INTR]                         = nop_on_interception,
1269         [SVM_EXIT_NMI]                          = nop_on_interception,
1270         [SVM_EXIT_SMI]                          = nop_on_interception,
1271         [SVM_EXIT_INIT]                         = nop_on_interception,
1272         [SVM_EXIT_VINTR]                        = interrupt_window_interception,
1273         /* [SVM_EXIT_CR0_SEL_WRITE]             = emulate_on_interception, */
1274         [SVM_EXIT_CPUID]                        = cpuid_interception,
1275         [SVM_EXIT_INVD]                         = emulate_on_interception,
1276         [SVM_EXIT_HLT]                          = halt_interception,
1277         [SVM_EXIT_INVLPG]                       = emulate_on_interception,
1278         [SVM_EXIT_INVLPGA]                      = invalid_op_interception,
1279         [SVM_EXIT_IOIO]                         = io_interception,
1280         [SVM_EXIT_MSR]                          = msr_interception,
1281         [SVM_EXIT_TASK_SWITCH]                  = task_switch_interception,
1282         [SVM_EXIT_SHUTDOWN]                     = shutdown_interception,
1283         [SVM_EXIT_VMRUN]                        = invalid_op_interception,
1284         [SVM_EXIT_VMMCALL]                      = vmmcall_interception,
1285         [SVM_EXIT_VMLOAD]                       = invalid_op_interception,
1286         [SVM_EXIT_VMSAVE]                       = invalid_op_interception,
1287         [SVM_EXIT_STGI]                         = invalid_op_interception,
1288         [SVM_EXIT_CLGI]                         = invalid_op_interception,
1289         [SVM_EXIT_SKINIT]                       = invalid_op_interception,
1290         [SVM_EXIT_WBINVD]                       = emulate_on_interception,
1291         [SVM_EXIT_MONITOR]                      = invalid_op_interception,
1292         [SVM_EXIT_MWAIT]                        = invalid_op_interception,
1293 };
1294
1295
1296 static int handle_exit(struct kvm_run *kvm_run, struct kvm_vcpu *vcpu)
1297 {
1298         struct vcpu_svm *svm = to_svm(vcpu);
1299         u32 exit_code = svm->vmcb->control.exit_code;
1300
1301         kvm_reput_irq(svm);
1302
1303         if (svm->vmcb->control.exit_code == SVM_EXIT_ERR) {
1304                 kvm_run->exit_reason = KVM_EXIT_FAIL_ENTRY;
1305                 kvm_run->fail_entry.hardware_entry_failure_reason
1306                         = svm->vmcb->control.exit_code;
1307                 return 0;
1308         }
1309
1310         if (is_external_interrupt(svm->vmcb->control.exit_int_info) &&
1311             exit_code != SVM_EXIT_EXCP_BASE + PF_VECTOR)
1312                 printk(KERN_ERR "%s: unexpected exit_ini_info 0x%x "
1313                        "exit_code 0x%x\n",
1314                        __FUNCTION__, svm->vmcb->control.exit_int_info,
1315                        exit_code);
1316
1317         if (exit_code >= ARRAY_SIZE(svm_exit_handlers)
1318             || !svm_exit_handlers[exit_code]) {
1319                 kvm_run->exit_reason = KVM_EXIT_UNKNOWN;
1320                 kvm_run->hw.hardware_exit_reason = exit_code;
1321                 return 0;
1322         }
1323
1324         return svm_exit_handlers[exit_code](svm, kvm_run);
1325 }
1326
1327 static void reload_tss(struct kvm_vcpu *vcpu)
1328 {
1329         int cpu = raw_smp_processor_id();
1330
1331         struct svm_cpu_data *svm_data = per_cpu(svm_data, cpu);
1332         svm_data->tss_desc->type = 9; /* available 32/64-bit TSS */
1333         load_TR_desc();
1334 }
1335
1336 static void pre_svm_run(struct vcpu_svm *svm)
1337 {
1338         int cpu = raw_smp_processor_id();
1339
1340         struct svm_cpu_data *svm_data = per_cpu(svm_data, cpu);
1341
1342         svm->vmcb->control.tlb_ctl = TLB_CONTROL_DO_NOTHING;
1343         if (svm->vcpu.cpu != cpu ||
1344             svm->asid_generation != svm_data->asid_generation)
1345                 new_asid(svm, svm_data);
1346 }
1347
1348
1349 static inline void svm_inject_irq(struct vcpu_svm *svm, int irq)
1350 {
1351         struct vmcb_control_area *control;
1352
1353         control = &svm->vmcb->control;
1354         control->int_vector = irq;
1355         control->int_ctl &= ~V_INTR_PRIO_MASK;
1356         control->int_ctl |= V_IRQ_MASK |
1357                 ((/*control->int_vector >> 4*/ 0xf) << V_INTR_PRIO_SHIFT);
1358 }
1359
1360 static void svm_set_irq(struct kvm_vcpu *vcpu, int irq)
1361 {
1362         struct vcpu_svm *svm = to_svm(vcpu);
1363
1364         svm_inject_irq(svm, irq);
1365 }
1366
1367 static void svm_intr_assist(struct kvm_vcpu *vcpu)
1368 {
1369         struct vcpu_svm *svm = to_svm(vcpu);
1370         struct vmcb *vmcb = svm->vmcb;
1371         int intr_vector = -1;
1372
1373         if ((vmcb->control.exit_int_info & SVM_EVTINJ_VALID) &&
1374             ((vmcb->control.exit_int_info & SVM_EVTINJ_TYPE_MASK) == 0)) {
1375                 intr_vector = vmcb->control.exit_int_info &
1376                               SVM_EVTINJ_VEC_MASK;
1377                 vmcb->control.exit_int_info = 0;
1378                 svm_inject_irq(svm, intr_vector);
1379                 return;
1380         }
1381
1382         if (vmcb->control.int_ctl & V_IRQ_MASK)
1383                 return;
1384
1385         if (!kvm_cpu_has_interrupt(vcpu))
1386                 return;
1387
1388         if (!(vmcb->save.rflags & X86_EFLAGS_IF) ||
1389             (vmcb->control.int_state & SVM_INTERRUPT_SHADOW_MASK) ||
1390             (vmcb->control.event_inj & SVM_EVTINJ_VALID)) {
1391                 /* unable to deliver irq, set pending irq */
1392                 vmcb->control.intercept |= (1ULL << INTERCEPT_VINTR);
1393                 svm_inject_irq(svm, 0x0);
1394                 return;
1395         }
1396         /* Okay, we can deliver the interrupt: grab it and update PIC state. */
1397         intr_vector = kvm_cpu_get_interrupt(vcpu);
1398         svm_inject_irq(svm, intr_vector);
1399         kvm_timer_intr_post(vcpu, intr_vector);
1400 }
1401
1402 static void kvm_reput_irq(struct vcpu_svm *svm)
1403 {
1404         struct vmcb_control_area *control = &svm->vmcb->control;
1405
1406         if ((control->int_ctl & V_IRQ_MASK)
1407             && !irqchip_in_kernel(svm->vcpu.kvm)) {
1408                 control->int_ctl &= ~V_IRQ_MASK;
1409                 push_irq(&svm->vcpu, control->int_vector);
1410         }
1411
1412         svm->vcpu.arch.interrupt_window_open =
1413                 !(control->int_state & SVM_INTERRUPT_SHADOW_MASK);
1414 }
1415
1416 static void svm_do_inject_vector(struct vcpu_svm *svm)
1417 {
1418         struct kvm_vcpu *vcpu = &svm->vcpu;
1419         int word_index = __ffs(vcpu->arch.irq_summary);
1420         int bit_index = __ffs(vcpu->arch.irq_pending[word_index]);
1421         int irq = word_index * BITS_PER_LONG + bit_index;
1422
1423         clear_bit(bit_index, &vcpu->arch.irq_pending[word_index]);
1424         if (!vcpu->arch.irq_pending[word_index])
1425                 clear_bit(word_index, &vcpu->arch.irq_summary);
1426         svm_inject_irq(svm, irq);
1427 }
1428
1429 static void do_interrupt_requests(struct kvm_vcpu *vcpu,
1430                                        struct kvm_run *kvm_run)
1431 {
1432         struct vcpu_svm *svm = to_svm(vcpu);
1433         struct vmcb_control_area *control = &svm->vmcb->control;
1434
1435         svm->vcpu.arch.interrupt_window_open =
1436                 (!(control->int_state & SVM_INTERRUPT_SHADOW_MASK) &&
1437                  (svm->vmcb->save.rflags & X86_EFLAGS_IF));
1438
1439         if (svm->vcpu.arch.interrupt_window_open && svm->vcpu.arch.irq_summary)
1440                 /*
1441                  * If interrupts enabled, and not blocked by sti or mov ss. Good.
1442                  */
1443                 svm_do_inject_vector(svm);
1444
1445         /*
1446          * Interrupts blocked.  Wait for unblock.
1447          */
1448         if (!svm->vcpu.arch.interrupt_window_open &&
1449             (svm->vcpu.arch.irq_summary || kvm_run->request_interrupt_window))
1450                 control->intercept |= 1ULL << INTERCEPT_VINTR;
1451          else
1452                 control->intercept &= ~(1ULL << INTERCEPT_VINTR);
1453 }
1454
1455 static int svm_set_tss_addr(struct kvm *kvm, unsigned int addr)
1456 {
1457         return 0;
1458 }
1459
1460 static void save_db_regs(unsigned long *db_regs)
1461 {
1462         asm volatile ("mov %%dr0, %0" : "=r"(db_regs[0]));
1463         asm volatile ("mov %%dr1, %0" : "=r"(db_regs[1]));
1464         asm volatile ("mov %%dr2, %0" : "=r"(db_regs[2]));
1465         asm volatile ("mov %%dr3, %0" : "=r"(db_regs[3]));
1466 }
1467
1468 static void load_db_regs(unsigned long *db_regs)
1469 {
1470         asm volatile ("mov %0, %%dr0" : : "r"(db_regs[0]));
1471         asm volatile ("mov %0, %%dr1" : : "r"(db_regs[1]));
1472         asm volatile ("mov %0, %%dr2" : : "r"(db_regs[2]));
1473         asm volatile ("mov %0, %%dr3" : : "r"(db_regs[3]));
1474 }
1475
1476 static void svm_flush_tlb(struct kvm_vcpu *vcpu)
1477 {
1478         force_new_asid(vcpu);
1479 }
1480
1481 static void svm_prepare_guest_switch(struct kvm_vcpu *vcpu)
1482 {
1483 }
1484
1485 static void svm_vcpu_run(struct kvm_vcpu *vcpu, struct kvm_run *kvm_run)
1486 {
1487         struct vcpu_svm *svm = to_svm(vcpu);
1488         u16 fs_selector;
1489         u16 gs_selector;
1490         u16 ldt_selector;
1491
1492         pre_svm_run(svm);
1493
1494         save_host_msrs(vcpu);
1495         fs_selector = read_fs();
1496         gs_selector = read_gs();
1497         ldt_selector = read_ldt();
1498         svm->host_cr2 = kvm_read_cr2();
1499         svm->host_dr6 = read_dr6();
1500         svm->host_dr7 = read_dr7();
1501         svm->vmcb->save.cr2 = vcpu->arch.cr2;
1502
1503         if (svm->vmcb->save.dr7 & 0xff) {
1504                 write_dr7(0);
1505                 save_db_regs(svm->host_db_regs);
1506                 load_db_regs(svm->db_regs);
1507         }
1508
1509         clgi();
1510
1511         local_irq_enable();
1512
1513         asm volatile (
1514 #ifdef CONFIG_X86_64
1515                 "push %%rbp; \n\t"
1516 #else
1517                 "push %%ebp; \n\t"
1518 #endif
1519
1520 #ifdef CONFIG_X86_64
1521                 "mov %c[rbx](%[svm]), %%rbx \n\t"
1522                 "mov %c[rcx](%[svm]), %%rcx \n\t"
1523                 "mov %c[rdx](%[svm]), %%rdx \n\t"
1524                 "mov %c[rsi](%[svm]), %%rsi \n\t"
1525                 "mov %c[rdi](%[svm]), %%rdi \n\t"
1526                 "mov %c[rbp](%[svm]), %%rbp \n\t"
1527                 "mov %c[r8](%[svm]),  %%r8  \n\t"
1528                 "mov %c[r9](%[svm]),  %%r9  \n\t"
1529                 "mov %c[r10](%[svm]), %%r10 \n\t"
1530                 "mov %c[r11](%[svm]), %%r11 \n\t"
1531                 "mov %c[r12](%[svm]), %%r12 \n\t"
1532                 "mov %c[r13](%[svm]), %%r13 \n\t"
1533                 "mov %c[r14](%[svm]), %%r14 \n\t"
1534                 "mov %c[r15](%[svm]), %%r15 \n\t"
1535 #else
1536                 "mov %c[rbx](%[svm]), %%ebx \n\t"
1537                 "mov %c[rcx](%[svm]), %%ecx \n\t"
1538                 "mov %c[rdx](%[svm]), %%edx \n\t"
1539                 "mov %c[rsi](%[svm]), %%esi \n\t"
1540                 "mov %c[rdi](%[svm]), %%edi \n\t"
1541                 "mov %c[rbp](%[svm]), %%ebp \n\t"
1542 #endif
1543
1544 #ifdef CONFIG_X86_64
1545                 /* Enter guest mode */
1546                 "push %%rax \n\t"
1547                 "mov %c[vmcb](%[svm]), %%rax \n\t"
1548                 SVM_VMLOAD "\n\t"
1549                 SVM_VMRUN "\n\t"
1550                 SVM_VMSAVE "\n\t"
1551                 "pop %%rax \n\t"
1552 #else
1553                 /* Enter guest mode */
1554                 "push %%eax \n\t"
1555                 "mov %c[vmcb](%[svm]), %%eax \n\t"
1556                 SVM_VMLOAD "\n\t"
1557                 SVM_VMRUN "\n\t"
1558                 SVM_VMSAVE "\n\t"
1559                 "pop %%eax \n\t"
1560 #endif
1561
1562                 /* Save guest registers, load host registers */
1563 #ifdef CONFIG_X86_64
1564                 "mov %%rbx, %c[rbx](%[svm]) \n\t"
1565                 "mov %%rcx, %c[rcx](%[svm]) \n\t"
1566                 "mov %%rdx, %c[rdx](%[svm]) \n\t"
1567                 "mov %%rsi, %c[rsi](%[svm]) \n\t"
1568                 "mov %%rdi, %c[rdi](%[svm]) \n\t"
1569                 "mov %%rbp, %c[rbp](%[svm]) \n\t"
1570                 "mov %%r8,  %c[r8](%[svm]) \n\t"
1571                 "mov %%r9,  %c[r9](%[svm]) \n\t"
1572                 "mov %%r10, %c[r10](%[svm]) \n\t"
1573                 "mov %%r11, %c[r11](%[svm]) \n\t"
1574                 "mov %%r12, %c[r12](%[svm]) \n\t"
1575                 "mov %%r13, %c[r13](%[svm]) \n\t"
1576                 "mov %%r14, %c[r14](%[svm]) \n\t"
1577                 "mov %%r15, %c[r15](%[svm]) \n\t"
1578
1579                 "pop  %%rbp; \n\t"
1580 #else
1581                 "mov %%ebx, %c[rbx](%[svm]) \n\t"
1582                 "mov %%ecx, %c[rcx](%[svm]) \n\t"
1583                 "mov %%edx, %c[rdx](%[svm]) \n\t"
1584                 "mov %%esi, %c[rsi](%[svm]) \n\t"
1585                 "mov %%edi, %c[rdi](%[svm]) \n\t"
1586                 "mov %%ebp, %c[rbp](%[svm]) \n\t"
1587
1588                 "pop  %%ebp; \n\t"
1589 #endif
1590                 :
1591                 : [svm]"a"(svm),
1592                   [vmcb]"i"(offsetof(struct vcpu_svm, vmcb_pa)),
1593                   [rbx]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_RBX])),
1594                   [rcx]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_RCX])),
1595                   [rdx]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_RDX])),
1596                   [rsi]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_RSI])),
1597                   [rdi]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_RDI])),
1598                   [rbp]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_RBP]))
1599 #ifdef CONFIG_X86_64
1600                   , [r8]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_R8])),
1601                   [r9]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_R9])),
1602                   [r10]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_R10])),
1603                   [r11]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_R11])),
1604                   [r12]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_R12])),
1605                   [r13]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_R13])),
1606                   [r14]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_R14])),
1607                   [r15]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_R15]))
1608 #endif
1609                 : "cc", "memory"
1610 #ifdef CONFIG_X86_64
1611                 , "rbx", "rcx", "rdx", "rsi", "rdi"
1612                 , "r8", "r9", "r10", "r11" , "r12", "r13", "r14", "r15"
1613 #else
1614                 , "ebx", "ecx", "edx" , "esi", "edi"
1615 #endif
1616                 );
1617
1618         if ((svm->vmcb->save.dr7 & 0xff))
1619                 load_db_regs(svm->host_db_regs);
1620
1621         vcpu->arch.cr2 = svm->vmcb->save.cr2;
1622
1623         write_dr6(svm->host_dr6);
1624         write_dr7(svm->host_dr7);
1625         kvm_write_cr2(svm->host_cr2);
1626
1627         load_fs(fs_selector);
1628         load_gs(gs_selector);
1629         load_ldt(ldt_selector);
1630         load_host_msrs(vcpu);
1631
1632         reload_tss(vcpu);
1633
1634         local_irq_disable();
1635
1636         stgi();
1637
1638         svm->next_rip = 0;
1639 }
1640
1641 static void svm_set_cr3(struct kvm_vcpu *vcpu, unsigned long root)
1642 {
1643         struct vcpu_svm *svm = to_svm(vcpu);
1644
1645         svm->vmcb->save.cr3 = root;
1646         force_new_asid(vcpu);
1647
1648         if (vcpu->fpu_active) {
1649                 svm->vmcb->control.intercept_exceptions |= (1 << NM_VECTOR);
1650                 svm->vmcb->save.cr0 |= X86_CR0_TS;
1651                 vcpu->fpu_active = 0;
1652         }
1653 }
1654
1655 static int is_disabled(void)
1656 {
1657         u64 vm_cr;
1658
1659         rdmsrl(MSR_VM_CR, vm_cr);
1660         if (vm_cr & (1 << SVM_VM_CR_SVM_DISABLE))
1661                 return 1;
1662
1663         return 0;
1664 }
1665
1666 static void
1667 svm_patch_hypercall(struct kvm_vcpu *vcpu, unsigned char *hypercall)
1668 {
1669         /*
1670          * Patch in the VMMCALL instruction:
1671          */
1672         hypercall[0] = 0x0f;
1673         hypercall[1] = 0x01;
1674         hypercall[2] = 0xd9;
1675 }
1676
1677 static void svm_check_processor_compat(void *rtn)
1678 {
1679         *(int *)rtn = 0;
1680 }
1681
1682 static bool svm_cpu_has_accelerated_tpr(void)
1683 {
1684         return false;
1685 }
1686
1687 static struct kvm_x86_ops svm_x86_ops = {
1688         .cpu_has_kvm_support = has_svm,
1689         .disabled_by_bios = is_disabled,
1690         .hardware_setup = svm_hardware_setup,
1691         .hardware_unsetup = svm_hardware_unsetup,
1692         .check_processor_compatibility = svm_check_processor_compat,
1693         .hardware_enable = svm_hardware_enable,
1694         .hardware_disable = svm_hardware_disable,
1695         .cpu_has_accelerated_tpr = svm_cpu_has_accelerated_tpr,
1696
1697         .vcpu_create = svm_create_vcpu,
1698         .vcpu_free = svm_free_vcpu,
1699         .vcpu_reset = svm_vcpu_reset,
1700
1701         .prepare_guest_switch = svm_prepare_guest_switch,
1702         .vcpu_load = svm_vcpu_load,
1703         .vcpu_put = svm_vcpu_put,
1704         .vcpu_decache = svm_vcpu_decache,
1705
1706         .set_guest_debug = svm_guest_debug,
1707         .get_msr = svm_get_msr,
1708         .set_msr = svm_set_msr,
1709         .get_segment_base = svm_get_segment_base,
1710         .get_segment = svm_get_segment,
1711         .set_segment = svm_set_segment,
1712         .get_cs_db_l_bits = kvm_get_cs_db_l_bits,
1713         .decache_cr4_guest_bits = svm_decache_cr4_guest_bits,
1714         .set_cr0 = svm_set_cr0,
1715         .set_cr3 = svm_set_cr3,
1716         .set_cr4 = svm_set_cr4,
1717         .set_efer = svm_set_efer,
1718         .get_idt = svm_get_idt,
1719         .set_idt = svm_set_idt,
1720         .get_gdt = svm_get_gdt,
1721         .set_gdt = svm_set_gdt,
1722         .get_dr = svm_get_dr,
1723         .set_dr = svm_set_dr,
1724         .cache_regs = svm_cache_regs,
1725         .decache_regs = svm_decache_regs,
1726         .get_rflags = svm_get_rflags,
1727         .set_rflags = svm_set_rflags,
1728
1729         .tlb_flush = svm_flush_tlb,
1730
1731         .run = svm_vcpu_run,
1732         .handle_exit = handle_exit,
1733         .skip_emulated_instruction = skip_emulated_instruction,
1734         .patch_hypercall = svm_patch_hypercall,
1735         .get_irq = svm_get_irq,
1736         .set_irq = svm_set_irq,
1737         .queue_exception = svm_queue_exception,
1738         .exception_injected = svm_exception_injected,
1739         .inject_pending_irq = svm_intr_assist,
1740         .inject_pending_vectors = do_interrupt_requests,
1741
1742         .set_tss_addr = svm_set_tss_addr,
1743 };
1744
1745 static int __init svm_init(void)
1746 {
1747         return kvm_init(&svm_x86_ops, sizeof(struct vcpu_svm),
1748                               THIS_MODULE);
1749 }
1750
1751 static void __exit svm_exit(void)
1752 {
1753         kvm_exit();
1754 }
1755
1756 module_init(svm_init)
1757 module_exit(svm_exit)